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Although many recently published modeling innovations have proven their validity in practical modeling situations [1]-[4], they are not sufficient means to facilitate complete modeling scalability. The main problem is that the designer has the full freedom to optimize the transistor layout with any desirable performance criteria in mind. This leads to extrinsic parasitics that are very significant for the device performance at gigahertz frequencies. Unfortunately, these parasitics are often very hard to predict in practice and thus very difficult to add manually during simulations. Hence, a scalable model is only fully applicable if it takes into account these effects and, hence, the specific layout of the device. In BSIM3v3 some extrinsic effects, e.g. diffusion implants, may be specified in terms of drawn dimensions. However, other very significant effects, such as bulk effects and gate resistance, are not considered and currently compensation is conducted through ballpark estimates or optimization techniques. This is a precarious situation since it requires that each device be considered individually. In the following, the different RF transistor layout techniques are discussed.

One important layout technique, which is often applied to improve the layout of large RF transistors, is PXOWLILQJHUGLVWULEXWLRQ illustrated in Figure 1. By distributing the total gate width into smaller parallel transistors, significant reduction of gate resistance and parasitic junction effects is achieved [6]. These improvements translate into higher cutoff and maximum oscillation frequencies as well as lower device noise [5,6]. Common practice includes the use of contacts on both sides of the gate fingers. This configuration leads to an overall gate resistance of [6]

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A drawback of distributing the transistor into many parallel structures is that (i) the extrinsic gate-bulk parasitics increase and (ii) more gate-source and gate-drain overpasses are required. In Figure 2b, this aspect is illustrated. Hence, extrinsic fringing effects are increased by employing multi-fingered layouts and thus a tradeoff between gate resistance and fringing effects is required in practice. These issues become very critical at gigahertz frequencies and the transistor performance depends significantly on the layout when used in RF applications. This aspect is illustrated in Figure 2a, which shows the extracted gate-drain susceptance for a 300x0.5 micron NMOSFET configured with a different number of fingers (from 10 to 50). It is clear from the 30% variation depicted in Figure 2a, that a specification of just transistor length and width is inadequate to completely describe its operation.


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Another important effect at gigahertz frequencies is associated with the substrate under the transistor. As has been generally accepted in the RF CMOS community, accurate modeling of the transistor bulk region is essential to obtain good RF models [1]-[4]. A cross-section of a single-finger transistor is shown in Figure 3 and it is seen that there is a non-zero distance between the nearest substrate contact placed by the designer and the intrinsic bulk just below the channel to which the modeling equations refer (the back-gate). The corresponding resistance is a complicated function of the process parameters and may be quite large for technologies offering good device isolation; e.g. VKDOORZWUHQFKLVRODWLRQ processes. Due to a relatively low transconductance per drain current, RF transistors are usually large enough to render the resistive and dielectric substrate losses very important for device operation in the gigahertz range. The cause is the relatively large junction capacitance of the drain and source implants which brings the substrate impedance into play. Consideration of these effects is particularly important for accurate modeling of the output characteristics of the MOSFET [1]-[4]. In general, the bulk interaction for a particular process is a complicated function of the individual transistor layout including the placement of bulk contacts. Usually, substrate contacts are placed for every 3-6 fingers in a multi-finger layout in order to make the device less susceptible to substrate-carried noise. By this approach, the bulk resistance to the nearest ground strap is also reduced without sacrificing too much of the parasitic reduction which is gained by sharing source and drain diffusion areas among gates.

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From observing the large importance of these layout-induced effects, it is clear that a viable solution must be sought. The designer may manually add fringing and other effects to the model. However, this is a tedious and complicated solution for large designs. Alternatively, the model may include an interface to specify the layout configuration of the device. However, as shall be evident from the following, extrinsic effects are not described by simple layout relations. Hence, the ultimate solution is to design transistors that are scalable in intrinsic as well as extrinsic effects. This is the approach studied here.

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The extrinsic effects, including underpass fringing, contact resistances, bulk effects, and gate interconnects, must be proportional to : (parallel effects) and 1/: (series effects).

The gate resistance must scale inversely with :. A limitation to this can be QRQTXDVLVWDWLF(NQS) effects that are most visible for large transistor widths or at higher frequencies.

In order to achieve the above conditions, it is required that some layout restraints are introduced. For a scalable configuration it is required that finger length remains constant. Further, it is essential that the number of fingers between substrate contacts is consistent. A way to accomplish this is to base all transistors on a unit FOXVWHURIILQJHUV (COF). An example COF is illustrated in Figure 4a.

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Larger transistor widths are accomplished by parallel coupling the COF instances. Note that by basing all transistors on a unit COF, the design flexibility is reduced. There are several disadvantages including: (i) Only widths that are a multiple of the COF width can be implemented and (ii) the COF configuration may not be optimum for all transistor widths. To overcome these disadvantages in practice it usually suffices to design 2-3 different COF instances to cover different width ranges and applications. Typical COF design guidelines are listed in Table 2. However, note that the values are very dependent on the particular type of process. Although some performance is lost by introducing high layout consistency, the derived advantages of scalability are usually important enough to justify this approach in practice.

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In order to illustrate the above concepts, several transistors have been fabricated in a 0.25m bulk polycide CMOS process. The process uses tungsten for its bottom metal layer, which has a lower conductivity than other aluminum-composites. Further, the resistivity of the polycide is a little higher than for many other similar processes. Due to these significant series effects, it has been estimated that best performance for transistors up to around 200 micron is achieved for finger widths around 5m. Hence, all transistor designs presented here are based on a 4-fingered COF with a finger length of 5m. The corresponding gate resistance for a single COF is estimated from the electrical specification document to typically 2.3; including contacts. Eight common-source NMOSFETs have been fabricated with very different widths, ranging from 40-320 micron. Using a calibrated vector network analyzer, the scattering parameters have been measured over a large frequency and bias range. Note that in order to verify scalability, different transistors must be given the same bias voltages. Transistor performance is


not generally scalable for constant bias current. Very careful de-embedding has been conducted to take into account contact effects and test-fixture parasitics. For verification of scalability down to very small transistor widths, very accurate de-embedding is required in order not to offset results. In order to facilitate a more intuitive comparison, the measured scattering parameters have been converted into admittance (


difficulty and that the accuracy of this parameter is typically quite low at the present frequency. With the high level of scalability indicated by Figure 6, it seems reasonable to present the parameters in terms of transistor width. This has been done in Table 3 for the considered bias points. Note that in general the presented extraction results are only valid at one bias point and one frequency. For lower frequencies where quasi-static operation can be assumed, it usually suffices to represent the admittances by a corresponding capacitor thereby facilitating a frequency-independent description.

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rf layout

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