rf measurements & modeling

8/12/2019 RF Measurements & Modeling

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Introduction

MOS Transistor

Cutoff Frequency Evolution

0

1020

30

40

50

60

0 0.1 0.2 0.3 0.4 0.5

L/um

ft/GHz

0

50

100150

200

250

300

350

1960 1970 1980 1990 2000

wafer diameter/mm

year

25mm

300mm

Silicon Substrate

Evolution

Silicon Devices:

An Affordable Technology Gets Ready For RF

Agilent Technologies

With the trend to even smaller MOS transistor geometries, the silicon technology is heading strongly

into the RF frequency application. This trend comes along with increasing wafer diameters. Compared

to the rather expensive Gallium-Arsenide (GaAs) technology, silicon allows to manufacture high

performance and high frequency chipset with affordable cost. Besides these technical and cost aspects,the possibility of MOS-RF circuits to be combined with digital circuits (memory circuits and, thus

programmability of the whole chip set depending on its custom application), makes MOS technology

especially interesting and effective.


3/34

Silicon Device Modeling compared to GaAs

GaAs Silicon

non-linear RF modeling

distortion effects

load pull

small signal modeling

RF noise

non-linear DC

CV space charge

linear S-parameter

1/f noise

This means that aspects and challenges related to RF, and mainlyapplied in the GaAs world, commence to play a more and more

important role also for silicon measurement and modeling !

Comparing further the existing GaAs RF and microwave technology with the upcoming silicon RF, and

relating it to modeling, many techniques developed in GaAs device modeling can be applied to silicon

too. The main issue hereby is to keep in mind that usually GaAs substrates exhibit RF-wise a much

higher impedance and are thus much more ideal than the more lossy silicon substrates.

Typically, GaAs modeling can be considered to move from fixed operating point high frequency

characterization (small signal modeling, RF noise modeling, as well as non-linear RF, distortion effectsetc.) towards RF modeling based on large signal DC characterization. Silicon modeling, on the other

hand, usually starts from large signal DC characterization via capacitor modeling and goes until linear

S-parameter modeling, including 1/f noise.

However, related to the previously mentioned shooting for complete RF MOS chipsets, the non-linear

RF modeling aspects become more and more important also for silicon. This comes along with the need

to bring the modeling world and the RF designer world much closer together, by offering both groups

access to the same tools: nonlinear RF simulators (harmonic balance) as well as nonlinear network

analyzers (to characterize the possible distortions of components and circuits).


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BASIC DEVICE MODELING MEASUREMENTS

in outtransmit

DC

in out

transmit

DUT

s11

RF R A B

85046AS-PARAMETER TESTSET

TF & total fitNWA

DUT

cvCVDUT12.05pF


The Device Modeling Process

MEASUREMENTS

DC

C(v)AC (S-parameters)

1/f Noise

MEASUREMENTS

DC

C(v)AC (S-parameters)

1/f Noise

SELECTED

SIMULATORSELECTED

SIMULATOR

MODEL PARAMETER EXTRACTION

solving the model equations for the parametersMODEL PARAMETER EXTRACTION

solving the model equations for the parameters

DESIGN KIT

DOCUMENTATIONDESIGN KIT

DOCUMENTATIONPARAMETER OPTIMIZATION,

TUNINGPARAMETER OPTIMIZATION,

TUNING

MODEL SELECTIONMODEL SELECTION

PHYSICAL DEVICEPHYSICAL DEVICE

determines


To begin with, the previous slide depicts a standard modeling scheme for today's silicon components.

For a given device, and related to the circuit designer's simulator of choice, a model is selected out of

the available simulator models. In many cases, custom models are selected for house-internal modeling,

while for external designer customers, industry-standard models like the BSIM3, EKV for MOS or the

VBIC, HiCum models for bipolar transistors are applied. Passive components are most often modeled

by sub-circuit models, i.e. a combination of ideal R, L, C, representing the non-ideal high-frequency

behavior of the measured device.


6/34


7/34

RF Measurements

In this chapter, we will concentrate on the interpretation and understanding of S-parameter plots

S-Parameter Analogy

incident reference

R

Areflected

Btransmitted


To help with better understanding S-parameters, they can be considered as a mean to characterize the

input and throughput characteristics of a pair of spectacles. Like with an optician who can characterizethe lenses of your spectacles, S-parameters allow to characterize a circuit in a well-defined

environment, the characteristic impedance Z0.

Staying with the pair of spectacles examples for a moment, i.e. power-wise, the S-parameters are

defined as:

=

2

2

2

1

2

22

2

21

2

12

2

11

2

2

2

1

a

a*

SS

SS

b

b

with

| ai|

2

power wave travelling towards the twoport gate| b

i|

2

power wave reflected back from the twoport gate

and

| S11|

2

power reflected from port1

| S12|

2

power transmitted from port1 to port2

| S21|

2

power transmitted from port2 to port1

| S22|

2

power reflected from port2

This means that S-parameters relate traveling waves (power) to a twoport's reflection and transmission

behavior. Since the twoport is imbedded in a characteristic impedance of Z0, these 'waves' can also be

interpreted in terms of normalized voltages or currents. This is explained below.


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|S11|2

|a1|2

|b1|2

Z0 Z0

|a2|2

|b2|2

|S21|2

|S12|2

|S22|2

0Zv*vi*vP ==

Starting with normalized gives normalized amplitudes

power to Z0 for voltage and current

00

Z*iZVP ==

Power

Domain|a1|

2 Voltage

Domaina1

S-Parameters and Characteristic Impedance Z0


Looking at the S-parameter coefficients individually, we have:

0a

v

v

a

bS

2

1porttowards

1portatreflected

1

111

=

==

0a

v

v

a

bS

1

2porttowards

1portofout

2

112

=

==

0a

v

v

a

bS

2

1porttowards

2portofout

1

221

=

==

0a

v

v

a

bS

1

2porttowards

2portatreflected

2

222

=

==

(3)

Let's now discuss some characteristic S-parameter values.

| S11, S22 .

-1 | all voltage amplitudes towards the twoport are inverted and reflected (0)

0 | impedance matching, no reflections at all (50 ) +1 | voltage amplitudes are reflected (infinite )

Note: The magnitudes of S11 and S22 are always 1


9/34

On the other hand, the magnitude of S21 (transfer characteristics) resp. S12 (reverse) can exceed the

value of 1 in the case of amplification within a Z0 impedance system:

| S21, S12 .

< -1 | input signal is amplified in the Z0 environment, the phase is inverted (transistor)

-1 | input signal is transmitted (unity gain), but the phase is inverted 0 | no signal transmission at all

+1 | unity gain signal transmission

> +1 | input signal is amplified in the Z0 environment

To perform an accurate device modeling, it is very important to first understand S-parameter plots.

This is the topic of the following slides.

Considering S11 in equation (3) and introducing equations (1) and (2), we can relate the signal

towards the twoport to its reflections at the twoport input like:

)tcoefficien_reflection(

towards

refl

1

1

02a11

v

v

a

bS ===

=

What makes Sxx

-parameters especially interesting for modeling, is that S11 and S22 can be interpreted

as complex input or output resistance of the twoport (including the termination at the opposite side of

the twoport with Z0!!). That's why they are usually plotted in a Smith chart.

The Smith chart is a transformation of the complex impedance plane R into the complex reflectioncoefficient (rho) following:

0ZR

0ZR

+

=

with the system's reference impedance Z0 = 50 .

This means that the right half of the complex impedance plane R is transformed into a circle in the

-domain with radius '1'


10/34

Interpreting the Smith Chart for S11 and S22

R

j50

50

1

4 3

2

-1 1

-j

j

1 2

3

4

R - Z0S11 = -----------

R + Z0

for e.g. Z0=50


The slide above consolidates this context a little further: it shows a square with the corners (0/0),

(50/0), (50/j50)and (0/j50)in the complex impedance plane and its equivalent in the Smith chart

for Z0=50. Please watch the angel-preserving property of this transform (rectangles stay rectangles

close to their origins). Also watch how the positive and negative imaginary axis of the R plane is

transformed into the Smith chart domain ( ), and where (50/j50) is located in the Smith chart.

Also verify that the center of the Smith chart represents Z0.

I.e. for Z0 = 50 in the impedance plane, this locus is transformed right into the center of the Smith

chart at (50/j0) .

WEB INFO:

Agilent Technologies Interactive Application Note 95-1,

S-Parameter Techniques for Faster, More Accurate Network Designs.

The next slide gives Smith chart plots for different electrical components connected to a single port of a

vector network analyzer (VNA). For an ohmic resistor, all measurement results are located on the x-

axis, RZ0 to the right. From the scaling of the Smith chart, we cancalculate the value of the resistor as x*Z0.

For inductors and capacitors, however, the measurement result is frequency dependent and follows the

sketched traces. Note that the curves turn to the right with increasing frequency.


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jL

1/jC

R

inductive

capacitive

Z0

Interpreting the Reflection S-Parameters

S11 and S22

Z

Note: for TwoPorts,

Sxx represents the

input impedance

at Sxx includingZ0

of the opposite port!

Example: 1-port


Referring to the transfer parameters Sxy, we consider the next slide. For a capacitor inserted between

both ports of a VNA, the Sxy trace starts at '0' for DC (the capacitor is an ideal OPEN), while it tends

towards +1 for infinite frequency (the capacitor is an ideal SHORT, all power is transmitted).

For transistors, with signal amplification in the Z0 environment, but (of course) phase inversion, thetrace starts at the negative x-axis, below -1. For infinite frequency, the transistor becomes a passive

component with no gain any more. I.e. its capacitors short the energy flow to ground, and S21 tends to

'0'.


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freq

Curve from 0 to +1 Curve from -1.9 to +0.2

freq freq

P2P1Passive DUT

P2

P1

Active DUT

Interpreting the Polar Plots of S12 and S21

With this in mind, let's lead over to specific S-parameter device measurement and modeling aspects. A

good model is able to cover both, the reflection (Sxx) and the transmit (Sxy) S-parameters, see the next

slide.

As a first and basic aspect, it must be noted that the starting point of all S-parameter traces is

determined by the DC behavior of the component, and therefore completely dependent on the DC

model fit! Only the course, the further trace of the S-parameters can be influenced by the RF modelparameters like the capacitors, the transit times (of transistors) etc. This is very important to consider.

S-Parameter Device Modeling in General

Sxx Sxy

freq

freq


The following series of slides give examples for possible S-parameter measurement and modeling

problems.


13/34

Considering transistor S-parameter modeling, the device has to be biased during the S-parameter

measurements, see the following block diagram:

DUT

External

Bias TEEs

FS S F

DC

Source/

Monitor

Synthesized

Sweeper

RF

DC

S-parameter

Test Set

Vector

Network

Analyzer

IC-CAP

If there is a problem with the fitting of the simulated S-parameters and the measurement curves for

lowest frequencies, especially for specific bias conditions, it must be considered if there is e.g. a DC

bias voltage drop in the AC/DC bias TEE. If this occurs, the measured voltage drop is notincluded in a

stand-alone simulation of the DUT. The simulation circuit must be enhanced with this resistor Rbias !

The following slide shows this effect with a comparison of measured and simulated curves, with and

without the additional resistor Rbias in the enhanced simulation test circuit. Note that in this example,

the transit time has not yet been modeled, and therefore, the fit for higher frequencies is not yet

obtained.

DC Bias Voltage Drop in the VNA Bias TEEs

DC

AC

transistor

LbiasCbias

Rbias

Measurement

DC bias

voltage drop

w/o Rbias with RbiasAgilent Technologies

Another important aspect is the fact that using a conventionally network analyzer, the stimulus

frequency and the measurement frequency are identical. Furthermore, the bandwidth of the received

signal is typically extremely small-band (for higher resolution), around a few Hertz. Therefore, care

must be taken to ensure that only small signal power be applied for the measurement. If the applied

signal power is too high, signal distortion can occur. The next slides cover the problems which may

arise.


14/34

AC Power Level during S-Parameter Measurements

Due to the nonlinear

transistor curves,

a too big AC amplitude

may become distorted.

Unsymmetrical distortions

include a DC part. This DC

part will shift the DC

operating point !

iC

vBEAgilent Technologies

Therefore, it is very important to check the signal integrity when performing VNA measurements on

non-linear components like transistors.

This can be done as follows: the VNA is calibrated for a very low signal power, e.g. 30..-40 dBm. An

S-parameter measurement is performed and the result is considered as being linear. After that, the RF

signal power is increased, a new calibration is performed and the new measurement checked against the

previous one. When a deviation of the curves occurs, the applied signal power is too high. This allows

to identify the max. applicable RF signal power for a specific transistor.

Another method, applicable to MOS and also bipolar transistors, is to measure the DC output

characteristic and to convert it into an Rout plot, see the next slide. The measurement is performed

using the AC/DC bias TEE coupler. With the first measurement, the VNA is switched off, and the

measurement result is regarded as non-distorted Rout curves. After that, the DC traces are re-measured,

and the signal power of the VNA is increased manually, until a distortion on Rout becomes visible.

This is, again, the max. applicable RF power level.


15/34


RF power ok.

too much RF power

Rout /k


In the next slide, a method to check the correct RF signal power is introduced for bipolar transistors. A

flat trace of fT vs. iC for low iC might indicate the RF rectification effect, and thus again a too big

value of the RF signal power.


log (fT)

log (iC)

vCEfT = ---------------2*PI*TFF

1


Finally, it must be mentioned that network analyzers offer best resolution for devices with impedances

'around' Z0. Like depicted with the following slide, it is difficult to resolve the impedance for values

greater than ~1kwith a Smith chart. However, since there are always inductors or capacitors

associated with such impedances, their frequency dependence helps in modeling considerably. This is

because these parasitic components will short the high impedances for higher frequencies. The S-

parameter traces of both, the high impedance starting and the parasitics, will come closer to the center

of the Smith chart. Since modeling means curve fitting, these starting points are covered automatically.

As an example, see the RG modeling of MOS transistors further below.


16/34

Transistors and Network Analyzers:

Obtainable Resolution Big Impedances

Resolution

is criticalfor resistances

>1k


Last not least, the next two slides give suggestions for the pad layout for measuring S-parameters.

Probe Types and Transistor Pad Layout for DC to RF

DC probes

S

G D

B

S

B

Ground-Signal-Ground

Probes

S

G D

BB

S

Source and Bulk are

shorted by the probes!

pitch

All 4 terminals can be

biased independently

DC S-parameter


Biasing the Bulk separately,

using G-S probes

B

G D

SS

S

Port1 Port2

to Bulk DC power supply


Publications:

Cascade Microtech Application Note: Layout Rules for GHz Probing, 1992,Publication LAYOUT19


17/34

Special Aspects of VNA Calibration

Generalized Block Diagram

of a Vector Network Analyzer (VNA)

INCIDENT (R)

REFLECTED

(A) TRANSMITTED(B)

RECEIVER / DOWNCONVERTER

PROCESSOR / DISPLAY

SOURCE

Incident

Reflected

Transmitted

DUT

small band IF (!)


Publications:

Agilent Technologies Application Notes

1287-1: Understanding the Fundamental Principles of Vector Network Analyzers,

Pub.No. 5965-7710E, 1997

1287-2: Exploring the Architectures of Network Analyzers,

Pub.No 5965-7708E, 1997

1287-4: Network Analyzer Measurements: Filter and Amplifier Examples,

Pub.No5965-7710E, 1997

Hewlett-Packard 1997 Back to Basics Seminar, D.Ballo, Network Analyzer Basics,

Pub.No. 5965-7917E

Cascade Microtech Application Note: On Wafer Vector Network Analyzer Calibration and

Measurements, 1997, Pub No. PYRPROBE-0597---------------------------------------------------------------------------------------------------------


18/34

As can be seen in the next slide, there are 6 error terms in forward direction:

Directivity: cross-talk of the power coupler

Crosstalk: cross-talk inside the S-parameter test set, overlying the DUT

Source Mismatch: multiple reflections due to non-Z0 input and output

impedance of the DUT

Load Mismatch: the same for the opposite portReflection Tracking A/R: frequency dependence of signal path source ->R->A

Transmission Tracking A/R: same for signal path source ->R->B

For the reverse calibration, another 6 error terms add up to a total of 12 terms.

directivity~

AC

source

power

splitter

DUT

R

power

coupler

BAreference

crosstalk

source

missmatch

load

mismatch

frequency response:

reflection tracking (A/R)

transmission tracking (B/R)

H(f)

f

.

Basic Components of a VNA

and Corresponding Error Terms

6 error terms to be corrected for each port,i.e. 12 error terms for both portsAgilent Technologies

It should be noted that VNA calibration means error correction for vectors, because the measured

signals represent magnitude and phase of voltages in a Z0 environment.


19/34

S-Parameter Error Correction

means Vector Error Correction

accounts for all major sources of systematic error

Sxy Measured

error vectors

Sxy Device

SxyC

orrection


The next slides shows the standards for a SHORT-OPEN-LOAD-THRU VNA calibration.

SOLT Calibration Standardsfor Ground-Signal-Ground probes (G_S_G)

OPEN

SHORT

50 LOAD

THRU

Probes in the air

calibration

All standard calkit data must be accurately entered into the VNA.


Some notes about these calibration standards:


20/34

While in the case of the LCRZ meter for the characterization of the space charge capacitors, the

calibration corrects for a single ideal offset capacitor, a NWA calibration uses cal standards(OPEN,

SHORT, LOAD, THRU etc.) from a cal kit. These cal standards do notrepresent ideal standards. It

means that a SHORT is not an ideal SHORT, but instead represents rather an inductance. The same

applies to the THRU, which has a non-ideal delay time. The OPEN corresponds rather to a capacitor

than to an ideal OPEN. Therefore, these non-idealities have to be entered into the NWA beforecalibration. This is called 'modifying the cal kit'. After that, the calibrationis performed and the

correction terms (which include the 12 error contributions from above and also those of the cal kit

components) are stored in the cal setof the NWA. Afterwards, when the measurementis performed,

the raw measured dataarrays will be corrected using a correction technique related to the selected

calibration method, and referring to the specific cal set. Finally, this corrected measurement result is

displayed on the NWA monitor.

Therefore, after the calibration, a re-measurement of the OPEN will not represent an ideal open, but

instead exactly those parasitic components as described in the documentation of the OPEN. In the same

way, a THROUGH shows up after calibration with its real delay time, and a SHORT represents its

inductive behavior!

Verifying NWA Calibration

Since the NWA calibration has to be performed always very carefully, it is of particular interest to

verify the quality of the applied calibration. This can be done easily, when using a modeling tool like

IC-CAP. After a re-measurement of a calibration standard, we define a test circuit representing exactly

the non-idealities of the standard. Calling a simulator, we can simulate the expected behavior of e.g. the

OPEN probes. If the calibration was executed correctly, there is an excellent match between measured

and simulated curves. This check is performed with all four SOLT calibration standards.

Note: This procedure can also be applied to check the quality of an elder calibration.

Verifying the Calibration

THRU

E.g.

1psec

OPEN SHORT LOAD

E.g. -

9fF

E.g. 50W

E.g.2.4pH

re-measuring each standard after calibration

should be identical to the simulation results

of the standard, based on the calkit data

The very best cal verification is, however,

to measure an accurately known golden device



21/34

De-embedding and Required Test Structures

When characterizing a device separately, test pads have to be added in order to be able to measure it.

This means that parasitic components due to the test structure degrade the performance of the 'inner'DUT. If it is possible to measure those parasitics separately, without the 'inner' DUT, they can be

'subtracted' from the total measurement.

Why De-embedding ?

/Hz

/VAgilent Technologies

In the case of a MOS transistor, we have the following situation:

Measurement and De-embedding

Source + Bulk

Source + Bulk

Reference

plane of

VNA port2

/Hz

Ground

Ground

Signal

Ground

Ground

Signal

Ground

Ground

Signal

Ground

Ground

SignalGate Drain

Reference

plane of

VNA port1

Reference

planes of

DUTAgilent Technologies


22/34

And in the simplest case, where only capacitances of the test pads are just in parallel with the DUT, we

have the following situation:

In the simplest case ...

YDUT = YTotal YOPEN-


This means, a simple subtraction of the Y matrices gives the performance of the inner DUT.

For higher frequencies, typically above 10GHz for Silicon, more test pad parasitics begin to play a role.

This means that not only the parallel parasitics need to be subtracted (Y matrix), but also those in series

with the inner DUT (Z matrix subtraction). In this case we not only need an OPEN dummy test

structure, but also a SHORT, where the DUT is replaced by a metal 1 short.

Note that before subtracting the Z matrix of the SHORT, the SHORT dummy has to be de-embedded

firstfrom the OPEN dummy!

The De-embedding Procedure

For OPEN And SHORT De-embedding

DUT

subtract the Y matrix

of the parallel parasitics

subtract the Z matrix

of the series parasitics

DUT

DUT

The SHORT has to be

de-embedded from the OPEN first!



23/34

For this commonly used method, it is an absolute prerequisitethat there are no series components

hidden in the OPEN dummy measurement, and no parallel componentsin the SHORT dummy

measurement. If such hidden components are present, the simple matrix subtractions will lead to a

wrong de-embedding.

Like with the calibration before, it is very important to verify the de-embedding quality, beforeapplying it finally to the inner DUT. This can be done easily if there is also a THRU dummy structure

available.

Provided the THRU has been de-embedded correctly, it can be modeled with a simple delay. If this is

the case and the delay time and characteristic impedance represent physical parameter values, it can be

assumed that the de-embedding is correct.

measured

deembedded

TD(trace)

De-embedding Verification

with a THRU Dummy

Z0(trace)

deembedded

measured

Sxx

Sxy

Z0, TD

equiv.schematic:

(de-embedded from

the OPEN and the SHORT)


Last not least, for this chapter on de-embedding, how does a bad de-embedding look like?

Basically, de-embedding shows up like a 'turning-back' of the non-de-embedded curves.

As can be seen on the next slide, over-de-embedding appears as non-physical curves for higher

frequencies, i.e.:curves no longer turn clock-wise

Sxx traces tend out of the Smith chart

the inner device cannot be modeled with physical model parameters


24/34


25/34

After a good and verified calibration, as well as an correct de-embedding, let's now look into

RF Modeling Examples

We will look at three RF modeling examples:

S-parameter modeling for a MOS transistor based on the BSIM3v3 model

small-signal S-parameter modeling for transistors

modeling of passive components, example: spiral inductor

Port1

S-parameter Modeling

Example: MOS TransistorPort2

Example: BSIM3v3

Cgs_ext

Cgd_ext

Djdb_areaDjdb_perim

Djdb_area

Djdb_perim

Rsub1 .. Rsub3


In this case, because the UCB BSIM3v3 model currently does not include a Gate resistor, and further

needs some enhancements regarding the space charge modeling and the bulk resistor characteristics,

the Berkeley BSIM3v3 model is imbedded into a sub-circuit covering the missing modeling features. In

the case of the space charge capacitors, the BSIM3v3 capacitors are switched off (capacity value set

to '0'), and replaced by extra diodes which allow better access to the RF diode parameters.


26/34

BSIM3v3 S-Parameter Modeling Result

S11 S22


As mentioned at the very beginning of this tutorial, the silicon modeling can also apply methods used

much for the GaAs modeling. In the case of an RF power transistor with a fixed operating point, it

might be an overkill to model that transistor for all DC bias conditions. A fixed operating point model

might be sufficient, possibly extended to features more relevant for that application like RF power

dependence etc.

The next slide gives an idea on what to do.

TAU)

Operating Point RF Modeling for Transistors

Ygd = -Y12

Ygs = Y11 + Y12

Yds = Y22 + Y12

Ygm = Y21 - Y12 = gm * exp(-j

Ygs

Ygd

YdsYgm

Solved for the admittances:

+

+=

YgdYdsYgdYgm

YgdYgdYgs

22Y21Y

12Y11Y



27/34

For this application, a new method has been developed in order to determine the schematic of the

components Ygs, Ygd and Yds. As can be seen on the next slide, the inverse of each of those

admittances are calculated. The now available complex impedance is plotted as a locus on the real-

imaginary impedance plane. From that domain, the accurate inner schematic of each of the Ygs, Ygd

and Yds components can be developed easily. In other words, this method delivers both, the structure

of the sub-circuits and the parameter values.

Modeling the Impedances

12Y11Y

1gsZ

+=

Rgs

Cgs

freq

complex impedance plane

Operating Point RF Modeling for Transistors (contd)


The same method of developing both, the schematic and the schematic component parameter values,

can also be applied to passive components. Since these components are often very much depending on

technology, the presented method offers an accurate way for modeling. Even overlays of TEE and PI

structures can be taken into account for an accurate modeling of e.g. spiral inductors, varactor diodes

etc.


28/34

Spiral Inductor Modeling

L = 1. 5n

R L = 1 0. 9

R = 1.6k

C = 25f

L = 1.3n

R L = 7.2

R = 600

C = 35f

C = 255f

RC = 600

C = 15f

Qmeasured

simulated


Finally, like with the calibration and the de-embedding before, and now also for the device itself, a

verification of the modeling result is a must. In the case of transistors, RF characteristics can be used to

do this. Here, we can calculate for both, the measured and simulated S-parameters, the stability factor

K which refers to all four S-parameters and then calculate the maximum available gain MAG. If,

besides a good fit for the Sxx and Sxy parameters, there is also a good fit between measured and

simulated data for MAG, the model quality is good.

= 1KK*

S

SMAG 2

12

21

Verifying the Modeling Quality

Since these

formulas includeall S-parameters,

they can be used

to check the fitting

Max Available Gain

{MAG(S21)}2


with the stability factor K

including all 4 S-parameters


29/34

Non-linear Harmonic Balance Modeling

For a proper design and a good production yield, RF modeling engineers should start thinking in terms

of how the RF designers will use their model parameters in the final circuit design. Therefore, besidesthe classical SPICE-like S-parameter modeling, also large signal RF modeling (harmonic balance)

including checking the non-linear signal behavior in the time domain comes into play.

Beyond S-Parameters ...

s11

RF R A B

85046AS-PARAMETERTESTSET

DUT

cvCVDUT12.05pF

in out

transmit in outtransmit

DCDUT

DC input, transfer, output

CV curves, w/o TF, Ls etc

S-par, linear (no harmonics),

op.pt. dependent, imbedded in Z0

Nonlinear frequency analysis, harmonics, etc...

Time domain


For this type of modeling, simulators such as ADS including harmonic balance features are required to

characterize the non-linear RF performance of devices and circuits, depending on operating point and

RF signal level.


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What is Harmonic Balance (HB) Simulation ?

IIRRIICC IILL IIDD

Error is notError is not

zero !!!zero !!!

Iterate again.Iterate again.

Test (Kirchoffs law):Test (Kirchoffs law):

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Start in theStart in the

Frequency DomainFrequency Domain Convert: ts -> fsConvert: ts -> fsCalculate currentsCalculate currents

With inWi th in

tolerancetolerance

Last Estim ateLast Estim ate

wi th least err orwi th least err or

IIRR IICC IILL IIDD

spectrum of harmonics available for all nodes/branches in the circuit


Harmonic balance (HB) is a frequency-domain simulation technique. Signals are treated as

summations of finite numbers of sine waves, i.e. as periodic signals. This approach is valid for most

signals that might be analyzed using a network analyzer or a spectrum analyzer. It is well suited to

stimulus-response and swept-parameter simulations. Harmonic balance simulations use one or two

sine-wave stimuli to determine (for example) conversion loss vs. drive level, distortion vs. frequency,and gain compression. Harmonic balance is also well suited to analyzing high-Q, reverberant, and

frequency conversion circuits.

Harmonic Balance and Time-Domain Simulation

Harmonic balance calculates voltages and currents in much the same way as time-domain simulators

such as SPICE do. But harmonic balance must solve for the magnitudes and phases of all spectral lines

simultaneously. In effect, the entire waveform is being solved for at once. Harmonic balance is

extremely efficient if the signals are simple in the frequency domain-as they are, for example, when an

amplifier is driven by a sine wave.

Circuits that have non-repeating transient behavior are best analyzed using a time-domain (transient)

simulator which, in contrary to SPICE, also includes accurate RF models. In general, harmonic balance

is not very useful for analyzing signals that might be analyzed using an arbitrary waveform generator or

a wide- bandwidth oscilloscope. Therefore, it is best to use a tool which offers a wide range of RF

simulation techniques in a single user environment.

What happens when an harmonic balance simulation is executed?

When a harmonic balance simulation is run, the following steps occur, in this order:

1. The DC operating point of the circuit is calculated.

2. A linear AC analysis is used to analyze linear and passive components in the frequency domain.


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3. Nonlinear devices (only) are analyzed in the time domain. The Fourier transform is then used to

include these results in the analysis.

4. The estimated voltage spectrum is refined until Kirchhoff's current and voltage laws (KCL and

KVL) are both satisfied for the circuit. Iterative, matrix-driven techniques are used.

5. The solution is a voltage spectrum which is the same at all nodes in the circuit. The mathematical

analysis has converged. The harmonics are now balanced.

In general, all S-parameters vary as a function of input power. For transistors, usually up to 30dBm,

they can nevertheless be considered as linear, without harmonics. However, keep in mind that when the

RF signal power increases, also harmonic frequencies show up. In this case, we can no longer talk of

(linear) S-parameters.

freq freq

DC bias DC bias

signalpower

Publications:

HP-EEsof symposium Advanced Techniques for Communication Signal Path Design, 1997, available

from Agilent-EEsof.

With respect to todays digital modulation schemes in communications systems, the operating

conditions of transistors cannot be considered as linear any more. We have to consider the magnitude

and phase of the DC bias, the base frequency and the harmonics.

For simulations, harmonic balance type simulators come into play, as said above. Regarding

measurements, non-linear network analyzers must be consider, which allow to measure the magnitude

and phase of the base frequencyplusall harmonics.

Let's now look at two examples of what can be modeled when using such measurement systems and RFsimulators.


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Example: HB Modeling of a Transistor

Pin -20dBm -10dBm

Pin -10dBm

Pin -20dBm


In the example above, the input RF signal is swept for fixed DC operating points, and the harmonics

are analyzed as a function of the input RF power. This gives the compression plot vs. RF input power

for the base frequency and the harmonics (level-wise below) as given to the left. From these signal

levels, corresponding sine functions can be derived (magnitude and phase) and the real-world, time-

domain signal can be calculated (plots to the right). This finally allows the modeling engineer to check

the performance of its models with respect to its application in the real-world design, and not only for

the case where the component is inserted in a fixed Z0 impedance environment, and linear operating

conditions.

Since in real-world, for maximum power transmission, impedance matching has to be applied to the

device input and output, another harmonic balance simulation result is given below for the dynamic

loadline. In case of impedance matching, and no longer Z0=50matching like for the linear S-

parameter measurements in the previous chapter, current and voltage at each port can be out of phase,

and the static (DC) loadline of a transistor can change.

This is given in the slide below: For low frequencies, the output current can follow the output voltageswing, and we measure the well-known DC loadline. For high frequencies, in the GHz range, this is no

longer the case. Besides the mentioned impedance matching, also the non-quasistatic transistor

behavior shows up, delaying the amplified signal further, and the previous straight DC loadline

degrades to an ellipse or a similar distortion. Check also the dot, indicating the operating point bias for

the AC analysis.


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Example: HB Dynamic Loadline Modeling

DC output characteristic

static loadline

dynamic loadline

operating point AC


Note:

for non-linear S-parameter measurements, a specific non-linear vector network analyzer system

(NNWA) has to be applied.

Publications on NNWAs:

Marc Vanden Bossche, Agilent Technologies NMDG, 'Accurate and Traceable High Frequency Large

Signal Measurements of TwoPorts', European Microwave Conference, Oct. 4-8, 1999, Munich


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Summary


>> For successfull RF MOS designs with high yield,accurate device models for all circuit components

are a must.

>> Basic understanding of S-parameters is essential

for modeling

>> Verification of all RF modeling steps is a must

>> Modeling engineers need to understand the

application conditions for their components

rf measurements & modeling

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