rh850/f1x,r1x 100-pin piggyback board v3...rh850/f1x 100-pin rh850/r1x 100-pin user’s manual:...

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All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (https://www.renesas.com)

RH850 Evaluation Platform

RH850/F1x 100-pin RH850/R1x 100-pin

User’s Manual: Piggyback Board V3 Y-RH850-F1X-100PIN-PB-T1-V3

Rev. 1.03 September 2020

32

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l The latest version of this document can be obtained from the following web location: Y-RH850-F1X-100PIN-PB-T1-V3 Documents

https://www.renesas.com/

http://www.renesas.eu/updates?oc=Y-RH850-F1X-100PIN-PB-T1-V3#documentInfo

http://www.renesas.eu/updates?oc=Y-RH850-F1X-100PIN-PB-T1-V3#documentInfo

1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products Before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ⎯ The characteristics of Microprocessing unit or Microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

Table of Contents

Chapter 1 Introduction ....................................................................... 5

1.1 Package Components .......................................................................... 6

Chapter 2 Overview ............................................................................ 7

2.1 Board EESS-0401-139-01 ..................................................................... 7

2.2 Board D015312-06-V02 ......................................................................... 8

2.3 Mounting of the Device ........................................................................ 8

Chapter 3 Jumper Configuration ....................................................... 9

Chapter 4 Power Supply ................................................................... 11

4.1 Board Power Connection ................................................................... 11

4.2 Voltage Distribution ........................................................................... 12

Chapter 5 Clock Sources ................................................................. 13

Chapter 6 Debug and Programming Interface ................................ 14

Chapter 7 Connectors for Device Ports .......................................... 15

7.1 Connectors to Main Board ................................................................. 15

Connector CN1 ............................................................................................................ 15

Connector CN2 (EESS0401-139-01) .......................................................................... 16

Connector CN2 (D015312-06-V02) ............................................................................. 18

Connector CN3 ............................................................................................................ 19

7.2 Connectors for User Access ............................................................. 21

Chapter 8 Other Circuitry ................................................................. 22

8.1 Push Button for RESET ..................................................................... 22

8.2 Mode Selection ................................................................................... 22

8.3 Signalling LEDs .................................................................................. 22

Chapter 9 Precautions ...................................................................... 23

9.1 Usage of LIN15 .................................................................................... 23

Adjustments on RH850/X1x Network Main Board ................................................... 23

Adjustments on RH850/X2x Main Board .................................................................. 24

Chapter 10 Mechanical dimensions .................................................. 25

Chapter 11 Schematic of PCB marked “EESS-0401-139-01” ........... 26

Chapter 12 Schematic of PCB marked “D015312-06-V02” .............. 29

Chapter 13 Revision History .............................................................. 32

RH850/F1x, R1x 100pin

RENESAS MCU

R20UT3959ED0103 Rev.1.03 of 35 September 09, 2020

R20UT3959ED0103

Rev.1.03

September 09, 2020

Introduction

The RH850/F1x Application Board is part of the RH850 Evaluation Platform and serves as a simple and easy to use platform for evaluating the features and performance of Renesas Electronics 32-bit RH850/F1x microcontrollers. The piggyback board (Y-RH850-F1X-100PIN-PB-T1-V3) can be used as a standalone board or it can be connected to a main board (Y-RH850-X1X-MB-Tx-Vx) for extended functionality.

Main features:

• Socket for mounting of device

• Standalone operation of the board

• Direct supply of device voltage (typ. 3.3V-5.0V)

• Device programming capability

• Device debugging capability

• Pin headers for direct access to each device pin

• Reset switch

• MainOSC circuitry

• Signal LEDs

• Jumpers for device mode selection

• Connectors to a main board

This document describes the functionality provided by the piggyback board and guides the user through its operation.

For details regarding the operation of the microcontroller, refer to the refer to the related User’s Manual and Datasheet.

This manual describes the following board revisions:

• RH850-F1X-100PIN-PB-T1-V3 Gen 1 (marked “EESS-0401-139-01”)

• RH850-F1X-100PIN-PB-T1-V3 Gen 2 (marked “D015312-06-V02”)

For differences to the RH850-F1X-100PIN-PB-T1-V2 see the Revision History.

RH850/F1x, R1x 100pin Chapter 1 Introduction


1.1 Package Components

The Y-RH850-F1X-100PIN-PB-T1-V3 product package consists of the items included in below table. After you have unpacked the box, check if your Y-RH850-F1X-100PIN-PB-T1-V3 package contains all these items.

Item Description Quantity

D015312 RH850/F1x 100pin piggyback board

1

Dxxxxxx Documentation CD 1

D010816-24 China RoHS document 1

Dxxxxxx Product contents List 1

Jumpers (2-way, 0.1”) In the bag 29

Red Hirschmann 4 mm power lab sockets

In the bag 2

Black Hirschmann 4 mm power lab sockets

In the bag 1

Crystals, HC49 (8MHz, 16MHz, 20MHz, 24MHz)

In the bag 3

Note: Please keep the Y-RH850-F1X-100PIN-PB-T1-V3 packing box at hand for later reuse in sending the product for repairs or for other purposes. Always use the original packing box when transporting the Y-RH850-F1X-100PIN-PB-T1-V3. If packing of your product is not complete, it may be damaged during transportation.

RH850/F1x, R1x 100pin Chapter 2 Overview


pin #1

Overview

There are 2 different production versions of the piggyback board.

Boards of the first generation have the marking “EESS-0401-139-01”. The boards have an issue in the connection of pin 34 and pin 36 on connector CN2. This is described in Chapter 9 Precautions.

Boards of the second generation have the marking “D015312-06-V02”. With these boards the connection on CN2 has been corrected and the precautions described in chapter 9 do NOT apply.

2.1 Board EESS-0401-139-01

Figures 1 and 2 provide the views of the RH850-F1X-100PIN-PB-T1-V3 Piggyback Board.

Figure 1 - RH850-F1X-100PIN-PB-T1-V3 top view

Figure 2 - RH850-F1X-100PIN-PB-T1-V3 bottom view

Device Pin 1

RH850/F1x, R1x 100pin Chapter 2 Overview


2.2 Board D015312-06-V02

Figure 3 - RH850-F1X-100PIN-PB-T1-V3 top view

Figure 4 - RH850-F1X-100PIN-PB-T1-V3 bottom view

2.3 Mounting of the Device

The board is designed for use with the following devices, all in 100pin package:

• RH850/F1L

• RH850/R1L

• RH850/F1K

• RH850/F1KM-S1

• RH850/F1KM-S4

The device must be placed inside the socket IC1. To insert the device, press down the lid, align the #1 pin of the device to the #1pin of the socket, insert the device inside the socket and release the lid.

Device pin #1

Device Pin 1

RH850/F1x, R1x 100pin Chapter 3 Jumper Configuration


Jumper Configuration

The function of the board can be configured via jumpers. This chapter describes the standard configuration, i.e. jumper setting for the intended devices. For the supported function of the used device, please refer to the corresponding HW user’s manual.

Jumper settings are valid for both generations of Y-RH850-F1X-100PIN-PB-T1-V3, even if the picture in Figure 5 - Example for jumper settings shows the generation 1 board.

The table has the following meaning:

• x-y: Connect the pins x and y; valid for 3-pin jumpers (e.g. JP14)

Pin #1 can be identified by a small circle in the vicinity of the jumper.

Depending on the used device a configuration of several jumpers is required. The detailed configuration is shown below:

Jumper F1L R1L F1K F1KM

-S1 F1KM

-S4 Function

JP3 1-2 1-2 1-2 1-2 2-3 Selection pin #4: Either P10_15 or ISOVCL

JP5 1-2 1-2 1-2 1-2 2-3 Selection pin #5: Either P11_0 or VSS


JP8 1-2 1-2 1-2 1-2 2-3 Selection pin #43: Either P8_1 or ISOVCL


JP13 1-2 1-2 1-2 1-2 2-3 Selection pin #75: Either P9_6 or REGVCC

JP14 [1-2] Close - Either Close - Selection of PWM34

JP14 [2-3] - - - or - Close Either from P9_5 or P0_11

JP15 [1-2] Close - Either Close - Selection of PWM35

JP15 [2-3] - - - or - Close Either from P9_6 or P0_6

The jumper settings also are shown in the picture on the next page.

RH850/F1x, R1x 100pin Chapter 3 Jumper Configuration


Figure 5 - Example for jumper settings

• The green jumper JP25 for FLMDO0 always must be closed (at the position 2-3) for a ‘normal’ (user mode and debug) operation of the device.

• The red jumpers must be set for a single “Voltage 1” (typ +5.0V) operation of the device.

• The blue jumper must be set for a single “Voltage 2” (typ +3.3V) operation of the device.

• The orange jumpers must be selected depending on the used device. See the printing on the board for the applicable setting.

For jumper settings related to the device operation mode, refer to chapter 8.2 Mode Selection

RH850/F1x, R1x 100pin Chapter 4 Power Supply


Power Supply

4.1 Board Power Connection

For operation of the device, a supply voltage must be connected to the board. Though a single supply voltage is sufficient to operate the device, it is possible to power the board with two different voltages.

Within this document the following voltages are considered as ‘typical’ connections:

Voltage1 = 5.0V

Voltage2 = 3.3V

The following connectors are available to supply those voltages:

• Three 4mm ‘banana-type’ connectors: - Two red connectors for voltages Voltage1 (CN10) and Voltage2 (CN11) - A black connector for VSS connection on CN12 Note: The three connectors are supplied with the board but are not assembled.

• The E2 emulator, that is used for debugging or flash programming, can also supply a single operating voltage (“DBG_Voltage”). The voltage is programmable via the E2 configuration as 3.3 or 5.0V (typ). See the documentation of E2 and Chapter 5 Clock Sources for details.

• In case the piggyback board is mounted on a main board, the voltages Voltage1 and Voltage2 are supplied by the on-board regulators of the main board.

NOTE: Do not supply any voltage directly to the piggyback board in case it is mounted on the main board.

For each of the two voltages, ‘Voltage 1 ‘ and ‘Voltage 2’, a green LED (LED1 and LED2) is available to signal that the related voltage is available on the piggyback board.

RH850/F1x, R1x 100pin Chapter 4 Power Supply


4.2 Voltage Distribution

The table shows the required device power supply pins and their function:

Device supply pin

Function

REGVCC Supply for the device internal regulators for the digital logic.

EVCC Supply for ports of AWO area.

A0VREF Supply for ports and analog functions of ADC0.

VDDIOF IO supply voltage for components located on a connected mainboard.

For each of the above voltages, the power supply can be selected from Voltage1 (typ. 5.0V) or Voltage2 (typ. 3.3V) by the jumpers JP0, JP1, JP2, JP4, JP9 and JP6. See the picture below for details.

REGVCC

VOLTAGE1

VOLTAGE2

VCCIOFEVCC

A0VREF

JP0

JP1

JP2

JP4

JP9

JP6

Figure 6 - Jumper settings to select supply voltage

RH850/F1x, R1x 100pin Chapter 5 Clock Sources


Clock Sources

For mounting of the external crystal oscillator, a socket is available.

A crystal or ceramic resonator in the range of 8MHz to 24MHz can be mounted on socket X1.

The package with generation 1 of Y-RH850-F1X-100PIN-PB-T1-V3 included 2 crystals of 8MHz and 16MHz.

The package with generation 2 of Y-RH850-F1X-100PIN-PB-T1-V3 includes 4 crystals with 8MHz, 16Mhz, 20MHz and 24MHz.

RH850/F1x, R1x 100pin Chapter 6 Debug and Programming Interface


Debug and Programming Interface

Connector 19 is provided as interface for debug and flash programming tools to the microcontroller.

The signal connection of connector CN19 is shown in the table below:

CN19 Device Port Device signal

1 JP0_2 DCUTCK / LPDCLK

2 GND GND

3 JP0_4 DCUTRST

4 FLMD0 FLMD0

5 JP0_1 DCUTDO / LPDO

6 P10_8* FLMD1

7 JP0_0 DCUTDI / LPDI

8 DBG_Voltage -

9 JP0_3 DCUTMS

10 - -

11 JP0_5 DCURDY / LPDCLKOUT

12 GND -

13 RESET -

14 GND -

* In case the FLMD1 signal must be controlled by the debug/programming tool, the pin header JP11 must be closed.

The DBG_Voltage (on CN19 pin 8) can be monitored by debug and flash programming tools. It is possible to select either Voltage1 or the Voltage2 by pin header JP10 for this monitoring:

JP10 Selection for DBG_Voltage

1-2 Voltage1 (5.0V) is selected

2-3 Voltage2 (3.3V) is selected

RH850/F1x, R1x 100pin Chapter 7 Connectors for Device Ports


Connectors for Device Ports

The piggyback board has 2 groups of connectors.

One group (CN1-CN3) provides the connection of the device pins to a main board.

The second group (CN5-CN8) provides access to each device pin to the user.

7.1 Connectors to Main Board

Three connectors (CN1 to CN3) are available to connect the piggyback board to a main board.

The signal connection of each connector is described in the following tables:

Connector CN1

Pin Function Device Port Pin Function Device Port

1 VOLTAGE1 - 2 VOLTAGE1 -


5 RESET _RESET 6 NMI P9_0

7 WAKE - 8 - -

9 INT0 P9_1 10 INT1 P0_6

11 INT2 P9_2 12 INT3 P9_3

13 - - 14 - -

15 UART0TX P10_10 16 UART1TX P0_5

17 UART0RX P10_9 18 UART1RX P0_4

19 LIN0TX P10_10 20 LIN1TX P0_8

21 LIN0RX P10_9 22 LIN1RX P0_7

23 IIC0SDL P10_3 24 IIC1SDL -

25 IIC0SDA P10_2 26 IIC1SDA -

27 CAN0TX P10_1 28 CAN1TX P0_3

29 CAN0RX P10_0 30 CAN1RX P0_2

31 SENTIN0 P8_0 32 SENTIN1 P9_0

33 SENTOUT0 P8_1 34 SENTOUT1 P9_1

35 PSI50Rx - 36 PSI51Rx -

37 PSI50Tx - 38 PSI51Tx -

39 PSI50Snyc - 40 PSI51Sync -

41 FLX0TX P11_1 42 FLX0EN P10_11

43 FLX0RX P10_14 44 FLXSTPWT

P10_12

45 FLX1TX P10_8 46 FX1EN P10_13

47 FLX1RX P10_9 48 FLXCLK

P10_10 49 - - 50 - -

51 ETH0MDIO - 52 ETH0MDC -

53 ETH0RXD0 - 54 EH0TXD0 -




61 ETH0RXDCLK - 62 ETH0TXCLK -




63 ETH0RXER - 64 ETH0TXER -

65 ETH0CRSDV - 66 ETH0TXEN -

67 ETH0RXDV - 68 ETH0COL -

69 ETH0RESET - 70 - -

71 - - 72 - -

73 USB0UDMF - 74 USB0UDMH -

75 USB0UDPF - 76 USB0UDPH -

77 - - 78 - -

79 - - 80 - -

81 - - 82 - -

83 - - 84 - -

85 DIGIO_0 P8_0 86 DIGIO_1 P8_1

87 DIGIO_2 P8_2 88 DIGIO_3 P8_3

89 DIGIO_4 P8_4 90 DIGIO_5 P8_5

91 DIGIO_6 P8_6 92 DIGIO_7 P11_0

93 DIGIO_8 P10_0 94 DIGIO_9 P10_7

95 DIGIO_10 P10_8 96 DIGIO_11 P10_15

97 DIGIO_12 P0_9 98 DIGIO_13 P0_10

99 DIGIO_14 P0_11 100 DIGIO_15 P0_12

101 - - 102 - -

103 MUX0 P10_4 104 MUX1 P10_5

105 MUX2 P10_6 106 - -

107 ADC0 AP0_0 108 ADC1 AP0_1

109 ADC2 AP0_2 110 ADC3 AP0_3

111 ADC4 AP0_4 112 ADC5 AP0_5

113 ADC6 AP0_6 114 ADC7 AP0_7

115 VDDIOF - 116 VDDIOF -



Connector CN2 (EESS0401-139-01)


1 CAN2Tx P0_4 2 CAN3Tx P11_4

3 CAN2Rx P0_5 4 CAN3Rx P11_3



9 LIN2Tx P0_10 10 LIN3Tx -

11 LIN2Rx P0_9 12 LIN3Rx -



17 LIN6Tx - 18 LIN7Tx -

Q LIN6Rx - 20 LIN7Rx -


23 LIN8Rx - 24 LIN9Rx -




25 LIN10Tx P10_10 26 LIN11Tx P0_5

27 LIN10Rx P10_9 28 LIN11Rx P0_4

29 LIN12Tx P10_14 30 LIN13Tx P11_5

31 LIN12Rx P10_13 32 LIN13Rx P11_6

33 LIN14Tx - 34 LIN15Rx P10_11

35 LIN14Rx - 36 LIN15Tx P10_12

37 - - 38 - -

39 - - 40 - -

41 MLBCLK - 42 MLBRESET -

43 MLBSIG - 44 MLBDAT -

45 - - 46 - -

47 CAN6Tx P10_4 48 CAN7Tx P10_13

49 CAN6Rx P10_5 50 CAN7Rx P10_14

51 - - 52 - -

53 - - 54 - -

55 - - 56 - -

57 - - 58 - -

59 - - 60 - -

61 - - 62 - -

63 - - 64 - -

65 - - 66 - -

67 - - 68 - -

69 - - 70 - -

71 - - 72 - -

73 - - 74 - -

75 - - 76 - -

77 - - 78 - -

79 - - 80 - -

81 - - 82 - -

83 - - 84 - -

85 - - 86 - -

87 - - 88 - -

89 - - 90 - -

91 - - 92 - -

93 - - 94 - -

95 - - 96 - -

97 - - 98 - -

99 - - 100 - -

101 - - 102 - -

103 - - 104 - -

105 - - 106 - -

107 - - 108 - -

109 - - 110 - -

111 - - 112 - -




113 - - 114 - -

115 - - 116 - -

117 - - 118 - -

119 - - 120 - -

Connector CN2 (D015312-06-V02)











Q LIN6Rx - 20 LIN7Rx -


23 LIN8Rx - 24 LIN9Rx -

25 LIN10Tx P10_10 26 LIN11Tx P0_5

27 LIN10Rx P10_9 28 LIN11Rx P0_4

29 LIN12Tx P10_14 30 LIN13Tx P11_5

31 LIN12Rx P10_13 32 LIN13Rx P11_6

33 LIN14Tx - 34 LIN15Rx P10_12

35 LIN14Rx - 36 LIN15Tx P10_11

37 - - 38 - -

39 - - 40 - -

41 MLBCLK - 42 MLBRESET -

43 MLBSIG - 44 MLBDAT -

45 - - 46 - -

47 CAN6Tx P10_4 48 CAN7Tx P10_13

49 CAN6Rx P10_5 50 CAN7Rx P10_14

51 - - 52 - -

53 - - 54 - -

55 - - 56 - -

57 - - 58 - -

59 - - 60 - -

61 - - 62 - -

63 - - 64 - -

65 - - 66 - -

67 - - 68 - -

69 - - 70 - -

71 - - 72 - -

73 - - 74 - -




75 - - 76 - -

77 - - 78 - -

79 - - 80 - -

81 - - 82 - -

83 - - 84 - -

85 - - 86 - -

87 - - 88 - -

89 - - 90 - -

91 - - 92 - -

93 - - 94 - -

95 - - 96 - -

97 - - 98 - -

99 - - 100 - -

101 - - 102 - -

103 - - 104 - -

105 - - 106 - -

107 - - 108 - -

109 - - 110 - -

111 - - 112 - -

113 - - 114 - -

115 - - 116 - -

117 - - 118 - -

119 - - 120 - -

Connector CN3

Pin Function Device Port


1 PWM00 P10_0 2 PWM01 P10_1

3 PWM02 P10_2 4 PWM03 P10_3

5 PWM04 P10_7 6 PWM05 P10_8

7 PWM06 P10_9 8 PWM07 P10_10

9 PWM08 P9_0 10 PWM09 P9_1

11 PWM10 P0_4 12 PWM11 P0_1

13 PWM12 P0_2 14 PWM13 P0_3

15 PWM14 P8_0 16 PWM15 P8_1

17 PWM16 P10_11 18 PWM17 P10_12

19 PWM18 P10_13 20 PWM19 P10_14

21 PWM20 P9_2 22 PWM21 P9_3

23 PWM22 P8_2 24 PWM23 P8_3

25 PWM24 P10_14 26 PWM25 P11_0

27 PWM26 P11_1 28 PWM27 P11_2

29 PWM28 P11_3 30 PWM29 P11_4

31 PWM30 P11_5 32 PWM31 P11_6

33 PWM32 P11_7 34 PWM33 P9_4





35 PWM34 P9_5 or P0_11

36 PWM35 P9_6 or

P0_6

37 PWM36 P8_4 38 PWM37 P8_5

39 PWM38 P8_6 40 PWM39 P8_7

41 PWM40 P8_8 42 PWM41 P8_9

43 PWM42 P8_10 44 PWM43 P8_11

45 PWM44 P8_12 46 PWM45 P0_12

47 PWM46 P0_13 48 PWM47 P0_14

49 PWM48 - 50 PWM49 -

51 PWM50 - 52 PWM51 -

53 PWM52 - 54 PWM53 -

55 PWM54 - 56 PWM55 -

57 PWM56 - 58 PWM57 -

59 PWM58 - 60 PWM59 -

61 PWM60 - 62 PWM61 -

63 PWM62 - 64 PWM63 -

65 PWM64 - 66 PWM65 -

67 PWM66 - 68 PWM67 -

69 PWM68 - 70 PWM69 -

71 PWM70 - 72 PWM71 -

73 PWM72 - 74 PWM73 -

75 PWM74 - 76 PWM75 -

77 PWM76 - 78 PWM77 -

79 PWM78 - 80 PWM79 -

81 PWMADC00 AP0_8 82 PWMADC01 AP0_9




89 PWMADC08 - 90 PWMADC09 -




97 - - 98 - -

99 - - 100 - -

101 - - 102 - -

103 - - 104 - -

105 - - 106 - -

107 - - 108 - -

109 - - 110 - -

111 - - 112 - -

113 - - 114 - -

115 - - 116 - -

117 - - 118 - -

119 - - 120 - -



7.2 Connectors for User Access

Connection to each pin of the device is possible via the connectors CN5 to CN8.

Note :The pin headers are directly connected to the pins of the device, therefore special care must be taken to avoid any electrostatic or other damage to the device.

Pin Device Function

CN5 CN6 CN7 CN8

1 P10_3 JP0_2 A0VSS EVCC

2 P10_4 JP0_1 A0VREF ISOVCL

3 P10_5 JP0_0 AP0_15 ISOVSS

4 P10_15 RESET AP0_14 EVSS

5 P11_0 EVCC AP0_13 P10_6

6 P0_0 AWOVSS AP0_12 P10_7

7 P0_1 AWOVCL AP0_11 P10_8

8 P0_2 REGVCC AP0_10 P10_9

9 P0_3 X2 AP0_9 P10_10

10 EVCC X1 AP0_8 P10_11

11 P0_4 FLMD0 AP0_7 P10_12

12 P0_5 P0_10 AP0_6 P10_13

13 P0_6 P0_9 AP0_5 P10_14

14 P0_11 P0_8 AP0_4 P11_1

15 P0_12 P0_7 AP0_3 P11_2

16 P0_13 EVSS AP0_2 P11_3

17 P0_14 P8_0 AP0_1 P11_4

18 EVSS P8_1 AP0_0 P11_5

19 P8_2 P8_3 P9_0 P11_6

20 P8_10 P8_4 P9_1 P11_7

21 P8_11 P8_5 P9_2 EVCC

22 P8_12 P8_6 P9_3 EVSS

23 JP0_5 P8_7 P9_4 P10_0

24 JP0_4 P8_8 P9_5 P10_1

25 JP0_3 P8_9 P9_6 P10_2

RH850/F1x, R1x 100pin Chapter 8 Other Circuitry


Other Circuitry

8.1 Push Button for RESET

In order to issue a RESET to the device, the push-button SW1 is available.

8.2 Mode Selection

The PiggyBack Board gives the possibility to configure the following mode pins

• FLMD0 via jumper JP25

• FLMD1 via jumper JP19

• MODE0 via jumper JP28



To apply “High” or “Low” to the mode pins, the pins 1 and 2, or the pins 2 and 3 (if available) of the corresponding jumper must be closed, respectively.

Note: Pin 1 of all jumpers is marked by a small circle.

CAUTION: Be careful in configuration of mode related pins. Wrong configuration and operation of the device outside of its specification can cause irregular behaviour of the device and long term damage cannot be ruled out completely. Be sure to check the corresponding User’s Manual for details, which modes are specified for the used device.

Note: In most cases the ‘Normal operating mode’ of the device will be used. This mode is for execution of the user program. The on-chip debug functions also use this mode.

To select the ‘Normal operating mode’ of the device, the FLMD0 pin must be pulled low. To do so, close the pins 2-3 on the jumper JP25:

All other jumper related to the mode selection can be left open.

8.3 Signalling LEDs

Eight LEDs are provided to allow visual observation of the output state of device port pins. Device pins P8_0 to P8_7 are connected to the odd pins 1 to 15 of the pin header CN13, while the LEDs 1 to 8 are connected to the even pins 2 to 16, respectively.

The LEDs can be either connected to

• the device port pins P8_0 to P8_7 by closing the connection on CN13 using a jumper, or

• any device port pin by using wire connections provided with the main board.

RH850/F1x, R1x 100pin Chapter 9 Precautions


Precautions

9.1 Usage of LIN15

On piggyback board V3 the LIN15 Rx/Tx signals on CN2 have been crossed.

This applies only to the pcb with the marking “EESS-0401-139-01”.

Port P10_11 is LIN15RX, but it is connected to LIN15TX.

Port P10_12 is LIN15TX, but it is connected to LIN15RX.

In order to fix this it is best to make the appropriate modifications on the RH850/X1x Network Main Board (Y-RH850-X1X-MB-T2-V1 or Y-RH850-X1X-MB-T2-V2) or on the RH850/X2x Main Board (Y-RH850-X2X-MB-T1-V1).

Adjustments on RH850/X1x Network Main Board

In order to use LIN15 on the RH850/X1x Network Main Board following modifications on the main board are needed:

1. Disconnect LIN15Tx and LIN15Rx from connector CN2 by setting switch SW26-1 and SW26-2 to “OFF”.

2. Connect LIN15Tx manually from jumper JP60-1 to connector CN2-36.

3. Connect LIN15Rx manually from jumper JP60-2 to connector CN2-34.

Please see below picture for the necessary changes.

LIN*14*

LIN*15*

2

1

3

TR15

2

1

3

TR16

6 5 4321

SW

24

D15

B9B8B7B6B5B4B3B2B1

A9A8A7A6A5A4A3A2A1

B11B10

A11A10

CN79

R125

R123

R19

41

32 6

8 57

IC18

21 JP66

R121R119

1TP16

21 JP64

R116

1TP15

R117

432

1 SW25

4321

CN63

21

JP60

432

1 SW26

D16C107

R126

C108

C106

R122

R124

R120R118

41

32 6

8 57

IC17

4321

CN62

21

JP61

C4

header 2way longjumper 2.54mm




NDS331NTR

SMD-TESTPOINT

NDS331NTR

SMD-TESTPOINT

1K0

1K0

DIP-SWITCH-2POL-SMD

HEADER4WAY

HEADER4WAY

10K

TJA1020T/TJA1021T

10K

10K

0

10K

10K

VDDIOF12.0V

VBATF

TJA1020T/TJA1021T

0

100N

161-10005823SUBD9_M_DUAL

THT

1N4148W-V

1.0N

100N

LIN14TXLIN14RX

LIN15TXLIN15RX

VBAT_LIN_14

VDDIOF_LIN_15

10K

0

DONOTFIT

VDDIOF_LIN_16

1.0N

0

DONOT FIT

DIP-SWITCH-2POL-SMD

VBATF12.0V

VDDIOF

1N4148W-V

VBAT_LIN_15

DIP

-SW

ITC

H-3

PO

L-S

MD

21

21

D

S

G

GNDBATLIN

INH

TXD

NWAKENSLPRXD

D

S

G

4321

21

IN

O U T

4321

21

IN

O U T

GND [4]

GND [3]

PINB9

PINB8

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

GND [2]

GND [1]

PINA9

PINA8

PINA7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

GNDBATLIN

INH

TXD

NWAKENSLPRXD

Open to disconnect LIN15 signal

Connect manually to CN2:

Pin1 to CN2-36

Pin2 to CN2-34

RH850/F1x, R1x 100pin Chapter 9 Precautions


Adjustments on RH850/X2x Main Board

To be able to use LIN15 with the RH850/X2x Main Board changes are very simple.

On RH850/X2x Main Board the connection of LIN15Tx and LIN15Rx to connector CN2 is by jumper JP35. This can be modified easily to accommodate the pin swap on CN2:

1. Remove the jumpers on JP35.

2. On JP35 connect JP35-1 with JP35-4 for LIN15Rx.

3. On JP35 connect JP35-2 with JP35-3 for LIN15Tx

Please see below picture for the necessary changes.

LIN*14*

LIN*15*

header 4way

header 4way

NDS331NTR

header 8way

header 8way

DO NOT FIT

0

0

DO NOT FIT

header 10way shrouded

header 10way shrouded

NDS331NTR

SMD-TESTPOINT

SMD-TESTPOINT

TJA1021T

1n

100n

1K

0

1N4148W-V

TJA1021T

100n

1K

0

1N4148W-V

1n

VCC12V0

VDDIOF VCC12V0 VDDIOF_LIN_14

VBAT_LIN_14

VBAT_LIN_15

VDDIOF VDDIOF_LIN_1512.0V

3.3V/OR 5 V 12.0V

10K

10K

10K

10K

DIP

-SW

ITC

H-3

PO

L-S

MD

10K

10K

3.3V/OR 5V

JP35

JP36

TR27

CN33

CN34

R108

R154

CN72

CN71

TR26

TP16

TP17

IC22

C88

C85

R157

D20

IC23

C86

R158

D21

C90

SW

27

R140

R147

R144

R143

R148

R139

12C5>12C5<

12C4>12C4<

LIN15TXLIN15RX

LIN_15TX

LIN14TXLIN14RX

LIN14_TX

LIN_15RX

LIN14_RX

LIN15_BAT

NCNC

NC

NCNC

LIN14_BATNC

NCNC

NCNC

LIN15

LIN14

1 23 4

1 23 4

3

1

2

1 23 45 67 8

1 23 45 67 8

123456789

10

123456789

103

1

2

1

1

758

623

1 4

758

623

1 4

6 5 4321

4321

OUT

GNDBATLIN

INH

TXD

NWAKENSLPRXD

IN

GNDBATLIN

INH

TXD

NWAKENSLPRXD

4321

87654321

87654321

D

S

G

7

9

43

5

8

6

1

10

2

7

9

43

5

8

6

1

10

2

IN

D

S

G

OUT

Cross Rx and Tx line on jum per JP35.

Connect pin 1 to pin 4 for Rx

Connect pin 3 to pin 2 for Tx

RH850/F1x, R1x 100pin Chapter 10 Mechanical dimensions


Mechanical dimensions

100,00mm

160,

00m

m

CN2

CN1

24,0

0m

m24

,00

mm

CN3

9,00

mm

CN4

9,00

mm

80,0

0m

m

50,00mm

RH850/F1x, R1x 100pin Chapter 11 Schematic of PCB marked “EESS-0401-139-01”


Schematic of PCB marked “EESS-0401-139-01”

RH

850_F1X

_100P

IN_P

B_T1_V

3

14.1

2.2

016

W.R

ause

r

W.R

ause

r02.1

2.2

016

changed R

38;R

39;R

41;R

42 to 1

k

changed R

40;R

31;R

37 to 1

k

1.0

2

1.0

1

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

RH

850/F

1K

M -

S4

RH

850 /F

1L /F

1K

/F

1K

M-S

1

ISO

VS

S

P11<0>

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

ISO

VS

SIS

OV

CL

P10<15>

F1K

M

ISOVCLISOVSS

ISO

VS

SF

1K

M

ISOVSSREGVCC

F1K

M

PIN

5

P8<1>

ISO

VS

SR

EG

VC

C

P9<5>

PIN

43

PIN

4P

IN74

ISO

VC

L

P9<6>

PIN

75

ISO

VC

L

PIN

42

P8<0>

Wed D

ec

14 0

7:2

5:1

0 2

01

6P

AG

E 1

OF

31.0

0

EE

SS

-0400-1

39-0

1

rh850_f1

x_100pin

_pb_t1

_v3

Ele

ctro

nic

s E

uro

pe G

mbH

06.1

0.2

016

W.R

ause

r

14

686766656463

HE

AD

ER

25W

AY

26

HE

AD

ER

25W

AY

66

64

54

6

HE

AD

ER

25W

AY

ISO

VC

L

18

1110

51

24

654

23

10

54 12

15

01

41

7

45

46

0

5

93

97

1 3

91

95

96

97

3.3

OR

5V

RE

GV

CC

35

34

100n

100n

78

80

75

35

3.3

OR

5V

RE

GV

CC

100n

ISO

VC

L

10099

98

96

97

95

93

94

90

92

91

88

89

86

87

85

84

83

82

81

80

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77

76

50

48

49

47

46

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43

44

42

40

41

38

39

37

35

36

32

33

34

30

31

29

27

28

HE

AD

ER

25W

AY

75

74

72

73

71

69

70

67

68

66

64

65

62

63

61

59

60

58

57

56

54

55

53

52

25

23

22

21

20

19

17

16

15

13

14

12

10

118 975 64321

100N

1 20

76

99

98

100

99

98

96

94

95

100N

100N

100N

3.3

OR

5V

EV

CC

12

54

3

6

100N

ISO

VC

L

1112

1413

102

125

11

100N

A0V

RE

F3.3

OR

5V

43

100N

AW

OV

CL

5

7

45

3

78

9

1112

9

1313

1617

1415

1716

181819

212223

1920

232221

242525

24

26

27

28

29

30

31

32

54321

13

12

10

11

9876

90

89

88

87

86

85

84

92

93

91

89

90

88

86

87

84

85

83

83

82

81

79

82

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79

80

78

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7271

69

7271

73

6970

68

65

63

6059

6261

5960

58 58

5655

53

5756

535455

33

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

52

23

6789

10

12131415

3.3

OR

5V

A0V

RE

F

27

26

28

30

32

31

210

12P

12P

18P

F16.0

00 M

HZ

+ S

OC

KE

T

33

34

37

36

38

39

40

42

43

44

47

48

49

50

1098

3456789

RE

GV

CC

3.3

OR

5V

AW

OV

CLE

VC

C3.3

OR

5V

10

11 57

62

70

73

12 2 4

1534

8

20

14

10

6

74

61

525151

67

77

76

ISO

VC

L

29

RH

850_F

1L_100_ya

m_S

ock

et

94

92

3.3

OR

5V

EV

CC

100

100N

0

C11

JP13

JP12

C9

JP8

JP7

JP3 JP

5

C8

3C

4C

1C

2C

CN

6

CN

8C

N7

X1

C10

C7

C18

C13

C17

C16

CN

5

IC1

Z_P

INS

<100..1>

Z_P

INS

<100..1>

P11<0>

P9<6>

P8<1>

P8<1>

P11<0>

P9<5>

P11<7..1>

P10<15..0>

P8<12..0>JP

0<5..0>

Z_P

INS

<100..1>

RE

SE

T_Z

JP0<5..0>

X2

X1

FLM

D0

P0<10..7>

P8<9..0>

AP

0<15..0>

P10<15..0>

P8<0>

P10<15..0>

P9<6..0>

P8<0>

P9<5>

P9<6>

P0<14..0>

P10<15>

P10<15>

P11<0>

321

321

321

321

321

321

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

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98765432125

24

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35

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94

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222120

50

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17161514

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53545556575859606162636465666768

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IN

25

24

23

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20

19

18

17

16

15

14

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10987654321

P10[2

]P

10[1

]P

10[0

]E

VS

S[3

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VC

C[3

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11[7

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11[6

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11[5

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11[4

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11[3

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11[2

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11[1

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10[1

4]

P10[1

3]

P10[1

2]

P10[1

1]

P10[1

0]

P10[9

]P

10[8

]P

10[7

]P

10[6

]E

VS

S[2

]IS

OV

SS

ISO

VC

LE

VC

C[2

]

P9[6]P9[5]P9[4]P9[3]P9[2]P9[1]P9[0]

AP0[0]AP0[1]AP0[2]AP0[3]AP0[4]AP0[5]AP0[6]AP0[7]AP0[8]AP0[9]

AP0[10]AP0[11]AP0[12]AP0[13]AP0[14]AP0[15]

A0VREFA0VSS

P8[9

]P

8[8

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8[7

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8[6

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8[5

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8[4

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8[3

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8[1

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VS

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0[7

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0[8

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0[9

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0[1

0]

FLM

D0

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X2

RE

GV

CC

AW

OV

CL

AW

OV

SS

EV

CC

[1]

RE

SE

T#

JP0[0

]JP

0[1

]JP

0[2

]

JP0[3]JP0[4]JP0[5]P8[12]P8[11]P8[10]P8[2]EVSS[0]P0[14]P0[13]P0[12]P0[11]P0[6]P0[5]P0[4]EVCC[0]P0[3]P0[2]P0[1]P0[0]P11[0]P10[15]P10[5]P10[4]P10[3]

CO

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cu

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ve

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me

nt

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mb

er

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Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F



FID

UC

IALS

AN

D G

RO

UN

D T

ES

T P

OIN

TS

VO

LTA

GE

DIS

TR

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TIO

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TO

BE

PR

INTE

D O

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CB

LE

D - P

8<12..0>

PO

WE

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ELE

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ION

: 3

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14 0

7:2

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1 2

01

6P

AG

E 2

OF

31.0

0

EE

SS

-0400-1

39-0

1

rh850_f1

x_100pin

_pb_t1

_v3

Ele

ctro

nic

s E

uro

pe G

mbH

GN

D-T

ES

TP

OIN

T

header

16w

ay

EV

CC

3.3

OR

5V

6

header

3w

ay

long ju

mper

2.5

4m

m

3

10K

2

ST

D P

OW

ER

LA

B S

OC

KE

T 4

MM

RE

D

not to

fit

/ to

deliv

er

with

the b

oard

s

3.3

OR

5V

3.3

OR

5V

EV

CC

3.3

OR

5V

SM

A S

TR

AIG

HT

3.3

OR

5V

EV

CC

PU

SH

BU

TT

ON

4 P

IN S

MD

10N

3.3

V

3

81

10K

1S

MA

5919B

T3G

_5.6

V

4

5.0

V

0

47K

0

0

5

1 2 3 5 76

0 1 2 5 7

TE

ST

PO

INT

_S

MA

LL_R

D

150

100U

51

5.0

VV

IN_5V

5V

3.3

V

MF

-NS

MF

035x

MF

-NS

MF

035x

VIN

_3.3

V3.3

V

1S

MA

5914B

T3G

_3.6

V

ST

D P

OW

ER

LA

B S

OC

KE

T 4

MM

BLA

CK

Not to

fit

/ to

deliv

er

with

the b

oard

s

ST

D P

OW

ER

LA

B S

OC

KE

T 4

MM

RE

D

Not to

fit

/ to

deliv

er

with

the b

oard

s

GR

EE

N

100U

1S

MA

5919B

T3G

_5.6

VG

ND

-TE

ST

PO

INT

GN

D-T

ES

TP

OIN

T

FID

UC

IAL_1M

M

EV

CC

GR

EE

N

TE

ST

PO

INT

_S

MA

LL_R

D

51

GN

D-T

ES

TP

OIN

T

EV

CC

header

3w

ay

long ju

mper

2.5

4m

m

header

2w

ay

long ju

mper

2.5

4m

m

3V

V3V

3.3

OR

5V

EV

CC

RE

GV

CC

V5V

5V

A0V

RE

F

5.0

V

header

3w

ay

long ju

mper

2.5

4m

mheader

3w

ay

long ju

mper

2.5

4m

m

3.3

OR

5V

3.3

OR

5V

VC

CIO

F

3.3

V

440

3.3

OR

5V

EV

CC

GN

D-T

ES

TP

OIN

T

NX

P_B

C847C

10K

10K

NX

P_B

C847C

10K

1K5

yello

w

1K5

yello

w

1K5

header

2w

ay

long ju

mper

2.5

4m

m

header

3w

ay

long ju

mper

2.5

4m

m

header

2w

ay

long ju

mper

2.5

4m

m

56K

56K

56K

56K

10K

10K

10K

yello

wye

llow

1K5

1K5

1K5 NX

P_B

C847C

56K

56K

56K

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

FID

UC

IAL_1M

MRU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

10K

56K

EV

CC

3.3

OR

5V

yello

w

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

not to

fit

/ not to

buy

1S

MA

5919B

T3G

_5.6

V

not to

fit

/ not to

buy

1K5

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

GN

D-T

ES

TP

OIN

T

3.3

OR

5V

TE

ST

PO

INT

_S

MA

LL_R

D

yello

w

NX

P_B

C847C

1K5

yello

w

EV

CC

3.3

OR

5V

NX

P_B

C847C

EV

CCNX

P_B

C847C

3.3

OR

5V

yello

w

NX

P_B

C847C

NX

P_B

C847C

10K

HE

AD

ER

14W

AY

SH

RO

UD

ED

MP

5

R10

R25

R19

R13

R11

R30

R24

R18

R12

CN

13

TR

8T

R6

TR

4T

R2

TR

5T

R7

TR

3T

R1LE

D4

LE

D6

LE

D8

LE

D11

LE

D9

LE

D7

LE

D5

LE

D10

R17

R15

R23

R21

R27

R29

R33

R35

R14

R16

R20

R22

R34

R32

R28

R26

JP10

JP6

D4

MP

4

MP

3

MP

2

MP

1

TP

13

JP0

JP1

JP2

JP4

JP9

TP

4

TP

3

TP

5

TP

6

TP

7

TP

8

TP

9

TP

10

TP

11

TP

12

TP

1

C19

R8

LE

D1

TP

2

C20

R9

LE

D2

D1

FU

1

D3

FU

2

CN

11

CN

12

CN

10

SW

1

R1

C15

R5

R6

JP11

CN

19

R2

R3

D2

CN

9

LE

DP

8<12..0>

JP0<5..0>

RE

SE

T_Z

L2

P10<15..0>

P8<12..0>

LX

RE

SE

T_Z

LE

DP

8<3>

LE

DP

8<2>

LE

DP

8<4>

LE

DP

8<1>

LE

DP

8<0>

LE

DP

8<6>

LE

DP

8<7>

LE

DP

8<5>

FLM

D0

16

15

14

13

12

11

10

98

76

54

32

1

23

1

23

1

23

1

23

1

23

1

23

1

23

1

23

1

321

321

12

1

321 321 321

21

11 1 1

1 1 1 1 1 1

1 121

21

21

21

14

13

12

11

10

98

76

54

32

1

1

5 43 2

31

41

11

21

90

18

76

54

32

1

21

321 321 321

21

OU

T

OU

T

ININ

OU

T

ININ

ININ

ININ

51

61

31

41

11

21

90

18

76

54

32

1

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

BI

OU

T

BI

21

IN

321

321

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F



LIN

15T

xLIN

15R

x

LIN

11Tx

LIN

11R

xLIN

13T

xLIN

13R

x

MLB

RE

SE

T

CO

NN

EC

TO

R1

PW

M48

MO

DE

Jum

per

EH

0T

XD

1E

TH

0R

XD

1E

TH

0R

XD

0

FLX

1E

N

-

PW

MA

DC

06

PW

M66

PW

M71

PW

M46

PW

M44

PW

M42

PW

M40

TO

MA

IN B

OA

RD

CO

NN

EC

TO

RS

INT

0P

WM

07

PW

MA

DC

07

ET

H0R

ES

ET

ET

H0R

XD

VE

TH

0C

RS

DV

ET

H0R

XE

RE

TH

0R

XD

CLK

-

WA

KE

UA

RT

0T

X

LIN

0T

X

CA

N0TX

SE

NT

OU

T0

PS

I50T

x

ET

H0M

DIO

FLX

1T

XF

LX

0R

XF

LX

0T

X

PW

M78

PW

M76

CO

NN

EC

TO

R4

CO

NN

EC

TO

R2

------------- ----- -- - - - -- -- -

- - - - - - - --

- --- - - - -

- -

- - - - ---- - -

(RLIN

34)

(RLIN

34)

(RLIN

32)

(RLIN

32)

(RLIN

30)

(RLIN

30)

-----

-

-

- -

(RLIN

28)

(RLIN

28)

(RLIN

26)

(RLIN

26)

(RLIN

20)

(RLIN

20)

(RLIN

22)

(RLIN

22)

LIN

4R

x

CA

N2T

x

CA

N4T

xC

AN

4R

xLIN

2T

xLIN

2R

xLIN

4T

x

LIN

6T

x

CA

N2R

x

LIN

6R

xLIN

8T

xLIN

8R

xLIN

10Tx

LIN

10R

x

LIN

14T

xLIN

14R

x

LIN

12R

xLIN

12T

x

MLB

SIG

CA

N6R

xC

AN

6Tx

MLB

CLK

--- --- -CA

N7Tx

CA

N7R

x

MLB

DA

T

- -LIN

9R

x

LIN

7T

x

CA

N3R

xC

AN

5T

xC

AN

5R

xLIN

3T

xLIN

3R

xLIN

5T

xLIN

5R

x

LIN

7R

xLIN

9T

x

CA

N3T

x

(RLIN

31)

(RLIN

31)

(RLIN

33)

(RLIN

33)

(RLIN

31)

(RLIN

31)

(RLIN

29)

(RLIN

29)

(RLIN

27)

(RLIN

27)

(RLIN

25)

(RLIN

25)

(RLIN

23)

(RLIN

23)

VD

DB

VD

DB

MU

X0

MU

X2

AD

C0

-

AD

C6

AD

C4

AD

C2

- --- DIG

IO_0

VD

DIO

F

DIG

IO_8

DIG

IO_6

DIG

IO_10

DIG

IO_12

DIG

IO_14

VD

DB

VD

DB

----

- - DIG

IO_1

DIG

IO_5

DIG

IO_3

AD

C3

AD

C5

AD

C7

VD

DIO

F

AD

C1

MU

X1

DIG

IO_13

DIG

IO_15

DIG

IO_11

DIG

IO_9

DIG

IO_7

-

-

US

B0U

DM

FU

SB

0U

DP

F

FLX

1R

X

ETH

0R

XD

3E

TH

0R

XD

2

PS

I50S

nyc

(RLIN

30)

(RLIN

30)

(RLIN

30)

(RLIN

30)

INT

2

RE

SE

T

PS

I50R

x

SE

NT

IN0

CA

N0R

X

IIC

0S

DA

IIC

0S

DL

LIN

0R

X

UA

RT

0R

X

VD

DA

VD

DA

-

NC

-- US

B0U

DM

HU

SB

0U

DP

H

ET

H0C

OL

ET

H0T

XE

N

FLX

CLK

EH

0T

XD

0

EH

0T

XD

2E

H0TX

D3

ET

H0T

XE

R

FLX

0E

NF

LX

ST

PW

T

PS

I51S

ync

ET

H0T

XC

LK

ET

H0M

DC

PS

I51T

x

INT

1

NM

IV

DD

A

- -VD

DA

CA

N1R

XS

EN

TIN

1S

EN

TO

UT

1P

SI5

1R

x

CA

N1TX

UA

RT

1T

XU

AR

T1R

XLIN

1T

XLIN

1R

XIIC

1S

DL

IIC

1S

DA

(RLIN

21)

(RLIN

21)

(RLIN

31)

(RLIN

31)

--- - ---- - - --PW

MA

DC

02

PW

M74

PW

M72

PW

M70

PW

M68

PW

M60

PW

M64

PW

M62

PW

M56

(CS

IH2S

C)

PW

M36

PW

M18

PW

M20

PW

M16

PW

M14

CO

NN

EC

TO

R3

--- -- - - - -PW

MA

DC

11

PW

MA

DC

15

PW

MA

DC

13

PW

MA

DC

09

PW

M65

PW

M51

PW

M61

PW

M63

PW

M67

PW

M69

PW

M77

PW

M79

PW

MA

DC

01

PW

M75

PW

M73

PW

MA

DC

03

PW

MA

DC

05

PW

M33

PW

M47

PW

M45

PW

M37

MO

DE

2M

OD

E1

MO

DE

0F

LM

D1

PW

M55

PW

M53

PW

M28

PW

M26

(CS

IH2C

SS

2)

PW

M12

(Dig

italIO

)P

WM

38

-

PW

M30

PW

M19

PW

M23

PW

M43

PW

M39

PW

M08

PW

M02

PW

M00

PW

M01

PW

M24

PW

M29

PW

M31

PW

M59

PW

M57

PW

M34

PW

M32

(CS

IH2S

O)

PW

M06

PW

M25

PW

M27

PW

M35

PW

M41

PW

M49

(CS

IH2S

I)

PW

M21

PW

M03

PW

M11

(CS

IH2C

SS

3)

PW

M17

PW

M15

PW

M05

(CS

IH2C

SS

1)

PW

M04

PW

M58

PW

M10

DIG

IO_2

DIG

IO_4

-

INT

3

(Dig

italIO

)

PW

M13

PW

M50

PW

M52

PW

M54

PW

M09

PW

M22

PW

MA

DC

00

PW

MA

DC

04

PW

MA

DC

08

PW

MA

DC

10

PW

MA

DC

12

PW

MA

DC

14

Wed D

ec

14 0

7:2

5:1

2 2

01

6P

AG

E 3

OF

31.0

0

EE

SS

-0400-1

39-0

1

rh850_f1

x_100pin

_pb_t1

_v3

Ele

ctro

nic

s E

uro

pe G

mbH

1K0

1K0

1K0

1K01K0

1K0

1K0

QS

H-0

60-0

1-F

-D-A

3.3

OR

5V

NF

/NB

QT

H-0

60-0

1-F

-D-A

not to

fit/

not to

buy

QT

H-0

60-0

1-F

-D-A

3.3

VV

CC

IOF

VC

CIO

F3.3

OR

5V

3.3

V

5.0

V5.0

V

QS

H-0

60-0

1-F

-D-A

3.3

OR

5V

EV

CC

3.3

OR

5V

EV

CC

6

EV

CC

21

EV

CC

3.3

OR

5V

EV

CC

3.3

OR

5V

8

100K

3.3

OR

5V

JP15

JP14

R42

JP27

R41

JP26

R39

R40

JP28

R37

R38

JP19

R31

R36

JP25

CN

4

CN

2C

N1

CN

3

NC

P10<9>

P8<7>

P10<15..0>

P10<5>

NC

NC

NC

P11<7>

NC

NC

NC

NC

P10<10>

P10<10>

PW

M35

AP

0<9>

NC

NC

P0<9>

P10<8>

P0<11>

P9<5>

P10<0>

NC

P0<14>

NC

P8<5>

P9<4>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<14>

P10<13>

NC

NC

NC

NC

P10<12>

P10<11>

P11<6>

P11<5>

P0<4>

P0<5>

NC

NC

NC

NC

NC

NC

NC

NCP

11<5>

P11<6>

P11<3>

P11<4>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<4>

NC

NC

NC

NC

NC

NC

NC

P10<13>

P10<14>

P10<9>

P10<10>

NC

NC

NC

NC

P11<1>

P11<2>

P0<9>

P0<10>

P0<9>

P0<10>

P0<5>

P0<4>

AP

0<4>

AP

0<0>

AP

0<2>

P10<6>

P0<11>

P10<0>

P8<2>

AP

0<7>

AP

0<5>

AP

0<3>

AP

0<1>

NC

P10<5>

NC

P0<12>

P0<10>

P10<15>

P10<7>

P11<0>

P8<5>

P8<3>

P8<1>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<10>

P10<13>

P10<12>

P10<11>

NC

NC

NC

P9<1>

P9<0>

P0<2>

NC

NC

P0<7>

P0<8>

P0<4>

P0<5>

NC

P9<3>

P0<6>

NC

P9<0>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<14>

P11<1>

NC

P8<1>

P8<0>

P10<0>

P10<1>

P10<2>

P10<3>

P10<9>

P10<10>

NC

P9<2>

P9<1>

NC

RE

SE

T_Z

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

AP

0<13>

AP

0<11>

NC

NC

NC

NC

NC

NC

NC

NC

NC

P11<4>

P11<2>

P0<1>

NC

NC

NC

NC

NC

AP

0<14>

AP

0<12>

AP

0<10>

AP

0<8>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P0<13>

P8<12>

P8<10>

P8<8>

P11<5>

P11<3>

P11<1>

P10<14>

P8<2>

P9<2>

P10<13>

P10<9>

P10<7>

P10<2>

P10<8>

FLM

D0

P10<15..0>

P10<15..0>

P10<15..0>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

AP

0<6>

P10<4>

P8<6>

P11<6>

P9<3>

NC

P0<3>

NC

P8<0>

P8<4>

AP

0<15>

NC

NC

NC

P10<11>

P0<2>

P0<4>

P9<0>

P8<0>

P8<4>

PW

M34

P8<6>

NC

NC

P9<1>

P0<3>

NC

NC

P8<9>

P8<11>

P0<12>

P10<9>

P10<8>

P10<8>

P10<3>

P10<1>

P11<0>

P8<3>

P8<1>

P10<12>

P10<14>

P9<6>

P0<6>

24

321

321

2121

321

321

321

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98

76

54

32

1

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98

76

54

32

1

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

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ese

in

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lis

t (4

28

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09

) in

its

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Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F

RH850/F1x, R1x 100pin Chapter 12 Schematic of PCB marked “D015312-06-V02”


Schematic of PCB marked “D015312-06-V02”

RH

850_F1X

_100P

IN_P

B_T1_V

3

2.0

0C

N2

W.R

ause

r

P8<0>

ISO

VC

L

PIN

75

P9<6>

ISO

VC

L

PIN

74

PIN

4P

IN43

P9<5>

RE

GV

CC

ISO

VS

S

P8<1>

F1K

M

REGVCCISOVSS

F1K

MIS

OV

SS

ISOVSSISOVCL

F1K

M

ISO

VC

LIS

OV

SS (F

1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

(F1L, F

1K

, F

1K

M-S

1 )

P11<0>

ISO

VS

SR

H850/F

1K

M -

S4

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

(F1K

M-S

4)

(F1L, F

1K

, F

1K

M-S

1 )

1.0

2

1.0

1

PIN

34

changed

PIN

36

W.R

ause

rw

ith

W.R

ause

r02.1

2.2

016

14.1

2.2

016

09.1

2.2

019

connect

ion

changed R

38;R

39;R

41;R

42 to 1

k

changed R

40;R

31;R

37 to 1

k

PIN

42

RH

850 /F

1L /F

1K

/F

1K

M-S

1

PIN

5

(F1K

M-S

4)

(F1L, F

1K

, F

1K

M-S

1 )

(F1K

M-S

4)

P10<15>

Wed D

ec

11 0

6:3

6:5

2 2

01

9P

AG

E 1

OF

3

06.1

0.2

016

W.R

ause

r

2.0

0

D015312-0

4

rh850_f1

x_100pin

_pb_t1

_v3

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ctro

nic

s E

uro

pe G

mbH

header

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ay

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72

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70

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51

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33

34

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27

28

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23

22

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20

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17

16

15

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14

12

10

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5V

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1413

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5V

10

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67

77

76

ISO

VC

L

29

RH

850_F

1L_100_ya

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ock

et

92

3.3

OR

5V

EV

CC

100

0

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

header

25w

ay

header

25w

ay

98

12P

16.0

00 M

HZ

+ S

OC

KE

T

3.3

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5V

18P

F

34

AW

OV

CL

ISO

VC

L

CN

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JP13

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JP8

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3C

4C

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CN

6

X1

C10

C7

C18

C13

C17

C16

CN

5

IC1

Z_P

INS

<100..1>

P9<6>

P9<5>

P10<15>

P11<0>

P8<1>

P8<0>

Z_P

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<100..1>

Z_P

INS

<100..1>

P11<0>

P9<6>

P8<1>

P11<7..1>

P10<15..0>

P8<12..0>JP

0<5..0>

RE

SE

T_Z

X1

P0<10..7>

P8<9..0>

AP

0<15..0>

P10<15..0>

P10<15..0>

P9<6..0>

P8<0>

P9<5>

P0<14..0>

P10<15>

P11<0>

JP0<5..0>

X2

FLM

D0

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

14

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24

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25

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P10[2

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10[1

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10[0

]E

VS

S[3

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VC

C[3

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11[6

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11[5

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11[4

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P10[1

3]

P10[1

2]

P10[1

1]

P10[1

0]

P10[9

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10[8

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10[7

]P

10[6

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VS

S[2

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OV

SS

ISO

VC

LE

VC

C[2

]

P9[6]P9[5]P9[4]P9[3]P9[2]P9[1]P9[0]

AP0[0]AP0[1]AP0[2]AP0[3]AP0[4]AP0[5]AP0[6]AP0[7]AP0[8]AP0[9]

AP0[10]AP0[11]AP0[12]AP0[13]AP0[14]AP0[15]

A0VREFA0VSS

P8[9

]P

8[8

]P

8[7

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8[5

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8[4

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8[3

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8[1

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8[0

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0[8

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0[9

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0]

FLM

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GV

CC

AW

OV

CL

AW

OV

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CC

[1]

RE

SE

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JP0[0

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Th

ese

in

tan

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le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F

CO

MM

EN

TR

EV

1.0

0R

ele

as

e

DR

AW

N B

YD

AT

E



MA

X 3

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WE

D D

C S

UP

PLY

TO

BE

PR

INTE

D O

N P

CB

OV

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LTA

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PR

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INTE

D O

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CB

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OR

5V

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MA

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ND

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BB

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FE

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UC

IALS

AN

D G

RO

UN

D T

ES

T P

OIN

TS

Wed D

ec

11 0

6:5

2:1

2 2

01

9P

AG

E 2

OF

32.0

0

D015312-0

4

rh850_f1

x_100pin

_pb_t1

_v3

Ele

ctro

nic

s E

uro

pe G

mbH

not to

fit

/ to

deliv

er

with

the b

oard

s

Std

Pow

er

Lab s

ock

et 4m

m r

ed

VIN

_3.3

V3.3

V

1S

MA

5914B

T3G

_3.6

V

GR

EE

N

51

MF

-US

MF

050

3.3

V

100U

Test

poin

t_sm

all_

rd

VIN

_5V

not to

fit

/ to

deliv

er

with

the b

oard

s

1S

MA

5919B

T3G

_5.6

V

not to

fit

/ not to

buy

GN

D-T

est

poin

t

GN

D-T

est

poin

t

GN

D-T

est

poin

t

MF

-US

MF

050

NX

P_B

C847C

NX

P_B

C847C

NX

P_B

C847C

NX

P_B

C847C

NX

P_B

C847C

NX

P_B

C847C

EV

CC

3.3

OR

5V

63

2

3.3

OR

5V

EV

CC

3.3

OR

5V

3.3

OR

5V

EV

CC 10N

3.3

V

81

1S

MA

5919B

T3G

_5.6

V

4

5.0

V

47K

0

0

1 2 3 5 76

0 1 2 5 7150

5.0

V5V

GR

EE

N

100U

FID

UC

IAL_1M

M

EV

CC

51

EV

CC

EV

CC

RE

GV

CC

V5V

5V

A0V

RE

F

5.0

V

3.3

OR

5V

3.3

OR

5V

VC

CIO

F

3.3

V

440

3.3

OR

5V

EV

CC

10K

10K

10K

1K5

yello

w

1K5

yello

w

1K5

56K

56K

56K

56K

10K

10K

10K

yello

w

1K5

1K5

56K

56K

56K

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

10K

56K

EV

CC

3.3

OR

5V

yello

w

1K5

3.3

OR

5V

yello

w

1K5

yello

w

EV

CC

3.3

OR

5V

EV

CC

3.3

OR

5V

yello

w

10K

header

16w

ay

Push

button 4

pin

SM

D

Test

poin

t_sm

all_

rd

Test

poin

t_sm

all_

rd

10K

10K

header

14w

ay

shro

uded

1S

MA

5919B

T3G

_5.6

V

GN

D-T

est

poin

t

GN

D-T

est

poin

t

GN

D-T

est

poin

t

3.3

OR

5V

yello

w

1K5 NX

P_B

C847C

NX

P_B

C847C

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

3

SM

A s

traig

ht

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

RU

BB

ER

FO

OT

D=11.1

MM

/H=5M

M G

RE

Y

3.3

OR

5V

V3V

3V

5

not to

fit

/ not to

buy

0

Std

Pow

er Lab s

ock

et 4m

m b

lack

not to

fit

/ to

deliv

er

with

the b

oard

s

Std

Pow

er

Lab s

ock

et 4m

m r

ed

CN

11

D3

LE

D2R

9

FU

2

C20

TP

2

CN

9

D2

R3

5R

6R

C15

R1

SW

1

CN

12

FU

1

D1

LE

D1R

8

C19

TP

1

TP

12

TP

11

TP

10

TP

9

TP

8

TP

7

TP

6

TP

5

TP

3

TP

4

JP9

JP4

JP2

JP0

TP

13

MP

1

MP

2

MP

3

MP

4

MP

5

D4

JP6

R26

R28

R32

R34

R22

R20

R16

R14

R35

R33

R29

R27

R21

R23

R15

R17

LE

D10

LE

D5

LE

D7

LE

D11

LE

D6

LE

D4

TR

1T

R3

TR

7T

R5

TR

2T

R4

TR

6T

R8

CN

13

R12

R18

R24

R30

R11

R13

R19

R25

CN

19JP

10

JP1

CN

10

JP11

LE

D9

LE

D8

R10

R2

LE

DP

8<12..0>R

ES

ET

_Z

L2

P10<15..0>

P8<12..0>

LE

DP

8<3>

LE

DP

8<2>

LE

DP

8<4>

LE

DP

8<1>

LE

DP

8<0>

LE

DP

8<6>

LE

DP

8<7>

LE

DP

8<5>

FLM

D0

LX

RE

SE

T_Z

JP0<5..0>

1 21

2345

1

12

34

56

78

910

12

13

14

12

1

1 2

1

111111

111 1

12

2 31 2 31 3

12

2 3

1

3 2

1

3 2

1

3 2

1

3 2

1

3 2

1

3 2

1

3 2

1

3 2

12

34

56

78

910

11

12

13

14

15

16

321

12

2

11

1

1

21

321 321 321

21

OU

T

OU

T

ININ

OU

T

ININ

ININ

ININ

51

61

31

41

11

21

90

18

76

54

32

1

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

B

EC

BI

OU

T

BI

21

31

41

11

21

90

1

531

IN

321

321

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F

7642 8



CA

N3T

xC

AN

2T

x

CA

N5T

x

LIN

9R

x

LIN

11

Tx

LIN

11

Rx

LIN

13

Tx

LIN

13

Rx

LIN

15

Tx

LIN

15

Rx

(RLIN

33

)

(RLIN

31

)

(RLIN

31

)

(RLIN

29

)

(RLIN

29

)

(RLIN

27

)

(RLIN

31

)

MLB

RE

SE

T

MLB

SIG

--

MO

DE

Jum

per

EH

0T

XD

1E

TH

0R

XD

1

ET

H0R

XD

0

FLX

1E

N

-

PW

MA

DC

06

PW

M66

PW

M71

PW

M48

PW

M46

PW

M44

PW

M42

PW

M40

TO

MA

IN B

OA

RD

CO

NN

EC

TO

RS

INT

0P

WM

07

PW

MA

DC

07

ET

H0R

ES

ET

ET

H0R

XD

V

ET

H0C

RS

DV

ET

H0R

XE

R

ET

H0R

XD

CL

K

-

WA

KE

UA

RT

0T

X

LIN

0T

X

CA

N0T

X

SE

NT

OU

T0

PS

I50T

x

ET

H0M

DIO

FLX

1T

X

FLX

0R

X

FLX

0T

X

PW

M78

PW

M76

CO

NN

EC

TO

R4

CO

NN

EC

TO

R2

------------- ----- -- - - - -- -- -

- - - - - - - --

- --- - - - -

- -

- - - - ---- - -

(RLIN

34

)

(RLIN

34

)

(RLIN

32

)

(RLIN

32

)

(RLIN

30

)

(RLIN

30

)

-----

-

-

- -

(RLIN

28

)

(RLIN

28

)

(RLIN

26

)

(RLIN

26

)

(RLIN

20

)

(RLIN

20

)

(RLIN

22

)

(RLIN

22

)

LIN

4R

x

CA

N4T

x

CA

N4R

x

LIN

2T

x

LIN

2R

x

LIN

4T

x

LIN

6T

x

CA

N2R

x

LIN

6R

x

LIN

8T

x

LIN

8R

x

LIN

10

Tx

LIN

10

Rx

LIN

14

Tx

LIN

14

Rx

LIN

12

Rx

LIN

12

Tx

CA

N6R

x

CA

N6T

x

MLB

CLK

--- --- -CA

N7T

x

CA

N7R

x

MLB

DA

T

LIN

7T

x

CA

N3R

x

CA

N5R

x

LIN

3T

x

LIN

3R

x

LIN

5T

x

LIN

5R

x

LIN

7R

x

LIN

9T

x

(RLIN

31

)

(RLIN

33

)

(RLIN

27

)

(RLIN

25

)

(RLIN

25

)

(RLIN

23

)

(RLIN

23

)

VD

DB

VD

DB

MU

X0

MU

X2

AD

C0

-

AD

C6

AD

C4

AD

C2

- --- DIG

IO_

0

VD

DIO

F

DIG

IO_

8

DIG

IO_

6

DIG

IO_

10

DIG

IO_

12

DIG

IO_

14

VD

DB

VD

DB

----

- -DIG

IO_

1

DIG

IO_

5

DIG

IO_

3

AD

C3

AD

C5

AD

C7

VD

DIO

F

AD

C1

MU

X1

DIG

IO_

13

DIG

IO_

15

DIG

IO_

11

DIG

IO_

9

DIG

IO_

7

-

-

US

B0U

DM

F

US

B0U

DP

F

FLX

1R

X

ET

H0R

XD

3

ET

H0R

XD

2

PS

I50S

nyc

(RLIN

30

)

(RLIN

30

)

(RLIN

30

)

(RLIN

30

)

INT

2

RE

SE

T

PS

I50R

x

SE

NT

IN0

CA

N0R

X

IIC

0S

DA

IIC

0S

DL

LIN

0R

X

UA

RT

0R

X

VD

DA

VD

DA

-

CO

NN

EC

TO

R1 N

C-- U

SB

0U

DM

H

US

B0U

DP

H

ET

H0C

OL

ET

H0T

XE

N

FLX

CL

K

EH

0T

XD

0

EH

0T

XD

2

EH

0T

XD

3

ET

H0T

XE

R

FLX

0E

N

FLX

ST

PW

T

PS

I51S

ync

ET

H0T

XC

LK

ET

H0M

DC

PS

I51T

x

INT

1

NM

I

VD

DA

- -VD

DA

CA

N1R

X

SE

NT

IN1

SE

NT

OU

T1

PS

I51R

x

CA

N1T

X

UA

RT

1T

X

UA

RT

1R

X

LIN

1T

X

LIN

1R

X

IIC

1S

DL

IIC

1S

DA

(RLIN

21

)

(RLIN

21

)

(RLIN

31

)

(RLIN

31

)

--- - ---- - - -- PW

MA

DC

02

PW

M74

PW

M72

PW

M70

PW

M68

PW

M60

PW

M64

PW

M62

PW

M56

(CS

IH2S

C)

PW

M36

PW

M18

PW

M20

PW

M16

PW

M14

CO

NN

EC

TO

R3

--- -- - - - -PW

MA

DC

11

PW

MA

DC

15

PW

MA

DC

13

PW

MA

DC

09

PW

M65

PW

M51

PW

M61

PW

M63

PW

M67

PW

M69

PW

M77

PW

M79

PW

MA

DC

01

PW

M75

PW

M73

PW

MA

DC

03

PW

MA

DC

05

PW

M33

PW

M47

PW

M45

PW

M37

MO

DE

2M

OD

E1

MO

DE

0F

LM

D1

PW

M55

PW

M53

PW

M28

PW

M26

(CS

IH2C

SS

2)

PW

M12

(Dig

italIO

)P

WM

38

-

PW

M30

PW

M19

PW

M23

PW

M43

PW

M39

PW

M08

PW

M02

PW

M00

PW

M01

PW

M24

PW

M29

PW

M31

PW

M59

PW

M57

PW

M34

PW

M32

(CS

IH2S

O)

PW

M06

PW

M25

PW

M27

PW

M35

PW

M41

PW

M49

(CS

IH2S

I)

PW

M21

PW

M03

PW

M11

(CS

IH2C

SS

3)

PW

M17

PW

M15

PW

M05

(CS

IH2C

SS

1)

PW

M04

PW

M58

PW

M10

DIG

IO_

2

DIG

IO_

4

-

INT

3

(Dig

italIO

)

PW

M13

PW

M50

PW

M52

PW

M54

PW

M09

PW

M22

PW

MA

DC

00

PW

MA

DC

04

PW

MA

DC

08

PW

MA

DC

10

PW

MA

DC

12

PW

MA

DC

14

Mon D

ec 0

9 1

4:2

8:0

2 2

01

9P

AG

E 3

OF

3

2.0

0

D0

15

312

-04

rh8

50_

f1x_1

00p

in_p

b_t1

_v3

Ele

ctr

on

ics E

uro

pe

Gm

bH

QS

H-0

60

-01-F

-D-A

QS

H-0

60

-01-F

-D-A

3.3

OR

5V

100K

8

3.3

OR

5V

EV

CC

3.3

OR

5V

EV

CC

12

EV

CC

6

EV

CC

3.3

OR

5V

EV

CC

3.3

OR

5V

5.0

V5.0

V

3.3

V

3.3

OR

5V

VC

CIO

FV

CC

IOF

3.3

V

3.3

OR

5V

QT

H-0

60-0

1-F

-D-A

NF

/NB

QT

H-0

60-0

1-F

-D-A

no

t to

fit/ n

ot to

bu

y

1K0

1K0

1K0

1K0

1K01K0

1K0

JP

15

JP

14

R4

2

JP

27

R4

1

JP

26

R3

9

R4

0

JP

28

R3

7

R3

8

JP

19

R3

1

R3

6

JP

25

CN

4

CN

2

CN

1

CN

3

FLM

D0

PW

M35

PW

M34

AP

0<

7>

AP

0<

6>

AP

0<

5>

AP

0<

4>

AP

0<

3>

AP

0<

2>

AP

0<

1>

AP

0<

0>

NC

P10<

6>

P10<

5>

P10<

4>

NC

NC

P0<

12>

P0<

10>

P10<

15>

P10<

7>

P11<

0>

P8<

5>

P8<

3>

P8<

1>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<

10>

P10<

13>

P10<

12>

P10<

11>

NC

NC

NC

P9<

1>

P9<

0>

P0<

2>

P0<

3>

NC

NC

P0<

7>

P0<

8>

P0<

4>

P0<

5>

NC

P9<

3>

P0<

6>

NC

P9<

0>

P0<

11>

P0<

9>

P10<

8>

P10<

0>

P8<

6>

P8<

4>

P8<

2>

P8<

0>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P10<

9>

P10<

8>

P10<

14>

P11<

1>

NC

NC

NC

P8<

1>

P8<

0>

P10<

0>

P10<

1>

P10<

2>

P10<

3>

P10<

9>

P10<

10>

P10<

9>

P10<

10>

NC

P9<

2>

P9<

1>

NC

RE

SE

T_Z

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

AP

0<

15

>

AP

0<

13

>

AP

0<

11

>

AP

0<

9>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P0<

14>

P0<

12>

P8<

11>

P8<

9>

P8<

7>

P8<

5>

P9<

4>

P11<

6>

P11<

4>

P11<

2>

P11<

0>

P8<

3>

P9<

3>

P10<

14>

P10<

12>

P8<

1>

P0<

3>

P0<

1>

P9<

1>

P10<

10>

P10<

8>

P10<

3>

P10<

1>

NC

NC

NC

NC

NC

NC

AP

0<

14

>

AP

0<

12

>

AP

0<

10

>

AP

0<

8>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P0<

13>

P8<

12>

P8<

10>

P8<

8>

P8<

6>

P8<

4>

P11<

7>

P11<

5>

P11<

3>

P11<

1>

P10<

14>

P8<

2>

P9<

2>

P10<

13>

P10<

11>

P8<

0>

P0<

2>

P0<

4>

P9<

0>

P10<

9>

P10<

7>

P10<

2>

P10<

0>

P10<

8>

P0<

6>

P9<

6>

P10<

15..

0>

P10<

15..

0>

P10<

15..

0>

P9<

5>

P0<

11>

P10<

15..

0>

P0<

4>

P0<

5>

P0<

10>

P0<

9>

P0<

10>

P0<

9>

P11<

2>

P11<

1>

NC

NC

NC

NC

P10<

10>

P10<

9>

P10<

14>

P10<

13>

NC

NC

NC

NC

NC

NC

NC

P10<

4>

P10<

5>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P11<

4>

P11<

3>

P11<

6>

P11<

5>

NC

NC

NC

NC

NC

NC

NC

NC P

0<

5>

P0<

4>

P11<

5>

P11<

6>

P10<

12>

P10<

11>

NC

NC

NC

NC

NC

P10<

13>

P10<

14>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

321

321

2121

321

321

321

12

81

27

12

61

25

12

41

23

12

21

21

12

01

19

11

81

17

11

61

15

11

41

13

11

21

11

11

01

09

10

81

07

10

61

05

10

41

03

10

21

01

10

09

99

89

79

69

59

49

39

29

19

08

98

88

78

68

58

48

38

28

18

07

97

87

77

67

57

47

37

27

17

06

96

86

76

66

56

46

36

26

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98

76

54

32

1

12

81

27

12

61

25

12

41

23

12

21

21

12

01

19

11

81

17

11

61

15

11

41

13

11

21

11

11

01

09

10

81

07

10

61

05

10

41

03

10

21

01

10

09

99

89

79

69

59

49

39

29

19

08

98

88

78

68

58

48

38

28

18

07

97

87

77

67

57

47

37

27

17

06

96

86

76

66

56

46

36

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RH850/F1x, R1x 100pin Chapter 13 Revision History


Revision History

The table provides information about the major changes of the document versions.

Rev. Date

Description

Page Summary

V1.00 2016-11-25 ‒ Initial release

V1.01 2019-11-27 16

20

Changed “Function” for pin 34 and pin 36 on CN2

Added precaution for LIN15 signal on connector CN2

V1.02 2020-01-17 ‒ Released an updated pcb with modified signals on CN2.

V1.03 2020-09-09 9 Corrected jumper setting for F1KM-S1 in table in chapter3. JP14 and JP15 setting was changed.

Main differences to the RH850-F1X-100PIN-PB-T1-V2:

• Added support for the RH850/F1KM-S1 and RH850/F1KM-S4 device. This mainly relates to the added jumpers on page 1 of the schematic for the device pin selection.

• Modified signals on CN1, CN2 and CN3.

• Added functionality for the mode selection of the device.

• Added signalling LEDs.

RH850/F1x, R1x 100pin Piggyback Board T1-V3 User’s Manual: Piggyback Board T1-V3

Publication Date: Rev.1.03 September 09, 2020

Published by: Renesas Electronics Corporation

RH850/F1x, R1x 100PIN

R20UT3959ED0103