rnc mgw unit mx1g6na descr

WCDMA RAN, Rel. RU30, Operating Documentation, Issue 12

MX1G6 and MX1G6-A

DN70181788

Issue 2-0Approval Date 2010-09-01

Confidential

2 DN70181788Issue 2-0

MX1G6 and MX1G6-A

Id:0900d805808dc570Confidential

The information in this document is subject to change without notice and describes only the product defined in the introduction of this documentation. This documentation is intended for the use of Nokia Siemens Networks customers only for the purposes of the agreement under which the document is submitted, and no part of it may be used, reproduced, modified or transmitted in any form or means without the prior written permission of Nokia Siemens Networks. The documentation has been prepared to be used by professional and properly trained personnel, and the customer assumes full responsibility when using it. Nokia Siemens Networks welcomes customer comments as part of the process of continuous development and improvement of the documentation.

The information or statements given in this documentation concerning the suitability, capacity, or performance of the mentioned hardware or software products are given "as is" and all liability arising in connection with such hardware or software products shall be defined conclusively and finally in a separate agreement between Nokia Siemens Networks and the customer. However, Nokia Siemens Networks has made all reasonable efforts to ensure that the instructions contained in the document are adequate and free of material errors and omissions. Nokia Siemens Networks will, if deemed necessary by Nokia Siemens Networks, explain issues which may not be covered by the document.

Nokia Siemens Networks will correct errors in this documentation as soon as possible. IN NO EVENT WILL Nokia Siemens Networks BE LIABLE FOR ERRORS IN THIS DOCUMENTA-TION OR FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO SPECIAL, DIRECT, INDI-RECT, INCIDENTAL OR CONSEQUENTIAL OR ANY LOSSES, SUCH AS BUT NOT LIMITED TO LOSS OF PROFIT, REVENUE, BUSINESS INTERRUPTION, BUSINESS OPPORTUNITY OR DATA,THAT MAY ARISE FROM THE USE OF THIS DOCUMENT OR THE INFORMATION IN IT.

This documentation and the product it describes are considered protected by copyrights and other intellectual property rights according to the applicable laws.

The wave logo is a trademark of Nokia Siemens Networks Oy. Nokia is a registered trademark of Nokia Corporation. Siemens is a registered trademark of Siemens AG.

Other product names mentioned in this document may be trademarks of their respective owners, and they are mentioned for identification purposes only.

Copyright Nokia Siemens Networks 2011. All rights reserved

f Important Notice on Product SafetyThis product may present safety risks due to laser, electricity, heat, and other sources of danger.

Only trained and qualified personnel may install, operate, maintain or otherwise handle this product and only after having carefully read the safety information applicable to this product.

The safety information is provided in the Safety Information section in the Legal, Safety and Environmental Information part of this document or documentation set.

The same text in German:

f Wichtiger Hinweis zur Produktsicherheit Von diesem Produkt knnen Gefahren durch Laser, Elektrizitt, Hitzeentwicklung oder andere Gefahrenquellen ausgehen.

Installation, Betrieb, Wartung und sonstige Handhabung des Produktes darf nur durch geschultes und qualifiziertes Personal unter Beachtung der anwendbaren Sicherheits-anforderungen erfolgen.

Die Sicherheitsanforderungen finden Sie unter Sicherheitshinweise im Teil Legal, Safety and Environmental Information dieses Dokuments oder dieses Dokumentations-satzes.

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MX1G6 and MX1G6-A


Table of contentsThis document has 22 pages.

Summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1 Overview of MX1G6 and MX1G6-A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 MX1G6 and MX1G6-A capacity and performance. . . . . . . . . . . . . . . . . . 9

3 MX1G6 and MX1G6-A structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Mechanical structure of the MX1G6 and MX1G6-A. . . . . . . . . . . . . . . . 113.2 Logical structure of MX1G6 and MX1G6-A . . . . . . . . . . . . . . . . . . . . . . 113.3 External interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 MX1G6 and MX1G6-A operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 MX1G6-A and MX1G6 power consumption. . . . . . . . . . . . . . . . . . . . . . 15

6 Jumper settings of MX1G6-A C110911, MX1G6 C109447 . . . . . . . . . . 16

7 MX1G6 and MX1G6-A connector maps . . . . . . . . . . . . . . . . . . . . . . . . 17

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List of figuresFigure 1 The immediate operating environment of the MX1G6 and MX1G6-A . . . 8Figure 2 Front panel of the MX1G6/ MX1G6-A. . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 3 Jumper blocks of MX1G6-A and MX1G6 . . . . . . . . . . . . . . . . . . . . . . . . 16

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List of tablesTable 1 Alarm signals of the MX1G6/ MX1G6-A . . . . . . . . . . . . . . . . . . . . . . . . 14Table 2 Typical MX1G6-A and MX1G6 power consumption . . . . . . . . . . . . . . . 15Table 3 Connector map of MX1G6 and MX1G6-A backplane connector J1 . . . 17Table 4 Explanation of signals in the J1 backplane connector map table . . . . . 18Table 5 Connector map of MX1G6 and MX1G6-A backplane connector J2 . . . 18Table 6 Explanation of signals in the J2 backplane connector map table . . . . . 19Table 7 Connector map of MX1G6 and MX1G6-A backplane connector J3 . . . 19Table 8 Connector map of MX1G6 and MX1G6-A backplane connector J4 . . . 20Table 9 Explanation of signals in the J4 backplane connector map table . . . . . 21Table 10 Connector map of MX1G6 and MX1G6-A backplane connector J5 . . . 21Table 11 Explanation of signals in the J5 backplane connector map table . . . . . 22

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MX1G6 and MX1G6-A Summary of changes

Id:0900d805808edf8aConfidential

Summary of changesChanges between document issues are cumulative. Therefore, the latest document issue contains all changes made to previous issues.

Please note that the issue numbering system, safety information, and product naming practice are changing. For more information, see Guide to WCDMA RAN and I-HSPA Operating Documentation.

Changes between issues 1-0 and 2-0A new plug-in unit variant MX1G6-A has been added.

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Overview of MX1G6 and MX1G6-A

1 Overview of MX1G6 and MX1G6-AMain functions of MX1G6 and MX1G6-AThe MX1G6 and MX1G6-A are 1.6 Gbit/s ATM multiplexer plug-in units. They multiplex and demultiplex ATM cells and perform ATM layer and traffic management functions. The MX1G6 and MX1G6-A enable connecting low speed units to the switching fabric and improve the use of switching fabric port capacity by multiplexing traffic from up to 20 tributary units to a single fabric port.

Operating environment of MX1G6 and MX1G6-AThe immediate operating environment of MX1G6 and MX1G6-A is presented in Figure 1. The grey boxes represent plug-in units and the white boxes are the interfaces.

Figure 1 The immediate operating environment of the MX1G6 and MX1G6-A

DN70169882

MX1G6-A/MX1G6

Timing and

synchronisation

Multiplexer port

interface

Switch port

interface

TSS3 or

TBUF

HMS interfaceService

terminal

Tributary units Switching fabric

Redundancy

interface

Co-operating

MX1G6-A/MX1G6 unit

LAN

interface

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MX1G6 and MX1G6-A MX1G6 and MX1G6-A capacity and performance

Id:0900d805808edfa2Confidential

2 MX1G6 and MX1G6-A capacity and perfor-manceProcessor and memoryThe capacity and performance of the processor and memory are as follows:

Unit processor 833 MHZ e500 PowerPC core 333 MHz RISC CPM 41 MHz local bus 32 kbyte data and 32 kbyte instruction L1 caches 256 kbyte L2 cache

Memory 256 Mbyte ECC-protected main memory (DDR333) MX1G6 has a 8 Mbyte local bus memory (SDRAM). For MX1G6-A, this local bus

memory is not equipped. 8 Mbyte boot flash

Network processorThe maximum multiprotocol information handling capacity of the APP650 network pro-cessor is 5 Gbit/s and can be freely distributed among ingress and egress directions.

Multiplexer port interfaceThe capacity and performance of the multiplexer port interface are as follows:

MX1G6-A has 20 serial interfaces for tributary units (plus five extra links to support up to 10 two-link slots), as well as four GIgaEthernet ports.

MX1G6 has 20 serial interfaces for tributary units (plus five extra links to support up to 10 two-link slots).

the maximum peak ATM cell rate of a single serial interface is 160 Mbit/s cable length up to 5 mTraffic Manager FPGAThe capacity and performance of the Traffic Manager Field Programmable Gate Array (FPGA) are as follows:

SPI-3 32-bit 117 MHz slave interface five UTOPIA Level 2 16-bit 50 MHz master interfaces one UTOPIA Level 2 8-bit 25 MHz slave interface 3.2 Gbit/s full duplex capacity2.5 Gbit/s serial switching fabric port interfaceThe capacity and performance of the 2.5 Gbit/s serial switching fabric port interface are as follows:

The line rate of the high-speed ports is 2.488 Gbit/s. However, due to the various cell overheads, the usable bandwidth is lower. With the 64-byte fabric cell size, the interface throughput is 3904000 cells/s, The cell rate of 3904000 cells/s translates into 1.655 Gbit/s of ATM throughput (3904000 x 53 x 8)

Cable length up to 5 m

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MX1G6 and MX1G6-A capacity and performance

Refresh PLLThe capacity and performance of the Refresh Phase-locked Loop (PLL) are as follows:

155.52 MHz and 77.76 MHz low jitter reference clocks for switching fabric port adapter interface

19.44 MHz reference clock for UTOPIA extender (UX) FPGAs and PowerQUICC III-based Computer Core (PQ3CC) real-time clock.

On MX1G6-A, the APP650 network processor is equipped with a 38 MHz reference clock.

Hardware management system slave nodeThe capacity and performance of the hardware management system slave node are as follows:

16-bit microcontroller, 10 kbyte on chip RAM, two integrated Controller Area Network (CAN) controllers

256 kbyte external program memory, 8 kbyte dualport RAM 25 MHz maximum operating frequency The maximum bit rate of the HMS bus is 1 Mbit/s (40 m cable). The maximum transfer speed of the CAN bus is 1 Mbit/s allowing 14925 CAN data

frames/s with no data bytes or 7633 CAN data frames/s with five data bytes to be transferred, resulting in the maximum payload capacity of 488 kbit/s at 1 Mbit/s wire speed. When using HMS message mapping to the CAN data frame, the maximum payload is 366 kbit/s at 1 Mbit/s wire speed.

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MX1G6 and MX1G6-A MX1G6 and MX1G6-A structure

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3 MX1G6 and MX1G6-A structure

3.1 Mechanical structure of the MX1G6 and MX1G6-AThe size of the MX1G6 and MX1G6-A printed circuit board is 265 mm x 285 mm. The nominal thickness of the board is 2.0 mm.

3.2 Logical structure of MX1G6 and MX1G6-AThe MX1G6 and MX1G6-A consist of the following functional blocks:

UTOPIA extender 20 x 160 Mbit/s (UX20-A) Traffic Manager (TM FPGA/ TM2 FPGA) Network processor 5 Gbit/s (NP5G/ NP5G-A) Advanced message extractor block for ATM (AMEBA) 2.5 Gbit/s Switching Fabric Port Serializer/Deserializer (SD2G5) PowerQUICC III-based Computer Core, adapted for MX1G6-A/ MX1G6 (PQ3CC) Refresh Phase-locked Loop, variant C (RFP-C) Hardware Management System Slave node, variant B (HMSS-B) DC/DC converters for MX1G6-A/ MX1G6 (DCDC) Physical layer 10/100 Mbit/s Ethernet, variant A (ETH-A)

3.3 External interfacesMultiplexer port interfaceThe multiplexer port interface has 20 serial interfaces for connecting the active MX1G6 or MX1G6-A plug-in unit to the tributary units.

The multiplexer port interface is the external interface of the UX20-A block. It connects the MX1G6 and MX1G6-A units, and tributary units. There are five UX FPGAs and four links per UX making a total of 20 links. All links use differential LVDS signalling. Each UX-FPGA has five links but due to UTOPIA bus capacity only four can be used at a time.

2.5 Gbit/s serial switching fabric port interfaceThe switch port interface connects the MX1G6-A and MX1G6 to the main and redundant switching fabrics.

The redundant 2.5 Gbit/s serial switching fabric port interface is implemented via the backplane connector J5. The switching fabric port is connected via the backplane to the back interface unit, where Small Form-factor Pluggable (SFP) modules are located.

Timing and synchronisation interfaceThe timing and synchronization interface connects the MX1G6-A and MX1G6 to a Timing and Synchronization, SDH, Stratum 3 unit (TSS3) or to a Timing Buffer (TBUF) unit. A 19.44 MHz clock signal is provided by either the TSS3 unit or by the TBUF unit.

The timing and synchronisation interface connects the RFP-C block to an external timing source. The external timing source can be the TSS3 unit or the TBUF unit. The interface has two 19.44 MHz inputs, one for the active source and one for the redundant source.

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MX1G6 and MX1G6-A structure

Redundancy interfaceThe ATM message channel MUX/DEMUX FPGA supports HW-based switchover. The switchover is implemented with two signals routed in the backplane between a redun-dant MX1G6 pair. The FPGA uses these signals to select the active or redundant oper-ating mode. In the active mode, traffic is passed normally through the FPGA. In the redundant mode, only traffic from/to the PQ3CC is passed.

In MX1G6-A, the ATM message channel MUX/DEMUX FPGA also supports HW-based plug-in unit status indication. Two signals are routed in the backplane between a redun-dant MX1G6 pair to inform the status of the PIU.

HMS interface to backplaneThe MX1G6 and MX1G6-A have an interface to the hardware management system (HMS).

The Hardware Management System Slave (HMSS) node of MX1G6-A and MX1G6 has an external connection which connects it to the HMS bus. The HMS bus comprises a 2N-redundant HMS master node, a 2N-redundant HMS bus bridge and one or more HMS slave nodes. The CAN protocol is used in the bus. The hardware management bus is a 2N-redundant ISO/DIS 11898 compliant differential bus.

In addition, the HMSS node has an interface to the slot number. Each cartridge slot has its individual number within the cartridge hardwired in the connector. The HMSS node gets this number through the backplane SLOT[5:0] signal.

PQ3CC debugging and service terminal interfacesDebugging and service terminal interfaces are provided for the PowerQUICC III unit computer. The supported interfaces are RS232 and 10/100Base-T, and they are con-nected to RJ45 connectors in the front panel

The MX1G6 and MX1G6-A provide three Ethernet interfaces, one in the front panel for testing purposes and two in the backplane for future Ethernet-based control plane mes-saging. The main (work) backplane interface and the front panel interface share the same ETH-A HW block. Only one interface can be used at a time.

Boundary scan interfaceThe MX1G6 and MX1G6-A have four boundary scan paths:

1. The first path goes to in the HMSS-B block. It is used for programming the Complex Programmable Logic Device (CPLD) in the HMSS block.

2. The second path goes to the computer and RFP-C HW blocks. It is used for testing the blocks as well as for programming the CPLD devices in the blocks. This path also provides an emulator connection to the unit computer.

3. The third path goes to all other devices with JTAG support. This path is meant for normal boundary scan testing purposes.

4. The fourth path goes to the DC/DC converter blocks. It is used for programming the PowerManager device.

Power feed interfaceThe power interface has two sets of incoming power pins, +5 V inputs for the HMSS node and -48 V inputs for the DC/DC converters, which feed the rest of the MX1G6 and MX1G6-A unit.

DN70181788 13

MX1G6 and MX1G6-A MX1G6 and MX1G6-A operation

Id:0900d805808edfdeConfidential

4 MX1G6 and MX1G6-A operationFront panelThe front panel of the MX1G6 and MX1G6-A measures 285 mm x 25 mm (height x width), see Figure 2.

Figure 2 Front panel of the MX1G6/ MX1G6-A

LED indicatorThe front plate of the MX1G6 and MX1G6-A plug-in unit contains one LED indicator. The LED is controlled by the HMSS-B hardware block.

Front panel connectorsThere are two connectors (RJ-45) for Ethernet (upper connector) and for the serial port interface (lower connector) in the front panel of the MX1G6 and MX1G6-A.

Both connectors are for test purposes only and should not be used during normal oper-ation.

Backplane connectorsThe MX1G6 and MX1G6-A plug-in unit is connected to the backplane with five Z-pack HM connectors. For detailed information on the connectors, see section MX1G6 and MX1G6-A connector maps.

MX1G6DN70170272

SERVICE TERMINAL

INTERFACES:

BACKPLANE:

- TIMING & SYNC

- HMS

- POWER FEED

- SFU

- TRIBUTARY UNITS

LED

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MX1G6 and MX1G6-A operation

AlarmsThe HMSS-B HW block detects changes in some of the plug-in unit alarm signals. These alarm signals indicate failure in the plug-in unit power supply, failure in the plug-in unit's 19.44 MHz system clock, and two types of reset. The HMSS-B also supervises the tem-perature of the plug-in unit. The alarm signals are described in Table 1.

Alarm signal Description

_AL0 Power alarm

_AL1 Clock alarm

_AL3 PQIII soft reset

_AL4 Hard reset

Table 1 Alarm signals of the MX1G6/ MX1G6-A

DN70181788 15

MX1G6 and MX1G6-A MX1G6-A and MX1G6 power consumption

Id:0900d805808edfeeConfidential

5 MX1G6-A and MX1G6 power consumptionThe total power consumption of the MX1G6-A and MX1G6 plug-in unit is shown in Table 2. The HMSS-B node receives its own power via the backplane.

Voltage Power consumption

-48 V 52 W

+5 V 1 W

Table 2 Typical MX1G6-A and MX1G6 power consumption

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Jumper settings of MX1G6-A C110911, MX1G6 C109447

6 Jumper settings of MX1G6-A C110911, MX1G6 C109447Figure 3 shows the jumper blocks of the plug-in unit. No jumpers should be set during normal operation.

Figure 3 Jumper blocks of MX1G6-A and MX1G6DN70170366 MX1G6-A/MX1G6

J1

J2

J3

J4

J5

1

1

1W3

W2

W1

DN70181788 17

MX1G6 and MX1G6-A MX1G6 and MX1G6-A connector maps

Id:0900d805808ee01aConfidential

7 MX1G6 and MX1G6-A connector mapsThe MX1G6 and MX1G6-A are connected to the backplane with five Z-pack HM con-nectors. The connectors are numbered from top 1 to bottom 5. The numbering of the connectors' rows runs from top to bottom (1 to 125). The connectors have five pin columns, marked from A to E. Pin column E is on the left and pin column A on the right.

Backplane connector J1Table 3 and 4 show the connector map of MX1G6 and MX1G6-A backplane connector J1 and explanation of signals in the connector map table.

A B C D E

1 UB1 UB1 UB1 UB1 UB1

2 - - - - -

3 BOV1 BOV1 BOV1 BOV1 BOV1

4 - - - - -

5 UB2 UB2 UB2 UB2 UB2

6 - - - - -

7 BOV2 BOV2 BOV2 BOV2 BOV2

8 - - - - -

9 SLOT(0) SLOT(1) SLOT(2) SLOT(3) SLOT(4)

10 HMS_+5V HMS_+5V(0) SLOT(5) HMS_+5V(1) GND

11 HMS_CAN0H HMS_CAN0L GND HMS_CAN1H HMS_CAN1L

12

13 Coding key area

14

15 GND GND GND GND GND

16 SYS_CLK_A+ SYS_CLK_A- GND SYS_CLK_B+ SYS_CLK_B-

17 GND GND GND GND GND

18 HMS_5V_out TDO1 TDI1 TMS1 TCK1

19 _HMS_Reset GND GND GND GND

20 _TRST2 TDO2 TDI2 TMS2 TCLK2

21 _AW - - GND GND

22 _TRST3 TDO3 TDI3 TMS3 TCLK3

23 RYBY - - GND GND

24 _TRST4 TDO4 TDI4 TMS4 TCK4

25 3V3_in - - GND GND

Table 3 Connector map of MX1G6 and MX1G6-A backplane connector J1

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MX1G6 and MX1G6-A connector maps

Backplane connector J2Tables 5 and 6 show the connector map of MX1G6 and MX1G6-A backplane connector J2 and explanation of signals in the connector map table

Signal Description

UBx, B0Vx -48 V inputs

SLOT(x) PIU position address to the HMSS-B

HMS_+5V(x) 5.35 V inputs to the HMSS-B

HMS_+5V 5 V output to the backplane

HMS_CAN0/1 HMS CAN buses 0 and 1

SYS_CLK_A/B System clock signals from TBU 0 and 1

HMS_5V_out 5 V output to the programming equipment

_HMS_Reset Enables HMSS-B PLD programming from the backplane

TDIx, TDOx, TMSx, TCKx JTAG interface signals

_AW, RYBY Signals supporting JTAG-based flash memory programming

3V3_in 3.3 V input to the power manager device (used during initial programming)

Table 4 Explanation of signals in the J1 backplane connector map table

A B C D E

26 TX3_GBE _P * TX3_GBE _N * - RX3_GBE _P * RX3_GBE _N *

27 - PIU_ACT * - - -


29 - PIU_ACT * - - -

30 - - - - -

31 ETHA_TX+ ETHA_TX- GND_C ETHA_RX+ ETHA_RX-

32 - - - - -

33 ETHB_TX+ ETHB_TX- GND_C ETHB_RX+ ETHB_RX-

34 - - - - -

35 - - - -

36 - - - -

37 - - - -

38 - - - -

39 - - - -


41 - PIU_ACT * - - -


DN70181788 19



Backplane connector J3Table 7 shows the connector map of MX1G6 and MX1G6-A backplane connector J3.

42 - - - - -

43 - - - - -

44 - - - - -

45 - - - - -


47 - PIU_ACT * - - -

48 - - - - -

49 - - - - -

50 - - - - -

* In MX1G6-A

A B C D E

Table 5 Connector map of MX1G6 and MX1G6-A backplane connector J2 (Cont.)

Signal Description

ETHA, ETHB PQ3CC 10/100Base-T Ethernet interfaces


A B C D E

51 - - GND_C - -

52 - - GND_C - -

53 - - GND_C - -

54 - - GND_C - -

55 - - GND_C - -

56 GND GND GND_C GND GND

57 RD + 1 RD - 1 GND_C TD + 1 TD - 1

58 VccR VccR GND_C VccT VccT

59 RX_Rate RX_LOS GND_C TX_Fault TX_Disable

60 Mod_def2 GND_C Mod_def1 Mod_def0


62 RD + 2 RD - 2 GND_C TD + 2 TD - 2






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GND_C (GND_CABLE) is the connector ground island area. It is cut off from the common unit ground (GND).

All signals in J3 are for the SFP module interface.

Backplane connector J4Tables 8 and 9 show the connector map of MX1G6 and MX1G6-A backplane connector J4 and explanation of signals in the connector map table.

67 RD + 3 RD - 3 GND_C TD + 3 TD - 3





72 RD + 4 RD - 4 GND_C TD + 4 TD - 4




A B C D E


A B C D E

76 - - GND_C - -

77 - - GND_C - -

78 - - GND_C - -

79 - - GND_C - -

80 - - GND_C - -

81 - - GND_C - -

82 - - GND_C - -

83 - - GND_C - -

84 - - GND_C - -

85 - - GND_C - -

86 - - GND_C - -

87

88 Coding key area

89

90 - PIU_OK GND_C - PAIR_OK

91 _HMS_RESET HMS_TxD GND_C HMS_RxD _HMS_BSEN

92 - SWITCHOVER_A GND_C - SWITCHOVER_B

93 - - GND_C - -


DN70181788 21




Backplane connector J5Table 10 and 11 show the connector map of MX1G6 and MX1G6-A backplane connec-tor J5 and explanation of signals in the connector map table.

94 - - GND_C - -

95 - - GND_C - -

96 RX0_LVDS0_P RX0_LVDS0_N GND_C TX0_LVDS0_P TX1_LVDS0_N





A B C D E


Signal Description

_HMS_RESET, HMS_TxD,

HMS_RxD, _HMS_BSEN

HMSS-B serial port

RXy_LVDSx Tributary link receive signals (UX FPGA y, Link x)

TXy_LVDSx Tributary link transmit signals (UX FPGA y, Link x)


A B C D E






106 - - GND_C - -




110 - - GND_C - -





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121 - - GND_C - -



124 - - GND_C - -

125 - - GND_C - -

A B C D E


Signal Description

RXy_LVDSx Tributary link receive signals (UX FPGA y, Link x)

TXy_LVDSx Tributary link transmit signals (UX FPGA y, Link x)


MX1G6 and MX1G6-ATable of contentsList of figuresList of tablesSummary of changes1Overview of MX1G6 and MX1G6-A2MX1G6 and MX1G6-A capacity and performance3MX1G6 and MX1G6-A structure3.1Mechanical structure of the MX1G6 and MX1G6-A3.2Logical structure of MX1G6 and MX1G6-A3.3External interfaces

4MX1G6 and MX1G6-A operation5MX1G6-A and MX1G6 power consumption6Jumper settings of MX1G6-A C110911, MX1G6 C1094477MX1G6 and MX1G6-A connector maps

rnc mgw unit mx1g6na descr

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product safetythis product

operating documentation

documentation set

safety information applicable

safety information section

environmental information

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