rode seminar report

7/25/2019 Rode Seminar Report

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Royal Education Societys

COLLEGE OF COMPUTER SCIENCE & INFORMATION

TECHNOLOGY, LATUR

SEMINAR REPORT

On

VLSI

Submittedby

Rode Sh!d Pndu!n"

#E$m Set No%'

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1. 3%TR!&+T3%

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2.2 =S3 3% +//&%3+#T3%

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;.1 !ES3'% "3ER#R+"

;.2 !ES3'% ST=E

=S3 &SES 21

.1 &SES A#!#%T#'ES 22

+%+=&S3% 25

*3*=3'R#$" 2B


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INTRODUCTION

The =S3 desi(n is considered as one of the maCor fields of tremendous interest in

industry A academics. 3t has interdisci)linary rele6ance. #t )resent =S3 is the

emer(in( area of interest amon( the researchers and en(ineers from 3nformation

Technolo(y +om)uter Science Electrical and Electronics En(ineerin(. 3t is re)orted

that around 5000 En(ineers )er year 8ould be a))ointed by the =S3 industry in 3ndia

in the comin( years. 3n order to co)e u) 8ith this demand 8e reDuire at least 10 times

as many en(ineers and researchers as 3ndia is )roducin( no8. The )ro)osed acti6ities of

=S3 education at *en(al En(ineerin( and Science &ni6ersity Shib)ur ,*ES&S

tar(ets to cater to the needs of )otential researchers and en(ineers in this field. *en(al

En(ineerin( and Science &ni6ersity Shib)ur is (oin( to )resent a =S3 education

)ro(ramme 8ith modern technolo(y enhanced 4no8led(e a set of brilliant studentsand hi-tech research. The aim of this mo6e is to )roduce researchersen(ineers ha6in(

8orld class e7)ertise and )ut them to 8or4 8ith the best =S3 technolo(y inno6ated

and indi(enous across a 8ide ran(e. =S3 desi(n industry is a fast (ro8in( industry

our aim is to ta4e )art acti6ely in the )rocess to ma4e it e6en faster. There are t8o

functional )rofiles of the )ro)osed mo6e of =S3 education and research at *ES&S- ,i

to de6elo) a research team in the field of =S3 desi(n for achie6in( e7cellence in this

field

to train )otential =S3 desi(n en(ineers for 3ndian =S3 industry as 8ell as to satisfy

the (lobal need. ormal =S3 desi(n methodolo(y too4 off in &S#Euro)e in the late

1F?0Gs. !e)artment of Electronics ,!E 'o6t. of 3ndia reco(nied its )otentiality in

mid @0Gs and formed a =S3 tas4 force 8ith nodal centers at 33Ts 33Sc +EER3 etc.5


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"o8e6er the boost in this direction 8as recei6ed in mid F0Gs and the focus 8as directed

to8ards =S3 desi(n acti6ities in industries and academia. !urin( late F0Gs the then

*en(al

En(ineerin( +olle(e ,!& 8as ac4no8led(ed as one of the )romisin( centers for =S3

neducation and research.

#lthou(h the )ro(ress in =S3 education at *ES&S is ha6in( a )lethora of constraints

since ince)tion but the determination to build u) a centre of e7cellence in =S3 had

ne6er lac4in( on the )art of e7)ertise in this area. !urin( the last fi6e years more than

?0 research )a)ers in =S3 desi(n A test authored by our faculty members ha6e been

)ublished in different international Cournalsconferences. aculty members of this

3nstitute are also runnin( a number of research )roCects in =S3 related fields funded by

different multinational a(encies and /"R! 'o6t. of 3ndia. # number of tools ha6e

been de6elo)ed to carry on the =S3 research. #bout B $h! theses ha6e been com)leted

durin( the last fi6e years in the field of =S3 desi(n and test. To achie6e the (oal of

=S3 research and education at *ES&S 8e need to de6elo) laboratories 8ith the latest

=S3 +#! tools test eDui)ments and fabrication libraries. The establishment of

'ana)ati Sen(u)ta =S3 =aboratory )rimarily funded by the #lumni #ssociation is a

ste) to8ards this direction. "o8e6er 8ithout acti6edirect su))ort from the industry

and the faculty memberstrained staff our (oal can not be achie6able. We e7)ect acti6e

)artici)ation from all corners in this endea6or. The /ana(ement +ommitteeGs

res)onsibility is to initiate ne8 acti6ities and )ro6ide an o)en )latform to e7)edite the

=S3 research acti6ities at *ES&S. The acti6ities may include im)artin( =S3 trainin(

for the )rofessional en(ineers and students offerin( )artfull time interdisci)linary

de(reedi)loma )ro(rammes for EE3TET++SE students startin( 6enture of

collaboration 8ith the industries etc. The laboratory in its )resent form is the outcome

of co-o)eration and hel) of a lot of

B


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-ht i1 VLSI7

ery =ar(e Scale 3nte(ration ,noun ery =ar(e Scale 3nte(rated ,adCecti6e e7am)leH

=S3 +ircuit definition - 100s of thousands of transistors on a sin(le inte(rated circuit

,3+ or Ichi)J

.e+inition%

ery =ar(e Scale 3nte(ration is term describin( about semiconductor inte(rated circuits

com)osed of hundreds of thousands of lo(ic elements or memory cells. =S3 is the

techniDue of circuit desi(nin( and im)lementation to )ro6ide more com)utational s)eed

8ith

less )o8er dissi)ation and less circuit board area.

?


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Hito!/ o+ VLSI%late 0s Transistor in6ented at *ell =abs late 50s irst 3+ ,K9- by Kac4 9ilby at T3

early B0s Small Scale 3nte(ration ,SS3 10s of transistors on a chi)

late B0s /edium Scale 3nte(ratoin ,/S3 100s of transistors on a chi) early ?0s =ar(e

Scale 3nte(ration ,=S3 1000s of transistor on a chi) early @0s =S3 10000s of

transistors on a chi) ,later 100000s A no8 1000000s

&ltra =S3 is sometimes used for 1000000s

Hi1to!i)* e!1e)ti8e%

The number of a))lications of inte(rated circuits in hi(h-)erformance com)utin(

telecommunications and consumer electronics has been risin( steadily and at a 6ery

fast )ace. This trend is e7)ected to continue 8ith 6ery im)ortant im)lications on =S3

and systems desi(n .Table 1 sho8s the e6olution of lo(ic com)le7ity in inte(rated

circuits o6er the last three decades and mar4s the milestones of each era.

@


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VLSI Im*ementtion Medi

Medi !e9ui!in" +b!i)tion%

ull +ustom - desi(n and )hysical layout at transistor le6el Standard +ell ,a4a Semi-

+ustom L desi(n and )hysical layout at (atefli)-flo) le6el 'ate #rray - desi(n and

)hysical layout at (ate le6el ,li4e standard cell but 8ith some )refabrication of 8afer

P!e+b!i)ted medi%

ield $ro(rammable 'ate #rrays ,$'#s - desi(n at (atefli)-flo) or re(ister transfer

le6el

+om)le7 $ro(rammable =o(ic !e6ices ,+$=!s L desi(n at (atefli)-flo) or re(ister

transfer le6el $ro(rammable =o(ic !e6ices ,$=!s - desi(n at (atefli)-flo) le6el

System-on-+hi) ,So+ may incor)orate se6eral of these im)lementation media on a

sin(le chi)

F


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A*i)tion1%

=S3 has since 1F?0s in6aded all fields and a))lications brin(in( a re6olution in

E6erythin( - from small di(ital 8atches to com)le7 !S$ a))lications. The fastest of

micro)rocessor 3%TE=-$entium embedded systems smart de6ices etc are all )ossible

and 6iable today only because of =S3 and &=S3. Some of the #))lications are

discussed belo8H

:2Mu*timedi%

Today there is a race to desi(n intero)erable 6ideo systems for basic di(ital com)uter

functions in6ol6in( multimedia a))lications in areas such as media information

education medicine and entertainment to name but a fe8 are

.i"iti;tion o+ 3TV Fun)tion14%

3n todays state-of-the-art solution one can reco(nie all the basic functions of the

analo( T set 8ith ho8e6er a modularity in the conce)t )ermittin( additional features

becomes )ossible some s)ecial di(ital )ossibilities aree7)loited e.(. stora(e and

filterin( techniDues to im)ro6e si(nal re)roduction ,ada)ti6e filterin( 100 "

technolo(y to inte(rate s)ecial functions ,)icture-in-)icture oom still )icture or to

recei6e di(ital broadcastin( standards ,/#+ %3+#/.

Fi"2 :< = The .IGIT>


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To8ards standardiation namely the inte(ration of 1B identical hi(h-s)eed )rocessors

8ith communication and )ro(rammability conce)ts com)rised in the architecture. The

hoto(ra)h of 8hich is sho8n belo8

Fi"2 :: @ Chi Photo"!h

>2 VLSI in Communi)tion

Fi"2 :> = The No!di) VLSI nRF


12/26

in 1F@0s and number of de6ices on a chi) doubled e6ery 2 months. This trend is

e7)ected to

+ontinue for another cou)le of decades 8ithout any maCor )roblems. *ut after that

further inte(ration may )ose se6eral )roblems. Some of these further challen(es are as

follo8sH

:'T!n1i1to! 1)*in"%

1. !e6ice )hysics )oses se6eral challen(es to further scalin( of the bul4 /SET

structure. ne maCor )roblem is the controllin( of short channel effects manifested

as T roll-off and !rain 3nduced *arrier =o8erin( effects. To minimie these short

channel effects the transistor lateral-to-6ertical as)ect ratio must be )reser6ed from

one technolo(y (eneration to the ne7t. or this (ate o7ide thic4ness the Cunction

de)th and the de)letion de)th all need to scale do8n by ;0M )er (eneration.

=ea4a(e throu(h the (ate o7ide by direct band-to-band tunnelin( limits )hysical

o7ide thic4ness scalin(. Reducin( the source drain Cunction e7tensions is limited by

the increase in the )arasitic resistances. Reducin( Cunction de)ths belo8 ;0nm

de(rades dri6e current e6en thou(h short channel effect is im)ro6ed.

>'Subth!e1ho*d *e?"e%

Su))ly 6olta(es 8ill continue to reduce 8ith each technolo(y (eneration and

continue to contribute to lo8er the )o8er dissi)ation. "o8e6er transistor threshold

6olta(e ,T must reduce at the same rate to maintain enou(h (ate o6erdri6e and

enable circuit )erformance to im)ro6e ;0 M each (eneration. =o8er T causes the

transistor subthreshold lea4a(e current to increase e7)onentially

B'2 Inte!)onne)t 1)*in"%

+hi) )erformance is increasin(ly limited by the inter connect R+ delay as the transistor

delays decrease )ro(ressi6ely 8hile the narro8er metal lines and s)ace actually

increase the delay associated 8ith the interconnects. "ence interconnect scalin(

12


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cou)led 8ith hi(her o)eratin( freDuencies reDuires careful ca)aciti6e and inducti6e

noise modelin(.

' Poe! di11ition%

$o8er dissi)ation is increasin( due to hi(her o)eratin( freDuencies and transistor

counts. Su))ly 6olta(es 8ill continue but its contribution to )o8er reduction is

definitely not enou(h. "ence )o8er efficient micro-architectures are reDuired and the

die sie and the freDuency (ro8th may need to be contained.

D2 P*t+o!m inte"!tion%

#t the )latform le6el e7ternal bus freDuencies ha6e not 4e)t )ace 8ith )rocessor

freDuencies. #lso the (a) bet8een 3 6olta(es of ad6anced micro)rocessors and other

motherboard com)onents is increasin(. This reDuires ne8 hi(h-6olta(e tolerant circuits

or )rocess o)tions. 3ns)ite of these challen(es there is no fundamental barrier for

/oores la8 to e7tend for another

cou)le of decades.

1;


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VLSI .e1i"n F*o%

The desi(n )rocess at 6arious le6els is usually e6olutionary in nature. 3t starts 8ith a

(i6en set of reDuirements. 3nitial desi(n is de6elo)ed and tested a(ainst the

reDuirements. When reDuirements are not met the desi(n has to be im)ro6ed. 3f such

im)ro6ement is either

not )ossible or too costly then the re6ision of reDuirements and its im)act analysis must

be considered. The -chart ,first introduced by !. 'aCs4i sho8n in the follo8in( fi(ure

illustrates a desi(n flo8 for most lo(ic chi)s usin( desi(n acti6ities on three different

a7es ,domains 8hich resemble the letter . The -chart consists of three maCor

domains namelyH

N beha6ioral domainN structural domain

N (eometrical layout domain.

1


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.e1i"n Hie!!)h/%

The use of hierarchy techniDue in6ol6es di6idin( a module into sub- modules and

then re)eatin( this o)eration on the sub-modules until the com)le7ity of the smaller

)arts becomes mana(eable.

Con)et1 o+ Re"u*!it/, Modu*!it/ nd Lo)*it/% Re"u*!it/ means that the

hierarchical decom)osition of a lar(e system should result in not only sim)le but also

similar bloc4s as much as )ossible. # (ood e7am)le of re(ularity is the desi(n of array

structures consistin( of identical cells - such as a )arallel multi)lication array.

Re(ularity usually reduces the number of different modules that need to be desi(ned and

6erified at all le6els of abstraction. /odularity in desi(n means that the 6arious

functional bloc4s 8hich ma4e u) the lar(er system must ha6e 8ell-defined functions

and interfaces. /odularity allo8s that each bloc4 or

module can be desi(ned relati6ely inde)endently from each other #ll of the bloc4s can

be combined 8ith ease at the end of the desi(n )rocess to form the lar(e system. The

conce)t of modularity enables the )arallelisation of the desi(n )rocess*y definin( 8ell-

characteried

interfaces for each module in the system 8e effecti6ely ensure that the internals of each

module become unim)ortant to the e7terior modules. 3nternal details remain at the local

le6el. The conce)t of *o)*it/ also ensures that connections are mostly bet8een

nei(hborin( modules a6oidin( lon(-distance connections as much as )ossible.

15


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VLSI .e1i"n St/*e1

arious desi(n styles used for =S3 chi) fabrication are as follo8sH

:2Fie*d P!o"!mmb*e Gte A!!/ #FPGA'% ully fabricated $'# chi)s containin(

thousands of lo(ic (ates or e6en more 8ith )ro(rammable interconnects are a6ailable

to users for their custom hard8are )ro(rammin( to realie desired functionality. #

ty)ical ield $ro(rammable 'ate #rray ,$'# chi) consists of 3 buffers an array of

+onfi(urable =o(ic *loc4s ,+=*s and )ro(rammable interconnect structures. The

)ro(rammin( of the interconnects is im)lemented by )ro(rammin( of R#/ cells 8hose

out)ut terminals are connected to the (ates of /S )ass transistors.The ad6anta(es of

$'# are 6ery short turn around time and no )hysical manufacturin( reDuired for

customiin( it.The disad6anta(e isty)ical )rice of $'# chi)s are usually hi(her than other realiation alternati6es.

Fi" @ Gene!* !)hite)tu!e o+ 6i*in$ FPGA12

1B


17/26

>2Gte A!!/ .e1i"n% 3n 6ie8 of the fast )rototy)in( ca)ability the (ate array ,'#

comes after the $'#. While the desi(n im)lementation of the $'# chi) is done 8ith

user )ro(rammin( that of the (ate array is done 8ith metal mas4 desi(n and

)rocessin(.'ate array

im)lementation reDuires a t8o-ste) manufacturin( )rocessH The first )hase 8hich

isbased on (eneric ,standard mas4s results in an array of uncommitted transistors on

each '# chi). These uncommitted chi)s can be stored for later customiation 8hich is

com)leted by definin( the metal interconnects bet8een the transistors of the array.Since

the )atternin(

of metallic interconnects is done at the end of the chi) fabrication the turn-around time

can be still short a fe8 days to a fe8 8ee4s. The ad6anta(es of '# are better chi)

utiliation factormore chi) s)eed and more customied desi(n.

Fi"2 D = (1i) !o)e11in" 1te1 !e9ui!ed +o! "te !!/ im*ementtion

1?


18/26

B2 Stnd!d=Ce**1 (1ed .e1i"nH The standard-cells based desi(n is one of the most

)re6alent full custom desi(n styles 8hich reDuire de6elo)ment of a full custom mas4

set. The standard cell is also called the )olycell. 3n this desi(n style all of the commonly

used lo(ic

cells are de6elo)ed characteried and stored in a standard cell library. The

characteriation of each cell is done for se6eral different cate(ories li4e delay time 6s.

load ca)acitance circuit timin( and fault simulation models cell data for )lace-and-

route mas4 data.

Fi"2 = A 1tnd!d )e** */out e$m*e2To enable automated )lacement of the cells and routin( of inter-cell connections each

cell layout is desi(ned 8ith a fi7ed hei(ht so that a number of cells can be abutted side-

byside

to form ro8s. The )o8er and (round rails ty)ically run )arallel to the u))er and lo8er

boundaries of the cell thus nei(hborin( cells share a common )o8er and (round bus.

The in)ut and out)ut )ins are located on the u))er and lo8er boundaries of the cell. The

fi(ure that follo8s sho8s the layout of a ty)ical standard cell. "ere the n/S

transistors are located closer to the (round rail 8hile the )/S transistors are )laced

closer to the )o8er rail.

1@


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2 Fu** Cu1tom .e1i"n% 3n a full custom desi(n the entire mas4 desi(n is done ane8

8ithout use of any library. "o8e6er the de6elo)ment cost of such a desi(n style is

becomin( )rohibiti6ely hi(h. Thus the conce)t of desi(n reuse is becomin( )o)ular in

order to reduce

desi(n cycle time and de6elo)ment cost. 3n real full-custom layout in 8hich the

(eometry orientation and )lacement of e6ery transistor is done indi6idually by the

desi(ner desi(n )roducti6ity is usually 6ery lo8 - ty)ically 10 to 20 transistors )er day

)er desi(ner. 3n

di(ital +/S =S3 full-custom desi(n is rarely used due to the hi(h labor cost.

E7ce)tions to this include the desi(n of hi(h-6olume )roducts such as memory chi)s

hi(h- )erformance micro)rocessors and $'# masters.

1F


20/26

Limitin" +)to!1 in VLSI de1i"n%

There are a certain )hysical factors of real =S3 desi(ns 8hich limit the )erformance of di(ital =S3

circuits. The s8itchin( characteristics of di(ital

inte(rated circuits essentially dictate the o6erall o)eratin( s)eed of di(ital systems. The dynamic

)erformance reDuirements of a di(ital system are usually amon( the most im)ortant desi(n

s)ecifications. Therefore the s8itchin( s)eed of the circuits must be estimated and o)timied 6ery

early in the desi(n. 3t is obser6ed that ,1 The interconnection delay is becomin( the dominatin( factor

8hich determines the dynamic )erformance of lar(e-scale systems and ,2 The interconnect )arasitics

are difficult to model and to simulate. arious )arasitics that affect the desi(n of a chi) are /SET

and interconnect ca)acitance and interconnect resistance

20


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-/1 nd Method1 +o! Lo Poe! VLSI .e1i"n%

The a6era(e )o8er consum)tion in con6entional +/S di(ital circuits can be e7)ressed as the sum of

three main com)onents namely ,1 the dynamic ,s8itchin( )o8er consum)tion ,2 the short-circuit

)o8er consum)tion and ,; the lea4a(e )o8er consum)tion. The increasin( )rominence of )ortablesystems and the need to limit )o8er consum)tion ,and hence heat dissi)ation in 6ery-hi(h density

&=S3 chi)s ha6e led to ra)id and inno6ati6e de6elo)ments in lo8-)o8er desi(n durin( the recent

years. the reDuirements of lo8 )o8er consum)tion must be met alon( 8ith eDually demandin( (oals of

hi(h chi) density and hi(h throu(h)ut. "ence lo8-)o8er desi(n of di(ital inte(rated circuits has

emer(ed as a 6ery acti6e and ra)idly de6elo)in( field of +/S desi(n. Ways to reduce )o8er

dissi)ation at different le6els of desi(nin( areas follo8sH

Fi"2 @ Lo Poe! .e1i"n

21


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VLSI nd it1 U1e1%

#s 8e ha6e seen that =S3 is a technolo(y by 8hich 10000-1 /illion Transistors can be

fabricated on a sin(le chi). %o8 8hat is the necessity for fabricatin( that

manyofTransistorsonasin(lechi)O

3n olden days durin( the 6acuum tube era the sie of Electronic !e6ices 8ere hu(e

reDuired more )o8er dissi)ated more amount of heat and 8ere not so reliable. So there

8as certainly a need to reduce the sie of these de6ices and their heat dissi)ation. #fter

the in6ention of SS!Gs the sie and the heat )roduced by de6ices 8as undoubtedly

reduced drastically but as the days )assed the reDuirement of additional features in

Electronic !e6ices increased 8hich a(ain made the de6ices loo4 bul4y and com)le7.

This (a6e birth to the in6ention of technolo(y 8hich can fabricate more number of

com)onents onto a sin(le chi).

Moo!e1L%

3n 1FB5 'ordon /oore an industry )ioneer )redicted that the number of Transistors on

a chi) doubles e6ery 1@ to 2 months. "e also )redicted that Semiconductor Technolo(y

8ill double its effecti6eness e6ery 1@ months and many other factors (ro8

e7)onentially.

22


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Ad8nt"e1 o+ VLSI%

=S3 has many ad6anta(esH

1. Reduces the Sie of +ircuits.

2. Reduces the effecti6e cost of the de6ices.

;. 3ncreases the )eratin( s)eed of circuits

. ReDuires less )o8er than !iscrete com)onents.

5. "i(her Reliability

B. ccu)ies a relati6ely smaller area.

2;


24/26

USES OF VLSI

3n todayGs 8orld =S3 chi)s are 8idely used in 6arious branches of En(ineerin( li4eH

oice and !ata +ommunication net8or4s

!i(ital Si(nal $rocessin(

+om)uters

+ommercial Electronics

#utomobiles

/edicine and many more.

2
http://www.techulator.com/articles/Computer-Hardwares.aspxhttp://www.techulator.com/articles/Automobiles.aspxhttp://www.techulator.com/articles/Computer-Hardwares.aspxhttp://www.techulator.com/articles/Automobiles.aspx


25/26

Con)*u1ion%

N =S3 )ro6ides circuit desi(ns 8ith more com)utational s)eed 8ith less )o8er dissi)ation and less

circuit board area alon( 8ith hi(her s)eeds and hi(her reliability at lo8er costs.

N There are 6ery stron( lin4s bet8een the fabrication )rocess the circuit desi(n )rocess and the

)erformance of the resultin( chi). "ence circuit desi(ners must ha6e a 8or4in( 4no8led(e of chi)

fabrication to create effecti6e desi(ns and in order to o)timie the circuits 8ith res)ect to 6arious

manufacturin( )arameters.

N =S3 has re6olutionied the electronic industry and has a 8ide ran(e of a))lications li4e

micro)rocessors memory de6ices !S$ chi)s in communication multimedia sensors embedded

systems etc.

N There are certain factors that )ose as future challen(es for further inte(ration. Thou(h the trend in

inte(ration may continue for another cou)le of decades but maybe after that there may be a need toin6ent ne8 materials for further inte(rationP as of today no such other material is 4no8n.

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Re+e!en)e1%

1. $rinci)les of +/S =S3 desi(n L9amran Eshra(hian

2 !i(ital desi(n )rinci)les A )ractices LKohn . Wa4erly.

;.htt)H888.nationmaster.comencyclo)edia

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