roprocessor and microcontroller

Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Module 1 learning unit 1

• A Computer is a programmable machine. • The two principal characteristics of a computer are: • It responds to a specific set of instructions in a well-defined manner. • It can execute a prerecorded list of instructions (a program ). • Modern computers are electronic and digital. • The actual machinery wires, transistors, and circuits is called hardware. the

instructions and data are called software. •

• All general-purpose computers require the following hardware components: • Memory: Enables a computer to store, at least temporarily, data and programs. • Mass storage device: Allows a computer to permanently retain large amounts of

data. Common mass storage devices include disk drives and tape drives. • Input device: Usually a keyboard and mouse are the input device through which

data and instructions enter a computer. • Output device: A display screen, printer, or other device that lets you see what

the computer has accomplished. • Central processing unit (CPU): The heart of the computer, this is the component

that actually executes instructions. • In addition to these components, many others make it possible for the basic

components to work together efficiently. • For example, every computer requires a bus that transmits data from one part of

the computer to another.

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1


• Computers can be generally classified by size and power as follows, though there is considerable overlap:

• Personal computer: A small, single-user computer based on a microprocessor. • In addition to the microprocessor, a personal computer has a keyboard for

entering data, a monitor for displaying information, and a storage device for saving data.

• Working station: A powerful, single-user computer. A workstation is like a personal computer, but it has a more powerful microprocessor and a higher-quality monitor.

• Minicomputer: A multi-user computer capable of supporting from 10 to hundreds of users simultaneously.

• Mainframe: A powerful multi-user computer capable of supporting many hundreds or thousands of users simultaneously.

• Supercomputer: An extremely fast computer that can perform hundreds of millions of instructions per second.

Minicomputer: • A midsized computer. In size and power, minicomputers lie between workstations

and mainframes. • A minicomputer, a term no longer much used, is a computer of a size intermediate

between a microcomputer and a mainframe. • Typically, minicomputers have been stand-alone computers (computer systems

with attached terminals and other devices) sold to small and mid-size businesses for general business applications and to large enterprises for department-level operations.

• In recent years, the minicomputer has evolved into the "mid-range server" and is part of a network. IBM's AS/400e is a good example.

• The AS/400 - formally renamed the "IBM iSeries," but still commonly known as AS/400 - is a midrange server designed for small businesses and departments in large enterprises and now redesigned so that it will work well in distributed networks with Web applications.

• The AS/400 uses the PowerPC microprocessor with its reduced instruction set computer technology. Its operating system is called the OS/400.

• With multi-terabytes of disk storage and a Java virtual memory closely tied into the operating system, IBM hopes to make the AS/400 a kind of versatile all-purpose server that can replace PC servers and Web servers in the world's businesses, competing with both Wintel and Unix servers, while giving its present enormous customer base an immediate leap into the Internet.

Workstation: 1) A type of computer used for engineering applications (CAD/CAM), desktop

publishing, software development, and other types of applications that require a moderate amount of computing power and relatively high quality graphics capabilities.

• Workstations generally come with a large, high- resolution graphics screen, at least 64 MB (mega bytes) of RAM, built-in network support, and a graphical user interface.



• Most workstations also have a mass storage device such as a disk drive, but a special type of workstation, called a diskless workstation, comes without a disk drive.

• The most common operating systems for workstations are UNIX and Windows NT.

• In terms of computing power, workstations lie between personal computers and minicomputers, although the line is fuzzy on both ends.

• High-end personal computers are equivalent to low-end workstations. And high-end workstations are equivalent to minicomputers.

• Like personal computers, most workstations are single-user computers. However, workstations are typically linked together to form a local-area network, although they can also be used as stand-alone systems.

2) In networking, workstation refers to any computer connected to a local-area network. It could be a workstation or a personal computer. • Mainframe: A very large and expensive computer capable of supporting

hundreds, or even thousands, of users simultaneously. In the hierarchy that starts with a simple microprocessors (in watches, for example) at the bottom and moves to supercomputer at the top, mainframes are just below supercomputers.

• In some ways, mainframes are more powerful than supercomputers because they support more simultaneous programs.

• But supercomputers can execute a single program faster than a mainframe. The distinction between small mainframes and minicomputers is vague, depending really on how the manufacturer wants to market its machines.

• Microcomputer: The term microcomputer is generally synonymous with personal computer, or a computer that depends on a microprocessor.

• Microcomputers are designed to be used by individuals, whether in the form of PCs, workstations or notebook computers.

• A microcomputer contains a CPU on a microchip (the microprocessor), a memory system (typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard.

• Microprocessor: A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably.

• A microprocessor (sometimes abbreviated µP) is a digital electronic component with miniaturized transistors on a single semiconductor integrated circuit (IC).

• One or more microprocessors typically serve as a central processing unit (CPU) in a computer system or handheld device.

• Microprocessors made possible the advent of the microcomputer. • At the heart of all personal computers and most working stations sits a

microprocessor. • Microprocessors also control the logic of almost all digital devices, from clock

radios to fuel-injection systems for automobiles. • Three basic characteristics differentiate microprocessors: • Instruction set: The set of instructions that the microprocessor can execute. • Bandwidth: The number of bits processed in a single instruction. • Clock speed: Given in megahertz (MHz), the clock speed determines how many

instructions per second the processor can execute.



• In both cases, the higher the value, the more powerful the CPU. For example, a 32 bit microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz.

• In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer).

• Supercomputer: A supercomputer is a computer that performs at or near the currently highest operational rate for computers.

• A supercomputer is typically used for scientific and engineering applications that must handle very large databases or do a great amount of computation (or both).

• At any given time, there are usually a few well-publicized supercomputers that operate at the very latest and always incredible speeds.

• The term is also sometimes applied to far slower (but still impressively fast) computers.

• Most supercomputers are really multiple computers that perform parallel processing.

• In general, there are two parallel processing approaches: symmetric multiprocessing (SMP) and massively parallel processing (MPP).

• Microcontroller: A highly integrated chip that contains all the components comprising a controller.

• Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers. • Unlike a general-purpose computer, which also includes all of these components,

a microcontroller is designed for a very specific task - to control a particular system.

• A microcontroller differs from a microprocessor, which is a general-purpose chip that is used to create a multi-function computer or device and requires multiple chips to handle various tasks.

• A microcontroller is meant to be more self-contained and independent, and functions as a tiny, dedicated computer.

• The great advantage of microcontrollers, as opposed to using larger microprocessors, is that the parts-count and design costs of the item being controlled can be kept to a minimum.

• They are typically designed using CMOS (complementary metal oxide semiconductor) technology, an efficient fabrication technique that uses less power and is more immune to power spikes than other techniques.

• Microcontrollers are sometimes called embedded microcontrollers, which just means that they are part of an embedded system that is, one part of a larger device or system.

• Controller: A device that controls the transfer of data from a computer to a peripheral device and vice versa.

• For example, disk drives, display screens, keyboards and printers all require controllers.

• In personal computers, the controllers are often single chips. • When you purchase a computer, it comes with all the necessary controllers for

standard components, such as the display screen, keyboard, and disk drives.



• If you attach additional devices, however, you may need to insert new controllers that come on expansion boards.

• Controllers must be designed to communicate with the computer's expansion bus. • There are three standard bus architectures for PCs - the AT bus, PCI (Peripheral

Component Interconnect ) and SCSI. • When you purchase a controller, therefore, you must ensure that it conforms to

the bus architecture that your computer uses. • Short for Peripheral Component Interconnect, a local bus standard developed by

Intel Corporation. • Most modern PCs include a PCI bus in addition to a more general IAS expansion

bus. • PCI is also used on newer versions of the Macintosh computer. • PCI is a 64-bit bus, though it is usually implemented as a 32 bit bus. It can run at

clock speeds of 33 or 66 MHz. • At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps. • Short for small computer system interface, a parallel interface standard used by

Apple Macintosh computers, PCs, and many UNIX systems for attaching peripheral devices to computers.

• Nearly all Apple Macintosh computers, excluding only the earliest Macs and the recent iMac, come with a SCSI port for attaching devices such as disk drives and printers.

• SCSI interfaces provide for faster data transmission rates (up to 80 megabytes per second) than standard serial and parallel ports. In addition, you can attach many devices to a single SCSI port, so that SCSI is really an I/O bus rather than simply an interface

• Although SCSI is an ANSI standard, there are many variations of it, so two SCSI interfaces may be incompatible.

• For example, SCSI supports several types of connectors. • While SCSI has been the standard interface for Macintoshes, the iMac comes with

IDE, a less expensive interface, in which the controller is integrated into the disk or CD-ROM drive.

• The following varieties of SCSI are currently implemented: • SCSI-1: Uses an 8-bit bus, and supports data rates of 4 MBps. • SCSI-2: Same as SCSI-1, but uses a 50-pin connector instead of a 25-pin

connector, and supports multiple devices. This is what most people mean when they refer to plain SCSI.

• Wide SCSI: Uses a wider cable (168 cable lines to 68 pins) to support 16-bit transfers.

• Fast SCSI: Uses an 8-bit bus, but doubles the clock rate to support data rates of 10 MBps.

• Fast Wide SCSI: Uses a 16-bit bus and supports data rates of 20 MBps. • Ultra SCSI: Uses an 8-bit bus, and supports data rates of 20 MBps. • Wide Ultra2 SCSI: Uses a 16-bit bus and supports data rates of 80 MBps. • SCSI-3: Uses a 16-bit bus and supports data rates of 40 MBps. Also called Ultra

Wide SCSI. • Ultra2 SCSI: Uses an 8-bit bus and supports data rates of 40 MBps.



• Embedded system: A specialized computer system that is part of a larger system or machine.

• Typically, an embedded system is housed on a single microprocessor board with the programs stored in ROM.

• Virtually all appliances that have a digital Interface- watches, microwaves, VCRs, cars -utilize embedded systems.

• Some embedded systems include an operating system, but many are so specialized that the entire logic can be implemented as a single program.

MICRO CONTROLLER MICRO PROCESSER

• It is a single chip • It is a CPU • Consists Memory,

I/o ports • Memory, I/O Ports to be

connected externally

Definitions:

CPCPU MEMORY

MEMORY

I/O PORTS I/O PORTS

• A Digital Signal Processor is a special-purpose CPU (Central Processing Unit) that provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive signal processing applications.

• A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real time.

Digital – operating by the use of discrete signals to represent data in the form of

numbers. Signal

– a variable parameter by which information is conveyed through an electronic circuit.

Processing – to perform operations on data according to programmed instructions.

Digital Signal processing – changing or analysing information which is measured as discrete

sequences of numbers. • Digital signal processing (DSP) is the study of signals in a digital representation

and the processing methods of these signals. • DSP and analog signal processing are subfields of signal processing.



DSP has three major subfields: • Audio signal processing, Digital image processing and Speech processing. • Since the goal of DSP is usually to measure or filter continuous real-world analog

signals, the first step is usually to convert the signal from an analog to a digital form, by using an analog to digital converter.

• Often, the required output signal is another analog output signal, which requires a digital to analog converter.

Characteristics of Digital Signal Processors: • Separate program and data memories (Harvard architecture). • Special Instructions for SIMD (Single Instruction, Multiple Data) operations. • Only parallel processing, no multitasking. • The ability to act as a direct memory access device if in a host environment. • Takes digital data from ADC (Analog-Digital Converter) and passes out data

which is finally output by converting into analog by DAC (Digital-Analog Converter).

• analog input-->ADC-->DSP-->DAC--> analog output. Analog front end Analog back end

DSP Processor

Analog signal output

Antialiasing filter, S/H, A/D converter

D/A converter, reconstruction filter

Analog signal in

DAP System Multiply-accumulate hardware:

• Multiply accumulate is the most frequently used operation in digital signal processing.

• In order to implement this efficiently, the DSP has an hardware multiplier, an accumulator with an adequate number of bits to hold the sum of products and at explicit multiply-accumulate instructions.

• Harvard architecture: in this memory architecture, there are two memory spaces. Program memory and data memory.



X Yn n

Multiplier

Product register

2n

ADD / SUB

Accumulator

2n

A MAC



X Y 16 16

Multiplier

32

• The processor core connects to these memory spaces by two separate bus sets,

allowing two simultaneous access to memory. This arrangement doubles the processor memory bandwidth.

• • Zero-overhead looping: one common characteristics of DSP algorithms is that

most of the processing time is split on executing instructions contained with relatively small loops.

• The term zero overhead looping means that the processor can execute loops without consuming cycles to test the value of the loop counter, perform a conditional branch to the top of the loop, and decrement the loop counter.

A MAC unit with accumulator guard bits

ADD / SUB

40

40 Guard bits

8 32



Processing unit

Result Data bus

Operands

Status Opcode Data / Instructions Instructions

Data program memory

Control unit

Von Neuman Architecture

Processing unit

Result / operands Data memory

Control unit Program memory

Status Opcode

Address

Instructions

Address

Harvard Architecture



• The advantages of DSP are:

Versatility: • digital systems can be reprogrammed for other applications (at least where

programmable DSP chips are used) • digital systems can be ported to different hardware (for example a different DSP

chip or board level product) Repeatability:

• digital systems can be easily duplicated • digital system responses do not drift with temperature

Processing unit

Result / operands Data memory

Address

Control unit program memory

Status Opcode

Instructions

Address

Modified Harvard Architecture

Internal Architecture of the TMS320C5X DSP

Data bus

Program bus

MEMORY

Data bus

CPU

Parallel logic unit (PAL)

MuAccumulator ACC buffer shifters arithmetic logic unit (ALU)

ltiplier CALU Memory

mapped registers

Auxiliary Resisters Arithmetic Unit (ARAU)

Program controller Program counter Status/control

registers Hardware stack Generation logic

IInitialisation

nstruction register

Memory control Multiprocessing

Interrupt

Oscillator/ timer

Program ROM

Data / program SARAM Data /

program DARAM

Data DARAM

Peripheral Serial port 1

Serial port 2

TDM Serial port Buffered serial

Timer

Host port interface

Test / emulation

port



• digital systems do not depend on strict component tolerances. •

Simplicity: • some things can be done more easily digitally than with analogue systems • DSP is used in a very wide variety of applications but most share some common

features: • they use a lot of multiplying and adding signals. • they deal with signals that come from the real world. • they require a response in a certain time. •

Figure: A block diagram (or dataflow graph)

• What is the difference between a DSP and a microprocessor ? • The essential difference between a DSP and a microprocessor is that a DSP

processor has features designed to support high-performance, repetitive, numerically intensive tasks.

• In contrast, general-purpose processors or microcontrollers (GPPs / MCUs for short) are either not specialized for a specific kind of applications (in the case of general-purpose processors), or they are designed for control-oriented applications (in the case of microcontrollers).

• Features that accelerate performance in DSP applications include: • Single-cycle multiply-accumulate capability; high-performance DSPs often have

two multipliers that enable two multiply-accumulate operations per instruction cycle; some DSP have four or more multipliers.

• • Specialized addressing modes, for example, pre- and post-modification of address

pointers, circular addressing, and bit-reversed addressing. • Most DSPs provide various configurations of on-chip memory and peripherals

tailored for DSP applications. DSPs generally feature multiple-access memory architectures that enable DSPs to complete several accesses to memory in a single instruction cycle.



• Specialized execution control. Usually, DSP processors provide a loop instruction that allows tight loops to be repeated without spending any instruction cycles for updating and testing the loop counter or for jumping back to the top of the loop

• DSP processors are known for their irregular instruction sets, which generally allow several operations to be encoded in a single instruction.

• For example, a processor that uses 32-bit instructions may encode two additions, two multiplications, and four 16-bit data moves into a single instruction.

• In general, DSP processor instruction sets allow a data move to be performed in parallel with an arithmetic operation. GPPs / MCUs, in contrast, usually specify a single operation per instruction.

• What is really important is to choose the processor that is best suited for your application.

• If a GPP/MCU is better suited for your DSP application than a DSP processor, the processor of choice is the GPP/MCU.

• It is also worth noting that the difference between DSPs and GPPs/MCUs is fading: many GPPs/MCUs now include DSP features, and DSPs are increasingly adding microcontroller features.

Module 1: learning unit 2 8085 Microprocessor ContentsGeneral definitions

• Overview of 8085 microprocessor • Overview of 8086 microprocessor • Signals and pins of 8086 microprocessor

The salient features of 8085 µp are: • It is a 8 bit microprocessor. • It is manufactured with N-MOS technology. • It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)

memory locations through A0-A15. • The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7. • Data bus is a group of 8 lines D0 – D7. • It supports external interrupt request. • A 16 bit program counter (PC) • A 16 bit stack pointer (SP) • Six 8-bit general purpose register arranged in pairs: BC, DE, HL. • It requires a signal +5V power supply and operates at 3.2 MHZ single phase

clock. • It is enclosed with 40 pins DIP (Dual in line package).

Overview of 8085 microprocessor 8085 Architecture

• Pin Diagram • Functional Block Diagram



Pin Diagram of 8085 Signal Groups of 8085

20

19 18 17 16

15 14

13

12 11

1

2 3 4 5 6 7 8

9 10

21

22 23

24 25 26 27 28 29

30

40 39 38 37 36 35 34 33 32

31

X1 Vcc X2 HOLD DMA

RESE OUT HLDACLK ( OUT) SOD

RESET INSerial i/p, o/p signals SID

READY TRAP IO / M

RST 7.5 S1 RST 6.5 8085 A RST 5.5RD

INTR WR

IN T A ALEAD0

S0AD1 A15

AD2 A14

AD3 A13

AD4 A12

AD5 A11

A10AD6

AD7 A9

A8 VSS

GND + 5 V

VssVccX1

XTALX2

4

5

SOD

SID A15High order Address bus

A8

REST OUT CLK OUT

WR

____

RD

IO / M

S0

S1

ALEAD0

AD7

HLDA

INTA

READY HOLD

RESET IN

INTR RESET 5.5 RESET 6.5 RESET 7.5

TRAP



RES RES RES TRAP SID INTA SIO 5. 5 6. 5 7. 5

Block Diagram

GND

+5V

X1

X2

TIMING AND CONTROLCLK GEN

CLK OUT READY

CONTROL

RD ALE S0 S1 RESET OUT IO / M HOLD HLDA

DMA STATUS

RESET IN

ARITHEMETIC LOGIC UNIT ( ALU)

(8)

ACCUMU-LATOR TEMP REG

(8)

(8)

FLAG ( 5) FLIP FLOPS

INTERRUPT CONTROL SERIAL I / O CONTROL INT

8 BIT INTERNAL DATA BUS

INSTRUCTION REGISTER MULTIPLXER

( 8 )

W ( 8 ) RTEMP. REG. E

C REG ( 8 ) G.

B REG ( 8 ) D REG ( 8 )S E REG ( 8 )

E H REG ( 8 ) INSTRUCTION DECODER AND MACHINE ENCODING

L REG ( 8 ) LE STACK POINTER CT

ADDRESS BUFFER ( 8 )

DATA / ADDRESS BUFFER ( 8 )

PROGRAM COUNTER ( 16 ) INCREAMENT / DECREAMENT ADDRESS LATCH ( 16 )

( 16 )

A 15 – A8 ADDRESS BUS AD7 – AD0 ADDRESS /

BUFFER BUSWR

Flag Registers D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

General Purpose Registers INDIVIDUAL B, C, D, E, H, L

COMBININATON B & C, D & E, H & L



Memory gram, data and stack memories occupy the same memory space. The total

• located anywhere in memory. Jump, branch

•

• limited only by the size of memory. Stack grows downward. T

Interrurocessor has 5 interrupts. They are presented below in the order of their

• NTR is maskable 8080A compatible interrupt. When the interrupt occurs the

: •

is a

• subroutine, address

• ocessor

• terrupt. When this interrupt is received the processor

• terrupt. When this interrupt is received the processor

• e interrupt. When this interrupt is received the processor

• can be enabled or disabled using EI and DI instructions.

Reset S IN: When this signal goes low, the program counter (PC) is set to Zero,

• ing RESET and

• to an R-C network

• Proaddressable memory size is 64 KB. Program memory - program can beand call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing. Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere. Stack memory is

• First 64 bytes in a zero memory page should be reserved for vectors used by RSinstructions. pts

• The ppriority (from lowest to highest):

• Iprocessor fetches from the bus one instruction, usually one of these instructionsOne of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N3-bit number from 0 to 7 supplied with the RST instruction). CALL instruction (3 byte instruction). The processor calls the of which is specified in the second and third bytes of the instruction. RST5.5 is a maskable interrupt. When this interrupt is received the prsaves the contents of the PC register into stack and branches to 2CH (hexadecimal) address. RST6.5 is a maskable insaves the contents of the PC register into stack and branches to 34H (hexadecimal) address. RST7.5 is a maskable insaves the contents of the PC register into stack and branches to 3CH (hexadecimal) address. TRAP is a non-maskablsaves the contents of the PC register into stack and branches to 24H (hexadecimal) address. All maskable interrupts RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction. ignals

• RESETµp is reset and resets the interrupt enable and HLDA flip-flops. The data and address buses and the control lines are 3-stated durbecause of asynchronous nature of RESET, the processor internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connectionfor power-on RESET delay.



• Upon power-up, RESET IN must remain low for at least 10 ms after minimum Vcc has been reached.

• For proper reset operation after the power – up duration, RESET IN should be kept low a minimum of three clock periods.

• The CPU is held in the reset condition as long as RESET IN is applied. Typical Power-on RESET RC values R1 = 75KΩ, C1 = 1µF.

• RESET OUT: This signal indicates that µp is being reset. This signal can be used to reset other devices. The signal is synchronized to the processor clock and lasts an integral number of clock periods.

Serial communication Signal • SID - Serial Input Data Line: The data on this line is loaded into accumulator bit

7 whenever a RIM instruction is executed. • SOD – Serial Output Data Line: The SIM instruction loads the value of bit 7 of

the accumulator into SOD latch if bit 6 (SOE) of the accumulator is 1. DMA Signals • HOLD: Indicates that another master is requesting the use of the address and data

buses. The CPU, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer.

• Internal processing can continue. The processor can regain the bus only after the HOLD is removed.

• When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are 3-stated.

• HLDA: Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle.

• HLDA goes low after the Hold request is removed. The CPU takes the bus one half-clock cycle after HLDA goes low.

• READY: This signal Synchronizes the fast CPU and the slow memory, peripherals.

• If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data.

• If READY is low, the CPU will wait an integral number of clock cycle for READY to go high before completing the read or write cycle.

• READY must conform to specified setup and hold times. Registers • Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and

load/store operations. • Flag Register has five 1-bit flags. • Sign - set if the most significant bit of the result is set. • Zero - set if the result is zero. • Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result. • Parity - set if the parity (the number of set bits in the result) is even. • Carry - set if there was a carry during addition, or borrow during

subtraction/comparison/rotation.



General Registers • 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When

used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.

• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.

• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

• Stack pointer is a 16 bit register. This register is always decremented/incremented by 2 during push and pop.

• Program counter is a 16-bit register. Instruction Set • 8085 instruction set consists of the following instructions: • Data moving instructions. • Arithmetic - add, subtract, increment and decrement. • Logic - AND, OR, XOR and rotate. • Control transfer - conditional, unconditional, call subroutine, return from

subroutine and restarts. • Input/Output instructions. • Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations,

etc. Addressing mode

• Register - references the data in a register or in a register pair. Register indirect - instruction specifies register pair containing address, where the data is located. Direct, Immediate - 8 or 16-bit data.

Module 1: learning unit 3 8086 Microprocessor

•It is a 16-bit µp. •8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). •It can support up to 64K I/O ports. •It provides 14, 16 -bit registers. •It has multiplexed address and data bus AD0- AD15 and A16 – A19. •It requires single phase clock with 33% duty cycle to provide internal timing. •8086 is designed to operate in two modes, Minimum and Maximum. •It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. •It requires +5V power supply. •A 40 pin dual in line package Minimum and Maximum Modes: •The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single microprocessor configuration. •The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration.



GND

Pin Diagram of 8086

20

19 18 17 16

15 14

13

12 11

1

2 3 4 5 6 7 8

9 10

21

22 23

24 25 26 27 28 29

30

40 39 38 37 36 35 34 33 32

31

VCC

AD14 AD15

AD13 A16 / S3

AD12 A17 / S4A18 / S5 AD11

A19/S6AD10BHE / S7 AD9

8086 ____

AD8 MN/ MXAD7 CPU RD _____ _____ AD6 RQ / GT0 ( HOLD) ___ _____AD5 RQ / GT1

GND

CLK

INTR

NMI

AD4

AD3

AD2

AD1

AD0

RESET

_______ ___

( HLDA) LOCK (WR) ____

(M / IO ) 2S ___ ___

READY

TEST

QS1

1S _____ (DT / R )

( DEN )0S QS0 (ALE) ________

( INTA )



VCC

Signal Groups of 8086

GND

A0 - A15, A16 / S3 – A19/S6

INTR

CLK

INTA ADDRESS / DATA BUS INTERRUPT INTERFACE

TEST D0 - D15

8086 NMI ALE MPU ___

BHE / S7 RESET

M / IO MEMORY I / O DT / R HOLD DMA ____ CONTROLS

HLDA

VCC

____

MN / MX

INTERFACE _____ RD

WR

DEN MODE SELECT READY



AH AL

Block Diagram of 8086 Internal Architecture of 8086 •8086 has two blocks BIU and EU. •The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. •EU executes instructions from the instruction system byte queue. •Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. •BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. •EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. BUS INTERFACR UNIT: •It provides a full 16 bit bidirectional data bus and 20 bit address bus. •The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: •Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. •The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. •This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU

BH BLCH CLDH DL

SP BP SI DI

ESCSSSDSIP

ADDRESS BUS∑

( 20 ) BITS GENERAL

REGISTERS DATA BUS

( 16 ) BITS

ALU DATA 8

16 BITS 0 8 BUS 6

CONTROL LOGIC

1

BUS

TEMPORARY REGISTERS

EU CONTROL SYSTEM

INSTRUCTION QUEUE ALU Q BUS

2 3 4 5 6 8 BIT

FLAGS BUS INTERFACE UNIT ( BIU) EXECUTION UNIT ( EU )



is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. •These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. •After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. •The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. •These intervals of no bus activity, which may occur between bus cycles are known as Idle state. •If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. •The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. •For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. •The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. EXECUTION UNIT The Execution unit is responsible for decoding and executing all instructions. •The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. •During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. •If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. •When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. •Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue. Module 1 and learning unit 4: Signal Description of 8086•The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. •The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode) and other function in maximum mode configuration (multiprocessor mode ). •The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as well as maximum mode. •The second are the signals which have special functions for minimum mode and third are the signals having special functions for maximum mode.



•The following signal descriptions are common for both modes. •AD15-AD0: These are the time multiplexed memory I/O address and data lines. • Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. •These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. •A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status lines. •During T1 these are the most significant address lines for memory operations. •During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. •The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. •The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as in below fig. •These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low. •The address bit are separated from the status bit using latches controlled by the ALE signal.

S3 S4

• BHE /S7: The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledges cycle.

• RD Read: This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge.

Alternate Data

Indication

0 0 Stack 0

Code or none Data 1 0

1

1 1

Upper byte from or to odd address

A0 BHE Indication Whole word 0 0

0 1 0

1 Lower byte from or to even address Upper byte from or to even address

1 None 1



•READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high. •INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. •This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. • TESTThis input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. •CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. •MN/ MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode. •The following pin functions are for the minimum mode operation of 8086. •M/ IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge “. • INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. •ALE – Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. •DT/ R – Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. •DEN – Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle. •HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. •The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.•At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. •If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided: 1.The request occurs on or before T2 state of the current cycle. 2.The current cycle is not operating over the lower byte of a word. 3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.



4. A Lock instruction is not being executed. •The following pin function are applicable for maximum mode operation of 8086. •S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.

• LOCK This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low. •The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. •The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller. •QS1, QS0 – Queue Status: These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after while the queue operation is performed. •This modification in a simple fetch and execute architecture of a conventional microprocessor offers an added advantage of pipelined processing of the instructions. •The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-bytes) instruction can be prefetched from the memory and stored in the prefetch. This results in a faster execution of the instructions. •In 8085 an instruction is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched. •By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipelining. •At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even. •The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte. •The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data.

1 1

S2 S1 S0 Indication 0 Interrupt Acknowledge

1

0 0 0

1 1 1

1

1 1

1

1

1

0 0 0

Read I/O port Write I/O port 0 Halt

0

0 0 0 Code Access

Passive Write memory Read memory

1 1



•The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions. •The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program.•The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit. •While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.

QS1 QS0 Indication No operation

• RQ / 0GT , RQ / 1GT – Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. •Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. •RQ/GT pins have internal pull-up resistors and may be left unconnected. •Request/Grant sequence is as follows: 1.A pulse of one clock wide from another bus master requests the bus access to 8086. 2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system. 3.A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange. •The request and grant pulses are active low. •For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode. General Bus Operation: •The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. •The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package.

0

1 1 1

1 0

First byte of the opcode from the queue 0 Empty queue 0 Subsequent byte from the queue



•The bus can be demultiplexed using a few latches and transreceivers, when ever required. •Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle. •The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. •Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Minimum Mode 8086 System •In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. •In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. •The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. •Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.

General Bus Operation Cycle in Maximum Mode

CLK

Memory read cycle Memory write cycle T1 T2 T3 Tw T4 T1 T2 T3 Tw T4

ALE

S2 – S0

A19-A16 S3-S7 A19-A16 S3-S7Add/stat

BHE BHE

WR

Bus reserve

DEN

DT/R

READY

RD/INTA

Add/data A0-A15 D15-D0 A0-A15

Data Out D15 – D0 for Data In D15-D0

Ready Ready

Wait Wait

Memory access time



•Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. •They are controlled by two signals namely, DEN and DT/R. •The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. •Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices. •The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. •The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. •The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus. •The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation. •At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2. •The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. •The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers. •A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. •The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). •The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. •The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.



T1 T2 T3 TW T4 T1

Clk

ALE

A –BHE S7 – S3ADD / STATUS 19 A16

ADD / DATA A15 – A0 Valid data D15 – D0

WR

DEN

DT / R

Write Cycle Timing Diagram for Minimum Mode •Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to another requesting master. •The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock.

Clk

HOLD

HLDA

Bus Request and Bus Grant Timings in Minimum Mode System



Maximum Mode 8086 System •In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. •In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information. •In the maximum mode, there may be more than one microprocessor in the system configuration. •The components in the system are same as in the minimum mode system. •The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines. •The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU. •It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. •AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin. •If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations. •INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. •IORC, IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. •The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. •All these command signals instructs the memory to accept or send data from or to the bus. •For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available. •Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.



•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1. •In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. •The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. •If reader input is not activated before T3, wait state will be inserted between T3 and T4. •Timings for RQ/ GT Signals: The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input. •When a request is detected and if the condition for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state. •When the requesting master receives this pulse, it accepts the control of the bus, it sends a release pulse to the processor using RQ/GT pin.

Clk DEN S0 DT/ R Control bus

Maximum Mode 8086 System.

Reset

RDY

Clk Generator

8284

Reset Clk Ready

8086 AD -AD6

A15

16-A19A/D

DEN G

DIR

DT/R

Data buffer

Data bus

PeripheralCS WR RD

S0

S1

S2

S1

S2

IORC 8288 IOWTMWTC AEN

IOB MRDC ALCEN + 5V

CLK Address bus Latches

Add bu

A0BHE

CS0H CS0L

Memory WR RD



Memory Read Timing in Maximum Mode

T1 T2 T3

One bus cycle T4 T1

Clk

ALE

Inactive S2 – S0 Active Active

Add/Status BHE, A19 – A16 S7 – S3

Add/Data A15 – A0 D15 – D0

MRDC

DT / R

DEN



Minimum Mode Interface •When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface.

Memory Write Timing in Maximum mode.

T1 T2 T3

One bus cycle T4 T1

Clk

ALE

Inactive S2 – S0 Active Active

ADD/STATUS BHE S7 – S3

A15-A0 Data out D15 – D0ADD/DATA

AMWC or AIOWC

MWTC or IOWC

high DT / R DEN

RQ/GT Timings in Maximum Mode.

Clk

RQ / GT

Another master request bus access

Master releases CPU grant bus



•The minimum mode signal can be divided into the following basic groups: address/data bus, status, control, interrupt and DMA. •Address/Data Bus: these lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length. •The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. •When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.

Vcc GND

INTR A0-A15,A16/S3 – A19/S6

INTA Interrupt interface Address / data bus

TEST

D0 – D15NMI

8086 ALE MPU RESET BHE / S7

M / IO Memory I/O controls HOLD DMA

interface DT / R

RD

•Status signal: The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines. •Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle. •Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.

WR

DEN

READY

HLDA

Vcc

Mode select

MN / MX

CLK clock

Block Diagram of the Minimum Mode 8086 MPU



•Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.

S4 S3 Segment Register

•Control Signals: The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus. •ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. •Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serves a second function, which is as the S7 status line. •Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. •The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. •The direction of data transfer over the bus is signaled by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device.

0 0 Extra

1 Stack 0

1 0 Code / none

1 1 Data

Memory segment status codes.



•On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. •The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. • On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when they should put data on the bus. •There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. •READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the data transfer to be completed. •Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge ( INTA). •INTR is an input to the 8086 that can be used by an external device to signal that it need to be serviced. •Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output. •The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input. •If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer executes instructions, instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. •As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware. •There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the reset interrupt RESET. •On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine. •DMA Interface signals:The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. •When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level. Maximum Mode Interface •When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environment.



•By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. •Usually in this type of system environment, there are some system resources that are common to all processors. •They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources. •Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. •One passes the control of the system bus to the other and then may suspend its operation. •In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.

•8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. •Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. •S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals.

MN/MX

RESET

NMI TEST

INTR

RQ / GT1 RQ / GT0

8086 MPU

Vcc GND CLK

CRQLCK

ANYREQ

RESB SYSB/RESB

AEN IOB LOCK S0

S1

S2

CLK

S0

S1

S2

CLK AEN IOB

S0

S1

S2LOCK

8289 Bus

CLK AEN IOB

8288 Bus controller

DENDT/ R ALE

Local bus control

QS1, QS0

READY RD

BHE

D0 – D15

A0-A15, A16/S3-A19/S6

ALE

DEN DT / R

MCE / PDEN INTA

AIOWC IOWC

MRDC MWTC

AMWC IORC

BCLK

BREQ

BPRN

BPRO CBRQ BUSY

INIT Multi Bus

8086 Maximum mode Block Diagram



Status Inputs 8288 Command

CPU Cycles S2 S1 S0

Interrupt Acknowledge 0 INTA 0 0 IORC

•The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read cycle is to be performed. •In the code 111 is output by the 8086, it is signaling that no bus activity is to take place. •The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems. •The output of 8289 are bus arbitration signals: Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock (BCLK). •They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086. •In this way the processor can be assured of uninterrupted access to common system resources such as global memory. •Queue Status Signals: Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0. •Following table shows the four different queue status.

Bus Status Codes

0 0 0

1

1

1

1 1 1

0

0

0

1 1

1 0 1

0

1

0

1

Read I/O Port IOWC, AIOWC Write I/O Port

None Halt MRDC Instruction Fetch MRDC Read Memory

MWTC, AMWC

None

Write Memory

Passive



Queue Status QS1 QS0

No Operation. During the last clock cycle, nothing was taken from the queue.

0 0 (low)

•Local Bus Control Signal – Request / Grant Signals: In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus. Internal Registers of 8086 •The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. •The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. •Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: •Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. •Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. •Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. •Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.

0 1 First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction.

1 (high) 0

1 1 Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.

Queue status codes



•Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. •Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation,. •Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. •The following registers are both general and index registers: •Stack Pointer (SP) is a 16-bit register pointing to program stack. •Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. •Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. •Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: •Instruction Pointer (IP) is a 16-bit register. •Flags is a 16-bit register containing 9 one bit flags. •Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand. •Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. •Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts. •Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction. •Sign Flag (SF) - set if the most significant bit of the result is set. •Zero Flag (ZF) - set if the result is zero. •Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. •Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. •Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation. Addressing Modes •Implied - the data value/data address is implicitly associated with the instruction. •Register - references the data in a register or in a register pair. •Immediate - the data is provided in the instruction. •Direct - the instruction operand specifies the memory address where data is located.



•Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. •Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. •Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides •Based Indexed:- the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. •Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides. Memory •Program, data and stack memories occupy the same memory space. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. •To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below). •16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte •Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. •All conditional jump instructions can be used to jump within approximately +127 to -127 bytes from current instruction. •Data memory - the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). •Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). •Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. •Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above). Reserved locations: •0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset. •FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. Interrupts The processor has the following interrupts:



•INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. •When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction. •NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt. •Software interrupts can be caused by: •INT instruction - breakpoint interrupt. This is a type 3 interrupt. •INT <interrupt number> instruction - any one interrupt from available 256 interrupts. •INTO instruction - interrupt on overflow •Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. •Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7). •Software interrupt processing is the same as for the hardware interrupts.


Atmel 8051 Microcontrollers Hardware 1

0509C–8051–07/06

Section 1

8051 Microcontroller Instruction Set

For interrupt response time information, refer to the hardware description chapter.

Note: 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.

Instructions that Affect Flag Settings(1)

Instruction Flag Instruction Flag

C OV AC C OV AC

ADD X X X CLR C O

ADDC X X X CPL C X

SUBB X X X ANL C,bit X

MUL O X ANL C,/bit X

DIV O X ORL C,bit X

DA X ORL C,/bit X

RRC X MOV C,bit X

RLC X CJNE X

SETB C 1

The Instruction Set and Addressing ModesRn Register R7-R0 of the currently selected Register Bank.

direct 8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)].

@Ri 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.

#data 8-bit constant included in instruction.

#data 16 16-bit constant included in instruction.

addr 16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address space.

addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction.

rel Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.

bit Direct Addressed bit in Internal Data RAM or Special Function Register.

20509C–8051–07/06

Table 1-1. Instruction Set Summary

Note: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle

0 1 2 3 4 5 6 7

0 NOP JBCbit,rel

[3B, 2C]

JBbit, rel

[3B, 2C]

JNBbit, rel

[3B, 2C]

JCrel

[2B, 2C]

JNCrel

[2B, 2C]

JZrel

[2B, 2C]

JNZrel

[2B, 2C]

1 AJMP(P0)

[2B, 2C]

ACALL(P0)

[2B, 2C]

AJMP(P1)

[2B, 2C]

ACALL(P1)

[2B, 2C]

AJMP(P2)

[2B, 2C]

ACALL(P2)

[2B, 2C]

AJMP(P3)

[2B, 2C]

ACALL(P3)

[2B, 2C]

2 LJMPaddr16[3B, 2C]

LCALLaddr16[3B, 2C]

RET[2C]

RETI[2C]

ORLdir, A[2B]

ANLdir, A[2B]

XRLdir, a[2B]

ORLC, bit

[2B, 2C]

3 RRA

RRCA

RLA

RLCA

ORLdir, #data[3B, 2C]

ANLdir, #data[3B, 2C]

XRLdir, #data[3B, 2C]

JMP@A + DPTR

[2C]

4 INCA

DECA

ADDA, #data

[2B]

ADDCA, #data

[2B]

ORLA, #data

[2B]

ANLA, #data

[2B]

XRLA, #data

[2B]

MOVA, #data

[2B]

5 INCdir

[2B]

DECdir

[2B]

ADDA, dir[2B]

ADDCA, dir[2B]

ORLA, dir[2B]

ANLA, dir[2B]

XRLA, dir[2B]

MOVdir, #data[3B, 2C]

6 INC@R0

DEC@R0

ADDA, @R0

ADDCA, @R0

ORLA, @R0

ANLA, @R0

XRLA, @R0

MOV@R0, @data

[2B]

7 INC@R1

DEC@R1

ADDA, @R1

ADDCA, @R1

ORLA, @R1

ANLA, @R1

XRLA, @R1

MOV@R1, #data

[2B]

8 INCR0

DECR0

ADDA, R0

ADDCA, R0

ORLA, R0

ANLA, R0

XRLA, R0

MOVR0, #data

[2B]

9 INCR1

DECR1

ADDA, R1

ADDCA, R1

ORLA, R1

ANLA, R1

XRLA, R1

MOVR1, #data

[2B]

A INCR2

DECR2

ADDA, R2

ADDCA, R2

ORLA, R2

ANLA, R2

XRLA, R2

MOVR2, #data

[2B]

B INCR3

DECR3

ADDA, R3

ADDCA, R3

ORLA, R3

ANLA, R3

XRLA, R3

MOVR3, #data

[2B]

C INCR4

DECR4

ADDA, R4

ADDCA, R4

ORLA, R4

ANLA, R4

XRLA, R4

MOVR4, #data

[2B]

D INCR5

DECR5

ADDA, R5

ADDCA, R5

ORLA, R5

ANLA, R5

XRLA, R5

MOVR5, #data

[2B]

E INCR6

DECR6

ADDA, R6

ADDCA, R6

ORLA, R6

ANLA, R6

XRLA, R6

MOVR6, #data

[2B]

F INCR7

DECR7

ADDA, R7

ADDCA, R7

ORLA, R7

ANLA, R7

XRLA, R7

MOVR7, #data

[2B]

30509C–8051–07/06

Table 1-2. Instruction Set Summary (Continued)

Note: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle

8 9 A B C D E F

0 SJMPREL

[2B, 2C]

MOVDPTR,#data 16[3B, 2C]

ORLC, /bit

[2B, 2C]

ANLC, /bit

[2B, 2C]

PUSHdir

[2B, 2C]

POPdir

[2B, 2C]

MOVX A,@DPTR

[2C]

MOVX@DPTR, A

[2C]

1 AJMP(P4)

[2B, 2C]

ACALL(P4)

[2B, 2C]

AJMP(P5)

[2B, 2C]

ACALL(P5)

[2B, 2C]

AJMP(P6)

[2B, 2C]

ACALL(P6)

[2B, 2C]

AJMP(P7)

[2B, 2C]

ACALL(P7)

[2B, 2C]

2 ANLC, bit

[2B, 2C]

MOVbit, C

[2B, 2C]

MOVC, bit[2B]

CPLbit

[2B]

CLRbit

[2B]

SETBbit

[2B]

MOVXA, @R0

[2C]

MOVXwR0, A

[2C]

3 MOVC A,@A + PC

[2C]

MOVC A,@A + DPTR

[2C]

INCDPTR[2C]

CPLC

CLRC

SETBC

MOVXA, @RI

[2C]

MOVX@RI, A

[2C]

4 DIVAB

[2B, 4C]

SUBBA, #data

[2B]

MULAB[4C]

CJNE A,#data, rel[3B, 2C]

SWAPA

DAA

CLRA

CPLA

5 MOVdir, dir

[3B, 2C]

SUBBA, dir[2B]

CJNEA, dir, rel[3B, 2C]

XCHA, dir[2B]

DJNZdir, rel

[3B, 2C]

MOVA, dir[2B]

MOVdir, A[2B]

6 MOVdir, @R0[2B, 2C]

SUBBA, @R0

MOV@R0, dir[2B, 2C]

CJNE@R0, #data, rel

[3B, 2C]

XCHA, @R0

XCHDA, @R0

MOVA, @R0

MOV@R0, A

7 MOVdir, @R1[2B, 2C]

SUBBA, @R1

MOV@R1, dir[2B, 2C]

CJNE@R1, #data, rel

[3B, 2C]

XCHA, @R1

XCHDA, @R1

MOVA, @R1

MOV@R1, A

8 MOVdir, R0

[2B, 2C]

SUBBA, R0

MOVR0, dir

[2B, 2C]

CJNER0, #data, rel

[3B, 2C]

XCHA, R0

DJNZR0, rel

[2B, 2C]

MOVA, R0

MOVR0, A

9 MOVdir, R1

[2B, 2C]

SUBBA, R1

MOVR1, dir

[2B, 2C]

CJNER1, #data, rel

[3B, 2C]

XCHA, R1

DJNZR1, rel

[2B, 2C]

MOVA, R1

MOVR1, A

A MOVdir, R2

[2B, 2C]

SUBBA, R2

MOVR2, dir

[2B, 2C]

CJNER2, #data, rel

[3B, 2C]

XCHA, R2

DJNZR2, rel

[2B, 2C]

MOVA, R2

MOVR2, A

B MOVdir, R3

[2B, 2C]

SUBBA, R3

MOVR3, dir

[2B, 2C]

CJNER3, #data, rel

[3B, 2C]

XCHA, R3

DJNZR3, rel

[2B, 2C]

MOVA, R3

MOVR3, A

C MOVdir, R4

[2B, 2C]

SUBBA, R4

MOVR4, dir

[2B, 2C]

CJNER4, #data, rel

[3B, 2C]

XCHA, R4

DJNZR4, rel

[2B, 2C]

MOVA, R4

MOVR4, A

D MOVdir, R5

[2B, 2C]

SUBBA, R5

MOVR5, dir

[2B, 2C]

CJNER5, #data, rel

[3B, 2C]

XCHA, R5

DJNZR5, rel

[2B, 2C]

MOVA, R5

MOVR5, A

E MOVdir, R6

[2B, 2C]

SUBBA, R6

MOVR6, dir

[2B, 2C]

CJNER6, #data, rel

[3B, 2C]

XCHA, R6

DJNZR6, rel

[2B, 2C]

MOVA, R6

MOVR6. A

F MOVdir, R7

[2B, 2C]

SUBBA, R7

MOVR7, dir

[2B, 2C]

CJNER7, #data, rel

[3B, 2C]

XCHA, R7

DJNZR7, rel

[2B, 2C]

MOVA, R7

MOVR7, A


Atmel 8051 Microcontrollers Hardware Manual 1-4

0509C–8051–07/06

Table 1-3. AT89 Instruction Set Summary(1)

Note: 1. All mnemonics copyrighted © Intel Corp., 1980.

Mnemonic Description Byte Oscillator Period

ARITHMETIC OPERATIONS

ADD A,Rn Add register to Accumulator

1 12

ADD A,direct Add direct byte to Accumulator

2 12

ADD A,@Ri Add indirect RAM to Accumulator

1 12

ADD A,#data Add immediate data to Accumulator

2 12

ADDC A,Rn Add register to Accumulator with Carry

1 12

ADDC A,direct Add direct byte to Accumulator with Carry

2 12

ADDC A,@Ri Add indirect RAM to Accumulator with Carry

1 12

ADDC A,#data Add immediate data to Acc with Carry

2 12

SUBB A,Rn Subtract Register from Acc with borrow

1 12

SUBB A,direct Subtract direct byte from Acc with borrow

2 12

SUBB A,@Ri Subtract indirect RAM from ACC with borrow

1 12

SUBB A,#data Subtract immediate data from Acc with borrow

2 12

INC A Increment Accumulator 1 12

INC Rn Increment register 1 12

INC direct Increment direct byte 2 12

INC @Ri Increment direct RAM 1 12

DEC A Decrement Accumulator 1 12

DEC Rn Decrement Register 1 12

DEC direct Decrement direct byte 2 12

DEC @Ri Decrement indirect RAM 1 12

INC DPTR Increment Data Pointer 1 24

MUL AB Multiply A & B 1 48

DIV AB Divide A by B 1 48

DA A Decimal Adjust Accumulator

1 12


LOGICAL OPERATIONS

ANL A,Rn AND Register to Accumulator

1 12

ANL A,direct AND direct byte to Accumulator

2 12

ANL A,@Ri AND indirect RAM to Accumulator

1 12

ANL A,#data AND immediate data to Accumulator

2 12

ANL direct,A AND Accumulator to direct byte

2 12

ANL direct,#data AND immediate data to direct byte

3 24

ORL A,Rn OR register to Accumulator

1 12

ORL A,direct OR direct byte to Accumulator

2 12

ORL A,@Ri OR indirect RAM to Accumulator

1 12

ORL A,#data OR immediate data to Accumulator

2 12

ORL direct,A OR Accumulator to direct byte

2 12

ORL direct,#data OR immediate data to direct byte

3 24

XRL A,Rn Exclusive-OR register to Accumulator

1 12

XRL A,direct Exclusive-OR direct byte to Accumulator

2 12

XRL A,@Ri Exclusive-OR indirect RAM to Accumulator

1 12

XRL A,#data Exclusive-OR immediate data to Accumulator

2 12

XRL direct,A Exclusive-OR Accumulator to direct byte

2 12

XRL direct,#data Exclusive-OR immediate data to direct byte

3 24

CLR A Clear Accumulator 1 12

CPL A Complement Accumulator

1 12

RL A Rotate Accumulator Left 1 12

RLC A Rotate Accumulator Left through the Carry

1 12

LOGICAL OPERATIONS (continued)


1-5 Atmel 8051 Microcontrollers Hardware Manual0509C–8051–07/06

RR A Rotate Accumulator Right

1 12

RRC A Rotate Accumulator Right through the Carry

1 12

SWAP A Swap nibbles within the Accumulator

1 12

DATA TRANSFER

MOV A,Rn Move register to Accumulator

1 12

MOV A,direct Move direct byte to Accumulator

2 12

MOV A,@Ri Move indirect RAM to Accumulator

1 12

MOV A,#data Move immediate data to Accumulator

2 12

MOV Rn,A Move Accumulator to register

1 12

MOV Rn,direct Move direct byte to register

2 24

MOV Rn,#data Move immediate data to register

2 12

MOV direct,A Move Accumulator to direct byte

2 12

MOV direct,Rn Move register to direct byte

2 24

MOV direct,direct Move direct byte to direct 3 24

MOV direct,@Ri Move indirect RAM to direct byte

2 24

MOV direct,#data Move immediate data to direct byte

3 24

MOV @Ri,A Move Accumulator to indirect RAM

1 12

MOV @Ri,direct Move direct byte to indirect RAM

2 24

MOV @Ri,#data Move immediate data to indirect RAM

2 12

MOV DPTR,#data16 Load Data Pointer with a 16-bit constant

3 24

MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc

1 24

MOVC A,@A+PC Move Code byte relative to PC to Acc

1 24

MOVX A,@Ri Move External RAM (8-bit addr) to Acc

1 24

DATA TRANSFER (continued)

MOVX A,@DPTR Move Exernal RAM (16-bit addr) to Acc

1 24


MOVX @Ri,A Move Acc to External RAM (8-bit addr)

1 24

MOVX @DPTR,A Move Acc to External RAM (16-bit addr)

1 24

PUSH direct Push direct byte onto stack

2 24

POP direct Pop direct byte from stack

2 24

XCH A,Rn Exchange register with Accumulator

1 12

XCH A,direct Exchange direct byte with Accumulator

2 12

XCH A,@Ri Exchange indirect RAM with Accumulator

1 12

XCHD A,@Ri Exchange low-order Digit indirect RAM with Acc

1 12

BOOLEAN VARIABLE MANIPULATION

CLR C Clear Carry 1 12

CLR bit Clear direct bit 2 12

SETB C Set Carry 1 12

SETB bit Set direct bit 2 12

CPL C Complement Carry 1 12

CPL bit Complement direct bit 2 12

ANL C,bit AND direct bit to CARRY 2 24

ANL C,/bit AND complement of direct bit to Carry

2 24

ORL C,bit OR direct bit to Carry 2 24

ORL C,/bit OR complement of direct bit to Carry

2 24

MOV C,bit Move direct bit to Carry 2 12

MOV bit,C Move Carry to direct bit 2 24

JC rel Jump if Carry is set 2 24

JNC rel Jump if Carry not set 2 24

JB bit,rel Jump if direct Bit is set 3 24

JNB bit,rel Jump if direct Bit is Not set

3 24

JBC bit,rel Jump if direct Bit is set & clear bit

3 24

PROGRAM BRANCHING

ACALL

addr11 Absolute Subroutine Call 2 24

LCALL addr16 Long Subroutine Call 3 24

RET Return from Subroutine 1 24




0509C–8051–07/06

RETI Return from interrupt

1 24

AJMP addr11 Absolute Jump 2 24

LJMP addr16 Long Jump 3 24

SJMP rel Short Jump (relative addr)

2 24

JMP @A+DPTR Jump indirect relative to the DPTR

1 24

JZ rel Jump if Accumulator is Zero

2 24

JNZ rel Jump if Accumulator is Not Zero

2 24

CJNE A,direct,rel Compare direct byte to Acc and Jump if Not Equal

3 24

CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal

3 24

CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal

3 24

CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal

3 24

DJNZ Rn,rel Decrement register and Jump if Not Zero

2 24

DJNZ direct,rel Decrement direct byte and Jump if Not Zero

3 24

NOP No Operation 1 12




Table 1-4. Instruction Opcodes in Hexadecimal Order

Hex Code

Number of Bytes

Mnemonic Operands

00 1 NOP

01 2 AJMP code addr

02 3 LJMP code addr

03 1 RR A

04 1 INC A

05 2 INC data addr

06 1 INC @R0

07 1 INC @R1

08 1 INC R0

09 1 INC R1

0A 1 INC R2

0B 1 INC R3

0C 1 INC R4

0D 1 INC R5

0E 1 INC R6

0F 1 INC R7

10 3 JBC bit addr,code addr

11 2 ACALL code addr

12 3 LCALL code addr

13 1 RRC A

14 1 DEC A

15 2 DEC data addr

16 1 DEC @R0

17 1 DEC @R1

18 1 DEC R0

19 1 DEC R1

1A 1 DEC R2

1B 1 DEC R3

1C 1 DEC R4

1D 1 DEC R5

1E 1 DEC R6

1F 1 DEC R7

20 3 JB bit addr,code addr

21 2 AJMP code addr

22 1 RET

23 1 RL A

24 2 ADD A,#data

25 2 ADD A,data addr

Hex Code

Number of Bytes

Mnemonic Operands

26 1 ADD A,@R0

27 1 ADD A,@R1

28 1 ADD A,R0

29 1 ADD A,R1

2A 1 ADD A,R2

2B 1 ADD A,R3

2C 1 ADD A,R4

2D 1 ADD A,R5

2E 1 ADD A,R6

2F 1 ADD A,R7

30 3 JNB bit addr,code addr


32 1 RETI

33 1 RLC A

34 2 ADDC A,#data

35 2 ADDC A,data addr

36 1 ADDC A,@R0

37 1 ADDC A,@R1

38 1 ADDC A,R0

39 1 ADDC A,R1

3A 1 ADDC A,R2

3B 1 ADDC A,R3

3C 1 ADDC A,R4

3D 1 ADDC A,R5

3E 1 ADDC A,R6

3F 1 ADDC A,R7

40 2 JC code addr

41 2 AJMP code addr

42 2 ORL data addr,A

43 3 ORL data addr,#data

44 2 ORL A,#data

45 2 ORL A,data addr

46 1 ORL A,@R0

47 1 ORL A,@R1

48 1 ORL A,R0

49 1 ORL A,R1

4A 1 ORL A,R2



0509C–8051–07/06

4B 1 ORL A,R3

4C 1 ORL A,R4

4D 1 ORL A,R5

4E 1 ORL A,R6

4F 1 ORL A,R7

50 2 JNC code addr


52 2 ANL data addr,A

53 3 ANL data addr,#data

54 2 ANL A,#data

55 2 ANL A,data addr

56 1 ANL A,@R0

57 1 ANL A,@R1

58 1 ANL A,R0

59 1 ANL A,R1

5A 1 ANL A,R2

5B 1 ANL A,R3

5C 1 ANL A,R4

5D 1 ANL A,R5

5E 1 ANL A,R6

5F 1 ANL A,R7

60 2 JZ code addr

61 2 AJMP code addr

62 2 XRL data addr,A

63 3 XRL data addr,#data

64 2 XRL A,#data

65 2 XRL A,data addr

66 1 XRL A,@R0

67 1 XRL A,@R1

68 1 XRL A,R0

69 1 XRL A,R1

6A 1 XRL A,R2

6B 1 XRL A,R3

6C 1 XRL A,R4

6D 1 XRL A,R5

6E 1 XRL A,R6

6F 1 XRL A,R7

70 2 JNZ code addr

Hex Code

Number of Bytes

Mnemonic Operands


72 2 ORL C,bit addr

73 1 JMP @A+DPTR

74 2 MOV A,#data

75 3 MOV data addr,#data

76 2 MOV @R0,#data

77 2 MOV @R1,#data

78 2 MOV R0,#data

79 2 MOV R1,#data

7A 2 MOV R2,#data

7B 2 MOV R3,#data

7C 2 MOV R4,#data

7D 2 MOV R5,#data

7E 2 MOV R6,#data

7F 2 MOV R7,#data

80 2 SJMP code addr

81 2 AJMP code addr

82 2 ANL C,bit addr

83 1 MOVC A,@A+PC

84 1 DIV AB

85 3 MOV data addr,data addr

86 2 MOV data addr,@R0

87 2 MOV data addr,@R1

88 2 MOV data addr,R0

89 2 MOV data addr,R1

8A 2 MOV data addr,R2

8B 2 MOV data addr,R3

8C 2 MOV data addr,R4

8D 2 MOV data addr,R5

8E 2 MOV data addr,R6

8F 2 MOV data addr,R7

90 3 MOV DPTR,#data


92 2 MOV bit addr,C

93 1 MOVC A,@A+DPTR

94 2 SUBB A,#data

95 2 SUBB A,data addr

96 1 SUBB A,@R0

Hex Code

Number of Bytes

Mnemonic Operands



97 1 SUBB A,@R1

98 1 SUBB A,R0

99 1 SUBB A,R1

9A 1 SUBB A,R2

9B 1 SUBB A,R3

9C 1 SUBB A,R4

9D 1 SUBB A,R5

9E 1 SUBB A,R6

9F 1 SUBB A,R7

A0 2 ORL C,/bit addr

A1 2 AJMP code addr

A2 2 MOV C,bit addr

A3 1 INC DPTR

A4 1 MUL AB

A5 reserved

A6 2 MOV @R0,data addr

A7 2 MOV @R1,data addr

A8 2 MOV R0,data addr

A9 2 MOV R1,data addr

AA 2 MOV R2,data addr

AB 2 MOV R3,data addr

AC 2 MOV R4,data addr

AD 2 MOV R5,data addr

AE 2 MOV R6,data addr

AF 2 MOV R7,data addr

B0 2 ANL C,/bit addr

B1 2 ACALL code addr

B2 2 CPL bit addr

B3 1 CPL C

B4 3 CJNE A,#data,code addr

B5 3 CJNE A,data addr,code addr

B6 3 CJNE @R0,#data,code addr

B7 3 CJNE @R1,#data,code addr

B8 3 CJNE R0,#data,code addr

B9 3 CJNE R1,#data,code addr

BA 3 CJNE R2,#data,code addr

BB 3 CJNE R3,#data,code addr

BC 3 CJNE R4,#data,code addr

Hex Code

Number of Bytes

Mnemonic Operands

BD 3 CJNE R5,#data,code addr

BE 3 CJNE R6,#data,code addr

BF 3 CJNE R7,#data,code addr

C0 2 PUSH data addr

C1 2 AJMP code addr

C2 2 CLR bit addr

C3 1 CLR C

C4 1 SWAP A

C5 2 XCH A,data addr

C6 1 XCH A,@R0

C7 1 XCH A,@R1

C8 1 XCH A,R0

C9 1 XCH A,R1

CA 1 XCH A,R2

CB 1 XCH A,R3

CC 1 XCH A,R4

CD 1 XCH A,R5

CE 1 XCH A,R6

CF 1 XCH A,R7

D0 2 POP data addr

D1 2 ACALL code addr

D2 2 SETB bit addr

D3 1 SETB C

D4 1 DA A

D5 3 DJNZ data addr,code addr

D6 1 XCHD A,@R0

D7 1 XCHD A,@R1

D8 2 DJNZ R0,code addr

D9 2 DJNZ R1,code addr

DA 2 DJNZ R2,code addr

DB 2 DJNZ R3,code addr

DC 2 DJNZ R4,code addr

DD 2 DJNZ R5,code addr

DE 2 DJNZ R6,code addr

DF 2 DJNZ R7,code addr

E0 1 MOVX A,@DPTR

E1 2 AJMP code addr

E2 1 MOVX A,@R0

Hex Code

Number of Bytes

Mnemonic Operands



0509C–8051–07/06

E3 1 MOVX A,@R1

E4 1 CLR A

E5 2 MOV A,data addr

E6 1 MOV A,@R0

E7 1 MOV A,@R1

E8 1 MOV A,R0

E9 1 MOV A,R1

EA 1 MOV A,R2

EB 1 MOV A,R3

EC 1 MOV A,R4

ED 1 MOV A,R5

EE 1 MOV A,R6

EF 1 MOV A,R7

F0 1 MOVX @DPTR,A

F1 2 ACALL code addr

F2 1 MOVX @R0,A

F3 1 MOVX @R1,A

F4 1 CPL A

F5 2 MOV data addr,A

F6 1 MOV @R0,A

F7 1 MOV @R1,A

F8 1 MOV R0,A

F9 1 MOV R1,A

FA 1 MOV R2,A

FB 1 MOV R3,A

FC 1 MOV R4,A

FD 1 MOV R5,A

FE 1 MOV R6,A

FF 1 MOV R7,A

Hex Code

Number of Bytes

Mnemonic Operands

110509C–8051–07/06

1.1 Instruction Definitions

ACALL addr11

Function: Absolute Call

Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected.

Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following instruction,

ACALL SUBRTN

at location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC contains 0345H.

Bytes: 2

Cycles: 2

Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

Operation: ACALL(PC) ← (PC) + 2(SP) ← (SP) + 1((SP)) ← (PC7-0)(SP) ← (SP) + 1((SP)) ← (PC15-8)(PC10-0) ← page address

120509C–8051–07/06

ADD A,<src-byte>

Function: Add

Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH (10101010B). The following instruction,

ADD A,R0

leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1.

ADD A,Rn

Bytes: 1

Cycles: 1

Encoding: 0 0 1 0 1 r r r

Operation: ADD(A) ← (A) + (Rn)

ADD A,direct

Bytes: 2

Cycles: 1

Encoding: 0 0 1 0 0 1 0 1 direct address

Operation: ADD(A) ← (A) + (direct)

ADD A,@Ri

Bytes: 1

Cycles: 1

Encoding: 0 0 1 0 0 1 1 i

Operation: ADD(A) ← (A) + ((Ri))

ADD A,#data

Bytes: 2

Cycles: 1

Encoding: 0 0 1 0 0 1 0 0 immediate data

Operation: ADD(A) ← (A) + #data

130509C–8051–07/06

ADDC A, <src-byte>

Function: Add with Carry

Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The following instruction,

ADDC A,R0

leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.

ADDC A,Rn

Bytes: 1

Cycles: 1


Operation: ADDC(A) ← (A) + (C) + (Rn)

ADDC A,direct

Bytes: 2

Cycles: 1


Operation: ADDC(A) ← (A) + (C) + (direct)

ADDC A,@Ri

Bytes: 1

Cycles: 1

Encoding: 0 0 1 1 0 1 1 i

Operation: ADDC(A) ← (A) + (C) + ((Ri))

ADDC A,#data

Bytes: 2

Cycles: 1


Operation: ADDC(A) ← (A) + (C) + #data

140509C–8051–07/06

AJMP addr11

ANL <dest-byte>,<src-byte>

Function: Absolute Jump

Description: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP.

Example: The label JMPADR is at program memory location 0123H. The following instruction,

AJMP JMPADR

is at location 0345H and loads the PC with 0123H.

Bytes: 2

Cycles: 2

Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

Operation: AJMP(PC) ← (PC) + 2(PC10-0) ← page address

Function: Logical-AND for byte variables

Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected.

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following instruction,

ANL A,R0

leaves 41H (01000001B) in the Accumulator.

When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The following instruction,

ANL P1,#01110011B

clears bits 7, 3, and 2 of output port 1.

ANL A,Rn

Bytes: 1

Cycles: 1


Operation: ANL(A) ← (A) ∧ (Rn)

150509C–8051–07/06

ANL A,direct

Bytes: 2

Cycles: 1


Operation: ANL(A) ← (A) ∧ (direct)

ANL A,@Ri

Bytes: 1

Cycles: 1

Encoding: 0 1 0 1 0 1 1 i

Operation: ANL(A) ← (A) ∧ ((Ri))

ANL A,#data

Bytes: 2

Cycles: 1


Operation: ANL(A) ← (A) ∧ #data

ANL direct,A

Bytes: 2

Cycles: 1


Operation: ANL(direct) ← (direct) ∧ (A)

ANL direct,#data

Bytes: 3

Cycles: 2

Encoding: 0 1 0 1 0 0 1 1 direct address immediate data

Operation: ANL(direct) ← (direct) ∧ #data

160509C–8051–07/06

ANL C,<src-bit>

Function: Logical-AND for bit variables

Description: If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.

Only direct addressing is allowed for the source operand.

Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:

MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN STATE

ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7

ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG

ANL C,bit

Bytes: 2

Cycles: 2

Encoding: 1 0 0 0 0 0 1 0 bit address

Operation: ANL(C) ← (C) ∧ (bit)

ANL C,/bit

Bytes: 2

Cycles: 2


Operation: ANL(C) ← (C) ∧ (bit)

170509C–8051–07/06

CJNE <dest-byte>,<src-byte>, rel

Function: Compare and Jump if Not Equal.

Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.

The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.

Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,

CJNE R7, # 60H, NOT_EQ

; . . . . . . . . ;R7 = 60H.

NOT_EQ: JC REQ_LOW ;IF R7 < 60H.

; . . . . . . . . ;R7 > 60H.

sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H.

If the data being presented to Port 1 is also 34H, then the following instruction,

WAIT: CJNE A, P1,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data changes to 34H.)

CJNE A,direct,rel

Bytes: 3

Cycles: 2

Encoding: 1 0 1 1 0 1 0 1 direct address rel. address

Operation: (PC) ← (PC) + 3IF (A) < > (direct)THEN

(PC) ← (PC) + relative offsetIF (A) < (direct)THEN

(C) ← 1ELSE

(C) ← 0

180509C–8051–07/06

CJNE A,#data,rel

Bytes: 3

Cycles: 2

Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address

Operation: (PC) ← (PC) + 3IF (A) < > dataTHEN

(PC) ← (PC) + relative offsetIF (A) < dataTHEN

(C) ← 1ELSE

(C) ← 0

CJNE Rn,#data,rel

Bytes: 3

Cycles: 2

Encoding: 1 0 1 1 1 r r r immediate data rel. address

Operation: (PC) ← (PC) + 3IF (Rn) < > dataTHEN

(PC) ← (PC) + relative offsetIF (Rn) < dataTHEN

(C) ← 1ELSE

(C) ← 0

CJNE @Ri,data,rel

Bytes: 3

Cycles: 2

Encoding: 1 0 1 1 0 1 1 i immediate data rel. address

Operation: (PC) ← (PC) + 3IF ((Ri)) < > dataTHEN

(PC) ← (PC) + relative offsetIF ((Ri)) < dataTHEN

(C) ← 1ELSE

(C) ← 0

190509C–8051–07/06

CLR A

CLR bit

Function: Clear Accumulator

Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected

Example: The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H (00000000B).

Bytes: 1

Cycles: 1

Encoding: 1 1 1 0 0 1 0 0

Operation: CLR(A) ← 0

Function: Clear bit

Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.

Example: Port 1 has previously been written with 5DH (01011101B). The following instruction,CLR P1.2 leaves the port set to 59H (01011001B).

CLR C

Bytes: 1

Cycles: 1

Encoding: 1 1 0 0 0 0 1 1

Operation: CLR(C) ← 0

CLR bit

Bytes: 2

Cycles: 1


Operation: CLR(bit) ← 0

200509C–8051–07/06

CPL A

CPL bit

Function: Complement Accumulator

Description: CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.

Example: The Accumulator contains 5CH (01011100B). The following instruction,

CPL A

leaves the Accumulator set to 0A3H (10100011B).

Bytes: 1

Cycles: 1

Encoding: 1 1 1 1 0 1 0 0

Operation: CPL(A) ← (A)

Function: Complement bit

Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.

Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.

Example: Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,CPL P1.1CPL P1.2 leaves the port set to 5BH (01011011B).

CPL C

Bytes: 1

Cycles: 1

Encoding: 1 0 1 1 0 0 1 1

Operation: CPL(C) ← (C)

CPL bit

Bytes: 2

Cycles: 1


Operation: CPL(bit) ← (bit)

210509C–8051–07/06

DA A

Function: Decimal-adjust Accumulator for Addition

Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.

If Accumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise.

If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.

All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions.

Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DAA apply to decimal subtraction.

Example: The Accumulator holds the value 56H (01010110B), representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B), representing the packed BCD digits of the decimal number 67. The carry flag is set. The following instruction sequence

ADDC A,R3

DA A

first performs a standard two’s-complement binary addition, resulting in the value 0BEH (10111110) in the Accumulator. The carry and auxiliary carry flags are cleared.

The Decimal Adjust instruction then alters the Accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of 56, 67, and 1 is 124.

BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the following instruction sequence,

ADD A, # 99H

DA A

leaves the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the sum can be interpreted to mean 30 - 1 = 29.

Bytes: 1

Cycles: 1

Encoding: 1 1 0 1 0 1 0 0

Operation: DA-contents of Accumulator are BCDIF [[(A3-0) > 9] ∨ [(AC) = 1]]

THEN (A3-0) ← (A3-0) + 6AND

IF [[(A7-4) > 9] ∨ [(C) = 1]]THEN (A7-4) ← (A7-4) + 6

220509C–8051–07/06

DEC byte

Function: Decrement

Description: DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.


Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The following instruction sequence,

DEC @R0

DEC R0

DEC @R0

leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.

DEC A

Bytes: 1

Cycles: 1

Encoding: 0 0 0 1 0 1 0 0

Operation: DEC(A) ← (A) - 1

DEC Rn

Bytes: 1

Cycles: 1


Operation: DEC(Rn) ← (Rn) - 1

DEC direct

Bytes: 2

Cycles: 1


Operation: DEC(direct) ← (direct) - 1

DEC @Ri

Bytes: 1

Cycles: 1

Encoding: 0 0 0 1 0 1 1 i

Operation: DEC((Ri)) ← ((Ri)) - 1

230509C–8051–07/06

DIV AB

Function: Divide

Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared.

Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case.

Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The following instruction,

DIV AB

leaves 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV are both cleared.

Bytes: 1

Cycles: 4

Encoding: 1 0 0 0 0 1 0 0

Operation: DIV(A)15-8 ← (A)/(B)(B)7-0

240509C–8051–07/06

DJNZ <byte>,<rel-addr>

Function: Decrement and Jump if Not Zero

Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction.

The location decremented may be a register or directly addressed byte.


Example: Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence,

DJNZ 40H,LABEL_1

DJNZ 50H,LABEL_2

DJNZ 60H,LABEL_3

causes a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero.

This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence,

MOV R2, # 8

TOGGLE: CPL P1.7

DJNZ R2,TOGGLE

toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin.

DJNZ Rn,rel

Bytes: 2

Cycles: 2

Encoding: 1 1 0 1 1 r r r rel. address

Operation: DJNZ(PC) ← (PC) + 2(Rn) ← (Rn) - 1IF (Rn) > 0 or (Rn) < 0

THEN(PC) ← (PC) + rel

DJNZ direct,rel

Bytes: 3

Cycles: 2

Encoding: 1 1 0 1 0 1 0 1 direct address rel. address

Operation: DJNZ(PC) ← (PC) + 2(direct) ← (direct) - 1IF (direct) > 0 or (direct) < 0

THEN (PC) ← (PC) + rel

250509C–8051–07/06

INC <byte>

Function: Increment

Description: INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.


Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The following instruction sequence,

INC @R0

INC R0

INC @R0

leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively.

INC A

Bytes: 1

Cycles: 1

Encoding: 0 0 0 0 0 1 0 0

Operation: INC(A) ← (A) + 1

INC Rn

Bytes: 1

Cycles: 1


Operation: INC(Rn) ← (Rn) + 1

INC direct

Bytes: 2

Cycles: 1


Operation: INC(direct) ← (direct) + 1

INC @Ri

Bytes: 1

Cycles: 1

Encoding: 0 0 0 0 0 1 1 i

Operation: INC((Ri)) ← ((Ri)) + 1

260509C–8051–07/06

INC DPTR

JB blt,rel

Function: Increment Data Pointer

Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected.

This is the only 16-bit register which can be incremented.

Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence,

INC DPTR

INC DPTR

INC DPTR

changes DPH and DPL to 13H and 01H.

Bytes: 1

Cycles: 2

Encoding: 1 0 1 0 0 0 1 1

Operation: INC(DPTR) ← (DPTR) + 1

Function: Jump if Bit set

Description: If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.

Example: The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The following instruction sequence,

JB P1.2,LABEL1

JB ACC. 2,LABEL2

causes program execution to branch to the instruction at label LABEL2.

Bytes: 3

Cycles: 2

Encoding: 0 0 1 0 0 0 0 0 bit address rel. address

Operation: JB(PC) ← (PC) + 3IF (bit) = 1


270509C–8051–07/06

JBC bit,rel

JC rel

Function: Jump if Bit is set and Clear bit

Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected.

Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin.

Example: The Accumulator holds 56H (01010110B). The following instruction sequence,

JBC ACC.3,LABEL1

JBC ACC.2,LABEL2

causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (01010010B).

Bytes: 3

Cycles: 2


Operation: JBC(PC) ← (PC) + 3IF (bit) = 1

THEN(bit) ← 0(PC) ← (PC) +rel

Function: Jump if Carry is set

Description: If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.

Example: The carry flag is cleared. The following instruction sequence,

JC LABEL1

CPL C

JC LABEL 2

sets the carry and causes program execution to continue at the instruction identified by the label LABEL2.

Bytes: 2

Cycles: 2

Encoding: 0 1 0 0 0 0 0 0 rel. address

Operation: JC(PC) ← (PC) + 2IF (C) = 1


280509C–8051–07/06

JMP @A+DPTR

Function: Jump indirect

Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.

Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL.

MOV DPTR, # JMP_TBL

JMP @A + DPTR

JMP_TBL: AJMP LABEL0

AJMP LABEL1

AJMP LABEL2

AJMP LABEL3

If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address.

Bytes: 1

Cycles: 2

Encoding: 0 1 1 1 0 0 1 1

Operation: JMP(PC) ← (A) + (DPTR)

290509C–8051–07/06

JNB bit,rel

JNC rel

Function: Jump if Bit Not set

Description: If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.

Example: The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The following instruction sequence,

JNB P1.3,LABEL1

JNB ACC.3,LABEL2

causes program execution to continue at the instruction at label LABEL2.

Bytes: 3

Cycles: 2


Operation: JNB(PC) ← (PC) + 3IF (bit) = 0


Function: Jump if Carry not set

Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified.

Example: The carry flag is set. The following instruction sequence,

JNC LABEL1

CPL C

JNC LABEL2

clears the carry and causes program execution to continue at the instruction identified by the label LABEL2.

Bytes: 2

Cycles: 2


Operation: JNC(PC) ← (PC) + 2IF (C) = 0


300509C–8051–07/06

JNZ rel

JZ rel

Function: Jump if Accumulator Not Zero

Description: If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

Example: The Accumulator originally holds 00H. The following instruction sequence,

JNZ LABEL1

INC A

JNZ LABEL2

sets the Accumulator to 01H and continues at label LABEL2.

Bytes: 2

Cycles: 2


Operation: JNZ(PC) ← (PC) + 2IF (A) ≠ 0


Function: Jump if Accumulator Zero

Description: If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

Example: The Accumulator originally contains 01H. The following instruction sequence,

JZ LABEL1

DEC A

JZ LABEL2

changes the Accumulator to 00H and causes program execution to continue at the instruction identified by the label LABEL2.

Bytes: 2

Cycles: 2


Operation: JZ(PC) ← (PC) + 2IF (A) = 0


310509C–8051–07/06

LCALL addr16

LJMP addr16

Function: Long call

Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memory address space. No flags are affected.

Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. After executing the instruction,

LCALL SUBRTN

at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H.

Bytes: 3

Cycles: 2

Encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0

Operation: LCALL(PC) ← (PC) + 3(SP) ← (SP) + 1((SP)) ← (PC7-0)(SP) ← (SP) + 1((SP)) ← (PC15-8)(PC) ← addr15-0

Function: Long Jump

Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected.

Example: The label JMPADR is assigned to the instruction at program memory location 1234H. The instruction,

LJMP JMPADR

at location 0123H will load the program counter with 1234H.

Bytes: 3

Cycles: 2

Encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0

Operation: LJMP(PC) ← addr15-0

320509C–8051–07/06

MOV <dest-byte>,<src-byte>

Function: Move byte variable

Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.

This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.

Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH).

MOV R0,#30H ;R0 < = 30H

MOV A,@R0 ;A < = 40H

MOV R1,A ;R1 < = 40H

MOV B,@R1 ;B < = 10H

MOV @R1,P1 ;RAM (40H) < = 0CAH

MOV P2,P1 ;P2 #0CAH

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2.

MOV A,Rn

Bytes: 1

Cycles: 1


Operation: MOV(A) ← (Rn)

*MOV A,direct

Bytes: 2

Cycles: 1


Operation: MOV(A) ← (direct)

* MOV A,ACC is not a valid Instruction.

MOV A,@Ri

Bytes: 1

Cycles: 1

Encoding: 1 1 1 0 0 1 1 i

Operation: MOV(A) ← ((Ri))

330509C–8051–07/06

MOV A,#data

Bytes: 2

Cycles: 1


Operation: MOV(A) ← #data

MOV Rn,A

Bytes: 1

Cycles: 1


Operation: MOV(Rn) ← (A)

MOV Rn,direct

Bytes: 2

Cycles: 2

Encoding: 1 0 1 0 1 r r r direct addr.

Operation: MOV(Rn) ← (direct)

MOV Rn,#data

Bytes: 2

Cycles: 1

Encoding: 0 1 1 1 1 r r r immediate data

Operation: MOV(Rn) ← #data

MOV direct,A

Bytes: 2

Cycles: 1


Operation: MOV(direct) ← (A)

MOV direct,Rn

Bytes: 2

Cycles: 2

Encoding: 1 0 0 0 1 r r r direct address

Operation: MOV(direct) ← (Rn)

340509C–8051–07/06

MOV direct,direct

Bytes: 3

Cycles: 2

Encoding: 1 0 0 0 0 1 0 1 dir. addr. (dest) dir. addr. (scr)

Operation: MOV(direct) ← (direct)

MOV direct,@Ri

Bytes: 2

Cycles: 2

Encoding: 1 0 0 0 0 1 1 i direct addr.

Operation: MOV(direct) ← ((Ri))

MOV direct,#data

Bytes: 3

Cycles: 2

Encoding: 0 1 1 1 0 1 0 1 direct address immediate data

Operation: MOV(direct) ← #data

MOV @Ri,A

Bytes: 1

Cycles: 1

Encoding: 1 1 1 1 0 1 1 i

Operation: MOV((Ri)) ← (A)

MOV @Ri,direct

Bytes: 2

Cycles: 2

Encoding: 1 0 1 0 0 1 1 i direct addr.

Operation: MOV((Ri)) ← (direct)

MOV @Ri,#data

Bytes: 2

Cycles: 1

Encoding: 0 1 1 1 0 1 1 i immediate data

Operation: MOV((Ri)) ← #data

350509C–8051–07/06

MOV <dest-bit>,<src-bit>

MOV DPTR,#data16

Function: Move bit data

Description: MOV <dest-bit>,<src-bit> copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.

Example: The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B).

MOV P1.3,C

MOV C,P3.3

MOV P1.2,C

leaves the carry cleared and changes Port 1 to 39H (00111001B).

MOV C,bit

Bytes: 2

Cycles: 1


Operation: MOV(C) ← (bit)

MOV bit,C

Bytes: 2

Cycles: 2


Operation: MOV(bit) ← (C)

Function: Load Data Pointer with a 16-bit constant

Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected.

This is the only instruction which moves 16 bits of data at once.

Example: The instruction,

MOV DPTR, # 1234H

loads the value 1234H into the Data Pointer: DPH holds 12H, and DPL holds 34H.

Bytes: 3

Cycles: 2

Encoding: 1 0 0 1 0 0 0 0 immed. data15-8 immed. data7-0

Operation: MOV(DPTR) ← #data15-0DPH ← DPL ← #data15-8 ← #data7-0

360509C–8051–07/06

MOVC A,@A+ <base-reg>

Function: Move Code byte

Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected.

Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive.

REL_PC: INC A

MOVC A,@A+PC

RET

DB 66H

DB 77H

DB 88H

DB 99H

If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. The INC A before the MOVC instruction is needed to “get around” the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead.

MOVC A,@A+DPTR

Bytes: 1

Cycles: 2

Encoding: 1 0 0 1 0 0 1 1

Operation: MOVC(A) ← ((A) + (DPTR))

MOVC A,@A+PC

Bytes: 1

Cycles: 2

Encoding: 1 0 0 0 0 0 1 1

Operation: MOVC(PC) ← (PC) + 1(A) ← ((A) + (PC))

370509C–8051–07/06

MOVX <dest-byte>,<src-byte>

Function: Move External

Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why “X” is appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM.

In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX.

In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports.

It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using R0 or R1.

Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence,

MOVX A,@R1

MOVX @R0,A

copies the value 56H into both the Accumulator and external RAM location 12H.

MOVX A,@Ri

Bytes: 1

Cycles: 2

Encoding: 1 1 1 0 0 0 1 i

Operation: MOVX(A) ← ((Ri))

MOVX A,@DPTR

Bytes: 1

Cycles: 2

Encoding: 1 1 1 0 0 0 0 0

Operation: MOVX(A) ← ((DPTR))

380509C–8051–07/06

MUL AB

MOVX @Ri,A

Bytes: 1

Cycles: 2

Encoding: 1 1 1 1 0 0 1 i

Operation: MOVX((Ri)) ← (A)

MOVX @DPTR,A

Bytes: 1

Cycles: 2

Encoding: 1 1 1 1 0 0 0 0

Operation: MOVX(DPTR) ← (A)

Function: Multiply

Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared.

Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction,

MUL AB

will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared.

Bytes: 1

Cycles: 4

Encoding: 1 0 1 0 0 1 0 0

Operation: MUL(A)7-0 ← (A) X (B)(B)15-8

390509C–8051–07/06

NOP

ORL <dest-byte> <src-byte>

Function: No Operation

Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected.

Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence,

CLR P2.7

NOP

NOP

NOP

NOP

SETB P2.7

Bytes: 1

Cycles: 1

Encoding: 0 0 0 0 0 0 0 0

Operation: NOP(PC) ← (PC) + 1

Function: Logical-OR for byte variables

Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected.


Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.

Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the following instruction,

ORL A,R0

leaves the Accumulator holding the value 0D7H (1101011lB).When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction,

ORL P1,#00110010B

sets bits 5, 4, and 1 of output Port 1.

ORL A,Rn

Bytes: 1

Cycles: 1


Operation: ORL(A) ← (A) ∨ (Rn)

400509C–8051–07/06

ORL A,direct

Bytes: 2

Cycles: 1


Operation: ORL(A) ← (A) ∨ (direct)

ORL A,@Ri

Bytes: 1

Cycles: 1

Encoding: 0 1 0 0 0 1 1 i

Operation: ORL(A) ← (A) ∨((Ri))

ORL A,#data

Bytes: 2

Cycles: 1


Operation: ORL(A) ← (A) ∨ #data

ORL direct,A

Bytes: 2

Cycles: 1


Operation: ORL(direct) ← (direct) ∨ (A)

ORL direct,#data

Bytes: 3

Cycles: 2

Encoding: 0 1 0 0 0 0 1 1 direct addr. immediate data

Operation: ORL(direct) ← (direct) ∨ #data

410509C–8051–07/06

ORL C,<src-bit>

POP direct

Function: Logical-OR for bit variables

Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.

Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0:

MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN P10

ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7

ORL C,/OV ;OR CARRY WITH THE INVERSE OF OV.

ORL C,bit

Bytes: 2

Cycles: 2


Operation: ORL(C) ← (C) ∨ (bit)

ORL C,/bit

Bytes: 2

Cycles: 2


Operation: ORL(C) ← (C) ∨ (bit)

Function: Pop from stack.

Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction sequence,

POP DPH

POP DPL

leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H. At this point, the following instruction,

POP SP

leaves the Stack Pointer set to 20H. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H).

Bytes: 2

Cycles: 2


Operation: POP(direct) ← ((SP))(SP) ← (SP) - 1

420509C–8051–07/06

PUSH direct

RET

Function: Push onto stack

Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The following instruction sequence,

PUSH DPL

PUSH DPH

leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and 0BH, respectively.

Bytes: 2

Cycles: 2


Operation: PUSH(SP) ← (SP) + 1((SP)) ← (direct)

Function: Return from subroutine

Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.

Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction,

RET

leaves the Stack Pointer equal to the value 09H. Program execution continues at location 0123H.

Bytes: 1

Cycles: 2

Encoding: 0 0 1 0 0 0 1 0

Operation: RET(PC15-8) ← ((SP))(SP) ← (SP) - 1(PC7-0) ← ((SP))(SP) ← (SP) - 1

430509C–8051–07/06

RETI

RL A

Function: Return from interrupt

Description: RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed.

Example: The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction,

RETI

leaves the Stack Pointer equal to 09H and returns program execution to location 0123H.

Bytes: 1

Cycles: 2

Encoding: 0 0 1 1 0 0 1 0

Operation: RETI(PC15-8) ← ((SP))(SP) ← (SP) - 1(PC7-0) ← ((SP))(SP) ← (SP) - 1

Function: Rotate Accumulator Left

Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B). The following instruction,

RL A

leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.

Bytes: 1

Cycles: 1

Encoding: 0 0 1 0 0 0 1 1

Operation: RL(An + 1) ← (An) n = 0 - 6(A0) ← (A7)

440509C–8051–07/06

RLC A

RR A

RRC A

Function: Rotate Accumulator Left through the Carry flag

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected.

Example: The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The following instruction,

RLC A

leaves the Accumulator holding the value 8BH (10001010B) with the carry set.

Bytes: 1

Cycles: 1

Encoding: 0 0 1 1 0 0 1 1

Operation: RLC(An + 1) ← (An) n = 0 - 6(A0) ← (C)(C) ← (A7)

Function: Rotate Accumulator Right

Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B). The following instruction,

RR A

leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected.

Bytes: 1

Cycles: 1

Encoding: 0 0 0 0 0 0 1 1

Operation: RR(An) ← (An + 1) n = 0 - 6(A7) ← (A0)

Function: Rotate Accumulator Right through Carry flag

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The following instruction,

RRC A

leaves the Accumulator holding the value 62 (01100010B) with the carry set.

Bytes: 1

Cycles: 1

Encoding: 0 0 0 1 0 0 1 1

Operation: RRC(An) ← (An + 1) n = 0 - 6(A7) ← (C)(C) ← (A0)

450509C–8051–07/06

SETB <bit>

SJMP rel

Function: Set Bit

Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected.

Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions,

SETB C

SETB P1.0

sets the carry flag to 1 and changes the data output on Port 1 to 35H (00110101B).

SETB C

Bytes: 1

Cycles: 1

Encoding: 1 1 0 1 0 0 1 1

Operation: SETB(C) ← 1

SETB bit

Bytes: 2

Cycles: 1


Operation: SETB(bit) ← 1

Function: Short Jump

Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it.

Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction,

SJMP RELADR

assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H.

Note: Under the above conditions the instruction following SJMP is at 102H. Therefore, the displacement byte of the instruction is the relative offset (0123H-0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH is a one-instruction infinite loop.

Bytes: 2

Cycles: 2


Operation: SJMP(PC) ← (PC) + 2(PC) ← (PC) + rel

460509C–8051–07/06

SUBB A,<src-byte>

Function: Subtract with borrow

Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6.

When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number.

The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction,

SUBB A,R2

will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set.

Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by CLR C instruction.

SUBB A,Rn

Bytes: 1

Cycles: 1


Operation: SUBB(A) ← (A) - (C) - (Rn)

SUBB A,direct

Bytes: 2

Cycles: 1


Operation: SUBB(A) ← (A) - (C) - (direct)

SUBB A,@Ri

Bytes: 1

Cycles: 1

Encoding: 1 0 0 1 0 1 1 i

Operation: SUBB(A) ← (A) - (C) - ((Ri))

SUBB A,#data

Bytes: 2

Cycles: 1


Operation: SUBB(A) ← (A) - (C) - #data

470509C–8051–07/06

SWAP A

XCH A,<byte>

Function: Swap nibbles within the Accumulator

Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B). The instruction,

SWAP A

leaves the Accumulator holding the value 5CH (01011100B).

Bytes: 1

Cycles: 1

Encoding: 1 1 0 0 0 1 0 0

Operation: SWAP(A3-0) D (A7-4)

Function: Exchange Accumulator with byte variable

Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing.

Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB). Internal RAM location 20H holds the value 75H (01110101B). The following instruction,

XCH A,@R0

leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator.

XCH A,Rn

Bytes: 1

Cycles: 1


Operation: XCH(A) D ((Rn)

XCH A,direct

Bytes: 2

Cycles: 1


Operation: XCH(A) D (direct)

XCH A,@Ri

Bytes: 1

Cycles: 1

Encoding: 1 1 0 0 0 1 1 i

Operation: XCH(A) D ((Ri))

480509C–8051–07/06

XCHD A,@Ri

XRL <dest-byte>,<src-byte>

Function: Exchange Digit

Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected.

Example: R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The following instruction,

XCHD A,@R0

leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator.

Bytes: 1

Cycles: 1

Encoding: 1 1 0 1 0 1 1 i

Operation: XCHD(A3-0) D ((Ri3-0))

Function: Logical Exclusive-OR for byte variables

Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected.


Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.

Example: If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the instruction,

XRL A,R0

leaves the Accumulator holding the value 69H (01101001B).

When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction,

XRL P1,#00110001B

complements bits 5, 4, and 0 of output Port 1.

XRL A,Rn

Bytes: 1

Cycles: 1


Operation: XRL(A) ← (A) V (Rn)

490509C–8051–07/06

Document Revision HistoryChanges from 0509B - 08/05 to 0509C - 07/06

1. Correcto to MOV Direct, page 49.

Printed on recycled paper.

0509C–8051–07/06

© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, and Everywhere You Are® are the trademarks or reg-istered trademarks, of Atmel Corporation or its subsidiaries. Copied by permission of Intel Corporation. Copyright Intel Corporation 1994. Other terms and product names may be trademarks of others.

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ADDRESSING MODES OF 8051 The 8051 instruction set supports 6 addressing modes: (1) Direct addressing (4) Register specific (Register implied) (2) Indirect addressing (5) Immediate mode (3) Register Instructions (6) Indexed addressing. 1) Direct addressing: In this mode, the operands are (addressed) specified using the 8 bit address field in the instruction format. Only internal data RAM and SFRS can be directly addressed. Example: MOV R0, 89H 89 H is an address of special function Register TMOD. 2) Register Indirect addressing: In this mode the 8 bit address of a operand is stored in a register. The register R0 and R1 of the selected bank of register or SP can be used as address register for storing the 8 bit addresses. Example: ADD A, @ R0. 3) Register Instructions: In this mode the operands are stored in the register R0R7 of the selected register Bank. One of these register is (R0R7) is specified in the instruction using the 3-bit register specification field of the opcode format. Example: ADD A, R7. 4) Register Specific instruction: In this case the operand is implicitly stated as a part of register. Some of the instruction always operate only on a specific register. Example: RLA rotates accumulator left. 5) Immediate Mode: In this mode an immediate data i.e., a constant is specified in the instruction after the opcode byte. Example: MOV A, # 100. 6) Indexed addressing: Only program memory can be accessed using this addressing mode. This mode is used in 8051 for look up table operation. PC and data pointers are allowed 16 bit address register is this mode of addressing. These 16 bit register points the base of the lookup table and accumulator register contains code to be converted using the looking table. In other words it contains the relative address of the code in the lookup table. The lookup table data address is found by adding the contents of accumulator register with that of PC or data pointer. In the case of jump instruction the contents of accumulator are added with one of the specified 16 bit register to form a jump destination address. Example: MOVC A, @A+DPTR JMP @A+DPTR.

ARCHITECTURE OF 8051 The internal architecture of 8051 is given in figure below. The functional description of each block is given below: 1. Accumulator (ACC): The accumulator register (ACC or A) acts as an operand register, in case of some instruction. This may be either implicit or specified in the instruction. The ACC register has been allotted an address in the on chip Special (register) function register bank. 2. B Register: This register is used to store one of the operands for multiplier (or) divide instruction. In other instruction it may be just used as a scratch pad. This register is considered as a special function register. 3. Program Status Word (PSW): Thus set of flags contains the status information and is considered as one of the special function register. 4. Stack Pointer: It’s a 8 bit register. It will be incremented before the data is stored on to the stack using push or call instruction. This register contains 8 -bit stack top address. The stack may be defined anywhere in the on chip 128-byte RAM. After reset the SP is initialized to 07. After each write to stack operation, the 8 bit contents of the operand are stored on to the stack; after incrementing the SP register by one. If SP contains 07H, the forthcoming PUSH operation will store the data at address 08 H in the internal RAM. The 8051 stack is not a Top-Down Data Structure like other intel processors. This register has also been allotted an address in the special function register bank. 5. Data Pointer (DPTR): This 16 bit register contains a higher byte (DPH) and the lower byte (DPL) of the 16 bit external data RAM address. It’s accessed as a 16 bit register or two 8 bit register as specified above. It has been allotted two addresses in the special function register bank for its two bytes DPH and DPL. 6. Port 0 to 3 Latches and Drivers: These 4 latches and driver pairs are allotted to each of the 4 on chip input output ports. These latches have been allotted addresses in the special function register bank. Using the allotted address the user can communicate with these ports. These are identifies as P0, P1, P2 and P3. 7. Serial Data Buffer: The serial data buffer internally contains 2 independent register one of them is transmit buffer, which is a parallel-in-serial-out register. The other is a (serial) receive buffer, which is called a serial-in-parallel-out register. The serial data buffer is identified as SBUF and is one of the special function register. If a byte is written to SBUF, it initiates the serial transmission and if the SBUF is read it reads the received serial data. 8. Timer Registers: These two 16 bit register can be accessed as their lower and upper bytes for example TL0 represents, the lower byte of the timer register 0, while TH0 register higher byte of the timer register 0 similarly TL1 and TH1 represent the lower and higher bytes of timing register 1. All these register can be accessed using the 4 addresses allotted to the which lie in the special function register SFR address range 80 H to FF. 9. Control Register: The special function register IP, IE, TMOD, TCON, SCON and PCON contain control and status information for interrupts, times/count and serial port. All of these register have been allotted addresses in the special function register bank of 8051. 10. Timing and Control Unit: This unit derives all the necessary timing at control signals register for internal operation of the circuit. It also derives the control signals required for controlling the external system bus. 11. Oscillator: Thus circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator. 12. Instruction Register: This register decodes the opcode of an instruction to be executed

and gives information to the timing and control unit to generate necessary signals on the execution of instruction. 13. EPROM and Program address Register: These blocks provides an on chip EPROM and a mechanism to internally address it. EPROM is not available in all 8051 versions. 14. RAM and RAM address Register: These blocks provide internal 128 bytes of RAM and a mechanism to address it internally. 15. ALU: It performs 8 bit arithmetic, logical operations over the operands held by temporary register TMP1 and TMP2. Users can’t access these temporary register. 16. SFR Register Bank: This is a set of special function register, which can be addressed using their respective addresses which lie in the range 80 H to FF H.

INTERRUPTS OF 8051 8051 provides 5 sources of interrupt, INT0 and INT1 are the two external interrupts. These can be edge triggered or level triggered, as program with bits IT0 and IT1 is Register TCON. These interrupts are processed internally by the flags IE0 and IE1. If the interrupts are programmed as edge sensitive, these flags are automatically cleared after the control is transferred to the respective vector. On the other hand if the interrupt are program as level sensitive, these flags are controlled by the external interrupt sources themselves. Both timers can be used in timer or counter mode. In counter mode it counts the pulses at T0 and T1 pin. In timer mode the oscillator clock is divided by a prescalar (1/32) and then given to the timer. So clock frequency for timer is 1/32th of the controller operating frequency. The timer is a UP counter and generate an interrupt when the count reaches FFFF H. The timer 0 and Timer 1 interrupt sources are generated by TF0 and TF1 bits of the register TCON; which are set; if a rollover takes place in their respective timer register except timer 0 in mode 3. The serial port interrupt is generated if alteast one of the (bits) two bits RI and TI is set Neither of the flag is cleared after the control is transferred to the service routine RI and TI flags need to be cleared using software. In addition to these 5 interrupts, 8051 also allows single step interrupt to be generate with the help of software. The different sources of interrupt program to have same level of priority, further follow a sequence of priority under that level as shown.

The All these interrupt are enabled using a special function register called Interrupt Enable Register (IE) and their priorities are program using a special function register called Interrupt Priority Register (IP).

MICROCONTROLLERS INTRODUCTION While studying microprocessor based system design, a stand alone microprocessor is not a self sufficient device. It requires other components like memory, and input output device to form a minimum workable system configuration. To have all these components in discrete form and to assemble them on a PCB (Printed Circuit Board) is not a affordable solution for the following reasons. 1. The overall system cost of a microprocessor based system built around a CPU, memory and other peripherals is high as compared to microcontroller based system. 2. A large sized PCB is required for assembling all these components, resulting in an enhanced cost of the system. 3. Design of such PCBs requires a lot of effort and time and thus the overall product design requires more time. 4. Due to the large size of the PCB and the discrete component used, physical size of the product is big and hence it is not handy. 5. As discrete components are used the system is not reliable nor is it easy to troubleshoot such a system. Considering all these problems, Intel decided to integrate a microprocessor along with IO ports and minimum memory in a single package. Another peripheral, Timer was also integrated to make this device a self sufficient one. A device which contains a microprocessor and the above mentioned devices has been named as microcontrollers. The Design with the microcontrollers has the following advantages. 1. As the peripherals are integrated in to a single chip, the overall system cost is very low. 2. The product is of a small size as compared to the microprocessor based system and is thus very handy. 3. The system design now requires very little efforts and is easy to trouble-shoot and maintain. 4. As the peripherals are integrated with a microprocessor the system is more reliable. 5. Though microcontrollers have on chip RAM, ROM and IO ports, additional RAM, ROM and IO Ports may be interfaced externally if required. 6. The microcontrollers with on chip ROM provide a software security feature which is not available with microprocessor based system using ROM/EPROM. 7. All these features are available in a 40 pin package as in an 8-bit processor. The following figure shows a typical microcontrollers internal block diagram.

As the microcontroller contains most of the components required to form a microprocessor system, it’s some time called single chip microcomputer.

MEMORY AND IO ADDRESSING The total memory of an 8051 system is logically divided into program memory and data memory. Program memory stores the program to be executed while data memory stores data like immediate results, variables, and constants required for execution of the program. Program memory is invariably implemented using EPROM, because it stores only program code which is to be executed thus it need not be written into. However the data memory may be read from or written into, thus implemented using RAM. Further the program memory and data memory both may be categorized as on-chip (internal) and external memory, depending on whether the memory is physically exists on chip or it is externally interfaced. 8051 can (address support) 4kB on chip program memory whose map starts from 0000 H to 0FFF H. It can address 64kB of external program memory under the control of PSEN signal, whose address map is from 0000 H to FFFF H. Here the map of internal program memory and external program memory may overlap. However, these two memory spaces can be distinguished by PSEN signal.

8051 supports 64 kB of external data memory whose map starts at 0000 H and ends at FFFF H. This external data memory can be accessed under the control of register DPTR which stores he addresses of external data memory accesses. 8051 generators RD and WR signals during external memory accesses. The chip select line of external data memory may be derived from the address lines. Internal data memory 8051 consists of two parts: (1) RAM block of 128 bytes (256 bytes in some various of 8051). (2) Is a set of addresses from 80 H to FF H which includes addresses allotted to the special function register. The address map of 8051 internal 128 bytes RAM starts from 00 to 7F H. This RAM can be addressed by using direct or indirect addressing modes. However the special function register address map i.e., from 80 H to FF H is accessed only with direct addressing mode. In case of 8051 versions with 256 bytes on-chip RAM, the map starts from 00 H tan FF H. In this case it may be noted that the address map of special function register i.e., 80 H to FF overlaps with upper 128 bytes of RAM. The way of addressing i.e., addressing mode is differentiates between these two memory spaces. The upper 128 bytes of 256 byte on-chip RAM can be accessed only using indirect addressing; while the lower 128 bytes can be accessed using either direct or indirect addressing. The SFR can be accessed only by using direct addressing.

The lower 128 bytes of RAM whose address map is from 00 to 7F is functionally organized in 3 sections. The address block from 00 to 1F i.e., the lowest 32 bytes from the 1st section, is divided into 4 banks of 8 register denoted as 00, 01, 10 and 11. Each of these banks contain 8. 8-bit register. The stack pointer gets initialized at address 0.7 H i.e., the last address of bank 00, after reset operation.

After reset bank 0 is selected by default but the actual stack data is stored from 08 H onwards; i.e., bank 01, 10 and 11. Note that 20 is the address of the 1st byes of the on-chip RAM. The 3rd block of internal memory occupies addresses from 30 H to 7F H. This block of memory is byte addressable memory space. After reset bank 0 is selected by default but the actual stack data is stored from 08 H onwards; i.e., bank 01, 10 and 11. Note that 20 is the address of the 1st byes of the on-chip RAM. The 3rd block of internal memory occupies addresses from 30 H to 7F H. This block of memory is byte addressable memory space.

Microcontroller

PresentationBy

Rajul Patkar

Microprocessor and Microcontroller

Microprocessors is a general purpose computer. Multi chip required for all the functions.

Microcontrollers is a true computer on a single chip. Logic functions, bit addressing, small cheap and fast.

Microprocessor andMicrocontroller

Essential elements of any computer are:

– CPU– Memory for both data and program– I/O or Input Output system

Microprocessor andMicrocontroller

Various different architectures exist depending on the application

Mini-computer: all 3 systems on a board Micro-controller: All systems on a single chip

Microprocessor

Microcontroller

A Microcontroller application

Intel 8051 Microcontroller

8051 is made by Intel. It is one of the most widely used microcontroller in the world.

– A stand alone, high performance, single chip computer for control applications.

– Small, cheap and 40 pins.– 64K program memory.– 64K data memory.

8051 Pin layout

8051 Controller

A minimal 8051 based controller needs only the following components

CPU Memory I/O

8051 Block Diagram

8051 Architecture

8051 architecture contains the following: 8 bit CPU with registers A and B 16 bit program counter(PC) and data pointer(DPTR) 8 bit program status word(PSW) 8 bit stack pointer Internal ROM of 0(8031) to 4K(8051) Internal RAM of 128 Bytes

– 4 register banks 00-1f– 16 bytes(bit addressable) 20-2f– 80 bytes of general purpose data memory 30-7f

8051 Architecture

32 I/O pins arranged as four 8 bit ports (P0 – P3) 2 16-bit timer/counters: T0 and T1 Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP

and IE 2 external and 3 internal interrupt sources Oscillator and clock circuits

8051 Memory Types

The 8051 has two separate memory blocks, for data and program . Since both blocks have the same address, this is called a Harvard architecture.

Separating the program memory from the data memory improves reliability since we cannot overwrite the program code. and allows us to use program ROM , or read only memory.

Internal circuitry accesses the correct memory based on the nature of the operation in progress.

Program Memory

Program memory normally we have 4K on the chip (but not in the case of the 8031)

Data Memory

Data memory all 64K is off the chip except for (a miniscule 128 bytes).

Internal 256 bytes is divided into two parts: general scratch and the special function registers.

The 128 bytes in lower internal RAM have the following structure:

Only one of the 4 register banks can be active at any particular time Which one is active is given by flags in the PSW

Special Function Registers

The Special Function Registers (SFRs) contain memory locations that are used for special tasks. (They should not be used for general purpose tasks.)

Each SFR occupies internal RAM from 0x80 to 0xFF, (but some areas are empty!) They are 8 bits wide. Some examples are:

A register or accumulator is used for most ALU operations & external moves

B used for multiplication & division and can also be used for general purpose storage

PSW Program Status Word is a bit addressable register.

Two special 16- bit registers (double registers):PC or program counter. This is not directly addressable,

nor does it have a memory location. It is not part of SFR.

DPTR or data pointer. Is accessible as two 8- bit registers: DPL and DPH. DPTR doesn’t have a single internal address; DPH and DPL are each assigned an address.

This is used to furnish memory addresses for internal and external code access and external data access.

Program Status Word

The PSW is the most important of the SFRs. It is abyte register which holds 8 bits that can addressed individually.Each bit is referred to as a flag. Flags can be either set (1) or cleared (0). This is more efficient than using an entire byte memory location for a binary variable.

SFRs

SFRs which are also bit addressableA, B, IP, IE, TCON, SCON, PSW, P0, P1, P2, P3Other SFRsTMOD, THO, TLO, TH1, TL1, SBUF, PCON, SP,

DPTR

Port Operations

Total 4 portsPort 0 may serve as inputs, outputs, or as a low

order address and data bus for external memory.Port 1 may be used as input/output port.Port 2 may be used as input/output or high order address byte.Port 3 may be used as an input/output and for

some alternate function.

Port 3 Alternate Operations

Pin Alternate use SFRP3.0-RXD Serial data input SBUFP3.1-TXD Serial data output SBUFP3.2-INT0~ Ext. Int. 0 TCON.1P3.3-INT1~ Ext. Int. 1 TCON.3P3.4-T0 Ext. Tim. 0 TMODP3.4-T1 Ext. Tim. 1 TMODP3.6-WR~ Ext. Mem write pulseP3.7-RD~ Ext. Mem Read pulse

Port Operations

To read and write from port:MOV A, P0 or MOV A,80h- This copies data from port 0 pins to register A.MOV P1, #0a5h or MOV 90h,#0a5h- This moves a constant number into port1.Moving data to a port changes the port latch,

moving data from a port gets data from the port pins.

Memory Mapped Port Operations

Store the address of the memory mapped port into the DPTR register, and indirectly address this through Acc. Reading from a portMOV DPTR, #0F012h; address to read digital

inputMOVX A, @DPTR ; read the values into Acc Writing to a portMOV DPTR, #0F011h; address of LED outputsMOVX @DPTR, A ; write this value back out

again

Accessing external memory

Storage problems? What happens if a program is larger than 4096 bytes of

code?We have the ‘ROMless’ 8031 version, we must use the

movx (move external) to access the data block, and movc to fetch from code memory.We have two separate read signals,RD~, (read) and PSEN~, (program send enable).

Prototyping 8051 Design

For many small applications where we might want to Change the ROM code, we would like to use external EPROM , which means: We have lost the use of ports 0 and ports 2 since they

must be used to interface with external ROM and not available for I/ O.

We may need external RAM (since the 128 bytes may not be enough for our application), which means that we have lost port 3.6, WR~, and 3.7, RD~

Any serial communication requires 3.0 (RXD) and 3.1(TXD)

Loss of ports leaves us with: 1. All of port #1, and 2. Port P3.2 – P3.5for general purpose I/ O and external interrupts and timing inputs.What is to be done for the lost ports?

Programmable Logic Devices

The PROM chip is an example of a Programmable Logic Device PLD. Once programmed, it will retain the program even when the power is turned off.One- time programmable devices uses tiny fuseswhich are burnt or blown (or we can use antifuseswhich have the same end function.

Eraseable Programmable read Only memory (EPROMS) can be reprogrammed. This uses a modified MOS transistor with a floating gate that when uncharged does not effect the normal operation. However if it is subjected to (high)+12V, then a charge will move into the 2nd transistor which is stable (will last a decade).Reprogram by subjecting the cells to UV light via aceramic window on top of the package. Wiping time takes about 20 minutes.

EEPROM or Electrically erasable proms are about 2.5 times larger than eproms, and are quicker to clear.FLASH proms are much quicker to erase (hence the name), and can be reprogrammed while still on the circuit board . Suitable for easy upgrading by the public of ROM chips in Modems and PCs.

Interrupts

Interrupts are just special subroutines that may (or may not) be called explicitly.If conditions are “right”, when an interrupt occurs, then theprocessor will stop what it is doing, and jump to a specific place in memory (decided by the Intel 8051 designers) hooked by that particular interrupt.It is up to the programmer to make sure that you supply a sensible further course of action. This is called the interrupt handler routine or interrupt service routine , ISR.

Interrupts

Interrupt programmingSignals or conditions generated external to the main

program– External events such as a change in a logic value– Overflow of a counter– Arrival of data at the serial port.Interrupts can be enabled or disabled by the programmer.

(Although some interrupts are nonmaskable.)

Types of Interrupts

Five interrupts are provided on 8051.3 are generated by internal operations.

Generated by internal timer/counter Timer flag 0 – TF0 Timer flag 1 – TF1

Indicates that a character has been received or the buffer is emptyand a character can be transmitted

Serial port interrupt (RI or TI)2 are triggered by external signals INT0~ INT1~

Interrupts

All interrupt functions are under the control of the program. The programmer can alter the bits of IE, IP and TCON register. Each interrupt forces the processor to jump at theinterrupt location in the memory.The interrupted program must resume operation atthe instruction where the interrupt took place.Program resumption is done by storing the interrupted PC address on to stack.RETI instruction at the end of ISR will restore the PC address.

Timers and Counters

The 8051 comes equipped with two timers, both of which may be controlled, set, read, and configured individually. The 8051 timers have three general functions: 1) Keeping time and/or calculating the amount of

time between events, 2) Counting the events themselves, or 3) Generating baud rates for the serial port.

Timers and Counters

Could use software techniques, but this keeps the processor occupied. Better to use interrupts & the two 16- bit count- up timers. Can either be programmed to:1. count internal - acting as timer2. count external - acting as counterAll counter action is controlled by the TMOD (timer mode register) and the TCON (timer/ counter control register).

Timers and Counters

TCON Timer control SFR contains timer 1& 2 overflow flags, external interrupt flags, timer control bits, falling edge/ Low level selector bit etc.

TMOD timer mode SFR is two four- bit registers (timer #1, timer #0). Select timer/ counter & various modes.)

Timers and Counters

Applications: (counter)Say we want to count a specified number of events (clock pulses or external events), then1. Store the start number in the counter. (Value maxcount-desired count+ 1)2. Counter automatically increments (in the background)3. When it rolls over to zero, it will set the timer flag.4. Test the flag in the program, or generate an interrupt .

Timers and Counters

Applications: (Timer)Timing configures the counter to count the internal clock frequency/ 12. (E. g. if fc = 6:0Mhz, then the timer clock will have a frequency of 500kHz.)To configure as a timer:1. Clear C/T~ bit in TMOD (Count internal frequency)2. Set TRx in the TCON (timer run) and the gate bit in the TMOD must be 0, or the external pin INTx~ must be 1.3. Select one of 4 modes.

Timing Subroutines

In microcontroller applications we need to wait a specified time, and so we need to have programmable time delays.In all cases your application will be written for a specific clock frequency, say 12MHz, 16MHz, 11.0592 MHz etc.)If you subsequently change the clock frequency, you will need to update your code, & possibly do some timing tests.

Timing Subroutines

The timing options are:1. Pure software time delays (wastefull)2. Software polled timer (still wastefull, but OK in

non- critical apps)3. Pure hardware using interrupts (accurate &

preferred method)

REGISTER SET OF 8051 8051 has two 8-bit register A and B which can be used to store operands. Including these register (A and B), 8051 has a family of special purpose register called as Special Function Register (SFR). There are 21 8 bit register ACC (A), B, PSW, PO, P1, P2, P3, IP, IE, TCON and SCON are all 8-bit, bit addressable register. The remaining registers, namely SP, DPH, DPL, TMOD, TH0, TL0, TH1, TL1, SBUF and PCON register are to be addressed as bytes i.e., they are not bit addressable. The Register DPH and DPL are the higher and lower bytes of 16-bit register DPTR, i.e., Data pointer, which is used for accessing external data memory. The register TH0 and TL0 form a 16 bit counter/timer register with H-indicating the upper byte and L-indicatin the lower byte of the 16-bit timer register T0. TH1 and TL1 form the 16 bit count for timer T1. The 4 port latches are represented by P0, P1, P2 and P3. Any communication with these ports is established using SFR addresses to these register. SP - Stack pointer PSW - Program status word contains status information IP - Interrupt priority (is programmable to control interrupt). TCON: Timer/counter control register. Some of the bits of this register can be used to turn on/off the times. This register also contain interrupt control flags for external interrupts INT1 and INT0 . TMOD: Used for programming the modes of operation of timer/counter. SCON: Is a serial port mode control register is used for transmit and receive operation. PCON: Power control register, contains power bit and idle bit which activate the power down mode and idle mode in 8051. In power down mode the on chip oscillator is stopped and all the contents of the controller are held maintaining the contents of RAM. The only way to terminate this mode is to hardware reset. The reset redefines all SFRs but the RAM contents are left unchanged. In Idle mode, the oscillator continues to run and the interrupt, serial port and timer blocks are active but the clock to the CPU is disabled. The CPU status is preserved. This mode can be terminated by hardware interrupt or hardware reset.

TCON (Timer Control Register):

TF1 − Timer 1 overflow flag. This is set by hardware when the timer/counter 1

overflows and is cleared by hardware. TR1 − Timer 1 run control bit. This is set/cleared by software to turn

timer/counter1/ON/OFF. TF0 − Timer 0 overflow flag. This is set by hardware when the Timer/Counter0

overflows and is cleared by hardware. TR0 − Timer 0 run control bit. This is set/Reset by software to turn

Timer/Counter on/off. IE1 − External interrupt 1 edge flag. This is set by hardware when external

interrupt edge is detected and is cleared by hardware, i.e., when the interrupt is processed. IT1 − Interrupt 1 type control bit. This is Set/Reset by software to specify falling

edge/low level triggered external interrupt. IE0 − External Interrupt 0 edge flag. This is set by hardware when external

interrupt edge is detected, and is cleared by hardware when the hardware interrupt is processed.

IT0 − Interrupt 0 type control bit. Thus is Set/Reset by software to specify falling edge/low level triggered external interrupt. SCON (Serial Ports Control Register):

SM0

Serial port mode specifies. SM

SM2 This enables the multiprocessor communication feature in modes 2 and 3. If SM2 is set to 1 then R1 will not be activated, if the received 9th data bit is 0. In mode1 if SM2 = 1 then R1 will not be activated if a valid stop bit was not received. In mode 0 - SM2 should be 0. REN This is Set/Reset by software to enable/disable reception. TB8 This selects the 9th bit that will be transmitted in modes 2 and 3. This Set/Reset by software. RB8 In modes 2 and 3, this is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. TI Transmit interrupt flag. This is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. This must be cleared by software. RI Receive Interrupt flag. This is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes excepting the case where SM2 is set. This must be cleared by software. PCON (Power Control Register):

SMOD − Double band rate bit. If timer 1 is used to generate baud rate, the baud rate is doubled when the serial port is used in modes 1, 2, 3. — − Not implemented. Reserved for future use. GF1 General Purpose Flag Bit. GF0 PD − Power down bit. Setting this bit activates power down operation in the 8051. IDL − Idle mode bit setting. This bit activates idle modes operation in 8051.

SIGNAL DESCRIPTIONS OF 8051

1. VCC : It is a 5V power supply pin. 2. VSS : It’s a return pin for the supply. 3. Reset: The reset input pin resets the 8051 only when it goes high for 2 or more cycles. For a proper reinitialization after reset the clk must be running. 4. ALE/Program: The ALE output pulse indicates that the valid address bits are available on their respective pins. The ALE signal is valid only for external memory accesses. This pin acts as programmable pulse input during on chip EPROM programming. 5. EA/VPP: External access enable pin if tied low, indicates that the 8051 can address external program memory. In other words the 8051 can execute a program in external memory only if EA is tied low for execution of program in internal memory the EA is tied high. This pin also receive 21 V for programming of the on chip EPROM. 6. PSEN : Program store enable is an active low output signal that acts as a strobe to read the external (signal) program memory. This goes low during external program memory access. 7. Port 0 (P0.0 - P0.7): Port 0 is an 8 bit bi-directional bit addressable IO port. This has been allotted an address in the SFR address range port 0 acts as multiplexed address/ data lines.

8. Port 1 (Port 1.0 - P 1.7): Port 1 acts as a 8 bit bi-directional bit addresses port. This has been allotted an address in the SFR address range. 9. Port 2 (P 2.0 - P 2.7): Port 2 acts as 8 bit bi-directional bit addressable IO port. It has been allotted an address in the SFR address range. During external memory access, port 2 emits higher eight bits of address (A15-A8) which are valid, if ALE goes high and EA goes low. 10. Port 3 (P3.0 - P3.7): Port 3 is an 8 bit bi-directional bit addressable IO port which has been allotted address in SFR address range. 11. XTAL1 and XTAL2: There is an inbuilt oscillator which derives clk frequency for the operation of the controller. XTA1, is input of the amplifier and XTAL2 is the output of the amplifier. A crystal is to be connected externally between these two pins to complete the feedback path to start oscillations.

DIRECT MEMORY ACCESS CONTROLLER (8237) The 8237 is a LSI controller IC that is most widely used to implement the DMA transfer. DMA capability permits devices, such as peripherals, to perform high speed data transfers between either two section of memory or between memory and an input output device. DMA mode of operation is most frequently used when blocks or packets of data are to be transferred for instance disk controllers, Local area network controllers and communication controllers are devices that normally process data as blocks or packets. The following figure shows the 8237A DMA controller. In a microprocessor system the 8237A can acts as a peripheral device and its operation must be initialized through software. This is done by reading from or writing to the register of DMA controller. These data transfer takes place through microprocessor interface . Whenever 8237A is not in use by a peripheral device for DMA operation, it is in a state known as idle state. When in this state, the microprocessor can issue commands to the DMA controller and read from or write to its internal register. Data bus lines DB0

through DB7 are the path over which these data transfers take place. Which register is accessed is determined by a 4-bit register address that is applied to address inputs A0

through A3. During the data transfer bus cycle, other bits of the address are decoded external circuitry to produce a chip select (CS ) input for the 8237A when in the idle state, the 8237A continuously samples this input waiting for it to become active. Logic 0 at this input enables the microprocessor interface. The microprocessor tells the 8237A whether an input or output bus cycle is in progress with the signal IOR or IOW .

DMA Interface of the 8237A: With the above discussion, we have seen how a microprocessor talk to the register of 8237A. Now let us see how peripheral devices initiates DMA service. The 8237A contains 4 independent DMA channels, channels 0 through channel 3. Typically, each of these channel is dedicated to a specific device, such as a peripheral. The following figure shows the DMA interface. (Fig. 5.10) There are 4 DMA request inputs denoted as DREQ0 through DREQ3. These DREQ inputs corresponds to channels 0 through 3. In the idle state the 8327A continuously tests these inputs to see if one is active. When a peripheral device wants to perform DMA operation, it makes a request for service at its DREQ input by switching it to its active state. In response to DMA request, the DMA controller switches the hold request output to logic 1. Normally this output is supplied to the HOLD input of the 8086 and signals the microprocessor that the DMA controller needs to take control of the system bus. When the 8088/8086 is ready to give up control of the bus, it puts its bus signals in to the high impedance state and signals this fact to the 8237A by switching the HLDA (Hold acknowledge) output to the logic 1. HLDA of the 8088/86 is applied to the HLDA input of 8237A and signals that the system bus is now available for use by the DMA controller. The 8237A tells the requesting device that it is ready by outputting a DMA acknowledge (DACK) signal for each of these 4 DMA request inputs, DREQ0 through DREQ3, has a corresponding DMA acknowledge outputs DACK0 then DACK3. Once this DMA request/acknowledge handshake sequence is complete, the peripheral device gets direct access to the system bus and memory under the control 8237A following figure shows DMA interface.

During DMA bus cycles, the system bus is driven by the DMA controller not the microprocessor. The 8237A generates all the address and control signals needed to perform the memory and the input/output data transfers. At the beginning of the all DMA bus cycles, a 16-bit address is output on lines A0 - A7 and DB0 thru DB7. The upper 8 bits of the address, which are available on the data bus lines, appear at the same time that address strobe becomes active. The ADSTB is used to strobe the MSB of the address in to an external latch. This 16-bit address gives the 8237A the ability to directly address up to 64k bytes of storage location. The AEN (address latch enable) output signal is active during the complete DMA bus cycle and can be used to both enable the address latch and disable

other devices connected to the bus. Let us assume that an IO device wants to transfer data to memory. i.e., IO device want to write data to memory. In this case 8237A uses IOR output signal to the IO device to put the data onto data bus lines DB0 thru DB7. At the same time, it asserts MEMW to signal that the data available on the bus are to be written into memory. In this case the data are transferred directly from the IO device to memory and don’t go thru 8327A. In a similar way DMA transfer of Data can takes place from memory to an IO device. Now IO device reads data from the memory. For this data transfer the 8237A activates MEMR and IOW control signals. 5.2.2 Internal Architecture of 8237A: The following figure shows the internal architecture of 8237A. Here we have the following blocks. timing and control. priority encoder rotating priority logic. command control. 12 different types of registers. Let us consider these functional blocks in detail.

The timing and control part of 8237A generates the timing and control signals needed by the external bus interface. It accepts input as Ready and CS and produce output signals like ADSTB and AEN. READY input is used to accommodate for slow memory of IO devices. READY must go active, logic 1, before the 8237A will complete a memory or IO bus cycle. As long as READY is at logic 0, wait states are inserted to extend the duration of the current bus cycle. If multiple requests for DMA service are received by the 8237A, they are accepted on priority basis. One of two priority schemes can be selected for the 8237A under software control. They are called fixed priority and rotating priority. The fixed priority mode assigns priority to the channels in descending numeric order. That is channel 0 has the highest priority and channel 3 has the lowest priority. Rotating priority starts with the priority levels same way as in fixed priority. However, after a DMA request for a specific level gets services, the priority is rotated so that the previously active channel is reassigned to the lowest priority level for instance, assuming that channel, which was initially at priority level was just serviced, then DREQ2 is now at the highest priority level and DREQ1 rotates to the lowest level. The command control circuit decodes the register commands applied to 8237 A through microprocessor interface. In this way it determines which register is to be accessed and what type of operation is to be performed. However it is used to decode the

programmed operating modes of the device during the DMA operation. 8237 has 12 different types of Internal register.

Each DMA channel has two address register. They are called the base address register and current address register. The base address register holds the starting address for the DMA operation. Current address register contains the address of the next storage location to be accessed. These register must be loaded with appropriate value prior to initiating a DMA cycle. To load a new 16-bit address into the base register, we must write two separate byte one after the other to the address of the register. 8237A has an internal FF called first/last FF. This FF identifies which byte of the address is being written in to the register. If the FF = 0, then load low byte of address to the register. If FF = 1 then write high byte of address to the register. Current Word Register: Each channel has 16-bit current word register that carries number of data byte transfers to be carried out. The word count is decremented after each transfer and the new value is again stored back to current word register when a count becomes zero an EoP (End of Process) signal will be generated. Base Address and Base Word Count Register: Each channel has a pair of these register. These contain the original copy of the respective initial current address register and current word count register (before incrementing or decrementing). These are automatically written along with the current register. These can’t be read by CPU. The contents of these register are used for auto initialization. Command Register: This 8 bit register controls the complete operation of 8237. This can be programmed by the CPU and cleared by resent operation

Mode Register: Each DMA channel (contains) has an 8-bit mode register. This is written by CPU in programming mode.

Request Register: Each channel has a request bit associated with it in the required register. These are non-maskable and subject to prioritization by the priority resolving network of 8237. Each bit is set or reset under programming

Mask Register: Some times it may be required to disable a DMA request of certain channel. Each of the 4 channels has a mask bit which can be set under program control to disable the incoming DREQ requesting at the specific channel. This bit is set when the corresponding channel produces an EOP signal; if the channel is not programmed for autoinitialization. The register is set to FFH after a reset operation

Temporary Key: The temporary register holds data during memory-to-memory data transfers. After the completion of the transfer operation, the last word transferred remains in the temporary register till it is cleared by reset operation. Status Register: The status register keep track of all the DMA channel pending requests and status of their terminal counts (TC). Bits D0D3 are updated every time; the corresponding channel reaches TC or an external EOP occurs. These are cleared upon reset and also on each status read operation. Bits D4D7 are set, if the corresponding channels require services

Transfer Modes of 8237: Single Transfer Mode: In this mode the device transfers only one byte per second. The word count is decremented and address is decremented or incremented after each such transfer. The terminal count (TC) state is reached when the count becomes zero. For each transfer, the DREQ must be active until the DACK is activated. Block Transfer Mode: In this mode 8237 is activated by DREQ to continue the transfer until TC is reached i.e., block of data is transferred. The transfer cycle may be terminated due to EOP which forces the TC. The DREQ needs to be activated only till DACK signal is activated by DMA controller. Demand Transfer Mode: In this mode the device continuously transfers until a TC is reached or an external EOP is detected or DREQ signal goes inactive. Thus a transfer may

exhaust the capacity of data transfer of an input/output device. After the IO device is able to catch up, the service may be reestablished activating, the DREQ signal again. Cascade Mode: In this mode, more than one 8237 can be connected together to provide more than 4 DMA channels. The HRQ and HLDA signals from additional 8237s are connected with DREQ and DACK pins of a channel of the host 8237 respectively. The priorities of the DMA requests may be preserved at each level. The 1st device is only used for prioritizing the additional devices and it does not generate any address or control signal of its own. Memory to Memory Transfer: To perform the transfer of a block of data from one set of memory address to another one, this transfer mode to used. Program the corresponding mode bit in the command word, set the channel 0 and channel 1 to operate as source and destination channel. This transfer is initialized by setting the DREQ0 using software commands. The 8237 sends HRQ signal to the CPU as usual and when the HLDA signal is activated by the CPU; the device starts operating in block transfer mode to read the data from the memory. The channel 0 (CAR) Current Address Register acts as a source pointer. The byte read from the memory is stored in an temporary register of 8237. The channel 1 CAR acts as a destination pointer the pointers are automatically incremented a decremented, depending upon program. The channel 1 word count register is used as a counter and is decremented after each transfer.

PROGRAMMABLE COMMUNICATION INTERFACE (8251) Programmable communication interface is used for serial data transmission. It is an Universal Synchronous/Asynchronous Receiver Transmitter (USART). It is compatible with 8085, 8086, 8088 and 8748. It is fabricated using N-channel silicon gate technology 8251 can be used to transmit/ Receive serial data. It accepts data in the parallel format from the microprocessor and converts into serial data for transmission. It also receives serial data and converts them into parallel data and sends the data to the CPU. The following figures shows the schematic diagram of 8251. Pin Diagram

C /D (Control/ Data) when it is low data is transmitted on data bus when it is high control signals are transmits on the data bus. RD (Read). When it is low CPU reads data from 8251. WR (Write). When it is low CPU writes data into 8251. DSR (Data Set Ready). DTR (Data Terminal Ready). RTS (Request to Send). CTS (Clear to Send). A low or this pin enables 8251 to transmit (data) serial data. TXC (Transmitter Clock). It governs the rate of data transmission. T ξE (Transmitter Empty). TXE goes high when 8251 has no characters to transmit. It indicates the end of transmission. T ⋅ RDY (Transmitter Ready). R ⋅ RDY (Receiver Ready). R ⋅ D (Line for Recurring Data). T ⋅ D (Line for serial data transmission). R ⋅ C (Receiver Clock). It governs the rate at which the characters are received.

Methods of Data Communication: The data transmission between two points involves unidirectional or bi-directional transmission of digital data. There are basically 3 modes of data transfer. (a) Simplex (b) Half Duplex (c) Duplex. In Simplex mode data is transmitted only in one direction over a single communication channel. Example: a computer (CPU) may transmit data for a CRT display unit. In Half Duplex mode, data transmission may take place on either direction, but only one direction at a time. In a Duplex mode data may be transferred between two transreceivers in both directions simultaneously. ARCHITECTURE AND SIGNAL DESCRIPTION OF 8251 The following figure shows the block diagram. The data buffer interfaces the internal bus of the architecture with the system bus. The Read/write control logic controls the operation of the peripheral depending up on the operation initiated by the CPU. This unit also selects one of the two internal address these are control address and data address at the behest of the C/ D signal. The modem control unit handles the modem handshake signals to coordinate the communication between the modem and the USART. The transmit control unit transmits the data byte received by the data buffer from the CPU for further serial communication. This decides the transmission rate which is controlled by the Tx C ⋅ input frequency.

8251A Operating Modes: 8251A can be programmed to operate in its various modes using the mode control words. A set of control words may be written in the internal register of 8251A to make it operate in the desired mode. Once the 8251A is programmed as, required, the T X RDY is raised high to signal the CPU that 8251A is ready to receive data byte from it that is to be converted in to serial format and transmitted. This automatically goes low when the CPU writes the data in to 8251A. In the receiver mode 8251A receives serial data byte from modern or IO device. After receiving a entire data byte, R RDY ⋅ signal is raised high to inform the CPU that 8251A has a character read for it. The R RDY ⋅ , signal is automatically reset after the CPU reads the received byte from 8251A. The control words of 8251A are divided into two function type. (1) Mode Instruction Control Word. (2) Command Instruction Control Word. Asynchronous Mode: Mode instruction control word define the general operational characteristic of the 8251A. After the internal (reset command) or external (reset input pin) reset, this must be written to configure the 8251A as per the require operation once this has been written into 8251A,

SYNCH character or command instruction may be programmed further as per the requirement. To change the mode of operation from synchronous to asynchronous or viceversa, 8251A has to be reset using master chip reset.

Asynchronous Mode (Transmission): When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial data bits, followed by optional parity bit and stop bits using the asynchronous mode instruction control word format. This sequence is the transmitted using T X D output pin on the following edge T X C. When no data character are sent by the CPU to 8251a the T X D output remains “high” if a “break” has not been detected. Asynchronous Mode (Receive): A falling edge of R X D input line marks a start bit. At a baud rate of 16 X and 64 X, this start bit is again checked at the center of the start bit pulse and if detected low it is a valid start bit and the bit counter starts counting. The bit counter locates the data bits, parity bit and stop bit. If parity error occurs, the parity error flag is set. If a low level is detected as a stop bit, the framing error flag is set. The receiver require only one stop bit to mark end of the data bit string regardless of the stop bit program at the transmitting end. The 8-bit character is the loaded in to parallel IO buffer of 8251 A. R RDY × pin is then realised high to indicate to the CPU that a character is ready for it. If the previous character has not been read by the CPU the new character replaces it, and the overrun flag is set indicating that the previous character is lost. Synchronous Mode (Transmission): The T⋅ D output is high until the CPU sends a character to 8251, which usually is a SYNC character. When CTS line goes low the first character is serially transmitted out. All the characters are shifted out on the falling edges of TXC . Data is shifted out at the same rate as TXC , over TXD output line. If the CPU buffer becomes empty, the SYNC character or characters are inserted in the data stream over TXD output. The TX EMPTY pin is raised high to indicate that 8251A is empty; and is transmitting SYNC character. The TX EMPTY pin is reset, automatically when a data character is written to 8251 A by the CPU.

Synchronous Mode (Receiver): In this mode character synchronization can be achieved, internally or externally. If this

mode is programmed, then ‘ENTER HUNT’ command should be included in the 1st command instruction word written in to the 8251A. The data on RXD pin is sampled on the rising edge of the R C × . The content of the Receiver buffer is compared with the 1st SYNC character at every edge until it matches. It 8251 A is programmed for two SYNC character, the subsequent received character is also checked. When both the characters match, the hunting stops. The SYNDET pin is set high and is reset automatically by status read operation. If a parity bit is programmed, the SYNDET signal will not go high until the middle of parity bit, otherwise till the middle of the last data bit.

Serial IO

Basic concepts in serial IO• Interface requirements

– Address decoding, control signal generation• Alphanumeric codes

– ASCII, EBCDIC or any other coding• Transmission format

– Synch or asynch, simplex/duplex, rate of transmission• Error checks

– Parity, checksum, CRC• Data comm over telephone

– Voice:300Hz-3300Hz,Modem,fsk/psk/qpsk etc

Syn and asycn transmission

a) Synch format b) asynch format

Serial bit format

• Baud: number of signal changes per second; bits/second.• At 1200 baud; ASCII character I (49H) is presented• 11 bits includes 1 start, 8 data and 2 stop bits• D7 can be used as parity.

Data comm over telephone

Serial I/O standards• Commonly used to interface terminal, printer or

modem.• Standard is a common specification that all the

manufacturer have agreed upon.– Assigment of pin position for signal, voltage levels,

speed, length of cables and mechanical specs.• Current loop

– 20mA or 60mA, signals relatively noise free andsuitable over a long distance.

• voltage level– RS 232C, most commonly used method– DTE, DCE

RS 232C

• Speed 20Kbaud.• Distance 50 ft.• Logic zero: +3v to +15V• Logic one: -3v to -15V• Other signals are TTL.• 25 pins

Minimum interface with RS232C

• Usually printer is a DTE• Modem is a DCE

Other standard

Specs RS232C RS422A RS423ASpeed 20kbd 10Mbd 100kbdDistance 50ft 4000ft 4000ftLogic 0 3 to 15 B>A 4 to 6VLogic 1 -3 to -15 B<A -4 to -6Rcvrinput volt

±15V ±7 ±12

Software controlled Asycn serialI/O

• Output start bit• Convert chara into

serial stream withappr delay.

• Add parity• Output stop bits.

transmit

Init bit cntrSnd strt bit

Wait bit time

Get chr into A

o/p bit using D0

Wait bit time

Rotate nxt bit to D0.Dcr bit cntr

Last bit?

Add paritySnd stop bits

return

rcvRd o/p port

Wait ½ bit time

Set bit cntrClr data rgstr

Wait bit timeRd i/p

Save bit

Redy to rcv nxt bitDcr bit cntr

Last bit?

Chk parityWait for stop bits

return

Strt bit?

Bit still low?

N

N

N

N

Y

Y

Y

8085 serial I/O lines

• SOD (serial outputdata)

• SID (serial input data)SOD SDE X

D7 D6 D5 D4 D3 D2 D1 D0

1=enable0=disable

For interrupts

MVI A, 80H ; Set D7 =1RAR ; set D6 = 1, bring carry into D7SIM ; output D7

SID

D7 D6 D5 D4 D3 D2 D1 D0

For interruptsSerial i/p dataRIM ; reads a bit and put into D7

Data trans using SOD

• Send ascii char stored in B register.

SODATA: MVI C, OBH ;setup counter C to 11 bitsXRA A ; reset carry to 0

NXTBIT: MVI A, 80H ; set D7 to 1 of accumltrRAR ; Bring D7 into D6SIM ; output D7; start bitCALL BITTIM ; wait for 1 bit timeSTC ; set carry =1MOV A,B ; place ASCII chr into ACCRAR ; place ascii D0 in the carry, and 1 in D7MOV B,A ;save ACC to BDCR C ;one bit transmittedJNZ NXTBIT ; if not all bits transmitted, go backRET

(B) = 47H 0 1 0 0 0 1 1 1

CY D7 D6 D5 D4 D3 D2 D1 D0

XRA A 0 0 0 0 0 0 0 0 0MVI A, 80H 0 1 0 0 0 0 0 0 0RAR 0 0 1 0 0 0 0 0 0SIM outputs 0 as stop bitSTC 1 0 1 0 0 0 0 0 0MOV A,B 1 0 1 0 0 0 1 1 1

RAR 1 1 0 1 0 0 0 1 1MOV B,A B= 1 0 1 0 0 0 1 1DCR C C= 0 0 0 0 1 0 1 1JNZ NXTBIT 1 1 0 0 0 0 0 0 0RAR 0 1 1 0 0 0 0 0 0

.

When ascii D7 is sent out, register B will have all 1s from D0 to D7. In thelast two iterations logic 1s are sent out as stop bits.

Data reception using SIDSIDATA: RIM ; read input bit

RAL ; plc D7 into CYJC SIDATA ; if D7 = 1, not a start bit, go bck and read againCALL HALFBIT ; if D7=0. strt bit. wait hafl bit timeMVI C, 09 ; bit cont = 9

NXTBIT: CALL BITTIME ; wait for one bit timeRIM ; read input bitRAL ; save the bit D7 to CYDCR C ; one bit readJZ RETURN ; if all bits are read return to main progMOV A,B ; plc the bits saved so far into acc from BRAR ;plc bit saved in CY to D7 and sft all bits by 1 positionMOV B,A ; save bits in BJMP NXTBIT ; get nxt bit

HW controlled serial I/O

• SW control has following requirements:– An input port and an output port are req for

interfacing.– In transmission, MPU converts parallel data into serial

bits.– In reception, MPU converts bits from serial to parallel.– Trans and rec must match the time delay.

• In HW control has serial IO, all these featuresare incorporated in one chip, like 8251A(USART).

8251A• Chip select• Control/Data• Write• Read• Reset• Clock• Control register

•16 bit, modeinstr, commandinstr

• Status register•It has the sameadd as thecontrol register

• Data buffer•bidirectional

Control logic and registers• Control regstr

– 16 bit: 2 independent bytes– 1st byte: mode instr– 2nd byte command inst

• Status rgstr– Chks the rdy ststs of peripheral– Accessed when C/D’ is high– Same port add as control regstr

• Data buffer– Bi directional– At C/D’ is low

CS’ C/D’ RD’ WR’ Function0 1 1 0 MPU writes in the control register0 1 0 1 MPU reads status register0 0 1 0 MPU outputs data to data buffer0 0 0 1 MPU reads data from data buffer1 X X X USART is not selected

Blk diagram of Trn and Rcv section• Transmitter section

– TxD: serial bits are tran onthis line.

– TxC: controls bit trans rate.Clk freq can be 1,16,64times the baud.

– TxRDY: o/p signal,highindicates the trans buffer isempty and USRT ready toaccept a byte. Signal isreset when data is loadedin the buffer.

– TxE: o/p signal Highindicates that the O/Pregister is empty. Resetwhen a byte is trnasferdfrm buffer to o/p rgstr.

Receiver section

• RxD: bits are rcvd serially on this line• RxC: controls the rate at which bits are

rcvd by USART. In asych mode, it can be1, 16 or 64 times the baud.

• RxRDY: it goes high when USART has achar on the input buffer register and readyto transfer it to MPU. Can be used eitherto indicate the status or to interrupt MPU.

Initializing 8251A• Mode, baud, stop bits, parity, etc.• Control word: a) mode word b) command word• After a reset operation, a mode word must be written in

the control register followed by a command word.Command word can be changed at any time duringoperation, but mode can only be changed only after areset operation. It can be reset using internal reset bit(D6) in the command word.

Interfacing RS232 terminal using8251A

• TxC is 153.6 kHz.• Asycn mode with 9600 baud• Character length = 7 bits, two stop

bits• No parity check.• Port add

– Data register: FEh– Control/status register: FFh

D7 D6 D5 D4 D3 D2 D1 D0

Stop bits No parity7 bits chr

1 0 0 1 0 1 01

Baud= TxC/16=153.6k/16 = 9600

•Mode word:

•Command word (asynch mode):

0 X 1 X 0 X 1D7 D6 D5 D4 D3 D2 D1 D0

X

Tr EnblRcv DisblErr RstPrvntsIntrnalreset

X X X X X X 1D7 D6 D5 D4 D3 D2 D1 D0

X

•Status word:

Tr rdy

=01h

=11h

=CAh

Initialization intruction:SETUP: MVI A, CAh ; load mode word

OUT FFh ; write mode word to control rgstrMVI A, 11h ; load command wordOUT FFh ; enable trnsmitter

STATUS: IN FFh ; read stats wordANI 01h ; mask all bits except D0

JZ STATUS ; if D0 = 0, Tr buffer is full, go back and wait

PROGRAMMABLE INTERVAL TIMER (8253/8254) • The following fig shows a schematic diagram containing an 8-bit bidirectional port, 5- bit control port and the relation of INTR with the control pins. Port B can either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2. • Mode 2 is not available for port B. The following fig shows the control word. • The INTR goes high only if either IBF, INTE2, STB and RD go high or OBF,INTE1, ACK and WR go high. The port C can be read to know the status of the peripheral device, in terms of the control signals, using the normal I/O instructions.

• Compatible with All Intel and Most other Microprocessors • Handles Inputs from DC to 10 MHz • 8 MHz 8254 • 10 MHz 8254-2 • Status Read-Back Command • Six Programmable Counter Modes • Three Independent 16-Bit Counters • Binary or BCD Counting • Single a 5V Supply • Standard Temperature Range • The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. • It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz. • All modes are software programmable. The 8254 is a superset of the 8253. • The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

BLOCK DIAGRAM

Functional Description • The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems. • It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software. • The 8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay. • After the desired delay, the 8254 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated. Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are:

Real time clock Event-counter Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller

• DATA BUS BUFFER: This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus, see the figure : Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions. • READ/WRITE LOGIC : The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into. • A “low” on the RD input tells the 8254 that the CPU is reading one of the counters. • A “low” on the WR input tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 8254 has been selected by holding CS low. • CONTROL WORD REGISTER :The Control Word Register is selected by the Read/Write Logic when A1,A0 = 11. CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters. • The Control Word Register can only be written to; status information is available with the Read-Back Command. • COUNTER 0, COUNTER 1, COUNTER 2 : These three functional blocks are identical in operation, so only a single Counter will be described. • The Counters are fully independent. Each Counter may operate in a different mode. Each counter has 3 logical lines Clock (CLK) ,Gate and Out. Clock and Gate are input signals and OUT is the output signal. The functions of these lines changes depending on how the device is initialized. Gate signals act as start pulse , depending on the mode of operation of the counter. Clock acts as clock input to the counter. Each counter is a 16-bit presettable down counter. The counter can be easily read by the CPU and the data of the counter will not be altered. Read/write control supports five control signals RD, WR, A0, A1 and CS. The functions of first four control signals are tabulated above. Address lines A0 and A1 selects Counter 0 or Counter 1 Counter 2 or the Control word register. Based on the RD or WR signals are enabled at a particular time determines that the selected counter or the control word register can be read or written into.

Operating Modes of 8253/8254: The timer can be operated in six different operating modes . These six modes are denoted as mode 0, mode 1, mode 2, mode 3, mode 4, and mode 5. Mode 0: Interrupt on Terminal Count: The counter will be programmed to an initial value afterwards counts down at a rate equal to the input clock frequency. When the count becomes zero the OUT pin will be at logic 1. The output will stay at logic 1 until the counter is reloaded with a new value or the same value or the control word is written in to the device. Once the counter starts counting down the GATE input can disable the internal conting by setting the GATE to logic 0. Mode 1: Programmable one-Shot: In mode 1 the device can be setup to give an output pulse that is an integer number of clock pulses. The one-shot is triggered on rising edge of the GATE input. If the trigger occurs during the pulse output the 8253/8254 will be retriggered again. Mode 2: Rate Generator: In this mode the counter behaves as a “ divide by N “ counter. The OUT pin of the counter goes to low for one input clock period. The time between the pulses of going low is dependent on the present count in the counter’s register. The formula to find the count value, which have to be loaded in the counter is determined by input clock frequency and the output clock frequency. Count N = Fi / Fo =Input clock frequency / Output clock frequency Mode 3: Square wave generator: Mode 3 is same as mode 2 except that the output will be high for half the period and low for half. If the count is odd the output will be high for (n+1)/2 and low for (n-1)/2 counts. Mode 4: Software Triggered Strobe:In this mode the OUT is initially high. The counter is loaded with an initial value and upon the terminal count the output will go to a logic 0 for one clock period and then return to logic1. Mode 5: Hardware Triggered Strobe:This mode is similar to Mode 4. In this mode the rising edge of the trigger input will start counting of the counter. The output goes low for one clock at the

terminal count. The counter is retriggerable i.e if the trigger input is taken low and then high during a count sequence the sequence will start over. When the external trigger input goes to logic 1 the timer will start to time out. If the external trigger occurs again prior to the time completing a full time out the timer will retrigger.

M. Krishna Kumar MM/M3/LU9a/V1/2004 1

8254

• Compatible with All Intel and Most other Microprocessors• Handles Inputs from DC to 10 MHz

8 MHz 825410 MHz 8254-2

• Status Read-Back Command• Six Programmable Counter Modes• Three Independent 16-Bit Counters• Binary or BCD Counting• Single a 5V Supply• Standard Temperature Range


• The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design.

• It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz.

• All modes are software programmable. The 8254 is a superset of the 8253.

• The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

8254 (cont..)


Figure 1. Pin Configuration


Figure 2. 8254 Block Diagram


Pin DescriptionSymbol Pin

No.Type Name and Function

D7-D0 1 - 8 I/O DATA: Bi-directional three state data bus lines, connected to system data bus.

CLK 0 9 I CLOCK 0: Clock input of Counter 0.

OUT 0 10 O OUTPUT 0: Output of Counter 0.

GATE 0 11 I GATE 0: Gate input of Counter 0.

GND 12 GROUND: Power supply connection.

VCC 24 POWER: A 5V power supply connection.

WR 23 IWRITE CONTROL: This input is low during CPU write operations.

RD 22 IREAD CONTROL: This input is low during CPU read operations.


CS 21 ICHIP SELECT: A low on this input enables the 8254 to respond to RD and WR signals. RD and WR are ignored otherwise.

A1, A0 20 – 9 I ADDRESS: Used to select one of the three Counters or the Control Word Register for read or write operations. Normally connected to the system address bus.A1 A0 Selects0 0 Counter 00 1 Counter 11 0 Counter 21 1 Control Word Register


OUT 2 17 O OUT 2: Output of Counter 2.

Pin Description (cont..)





OUT 1 OUT 1 O OUT 1: Output of Counter 1.

Pin Description (cont..)


Functional Description

• The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems.

• It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software.

• The 8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay.


• After the desired delay, the 8254 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.

• Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are:

• Real time clock• Event-counter• Digital one-shot

Functional Description (cont..)


• Programmable rate generator• Square wave generator• Binary rate multiplier• Complex waveform generator• Complex motor controller

Functional Description (cont..)


Block Diagram

• DATA BUS BUFFER: This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus, see the figure below : Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions.

• READ/WRITE LOGIC : The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1 and A0select one of the three counters or the Control Word Register to be read from/written into.

• A “low” on the RD input tells the 8254 that the CPU is reading one of the counters.


Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions


• A “low” on the WR input tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 8254 has been selected by holding CS low.

• CONTROL WORD REGISTER :The Control Word Register (see Figure 4) is selected by the Read/Write Logic when A1,A0 = 11. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.

Block Diagram (cont..)


Figure 4. Block Diagram Showing Control Word Register and Counter Functions


• The Control Word Register can only be written to; status information is available with the Read-Back Command.

• COUNTER 0, COUNTER 1, COUNTER 2 :These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a single counter is shown in Figure 5.

• The Counters are fully independent. Each Counter may operate in a different Mode.

• The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates.



• The status register, shown in Figure 5, when latched, contains the current contents of the Control Word Register and status of the output and null count flag. (See detailed explanation of the Read-Back command.)

• The actual counter is labelled CE (for ``Counting Element''). It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for ``Output Latch''; the subscripts M and L stand for ``Most significant byte'' and ``Least significant byte'‘respectively.



Figure 5. Internal Block Diagram of a Counter


• Both are normally referred to as one unit and called just OL. These latches normally ``follow'‘ the CE, but if a suitable Counter Latch Command is sent to the 8254, the latches ``latch'' the present count until read by the CPU and then return to ``following'' the CE.

• One latch at a time is enabled by the counter's Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read.



• Similarly, there are two 8-bit registers called CRM and CRL (for ``Count Register''). Both are normally referred to as one unit and called just CR.

• When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously.

• CRM and CRL are cleared when the Counter is programmed. In this way, if the Counter has been programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero.



• Note that the CE cannot be written into, whenever a count is written, it is written into the CR.

• The Control Logic is also shown in the diagram.• CLK n, GATE n, and OUT n are all connected to the

outside world through the Control Logic.• 8254 SYSTEM INTERFACE :The 8254 is a component

of the Intel Microcomputer Systems and interfaces in the same manner as all other peripherals of the family.

• It is treated by the system's software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming.



• Basically, the select inputs A0,A1 connect to the A0,A1address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method. Or it can be connected to the output of a decoder, such as an Intel 8205 for larger systems.

• Programming the 8254 :Counters are programmed by writing a Control Word and then an initial count.

• The Control Words are written into the Control Word Register, which is selected when A1,A0 = 11. The Control Word itself specifies which Counter is being programmed.



Figure 6. 8254 System Interface


• Control Word Format: A1,A0 = 11, CS = 0, RD = 1, WR = 0.

• By contrast, initial counts are written into the Counters, not the Control Word Register. The A1,A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used.

• Write Operations: The programming procedure for the 8254 is very flexible. Only two conventions need to be remembered:

1) For each Counter, the Control Word must be written before the initial count is written.



2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).

• Since the Control Word Register and the three Counters have separate addresses (selected by the A1,A0 inputs), and each Control Word specifies the Counter it applies to (SC0,SC1 bits), no special instruction sequence is required.

• Any programming sequence that follows the conventions in Figure 7 is acceptable.



Figure 7. Control Word Format

NOTE: Don't care bits (X) should be 0 to insure compatibility with future Intel products.


• A new initial count may be written to a Counter at any time without affecting the Counter's programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format.

• If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count.



Figure 8. A Few Possible Programming Sequences


• Read Operations: It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 8254.

• There are three possible methods for reading the counters: a simple read operation, the Counter Latch Command, and the Read-Back Command.

• Each is explained below. The first method is to perform a simple read operation. To read the Counter, which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.

• Otherwise, the count may be in the process of changing when it is read, giving an undefined result.



• COUNTER LATCH COMMAND: The second method uses the ``Counter Latch Command''.

• Like a Control Word, this command is written to the Control Word Register, which is selected when A1,A0 = 11. Also like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word.

• The selected Counter's output latch (OL) latches the count at the time the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed).



Figure 9. Counter Latching Command Format


• The count is then unlatched automatically and the OL returns to ``following'' the counting element (CE).

• This allows reading the contents of the Counters ``on the fly'' without affecting counting in progress.

• Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter's OL holds its count until it is read.

• Counter Latch Commands do not affect the programmed Mode of the Counter in any way.



• If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.

• With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other, read or write or programming operations of other Counters may be inserted between them.



• Another feature of the 8254 is that reads and writes of the same Counter may be interleaved.

• Example: If the Counter is programmed for two byte counts, the following sequence is valid.

1) Read least significant byte.2) Write new least significant byte.3) Read most significant byte.4) Write new most significant byte.



• If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read.

• READ-BACK COMMAND: The third method uses the Read-Back Command. This command allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter (s).



• The command is written into the Control Word Register and has the format shown in Figure 10. The command applies to the counters selected by setting their corresponding bits D3, D2, D1 = 1.

• The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT bit D5 = 0 and selecting the desired counter (s). This single command is functionally equivalent to several counter latch commands, one for each counter latched.



Figure 10. Read-Back Command Format


• Each counter's latched count is held until it is read (or the counter is reprogrammed).

• The counter is automatically unlatched when read, but other counters remain latched until they are read. If multiple count read-back commands are issued to the same counter without reading the count, all but the first are ignored; i.e., the count which will be read is the count at the time the first read-back command was issued.

• The read-back command may also be used to latch status information of selected counter (s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a counter is accessed by a read from that counter.



• The counter status format is shown in Figure 11.• Bits D5 through D0 contain the counter's programmed

Mode exactly as written in the last Mode Control Word. OUTPUT bit D7 contains the current state of the OUT pin.

• This allows the user to monitor the counter's output via software, possibly eliminating some hardware from a system. NULL COUNT bit D6 indicates when the last count written to the counter register (CR) has been loaded into the counting element (CE).

• The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions, but until the count is loaded into the counting element (CE), it can't be read from the counter.



Figure 11. Status Byte


• If the count is latched or read before this time, the count value will not reflect the new count just written. The operation of Null Count is shown in Figure 12.

• If multiple status latch operations of the counter (s) are performed without reading the status, all but the first are ignored; i.e., the status that will be read is the status of thecounter at the time the first status read-back command was issued.

• Both count and status of the selected counter (s) may be latched simultaneously by setting both COUNT and STATUS bits D5,D4 = 0. This is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also.



Figure 12. Null Count Operation


• Specifically, if multiple count and/or status read-back commands are issued to the same counter (s) without any intervening reads, all but the first are ignored. This is illustrated in Figure 13.

• If both count and status of a counter are latched, the first read operation of that counter will return latched status, regardless of which was latched first. The next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. Subsequent reads return unlatched count.



Figure 13. Read-Back Command Example


Figure 14. Read/Write Operations Summary


• Mode Definitions :The following are defined for use in describing the operation of the 8254.

• CLK Pulse: A rising edge, then a falling edge, in that order, of a Counter's CLK input.

• Trigger: A rising edge of a Counter's GATE input.• Counter loading: The transfer of a count from the CR to

the CE (refer to the ``Functional Description'').• MODE 0: INTERRUPT ON TERMINAL COUNT :

Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero.

Modes (cont..)


• OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter.

• GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT.

• After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go high until N a 1 CLK pulses after the initial count is written.

• If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:

Modes (cont..)


1) Writing the first byte disables counting. OUT is set low immediately (no clock pulse required).

2) Writing the second byte allows the new count to be loaded on the next CLK pulse.

• This allows the counting sequence to be synchronized by software. Again, OUT does not go high until Na1 CLK pulses after the new count of N is written.

• If an initial count is written while GATE e 0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT will go high N CLK pulses later; no CLK pulse is needed to load the Counter as this has already been done.

Modes (cont..)


Figure 15. Mode 0


Note: 1. Counters are programmed for binary (not BCD) countingand for reading/writing least significant byte (LSB) only.2. The counter is always selected (CS always low).3. CW stands for ``Control Word''; CW = 10 means a controlword of 10 HEX is written to the counter.4. LSB stands for ``Least Significant Byte'' of count.5. Numbers below diagrams are count values. The lowernumber is the least significant byte. The upper number is themost significant byte. Since the counter is programmed toread/write LSB only, the most significant byte cannot beread. N stands for an undefined count. Vertical lines showtransitions between count values.

Modes (cont..)


• MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT: OUT will be initially high.

• OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero.

• OUT will then go high and remain high until the CLK pulse after the next trigger.

• After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.

Modes (cont..)


• The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT.

• If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.

Modes (cont..)


Figure 16. Mode 1


• MODE 2: RATE GENERATOR: This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt.

• OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.

• Mode 2 is periodic, the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles.

• GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low during an output pulse, OUT is set high immediately.

Modes (cont..)


• A trigger reloads the Counter with the initial count on the next CLK pulse, OUT goes low N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Counter.

• After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT goes low N CLK Pulses after the initial count is written.

• This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence.

Modes (cont..)


• If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count.

• Otherwise, the new count will be loaded at the end of the current counting cycle. In mode 2, a COUNT of 1 is illegal.

• MODE 3: SQUARE WAVE MODE :Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high.

Modes (cont..)


Figure 17. Mode 2


• When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely.

• An initial count of N results in a square wave with a period of N CLK cycles. GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high immediately; no CLK pulse is required.

• A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter.

Modes (cont..)


• After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also.

• Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle.

Modes (cont..)


• Mode 3:Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses.

• When the count expires OUT changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely.

• Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses.

Modes (cont..)


Figure 18. Mode 3


• One CLK pulse after the count expires, OUT goes low and the Counter is reloaded with the initial count minus one.

• Succeeding CLK pulses decrement the count by two.• When the count expires, OUT goes high again and the

Counter is reloaded with the initial count minus one. The above process is repeated indefinitely.

• So for odd counts, OUT will be high for (N - 1)/2 counts and low for (N - 1)/2 counts.

Modes (cont..)


• MODE 4: SOFTWARE TRIGGERED STROBE :• OUT will be initially high. When the initial count expires,

OUT will go low for one CLK pulse and then go high again. The counting sequence is ``triggered'‘ by writing the initial count.

• GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse.

• This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N + 1 CLK pulses after the initial count is written.

Modes (cont..)


• If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:

1) Writing the first byte has no effect on counting.2) Writing the second byte allows the new count to be loaded

on the next CLK pulse.• This allows the sequence to be ``retriggered'' by software.

OUT strobes low N a 1 CLK pulses after the new count of N is written.

Modes (cont..)


Figure 19. Mode 4


• MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE) :OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one CLK pulse and then go high again.

• After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N = 1 CLK pulses after a trigger.

Modes (cont..)


• A trigger results in the Counter being loaded with the initial count on the next CLK pulse. The counting sequence is retriggerable. OUT will not strobe low for N a 1 CLK pulses after any trigger. GATE has no effect on OUT.

• If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there.

Modes (cont..)


Figure 20. Mode 5


• Operation Common to All Modes: • PROGRAMMING: When a Control Word is written to a

Counter, all Control Logic is immediately reset and OUT goes to a known initial state; no CLK pulses are required for this.

• GATE: The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3, and 4 the GATE input is level sensitive, and the logic level is sampled on the rising edge of CLK. In Modes 1, 2, 3, and 5 the GATE input is rising-edge sensitive.

Modes (cont..)


• In these Modes, a rising edge of GATE (trigger) sets an edge-sensitive flip-flop in the Counter. This flip-flop is then sampled on the next rising edge of CLK; the flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occurs-a high logic level does not have to be maintained until the next rising edge of CLK.

• Note that in Modes 2 and 3, the GATE input is both edge-and level-sensitive. In Modes 2 and 3, if a CLK source other than the system clock is used, GATE should be pulsed immediately following WR of a new count value.

Modes (cont..)


Figure 21. Gate Pin Operations Summary


• COUNTER: New counts are loaded and Counters are decremented on the falling edge of CLK.

• The largest possible initial count is 0, this is equivalent to 2

16 for binary counting and 104 for BCD counting. The

Counter does not stop when it reaches zero.• In Modes 0, 1, 4, and 5 the Counter ``wraps around'' to the

highest count, either FFFF hex for binary counting or 9999 for BCD counting and continues counting.

• Modes 2 and 3 are periodic; the Counter reloads itself with the initial count and continues counting from there.

Modes (cont..)


Figure 22. Minimum and Maximum Initial Counts

NOTE: 0 is equivalent to 216 for binary counting and 104 for BCD counting.

Programmable Peripheral Interface (8255) • The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8- bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port. C upper. • The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C. • Both the port C are assigned the same address. Thus one may have either three 8- bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register ( CWR ). • The internal block diagram and the pin configuration of 8255 are shown in fig. • The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of both data and control words. • RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus. • This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer. • The signal description of 8255 are briefly presented as follows : • PA7−PA0: These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register. • PC7−PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines. • This port also can be used for generation of handshake lines in mode 1 or mode 2. • PC3−PC0 : These are the lower port C lines, other details are the same as PC7−PC4 lines. • PB0−PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A. • RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255. • WR : This is an input line driven by the microprocessor. A low on this line indicates write operation. • CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected. • A1−A0 : These are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i.e. three ports and a control word register as given in table below. • In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the

A0 and A1 pins of 8255 are connected with A1 and A2 respectively. • D0−D7 : These are the data bus lines those carry data or control word to/from the microprocessor. • RESET : A logic high on this line clears the control word register of 8255. All ports are set as input ports by default after reset. Block Diagram of 8255 • It has a 40 pins of 4 groups. 1. Data bus buffer 2. Read Write control logic 3. Group A and Group B controls 4. Port A, B and C • Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to system databus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU. • Control word and status information are also transferred through this unit. • Read/Write control logic: This unit accepts control signals ( RD, WR ) and also inputs from address bus and issues commands to individual group of control blocks ( Group A, Group B). • It has the following pins. a) CS – Chip select : A low on this PIN enables the communication between CPU and 8255. b) RD (Read) – A low on this pin enables the CPU to read the data in the ports or the status word through data bus buffer. c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to the control register through the data bus buffer. d) RESET: A high on this pin clears the control register and all ports are set to the input mode e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins control the selection of one of the 3 ports. • Group A and Group B controls : These block receive control from the CPU and issues commands to their respective ports. • Group A - PA and PCU ( PC7 –PC4) • Group B - PCL ( PC3 – PC0) • Control word register can only be written into no read operation of the CW register is allowed. a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes – mode 0, mode 1, mode 2. b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0, mode1. c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0.

Modes of Operation of 8255 • There are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR). • In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits. • Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2. • BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table. • I/O Modes : a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode. This mode provides simple input and output capabilities using each of the three ports. Data can be simply read from and written to the input and output ports respectively, after appropriate initialization. • The salient features of this mode are as listed below: 1. Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower) are available. The two 4-bit ports can be combinedly used as a third 8-bit port. 2. Any port can be used as an input or output port. 3. Output ports are latched. Input ports are not latched. 4. A maximum of four ports are available so that overall 16 I/O configuration are possible. • All these modes can be selected by programming a register internal to 8255 known as CWR. • The control word register has two formats. The first format is valid for I/O modes of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit set/ reset (BSR) mode of operation. b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input and output action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for port A. This group

including port A and PC3-PC5 from group A. Thus port C is utilized for generating handshake signals. The salient features of mode 1 are listed as follows: 1. Two groups – group A and group B are available for strobed data transfer. 2. Each group contains one 8-bit data I/O port and one 4-bit control/data port. 3. The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched. 4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3- PC5 are used to generate control signals for port A. the lines PC6, PC7 may be used as independent data lines. • The control signals for both the groups in input and output modes are explained as follows: Input Control Signal Definitions (Mode 1 ): • STB (Strobe input) – If this lines falls to logic low level, the data available at 8- bit input port is loaded into input latches. • IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data has been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising edge of RD input. • INTR (Interrupt request) – This active high output signal can be used to interrupt the CPU whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig. • INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of the processor by putting the data on the bus and sending the strobe signal. Output Control Signal Definitions (Mode 1) : • OBF (Output buffer full ) – This status signal, whenever falls to low, indicates that CPU has written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR signal and reset by a low going edge at the ACK input. • ACK ( Acknowledge input ) – ACK signal acts as an acknowledgement to be given by an output device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port is received by the output device. • INTR ( Interrupt request ) – Thus an output signal that can be used to interrupt the CPU when an output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2 respectively. Mode 2 ( Strobed bidirectional I/O ): This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of operation provides 8255 with an additional features for communicating with a peripheral device on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow and synchronization between the data transmitter and receiver. The interrupt generation and other functions are similar to mode 1 • In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The RD and WR signals decide whether the 8255 is going to operate as an input port or output port. • The salient features of Mode 2 of 8255 are listed as follows: 1. The single 8-bit port in group A is available. 2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.

3. Three I/O lines are available at port C.( PC2 – PC0 ) 4. Inputs and outputs are both latched. 5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the 8-bit data transfer on port A. • Control signal definitions in mode 2: • INTR – (Interrupt request) As in mode 1, this control signal is active high and is used to interrupt the microprocessor to ask for transfer of the next data byte to/from it. This signal is used for input (read) as well as output (write) operations. • OBF ( Output buffer full ) – This signal, when falls to low level, indicates that the CPU has written data to port A. • ACK ( Acknowledge ) This control input, when falls to logic low level, acknowledges that the previous data byte is received by the destination and next byte may be sent by the processor. This signal enables the internal tristate buffers to send the next data byte on port A. • INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset mode with PC6. • Control signals for input operations : • STB (Strobe input ) A low on this line is used to strobe in the data into the input latches of 8255. • IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises to logic ‘1’. This can be used as an acknowledge that the data has been received by the receiver. • The waveforms in fig show the operation in Mode 2 for output as well as input port. • Note: WR must occur before ACK and STB must be activated before RD.

The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel micsystems. Its function is that of a general purposes I/O component to Interface peripheral equmicrocomputer system bush. The functional configuration of the 8255A is programmed by thsoftware so that normally no external logic is necessary to interface peripheral devices or st

Data Bus Buffer

This 3-stable bi-directional 8-bit buffer is used to interface the 8255A to the systems data butransmitted or received by the buffer upon execution of input or output instructions by the CPwords and status information are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the Internal and External transfers of both DataStatus words. It accepts inputs from the CPU Address and Control business and in turn, issuto both of the Control Groups.

(CS)

Chip Select. A ¡§low¡¦ on this input pin enables the communication between the 8255A, and

(RD)

Read. A ¡§low¡¨ on this Input pin enables the 8255A to send the data or status information tothe data bus. In essence, it allows the CPU to ¡§read from the 8255A.

(WR)

Write. A. ¡§ low¡¨ on the input pin enables the CPU to write data or control words into the 82

(A0 and A1)

Port Select 0 and Port Select 1. The Input signals, in conjunction with the RD and WR Inputselection of one of the three ports or the control word registers. They are normally connectesignificant bits of the address bus (A0 and A1).

8255A BASIC OPERATION

___ ___ ___

A1 A0 RD WR CS INPUT OPERATION (READ)

Seite 1 von 168253/8254 Data Sheet for Decision Computer 8255/8254 Timer and Counter Card

07.03.2004http://www.pci8255.net/8255%20data%20sheet.htm

0 0 0 1 0 PORT A ¡V DATA BUS 0 1 0 1 0 PORT B ¡V DATA BUS 1 0 0 1 0 PORT C ¡V DATA BUS

OUTPUT OPERATION (WRITE) 0 0 1 0 0 DATA BUS ¡V PORT A 0 1 1 0 0 PORT B ¡V DATA BUS 1 0 1 0 0 PORT C ¡V DATA BUS 1 1 1 0 0 DATA BUS ¡V CONTROL

DISABLE FUNCTION X X X X 1 DATA BUS ¡V 3 STATE 1 1 0 1 0 ILLEGAL CONDITION X X 1 1 0 DATA BUS ¡V 3 STATE

Figure 3. 8255 A Block Diagram Showing Data Bus Buffer and Read/Write Control Log

(RESET)

Reset. A ¡§high¡¨ on this Input clears the control register and all ports (A, B, C) are set to th

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essenc



¡§output¡¨ a control word to the 8255A. The control word contains information such as ¡§moreset¡¨, etc. that Initializes the functional configuration of the 8255A.

Each of the Control blocks (Group A and Group B) accepts commands from the Read/Writereceives control words from the internal data bus and issues the proper commands to its as

Control Group A ¡V Port A and Port C upper (C7 C4)

Control Group B ¡V Port B and Port C lower (C3 C0)

The Control Word Register can only be written into. No.

Read operation of the Control Word Register is allowed.

Ports A, B, and C

The 8255A contains three 8-bit ports (A , B, and C). All can be configured in a wide variety ocharacteristics by the system software but each has its own special features or personally tothe power and flexibility of the 8255A.

Port A. One 8 bit data output latch/buffer and one 8-bit data input latch.

Port B. One 8-bit data output latch/buffer and one 8-bit data input buffer.

Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch andfor the controls signal outputs and status signal inputs in conjunction with ports A and B.



D7 ¡V D0 DATA BUS DIRECTIONAL RESET RESET INPUT CS CHIP SELECT RD READ INPUT WR WRITE INPUT A0 ¡V A1 PORT ADDRESS PA 7 PA 0 PORT A (BIT) PB 7 PB 0 PORT B (BIT) PC 7 PC 0 PORT C (BIT) Vcc 5 VOLTS GND 0 VOLTS

8255A OPERATIONAL DESCRIPTION

Mode Selection

There are three basic modes of operation that can be selected by the systems software:

Mode O ¡V Basic Input/Output

Mode 1 ¡V Strobed Input/Output

Mode 2 ¡V Bi-Directional Bus

When the reset Input goes ¡§high¡¨ all ports will be set to the Input mode (i.e., all 24 lines wiImpedance state). After the reset is removed the 8255A can remain in the input mode with nrequired. During the execution of the systems program any of the other modes may be selecoutput Instruction. This allows a single 8255A to service a variety of peripheral devices with maintenance routine.

The modes for Ports A and Port B can be separately defined, while Port C is divided into twothe Port A and Port B definitions. All of the output registers, including the status flip-flops, wimode is changed. Modes may be combined so that their functional definition can be ¡§tailorestricture. For instance; Group B can be programmed in Mode 0 to monitor simple switch closcomputational results, Group A could be programmed in Mode 1 to monitor a keyboard or tainterrupt-driven basis.



Figure 6. Mode Definition Format

The Mode definitions and possible mode combinations may seem confusing at first but aftercomplete device operation a simple , logical I/O approach will surface. The design of the 825things such as efficient PC board layout, control signal definition vs PC layout and complete almost any peripheral device with no use of the available pints.

Single Bit Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset using a single OUT put Instruction. This frequirements in Control-based applications.



When Port C is being used as status/control for Port A or B these Bits can be set or reset byjust as if they were data output port.

Interrupt Control Functions

When the 8255A is programmed to operate in mode 1 or mode 2, control signals are providerequest input to the CPU. The interrupt request signal generated from port C, can be inhibitethe associated INTE flip-flop, using the bit set/reset function of port C.

This function allows the Programmer to disallow or allow a specific I/O device to interrupt thedevice in the interrupt structure.

INTE flip-flop definition (BIT-SET) ¡V INTE is SET ¡V Interrupt enable

(BIT-RESET) ¡V INTE is RESET ¡V Interrupt disable

Note: All Mask flip-flops are automatically reset during mode selection and device reset.

Operating Modes

Mode 0 (Basic Input/Output). This functional configuration provides simple input operations f¡§handshaking¡¨ is required data is simply written to or read from a specified port.

Mode O Basic Functional Definitions:

*Two 8-bit ports and two 4-bit port



*Any port can be input or output. *Outputs are not latched. *Inputs are not latched. *16 different Input/output configurations are not possible in this Mode.

Mode 0 Configuration



Operating Modes

MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferrport in conjunction with strobes or ¡§handshaking¡¨ signals. In mode 1, port A and Port B useor accept these ¡§handshaking¡¨ signals.

Mode 1 Basic Functional Definitions:

*Two groups (Group A and Group B) *Each group contains one 8-bit data port and one 4-bit control/data port *The 8-bit data port can be either Inputs or output Both inputs and outputs are latched. *The 4-bit port is used for control and status of the 8-bit data port.

Input Control Signal Definition

STB (Strobe Input). A ¡§ low ¡§ on the input loads data into the input latch.

IBF (Input Buffer Full F/F)



A ¡§high¡¨ on this output indicates that the data has been loaded into the input latch. In esse

IBF is set by STB input being low and is reset by the rising edge of the RD input.

INTR (Interrupt Request)

A ¡§high¡¨ on this output can be used to interrupt the CPU when an input device is requestinis a ¡§one¡¨, IBF is a ¡§one ¡§ and INTE is ¡§one ¡§. It is reset by the falling edge of RD. Thisdevice to request service from the CPU by simply strobing its data into port.

INTE A

Controlled by bit set/reset of PC4

INTE B

Controlled by set/reset PC2

Output Control Signal Definition

OBF (Output Buffer Full F/F). The OBF output will go ¡§low¡¨ to indicate that the CPU has The OBF F/F will be set by rising edge of the WR input being low.



ACK (Acknowledge Input). A ¡§low¡¨ on this input informs the 8255A that the data from poessence, a response from the peripheral device indicating that it has received the data outpu

INTR (Interrupt Request). A ¡§high¡¨ on the output can be used to interrupt the CPU when transmitted by the CPU. INTR is set when ACK is a ¡§one¡¨, OBF is a ¡§one¡¨, and INTE is aedge of WR.

INTE A

Controlled by bit set/reset of PC6.

INTE B

Controlled by bit s

of

PC2.

Combination of MODE 1

Port A and B can be Individually defined as Input or output in Mode 1 to support a wide varle



Mode 2 (Strobed Bidirectional Bus I/O). This functional configuration provides a means fodevice or structure on a single 8-bit bus for both transmitting and receiving data (bi-directionare provided to maintain proper bus flow discipline in a similar manner to MODE.

1. Interrupt generation and enable/disable functions are also available.

MODE 2 Basic Functional Definitions:

*Used in Group A only. *One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C). *Both Inputs and Outputs are latched. *The 5-bit control port (Port C) is used for control and status for the 8-bit,bi-directional bus po

Bi-directional Bus I/O Control Signal Definition

INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for both in

Output Operations OBF (Output Buffer Full). The OBF output will go ¡§low¡¨ to indicate that the CPU has writt

ACK (Acknowledge). A ¡§low¡¨ on this input enables the iri-state output buffer of port A to soutput buffer will be in the high impedance state.

INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PC6

Input Operations STB (Strobe Interrupt)

STB (Strobed Input). A ¡§low¡¨ on this input loads data into the input latch.

IBF (Input Buffer Full F/F). A ¡§high¡¨ on this output indicates that data has been loaded into

INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PC4.

Mode Definition Summary



Special Mode Combination Considerations

There are several combinations or modes when not all of the bits in Port C are used for contcan be used as follows:



If Programmed as Inputs-

All input lines can be accessed during a normal Port C read.

If programmed as Outputs-

Bits in C upper (PC7-PC4) must be individually accessed using the bit set/reset function.

Bits in C lower (PC3_Pco) can be accessed using the bit set/reset function or accessed as a

Source Current Capability on Port B and Port C

Any set of eight output buffers, selected randomly from Ports B and Ports C can source 1mAthe 8255A to directly drive Darlington type drivers and high-voltage displays that require suc

Reading Port C Status

In Mode O, Port C transfers data to or from the peripheral device. When the 8255 is programPort C generates or accepts ¡§hand shaking¡¨ signals with the peripheral device. Reading thprogrammer to test or verify the ¡§status¡¨ of each peripheral device and change the program

There is co special instruction to read the status information from Port C. A normal read opeperform this function. Figure 17. MODE 1 STATUS WORD FORMAT INPUT CONFIGURATION

OUTPUT CONFIGURATION

Figure 18. Mode 2 Status Word Format



DEFINE BY MODE 0 MODE 1 SELECTION

DOWNLOAD 8255 DATA SHEET



M Krishna kumar MAM/M3/LU9e/V1/2004 1

PIO 8255 (cont..)• The parallel input-output port chip 8255 is also called as

programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port. C upper.


• The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C.

• Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register ( CWR ).

PIO 8255 (cont..)


• The internal block diagram and the pin configuration of 8255 are shown in fig.

• The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of both data and control words.

• RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus.

PIO 8255 (cont..)


• This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer.

• The signal description of 8255 are briefly presented as follows :

• PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register.

• PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines.

PIO 8255 (cont..)


• This port also can be used for generation of handshake lines in mode 1 or mode 2.

• PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.

• PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A.

• RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255.

• WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.

PIO 8255 (cont..)


• CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected.

• A1-A0 : These are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i.e. three ports and a control word register as given in table below.

• In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

PIO 8255 (cont..)


Input (Read) cycleRD WR CS A1 A0Port A to Data busPort B to Data busPort C to Data busCWR to Data bus

010

1 000000 11

1111

0000

Output (Write) cycleRD WR CS A1 A0Data bus to Port AData bus to Port B Data bus to Port CData bus to CWR

010

000000 11

100

00

1111

FunctionRD WR CS A1 A0Data bus tristatedData bus tristated

XX

X1X1 X0

X1

Control Word Register


• D0-D7 : These are the data bus lines those carry data or control word to/from the microprocessor.

• RESET : A logic high on this line clears the control word register of 8255. All ports are set as input ports by default after reset.

PIO 8255.


Block Diagram of 8255 (Architecture) ( cont..)

• It has a 40 pins of 4 groups.1. Data bus buffer2. Read Write control logic3. Group A and Group B controls4. Port A, B and C• Data bus buffer: This is a tristate bidirectional buffer

used to interface the 8255 to system databus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU.

• Control word and status information are also transferred through this unit.


• Read/Write control logic: This unit accepts control signals ( RD, WR ) and also inputs from address bus and issues commands to individual group of control blocks ( Group A, Group B).

• It has the following pins.a) CS – Chipselect : A low on this PIN enables the

communication between CPU and 8255.b) RD (Read) – A low on this pin enables the CPU to read

the data in the ports or the status word through data bus buffer.



c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to the control register through the data bus buffer.

d) RESET: A high on this pin clears the control register and all ports are set to the input mode

e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins control the selection of one of the 3 ports.

• Group A and Group B controls : These block receive control from the CPU and issues commands to their respective ports.



• Group A - PA and PCU ( PC7 –PC4)• Group B - PCL ( PC3 – PC0)• Control word register can only be written into no read

operation of the CW register is allowed.• a) Port A: This has an 8 bit latched/buffered O/P and 8

bit input latch. It can be programmed in 3 modes – mode 0, mode 1, mode 2.b) Port B: This has an 8 bit latched / buffered O/P and 8

bit input latch. It can be programmed in mode 0, mode1.



c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0.

Block Diagram of 8255 (Architecture).


Modes of Operation of 8255 (cont..)

• These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR).

• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.

• Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2.


• BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1of the CWR as given in table.

• I/O Modes :a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode. This mode provides simple input and output capabilities using each of the three ports. Data can be simply read from and written to the input and output ports respectively, after appropriate initialisation.



D3 D2 D1 Selected bits of port C

0

1

D00 00 00 01

1

0 1 111

0 00 1

1 1 01 1

D1D2D3D4D5D6D7

BSR Mode : CWR Format


8255

8255

PA

PCU

PCL

PB

PA

PCU

PCL

PB

PA6 – PA7

PC4 – PC7

PC0-PC3

PB0 – PB7

All Output Port A and Port C acting as O/P. Port B acting as I/P

PA

PC

PB0 – PB7

Mode 0


• The salient features of this mode are as listed below:1. Two 8-bit ports ( port A and port B )and two 4-bit ports

(port C upper and lower ) are available. The two 4-bit ports can be combinedly used as a third 8-bit port.

2. Any port can be used as an input or output port.3. Output ports are latched. Input ports are not latched.4. A maximum of four ports are available so that overall 16

I/O configuration are possible.• All these modes can be selected by programming a

register internal to 8255 known as CWR.



• The control word register has two formats. The first format is valid for I/O modes of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit set/reset (BSR) mode of operation. These formats are shown in following fig.

D6D7 D0D1D2D3D4D5

1 X X X

0-for BSR mode Bit select flags0- Reset

1- Set

I/O Mode Control Word Register Format and BSR Mode Control Word Register Format

D3, D2, D1 are from 000 to 111 for bits PC0 TO PC7



2019181716151413121110987654321

2122232425262728293031323334353637383940

PB3

PB4

PB5

PB6

PB7

VccD7

D6

D5

D4

D3

D2

D1

D0

ResetWRPA7

PA6

PA5

PA4

PB2

PB1

PB0

PC3

PC2

PC1

PC0

PC4

PC5

PC6

PC7

A0

A1

GNDCSRD

PA0

PA1

PA2

PA3

8255A

8255A Pin Configuration


8255A

D0-D7

CSRESET

A0

A1

RD

WR GND

Vcc

PB0-PB7

PC0-PC3

PC4-PC7

PA0-PA7

Signals of 8255


Block Diagram of 8255

D0-D7 Data bus Buffer

1

READ/ WRITE Control Logic

RDWR

A0A1

RESET

CS

Group B control

Group A control

Group A Port A(8)

Group A Port C upper(4)

Group B Port C Lower(4)

Group B Port B(8)

2

3 4

8 bit int data bus

PB7-PB0

PC0-PC3

PC7-PC4

PA0-PA7


Control Word Format of 8255

Group - B

PCL

PB

Mode Select

1 Input0 Output1 Input0 Output

0 mode- 01 mode- 1

D0D1D2D3D4D6 D5D7

Mode for Port A

PA PC U Mode for PB

PB PC L

Mode Select of PA

00 – mode 001 – mode 110 – mode 2

PA1 Input0 Output

Group - A

PC u 1 Input0 Output

Mode Set flag 1- active 0- BSR mode


b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input and output action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for port A. This group including port A and PC3-PC5 from group A. Thus port C is utilized for generating handshake signals. The salient features of mode 1 are listed as follows:



1. Two groups – group A and group B are available for strobed data transfer.

2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.

3. The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched.

4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may be used as independent data lines.



• The control signals for both the groups in input and output modes are explained as follows:

Input control signal definitions (mode 1 ):• STB( Strobe input ) – If this lines falls to logic low level,

the data available at 8-bit input port is loaded into input latches.

• IBF ( Input buffer full ) – If this signal rises to logic 1, it indicates that data has been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising edge of RD input.



• INTR ( Interrupt request ) – This active high output signal can be used to interrupt the CPU whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig.

• INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of the processor by putting the data on the bus and sending the strobe signal.



Output control signal definitions (mode 1) :• OBF (Output buffer full ) – This status signal, whenever

falls to low, indicates that CPU has written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR signal and reset by a low going edge at the ACK input.

• ACK ( Acknowledge input ) – ACK signal acts as an acknowledgement to be given by an output device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port is received by the output device.



• INTR ( Interrupt request ) – Thus an output signal that can be used to interrupt the CPU when an output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2respectively.



D0D1D2D3D4D5D6D7

1 1 1/000 X X X

Mode 1 Control Word Group A I/P

Mode 1 Control Word Group B I/P

PB0 – PB7

INTEB PC2PC1

PC0 INTRA

IBFB

STBB

I/O

INTRA

IBFA

STBAINTEA

PA0 – PA7

RD

PC3

PC5

PC4

PC6 – PC7

1 - Input0 - Output

For PC6 – PC7

D0D1D2D3D4D5D6D7

1 1 1X X X X X

RD

Input control signal definitions in Mode 1


DATA from Peripheral

RD

INTR

STB

IBF

Mode 1 Strobed Input Data Transfer


Data OP to Port

ACK

INTR

OBF

WR

Mode 1 Strobed Data Output


D0D1D2D3D4D5D6D7

1 1 1/000 X X X

Mode 1 Control Word Group A Mode 1 Control Word Group B

PB0 –PB7

INTEB PC1PC2

PC0 INTRB

ACKB

OBFB

I/O

INTRA

ACKA

OBFA

INTEA

PA0 – PA7

WR

PC3

PC6

PC7

PC4 – PC5

1 - Input0 - Output

For PC4 – PC5

D0D1D2D3D4D5D6D7

1 1 0X X X X X

Output control signal definitions Mode 1


• Mode 2 ( Strobed bidirectional I/O ): This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of operation provides 8255 with an additional features for communicating with a peripheral device on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow and synchronization between the data transmitter and receiver. The interrupt generation and other functions are similar to mode 1.

• In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The RD and WR signals decide whether the 8255 is going to operate as an input port or output port.



• The Salient features of Mode 2 of 8255 are listed as follows:

1. The single 8-bit port in group A is available.2. The 8-bit port is bidirectional and additionally a 5-bit

control port is available. 3. Three I/O lines are available at port C.( PC2 – PC0 )4. Inputs and outputs are both latched.5. The 5-bit control port C (PC3-PC7) is used for

generating / accepting handshake signals for the 8-bit data transfer on port A.



• Control signal definitions in mode 2:• INTR – (Interrupt request) As in mode 1, this control

signal is active high and is used to interrupt the microprocessor to ask for transfer of the next data byte to/from it. This signal is used for input ( read ) as well as output ( write ) operations.

• Control Signals for Output operations:• OBF ( Output buffer full ) – This signal, when falls to low

level, indicates that the CPU has written data to port A.



• ACK ( Acknowledge ) This control input, when falls to logic low level, acknowledges that the previous data byte is received by the destination and next byte may be sent by the processor. This signal enables the internal tristate buffers to send the next data byte on port A.

• INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset mode with PC6.

• Control signals for input operations :• STB (Strobe input ) A low on this line is used to strobe in

the data into the input latches of 8255.



• IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises to logic ‘1’. This can be used as an acknowledge that the data has been received by the receiver.

• The waveforms in fig show the operation in Mode 2 for output as well as input port.

• Note: WR must occur before ACK and STB must be activated before RD.



Data from 8085 Data towards 8255

RD

Data bus

IBF

STB

ACK

INTR

OBF

WR

Mode 2 Bidirectional Data Transfer


• The following fig shows a schematic diagram containing an 8-bit bidirectional port, 5-bit control port and the relation of INTR with the control pins. Port B can either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2.

• Mode 2 is not available for port B. The following fig shows the control word.

• The INTR goes high only if either IBF, INTE2, STB and RD go high or OBF, INTE1, ACK and WR go high. The port C can be read to know the status of the peripheral device, in terms of the control signals, using the normal I/O instructions.



D0D1D2D3D4D5D6D7

1 X XX 1 1/0 1/0 1/0

1 - Input0 - Output

PC2 – PC0

1/0 mode

Port A mode 2

Port B mode 0-mode 0 1- mode 1

Port B 1- I/P 0-O/P

Mode 2 control word


WR

RD

PC3

PC7PC6

PC4

PC5

INTE 1

I/O

IBF

STB

ACK

OBF

INTR

PA0-PA7

INTE 2

3

Mode 2 pins

PROGRAMMABLE INTERRUPT CONTROLLER (8259A) • The architectural block diagram of 8259A is shown in fig1. The functional explication of each block is given in the following text in brief. • Interrupt Request Register (RR): The interrupts at IRQ input lines are handled by Interrupt Request internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis. • In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR keeps a track of the requests being served.

• Priority Resolver : This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode. • Interrupt Mask Register (IMR) : This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver. • Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus. • Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words, status and vector information pass through data buffer during read or write operations. • Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus. • Cascade Buffer/Comparator: This block stores and compares the ID’s all the 8259A used in system. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected, will send its preprogrammed vector address on the data bus during the next INTA pulse. • CS: This is an active-low chip select signal for enabling RD and WR operations of

8259A. INTA function is independent of CS. • WR : This pin is an active-low write enable input to 8259A. This enables it to accept command words from CPU. • RD : This is an active-low read enable input to 8259A. A low on this line enables 8259A to release status onto the data bus of CPU. • D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or from status word registers. This also carries interrupt vector information. • CAS0 – CAS2 Cascade Lines : A signal 8259A provides eight vectored interrupts. If more interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master 8259A along with eight slaves 8259A can provide upto 64 vectored interrupt lines. These three lines act as select lines for addressing the slave 8259A. • PS/EN : This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is used as input to designate whether the chip is used as a master (SP =1) or slave (EN = 0). • INT : This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU and is connected to the interrupt input of CPU. • IR0 – IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU. In edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high state and holding it high until it is acknowledged, and just by latching it to high level, if used in level triggered mode. • INTA ( Interrupt acknowledge ): This pin is an input used to strobe-in 8259A interrupt vector data on to the data bus. In conjunction with CS, WR and RD pins, this selects the different operations like, writing command words, reading status word, etc. • The device 8259A can be interfaced with any CPU using either polling or interrupt. In polling, the CPU keeps on checking each peripheral device in sequence to ascertain if it requires any service from the CPU. If any such service request is noticed, the CPU serves the request and then goes on to the next device in sequence. • After all the peripheral device are scanned as above the CPU again starts from first device. • This type of system operation results in the reduction of processing speed because most of the CPU time is consumed in polling the peripheral devices. • In the interrupt driven method, the CPU performs the main processing task till it is interrupted by a service requesting peripheral device. • The net processing speed of these type of systems is high because the CPU serves the peripheral only if it receives the interrupt request. • If more than one interrupt requests are received at a time, all the requesting peripherals are served one by one on priority basis. • This method of interfacing may require additional hardware if number of peripherals to be interfaced is more than the interrupt pins available with the CPU. Interrupt Sequence in an 8086 System • The Interrupt sequence in an 8086-8259A system is described as follows: 1. One or more IR lines are raised high that set corresponding IRR bits. 2. 8259A resolves priority and sends an INT signal to CPU. 3. The CPU acknowledge with INTA pulse. 4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data during this period. 5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to a data bus from where it is read by the CPU. 6. This completes the interrupt cycle. The ISR bit is reset at the end of the second

INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine. Command Words of 8259A • The command words of 8259A are classified in two groups 1. Initialization command words (ICW) and 2. Operation command words (OCW). • Initialization Command Words (ICW): Before it starts functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as initialized command words. • If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It contains the control bits for edge/level triggered mode, single/cascade mode, call address interval and whether ICW4 is required or not. • If A0=1, the control word is recognized as ICW2. The ICW2 stores details regarding interrupt vector addresses. The initialisation sequence of 8259A is described in form of a flow chart in fig 3 below. • The bit functions of the ICW1 and ICW2 are self explanatory as shown in figure below.

• Once ICW1 is loaded, the following initialization procedure is carried out

internally. a. The edge sense circuit is reset, i.e. by default 8259A interrupts are edge

sensitive. b. IMR is cleared. c. IR7 input is assigned the lowest priority. d. Slave mode address is set to 7. e. Special mask mode is cleared and status read is set to IRR. f. If IC4 = 0, all the functions of ICW4 are set to zero. Master/Slave bit in ICW4

is used in the buffered mode only. g. In an 8085 based system A15-A8 of the interrupt vector address are the

respective bits of ICW2. h. In 8086 based system A15-A11 of the interrupt vector address are inserted in place of T7 – T3 respectively and the remaining three bits A8, A9, A10 are selected depending upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7. i. ICW1 and ICW2 are compulsory command words in initialization sequence of 8259A as is evident from fig, while ICW3 and ICW4 are optional. The ICW3 is read only when there are more than one 8259A in the system, cascading is used (SNGL=0 ). j. The SNGL bit in ICW1 indicates whether the 8259A in the cascade mode or

not. The ICW3 loads an 8-bit slave register. It detailed functions are as follows. k. In master mode [ SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-bit slave register will be set bit-wise to 1 for each slave in the system as in fig 5. l. The requesting slave will then release the second byte of a CALL sequence. In slave mode [ SP=0 or if BUF =1 and M/S = 0 in ICW4] bits D2 to D0 identify the slave, i.e. 000 to 111 for slave 1 to slave 8. The slave compares the cascade inputs with these bits and if they are equal, the second byte of the CALL sequence

is released by it on the data bus.

• Operation Command Words: Once 8259A is initialized using the previously discussed command words for initialisation, it is ready for its normal function, i.e. for accepting the interrupts but 8259A has its own way of handling the received interrupts called as modes of operation. These modes of operations can be selected by programming, i.e. writing three internal registers called as operation command words. • In the three operation command words OCW1, OCW2 and OCW3 every bit corresponds to some operational feature of the mode selected, except for a few bits those are either 1 or 0. The three operation command words are shown in Fig. with the bit selection details. • OCW1 is used to mask the masked and if it is 0 the request is enabled. In OCW2 the three bits, R, SL and EOI control the end of interrupt, the rotate mode and their combinations as shown in fig below. • The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected for operation, if SL bit is active i.e. 1. • The details of OCW2 are shown in fig. • In operation command word 3 (OCW3), if the ESMM bit, i.e. enable special mask mode bit is set to 1, the SMM bit is neglected. If the SMM bit, i.e. special mask mode. When ESMM bit is 0 the SMM bit is neglected. If the SMM bit. i.e. special mask mode bit is 1, the 8259A will enter special mask mode provided ESMM=1. • If ESMM=1 and SMM=0, the 8259A will return to the normal mask mode. The details of bits of OCW3 are given in fig along with their bit definitions.

M. Krishna Kumar MM/M3/LU9b/V1/2004 1

8259A

• If we are working with an 8086, we have a problem here because the 8086 has only two interrupt inputs, NMI and INTR.

• If we save NMI for a power failure interrupt, this leaves only one interrupt for all the other applications. For applications where we have interrupts from multiple source, we use an external device called a priority interrupt controller ( PIC ) to the interrupt signals into a single interrupt input on the processor.


Architecture and Signal Descriptions of 8259A (cont..)

• The architectural block diagram of 8259A is shown in fig1. The functional explication of each block is given in the following text in brief.

• Interrupt Request Register (RR): The interrupts at IRQ input lines are handled by Interrupt Request internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis.

• In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR keeps a track of the requests being served.


Fig:1 8259A Block Diagram

Interrupt Mask Register IMR

Control Logic

IN Service Register ISR

Priority Resolver

Interrupt Request Register IRR

Data Bus Buffer

Read/Write Logic

Cascade Buffer/ Comparator

D0-D7

RDWR

A0

CS

CAS0

CAS1CAS2

SP / EN

INTA INT

Internal Bus

IR0

IR1

IR7

Bus


• Priority Resolver : This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode.

• Interrupt Mask Register (IMR) : This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver.



• Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.

• Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words, status and vector information pass through data buffer during read or write operations.



• Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus.

• Cascade Buffer/Comparator: This block stores and compares the ID’s all the 8259A used in system. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected, will send its preprogrammed vector address on the data bus during the next INTA pulse.



1234567891011121314

2827262524232221

181920

15

1617

GND CAS2

SP / ENINTIR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

INTAA0

Vcc

CAS1

CAS0

D0

D1

D2

D3

D4

D5

D6

D7

RDWRCS

Fig : 8259 Pin Diagram

8259A


• CS: This is an active-low chip select signal for enabling RD and WR operations of 8259A. INTA function is independent of CS.

• WR : This pin is an active-low write enable input to 8259A. This enables it to accept command words from CPU.

• RD : This is an active-low read enable input to 8259A. A low on this line enables 8259A to release status onto the data bus of CPU.

• D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or from status word registers. This also carries interrupt vector information.



• CAS0 – CAS2 Cascade Lines : A signal 8259A provides eight vectored interrupts. If more interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master 8259A along with eight slaves 8259A can provide upto 64 vectored interrupt lines. These three lines act as select lines for addressing the slave 8259A.

• PS/EN : This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is used as input to designate whether the chip is used as a master (SP =1) or slave (EN = 0).



• INT : This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU and is connected to the interrupt input of CPU.

• IR0 – IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU. In edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high state and holding it high until it is acknowledged, and just by latching it to high level, if used in level triggered mode.



• INTA ( Interrupt acknowledge ): This pin is an input used to strobe-in 8259A interrupt vector data on to the data bus. In conjunction with CS, WR and RD pins, this selects the different operations like, writing command words, reading status word, etc.

• The device 8259A can be interfaced with any CPU using either polling or interrupt. In polling, the CPU keeps on checking each peripheral device in sequence to ascertain if it requires any service from the CPU. If any such service request is noticed, the CPU serves the request and then goes on to the next device in sequence.



• After all the peripheral device are scanned as above the CPU again starts from first device.

• This type of system operation results in the reduction of processing speed because most of the CPU time is consumed in polling the peripheral devices.

• In the interrupt driven method, the CPU performs the main processing task till it is interrupted by a service requesting peripheral device.

• The net processing speed of these type of systems is high because the CPU serves the peripheral only if it receives the interrupt request.



• If more than one interrupt requests are received at a time, all the requesting peripherals are served one by one on priority basis.

• This method of interfacing may require additional hardware if number of peripherals to be interfaced is more than the interrupt pins available with the CPU.

Architecture and Signal Descriptions of 8259A.


Interrupt Sequence in an 8086 system (cont..)

• The Interrupt sequence in an 8086-8259A system is described as follows:

1. One or more IR lines are raised high that set corresponding IRR bits.

2. 8259A resolves priority and sends an INT signal to CPU.3. The CPU acknowledge with INTA pulse.4. Upon receiving an INTA signal from the CPU, the

highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data during this period.


5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to a data bus from where it is read by the CPU.

6. This completes the interrupt cycle. The ISR bit is reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine.

Interrupt Sequence in an 8086 system.


Command Words of 8259A (cont..)

• The command words of 8259A are classified in two groups

1. Initialization command words (ICW) and2. Operation command words (OCW).• Initialization Command Words (ICW): Before it starts

functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as initialized command words.


• If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It contains the control bits for edge/level triggered mode, single/cascade mode, call address interval and whether ICW4 is required or not.

• If A0=1, the control word is recognized as ICW2. The ICW2 stores details regarding interrupt vector addresses. The initialisation sequence of 8259A is described in form of a flow chart in fig 3 below.

• The bit functions of the ICW1 and ICW2 are self explanatory as shown in fig below.



Fig 3: Initialisation Sequence of 8259A

ICW1

ICW2

A : IN CASCADE MODE ?A

ICW3

B B : IS ICW4 NEEDED ?

ICW4

Ready to Accept Interrupt Request

YES (IC4 = 1)

YES (SINGLE =0)

NO (SINGLE =1)

NO (IC4 =0)


D0D1D2D3D4D5D6D7A0

D0D1D2D3D4D5D6D7A0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

1 = ICW4 Needed 0 = No ICW4 Needed

1 – Single 0 - Cascaded

Call Address Interval 1 – Interval of 4 bytes 0 – Interval of 8 bytes.

1 – Level Triggered 0 – Edge Triggered

A7-A5 of Interrupt vector address MCs 80/85 mode only

ICW1

1 T7 T6 T5 T4 T3 A10 A9 A8

Fig 4 : Instruction Command Words ICW1 and ICW2

• T7 – T3 are A3 – A0 of interrupt address• A10 – A9, A8 – Selected according to interrupt request level.

They are not the address lines of Microprocessor• A0 =1 selects ICW2

ICW2


• Once ICW1 is loaded, the following initialization procedure is carried out internally.

a. The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive.

b. IMR is cleared.c. IR7 input is assigned the lowest priority.d. Slave mode address is set to 7.e. Special mask mode is cleared and status read is set to

IRR.f. If IC4 = 0, all the functions of ICW4 are set to zero.

Master/Slave bit in ICW4 is used in the buffered mode only.



• In an 8085 based system A15-A8 of the interrupt vector address are the respective bits of ICW2.

• In 8086 based system A15-A11 of the interrupt vector address are inserted in place of T7 – T3 respectively and the remaining three bits A8, A9, A10 are selected depending upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7.

• ICW1 and ICW2 are compulsory command words in initialization sequence of 8259A as is evident from fig, while ICW3 and ICW4 are optional. The ICW3 is read only when there are more than one 8259A in the system, cascading is used ( SNGL=0 ).



• The SNGL bit in ICW1 indicates whether the 8259A in the cascade mode or not. The ICW3 loads an 8-bit slave register. It detailed functions are as follows.

• In master mode [ SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-bit slave register will be set bit-wise to 1 for each slave in the system as in fig 5.

• The requesting slave will then release the second byte of a CALL sequence. In slave mode [ SP=0 or if BUF =1 and M/S = 0 in ICW4] bits D2 to D0 identify the slave, i.e. 000 to 111 for slave 1 to slave 8. The slave compares the cascade inputs with these bits and if they are equal, the second byte of the CALL sequence is released by it on the data bus.



D0D1D2D3D4D5D6D7A0

1 S7 S6 S5 S4 S3 S2 S1 S0

D0D1D2D3D4D5D6D7A0

1 0 0 0 0 0 ID2 ID1 ID0

Master mode ICW3

Sn = 1-IRn Input has a slave = 0 – IRn Input does not have a slave

Slave mode ICW3

D2D1D0 – 000 to 111 for IR0 to IR7 or slave 1 to slave 8

Fig : ICW3 in Master and Slave Mode, ICW4 Bit Functions

D0D1D2D3D4D5D6D7A0

1 0 0 0 SFNM BUF M/S AEOI µPM

ICW4


• ICW4: The use of this command word depends on the IC4bit of ICW1. If IC4=1, IC4 is used, otherwise it is neglected. The bit functions of ICW4 are described as follow:

• SFNM: If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as enable output and the master/slave is determined using the M/S bit of ICW4.

• M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave. If BUF = 0, M/S is to be neglected.

• AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.



• µPM : If the µPM bit is 0, the Mcs-85 system operation is selected and if µPM=1, 8086/88 operation is selected.

• Operation Command Words: Once 8259A is initialized using the previously discussed command words for initialisation, it is ready for its normal function, i.e. for accepting the interrupts but 8259A has its own way of handling the received interrupts called as modes of operation. These modes of operations can be selected by programming, i.e. writing three internal registers called as operation command words.



• In the three operation command words OCW1, OCW2 and OCW3 every bit corresponds to some operational feature of the mode selected, except for a few bits those are either 1 or 0. The three operation command words are shown in fig with the bit selection details.

• OCW1 is used to mask the masked and if it is 0 the request is enabled. In OCW2 the three bits, R, SL and EOI control the end of interrupt, the rotate mode and their combinations as shown in fig below.

• The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected for operation, if SL bit is active i.e. 1.



• The details of OCW2 are shown in fig.• In operation command word 3 (OCW3), if the ESMM bit,

i.e. enable special mask mode bit is set to 1, the SMM bit is neglected. If the SMM bit, i.e. special mask mode. When ESMM bit is 0 the SMM bit is neglected. If the SMM bit. i.e. special mask mode bit is 1, the 8259A will enter special mask mode provided ESMM=1.

• If ESMM=1 and SMM=0, the 8259A will return to the normal mask mode. The details of bits of OCW3 are given in fig along with their bit definitions.



D0D1D2D3D4D5D6D7

M7 M6 M5 M4 M3 M2 M1 M0

1 – Mask Set 0 – Mask Reset

A0

1

Fig (a) : OCW1

D0D1D2D3D4D5D6D7

0 ESMM SMM 0 1 P RR RIS

A0

0

Fig (b) : OCW3

0 00 11 01 1

0 00 11 01 1

No Action1 – Poll Command 0 – No Poll Command

Read IRR on next RD pulse

Read IRR on next RD pulse

No ActionReset Special MaskSet Special Mask

Fig : Operation Command Words


D0D1D2D3D4D5D6D7

R SL EOI 0 0 L2 L1 L0

A0

1

0 0 10 1 1

111

00 0

0001 1 11 1 0

00 1

0 1 2 3 4 5 6 7000 0

00 0 1 1 1 1

111

111 1 0

0000

0

NON-SPECIFIC EOI COMMANDSPECIFIC EOI COMMANDROTATE ON NON-SPECIFIC EOI MODE (SET)ROTATE IN AUTOMATIC EOI MODE (SET)ROTATE IN AUTOMATIC EOI (CLEAR)ROTATE ON SPECIFIC EOI COMMANDSET PRIORITY COMMAND*

NO OPERATION

Fig : Operation Command Word

Fig (c) :OCW2

END OF INTERRUPT

AUTOMATIC ROTATION

SPECIFIC ROTATION

* - In this Mode L0 – L2 are used


• The different modes of operation of 8259A can be programmed by setting or resting the appropriate bits of the ICW or OCW as discussed previously. The different modes of operation of 8259A are explained in the following.

• Fully Nested Mode : This is the default mode of operation of 8259A. IR0 has the highest priority and IR7 has the lowest one. When interrupt request are noticed, the highest priority request amongst them is determined and the vector is placed on the data bus. The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI command just before returning from the service routine or the AEOI bit is set.

Operating Modes of 8259 (cont..)


• If the ISR ( in service ) bit is set, all the same or lower priority interrupts are inhibited but higher levels will generate an interrupt, that will be acknowledge only if the microprocessor interrupt enable flag IF is set. The priorities can afterwards be changed by programming the rotating priority modes.

• End of Interrupt (EOI) : The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command, issued before returning from the interrupt service routine. There are two types of EOI commands specific and non-specific. When 8259A is operated in the modes that preserve fully nested structure, it can determine which ISR bit is to be reset on EOI.



• When non-specific EOI command is issued to 8259A it will be automatically reset the highest ISR bit out of those already set.

• When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to determine the last level acknowledged. In this case a specific EOI command is issued to reset a particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by non-specific EOI of 8259A, if it is in special mask mode.

• Automatic Rotation : This is used in the applications where all the interrupting devices are of equal priority.



• In this mode, an interrupt request IR level receives priority after it is served while the next device to be served gets the highest priority in sequence. Once all the device are served like this, the first device again receives highest priority.

• Automatic EOI Mode : Till AEOI=1 in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of the last INTA pulse automatically. This mode should be used only when a nested multilevel interrupt structure is not required with a single 8259A.



• Specific Rotation : In this mode a bottom priority level can be selected, using L2, L1 and L0 in OCW2 and R=1, SL=1, EOI=0.

• The selected bottom priority fixes other priorities. If IR5 is selected as a bottom priority, then IR5 will have least priority and IR4 will have a next higher priority. Thus IR6will have the highest priority.

• These priorities can be changed during an EOI command by programming the rotate on specific EOI command in OCW2.



• Specific Mask Mode: In specific mask mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupt from other levels, which are not masked.

• Edge and Level Triggered Mode : This mode decides whether the interrupt should be edge triggered or level triggered. If bit LTIM of ICW1 =0 they are edge triggered, otherwise the interrupts are level triggered.

• Reading 8259 Status : The status of the internal registers of 8259A can be read using this mode. The OCW3 is used to read IRR and ISR while OCW1 is used to read IMR. Reading is possible only in no polled mode.



• Poll Command : In polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by not connecting INT output or by masking INT input of the microprocessor. The poll mode is entered by setting P=1 in OCW3.

• The 8259A is polled by using software execution by microprocessor instead of the requests on INT input. The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a request. The priority level is read and a data word is placed on to data bus, after RD is activated. A poll command may give more than 64 priority levels.



D0D1D2D3D4D5D6D7

1 x x x x w2 w1 w0

If = 1, there is an interruptBinary code of highest priority level

Fig : Data Word of 8259


• Special Fully Nested Mode : This mode is used in more complicated system, where cascading is used and the priority has to be programmed in the master using ICW4. this is somewhat similar to the normal nested mode.

• In this mode, when an interrupt request from a certain slave is in service, this slave can further send request to the master, if the requesting device connected to the slave has higher priority than the one being currently served. In this mode, the master interrupt the CPU only when the interrupting device has a higher or the same priority than the one current being served. In normal mode, other requests than the one being served are masked out.



• When entering the interrupt service routine the software has to check whether this is the only request from the slave. This is done by sending a non-specific EOI can be sent to the master, otherwise no EOI should be sent. This mode is important, since in the absence of this mode, the slave would interrupt the master only once and hence the priorities of the slave inputs would have been disturbed.

• Buffered Mode: When the 83259A is used in the systems where bus driving buffers are used on data buses. The problem of enabling the buffers exists. The 8259A sends buffer enable signal on SP/ EN pin, whenever data is placed on the bus.



• Cascade Mode : The 8259A can be connected in a system containing one master and eight slaves (maximum) to handle upto 64 priority levels. The master controls the slaves using CAS0-CAS2 which act as chip select inputs (encoded) for slaves.

• In this mode, the slave INT outputs are connected with master IR inputs. When a slave request line is activated and acknowledged, the master will enable the slave to release the vector address during second pulse of INTA sequence.



• The cascade lines are normally low and contain slave address codes from the trailing edge of the first INTA pulse to the trailing edge of the second INTA pulse. Each 8259A in the system must be separately initialized and programmed to work in different modes. The EOI command must be issued twice, one for master and the other for the slave.

• A separate address decoder is used to activate the chip select line of each 8259A.

• Following Fig shows the details of the circuit connections of 8259A in cascade scheme.



Vcc

Fig : 8259A in Cascade Mode

Master Slave 0 Slave 7M0M1M2M3M4M5M6M7

SP/ENCS A0 D0-D7 INTA

INT

CS A0 D0-D7 INTASP/EN

INTIR0IR7

INT

IR0IR7

CS

A0

D0-D7

INTACAS0-CAS2

DATA BUS

CONTROL BUS

ADDRESS BUS

A1A1A1

KEYBOARD/DISPLAY INTERFACE (8279)

• Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives the display of a system and interfaces a keyboard with the CPU, leaving it free for its routine task. Architecture and Signal Descriptions of 8279 • The keyboard display controller chip 8279 provides: a) a set of four scan lines and eight return lines for interfacing keyboards b) A set of eight output lines for interfacing display. • Fig shows the functional block diagram of 8279 followed by its brief description. • I/O Control and Data Buffers : The I/O control section controls the flow of data to/ from the 8279. The data buffers interface the external bus of the system with internal bus of 8279. • The I/O section is enabled only if CS is low. The pins A0, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279. • Control and Timing Register and Timing Control : These registers store the keyboard and display modes and other operating conditions programmed by CPU. The registers are written with A0=1 and WR=0. The Timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. • Scan Counter : The scan counter has two modes to scan the key matrix and refresh the display. In the encoded mode, the counter provides binary count that is to be externally decoded to provide the scan lines for keyboard and display (Four externally decoded scan lines may drive upto 16 displays). In the decode scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3( Four internally decoded scan lines may drive upto 4 displays). The keyboard and display both are in the same mode at a time. • Return Buffers and Keyboard Debounce and Control: This section for a key closure row wise. If a key closer is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if thekey continues to be detected. The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. • FIFO/Sensor RAM and Status Logic: In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM. Each key code of the pressed key is entered in the order of the entry and in the mean time read by the CPU, till the RAM become empty. • The status logic generates an interrupt after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU. • Display Address Registers and Display RAM : The display address register holds the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU.

• The signal discription of each of the pins of 8279 as follows : • DB0-DB7 : These are bidirectional data bus lines. The data and command words to and from the CPU are transferred on these lines. • CLK : This is a clock input used to generate internal timing required by 8279. • RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31.

• CS : Chip Select – A low on this line enables 8279 for normal read or write operations. Other wise, this pin should remain high. • A0 : A high on this line indicates the transfer of a command or status information .A low on this line indicates the transfer of data. This is used to select one of the internal registers of 8279. • RD, WR ( Input/Output ) READ/WRITE – These input pins enable the data buffers to receive or send data over the data bus. • IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU. • Vss, Vcc : These are the ground and power supply lines for the circuit. • SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and display digits. These lines can be programmed as encoded or decoded, using the mode control register. • RL0 - RL7 - Return Lines : These are the input lines which are connected to one terminal of keys, while the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled low when a key is pressed. • SHIFT : The status of the shift input lines is stored along with each key code in FIFO, in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a key closure. • BD – Blank Display : This output pin is used to blank the display during digit switching or by a blanking closure. • OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4 or 16*8 internal display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port. • CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as a control input and stored in FIFO on a key closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up. Modes of Operation of 8279 • The modes of operation of 8279 are as follows : 1. Input (Keyboard) modes. 2. Output (Display) modes. • Input ( Keyboard ) Modes : 8279 provides three input modes. These modes are as follows: 1. Scanned Keyboard Mode : This mode allows a key matrix to be interfaced using either encoded or decoded scans. In encoded scan, an 8*8 keyboard or in decoded scan, a 4*8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM. 2. Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with 8279 using either encoded or decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor codes are stored in the CPU addressable sensor RAM. 3. Strobed input: In this mode, if the control lines goes low, the data on return lines, is stored in the FIFO byte by byte.

• Output (Display) Modes : 8279 provides two output modes for selecting the display options. These are discussed briefly. 1. Display Scan : In this mode 8279 provides 8 or 16 character multiplexed displays those can be organized as dual 4- bit or single 8-bit display units. 2. Display Entry : ( right entry or left entry mode ) 8279 allows options for data entry on the displays. The display data is entered for display either from the right side or from the left side. Keyboard Modes i. Scanned Keyboard mode with 2 Key Lockout : In this mode of operation, when a key is pressed, a debounce logic comes into operation. During the next two scans, other keys are checked for closure and if no other key is pressed the first pressed key is identified. • The key code of the identified key is entered into the FIFO with SHIFT and CNTL status, provided the FIFO is not full, i.e. it has at least one byte free. If the FIFO does not have any free byte, naturally the key data will not be entered and the error flag is set.The lines is pulled down with a key closer. • If FIFO has at least one byte free, the above code is entered into it and the 8279 generates an interrupt on IRQ line to the CPU to inform about the previous key closures. If another key is found closed during the first key, the keycode is entered in FIFO. • If the first pressed key is released before the others, the first will be ignored. A key code is entered to FIFO only once for each valid depression, independent of other keys pressed along with it, or released before it. • If two keys are pressed within a debounce cycle (simultaneously ), no key is recognized till one of them remains closed and the other is released. The last key, that remains depressed is considered as single valid key depression. ii. Scanned Keyboard with N-Key Rollover : In this mode, each key depression is treated independently. When a key is pressed, the debounce circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM. Any number of keys can be pressed simultaneously and recognized in the order, the keyboard scan recorded them. All the codes of such keys are entered into FIFO. In this mode, the first pressed key need not be released before the second is pressed. All the keys are sensed in the order of their depression, rather in the order the keyboard scan senses them, and independent of the order of their release. iii. Scanned Keyboard Special Error Mode : This mode is valid only under the NKey rollover mode. This mode is programmed using end interrupt / error mode set command. If during a single debounce period ( two keyboard scans ) two keys are found pressed, this is considered a simultaneous depression and an error flag is set. • This flag, if set, prevents further writing in FIFO but allows the generation of further interrupts to the CPU for FIFO read. The error flag can be read by reading the FIFO status word. The error Flag is set by sending normal clear command with CF = 1. iv. Sensor Matrix Mode : In the sensor matrix mode, the debounce logic is inhibited. The 8-byte FIFO RAM now acts as 8 * 8 bit memory matrix. The status of the sensor switch matrix is fed directly to sensor RAM matrix. Thus the sensor RAM bits contains the row-wise and column wise status of the sensors in the sensor matrix. • The IRQ line goes high, if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU. The IRQ line is reset by the first data read operation, if AI = 0, otherwise, by issuing the end interrupt command. AI is a bit in read sensor RAM word.

Display Modes • There are various options of data display. For example, the command number of

characters can be 8 or 16, with each character organised as single 8-bit or dual 4-bit codes. Similarly there are two display formats. • The first one is known as left entry mode or type writer mode, since in a type writer the first character typed appears at the left-most position, while the subsequent characters appear successively to the right of the first one. The other display format is known as right entry mode, or calculator mode, since in a calculator the first character entered appears at the rightmost position and this character is shifted one position left when the next characters is entered. • Thus all the previously entered characters are shifted left by one position when a new characters is entered. i. Left Entry Mode : In the left entry mode, the data is entered from left side of the display unit. Address 0 of the display RAM contains the leftmost display characters and address 15 of the RAM contains the right most display characters. It is just like writing in our address is automatically updated with successive reads or writes. The first entry is displayed on the leftmost display and the sixteenth entry on the rightmost display. The seventeenth entry is again displayed at the leftmost display position. ii. Right Entry Mode : In this right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position. The leftmost characters is shifted out of that display at the seventeenth entry and is lost, i.e. it is pushed out of the display RAM.

M. Krishna Kumar MM/M3/LU9c/V1/2004 1

8279• While studying 8255, we have explained the use of 8255 in

interfacing keyboards and displays with 8086. The disadvantages of this method of interfacing keyboard and display with 8086 is that the processor has to refresh the display and check the status of the keyboard periodically using polling technique. Thus a considerable amount of CPU time is wasted, reducing the system operating speed.

• Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives the display of a system and interfaces a keyboard with the CPU, leaving it free for its routine task.


• The keyboard display controller chip 8279 provides:a) a set of four scan lines and eight return lines for

interfacing keyboardsb) A set of eight output lines for interfacing display.• Fig shows the functional block diagram of 8279

followed by its brief description.• I/O Control and Data Buffers : The I/O control section

controls the flow of data to/from the 8279. The data buffers interface the external bus of the system with internal bus of 8279.

Architecture and Signal Descriptions of 8279 (cont..)


• The I/O section is enabled only if CS is low. The pins A0, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279.

• Control and Timing Register and Timing Control : These registers store the keyboard and display modes and other operating conditions programmed by CPU. The registers are written with A0=1 and WR=0. The Timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies.



• Scan Counter : The scan counter has two modes to scan the key matrix and refresh the display. In the encoded mode, the counter provides binary count that is to be externally decoded to provide the scan lines for keyboard and display (Four externally decoded scan lines may drive upto 16 displays). In the decode scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3( Four internally decoded scan lines may drive upto 4 displays). The keyboard and display both are in the same mode at a time.



• Return Buffers and Keyboard Debounce and Control: This section for a key closure row wise. If a key closer is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to be detected. The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status.

• FIFO/Sensor RAM and Status Logic: In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM. Each key code of the pressed key is entered in the order of the entry and in the mean time read by the CPU, till the RAM become empty.



• The status logic generates an interrupt after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU.

• Display Address Registers and Display RAM : The display address register holds the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU.



8279 Internal Architecture

Return

DB0-DB7

DATA BUFFERS

I/O CONTROL

INTERNAL 8 BIT DATA BUS

FIFO/SENSOR RAM STATUS

RD WR

DISPLAY ADDRESS REGISTERS

16*8 DISPLAY RAM

A0CS

CONTROL AND TIMING REGISTERS

8*8 FIFO/ SENSOR RAM

KEYBOARD DEBOUNCE AND CONTROL

DISPLAY REGISTERS

TIMING AND CONTROL UNIT

SCAN COUNTER

BDOUT A0-A3OUT B0-B3

SL0 – SL3RL0 – RL7 CNTL/

STB

SHIFT

CLK

RE

SET


8279

1234567891011121314151617181920

4039383736353433323130292827262524232221

VccRL1RL0CNTL/STBSHIFTSL3SL2SL1SL0OUT B0OUT B1OUT B2OUT B3OUT A0OUT A1OUT A2OUT A3BDCSA0

RL2RL3

CLKIRQRL4RL5RL6RL7

RESETRDWRDB0DB1DB2DB3DB4DB5DB6DB7Vss

8279 Pin Configuration


Vss

BD

4

KRY DATA

8RL0-7

SHIFT

CLK

RESET

A0

CS

WR

RD

DB0 – DB7

IRQ

8

CNTL/STB

SL0-3 4SCAN

OUT A0-A3

OUT B0 – B3

4

Vcc

DISPLAY DATA

CPU INTERFACE

8279


• The signal discription of each of the pins of 8279 as follows :

• DB0-DB7 : These are bidirectional data bus lines. The data and command words to and from the CPU are transferred on these lines.

• CLK : This is a clock input used to generate internal timing required by 8279.

• RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31.



• CS : Chip Select – A low on this line enables 8279 for normal read or write operations. Other wise, this pin should remain high.

• A0 : A high on this line indicates the transfer of a command or status information. A low on this line indicates the transfer of data. This is used to select one of the internal registers of 8279.

• RD, WR ( Input/Output ) READ/WRITE – These input pins enable the data buffers to receive or send data over the data bus.



• IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.

• Vss, Vcc : These are the ground and power supply lines for the circuit.

• SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and display digits. These lines can be programmed as encoded or decoded, using the mode control register.



• RL0 - RL7 - Return Lines : These are the input lines which are connected to one terminal of keys, while the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled low when a key is pressed.

• SHIFT : The status of the shift input lines is stored along with each key code in FIFO, in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a key closure.

• BD – Blank Display : This output pin is used to blank the display during digit switching or by a blanking closure.



• OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4 or 16*8 internal display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port.

• CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as a control input and stored in FIFO on a key closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up. The lines is pulled down with a key closer.

Architecture and Signal Descriptions of 8279



• The modes of operation of 8279 are as follows :1. Input (Keyboard) modes.2. Output (Display) modes.• Input ( Keyboard ) Modes : 8279 provides three input

modes. These modes are as follows:1. Scanned Keyboard Mode : This mode allows a key

matrix to be interfaced using either encoded or decoded scans. In encoded scan, an 8*8 keyboard or in decoded scan, a 4*8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM.


2. Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with 8279 using either encoded or decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor codes are stored in the CPU addressable sensor RAM.

3. Strobed input: In this mode, if the control lines goes low, the data on return lines, is stored in the FIFO byte by byte.



• Output (Display) Modes : 8279 provides two output modes for selecting the display options. These are discussed briefly.

1. Display Scan : In this mode 8279 provides 8 or 16 character multiplexed displays those can be organized as dual 4- bit or single 8-bit display units.

2. Display Entry : ( right entry or left entry mode ) 8279 allows options for data entry on the displays. The display data is entered for display either from the right side or from the left side.

Modes of Operation of 8279


Keyboard Modes (cont..)

i. Scanned Keyboard mode with 2 Key Lockout : In this mode of operation, when a key is pressed, a debounce logic comes into operation. During the next two scans, other keys are checked for closure and if no other key is pressed the first pressed key is identified.

• The key code of the identified key is entered into the FIFO with SHIFT and CNTL status, provided the FIFO is not full, i.e. it has at least one byte free. If the FIFO does not have any free byte, naturally the key data will not be entered and the error flag is set.


• If FIFO has at least one byte free, the above code is entered into it and the 8279 generates an interrupt on IRQ line to the CPU to inform about the previous key closures. If another key is found closed during the first key, the keycode is entered in FIFO.

• If the first pressed key is released before the others, the first will be ignored. A key code is entered to FIFO only once for each valid depression, independent of other keys pressed along with it, or released before it.



• If two keys are pressed within a debounce cycle (simultaneously ), no key is recognized till one of them remains closed and the other is released. The last key, that remains depressed is considered as single valid key depression.

ii. Scanned Keyboard with N-Key Rollover : In this mode, each key depression is treated independently. When a key is pressed, the debounce circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM.



• Any number of keys can be pressed simultaneously and recognized in the order, the keyboard scan recorded them. All the codes of such keys are entered into FIFO.

• In this mode, the first pressed key need not be released before the second is pressed. All the keys are sensed in the order of their depression, rather in the order the keyboard scan senses them, and independent of the order of their release.



iii. Scanned Keyboard Special Error Mode : This mode is valid only under the N-Key rollover mode. This mode is programmed using end interrupt / error mode set command. If during a single debounce period ( two keyboard scans ) two keys are found pressed , this is considered a simultaneous depression and an error flag is set.

• This flag, if set, prevents further writing in FIFO but allows the generation of further interrupts to the CPU for FIFO read. The error flag can be read by reading the FIFO status word. The error Flag is set by sending normal clear command with CF = 1.



iv. Sensor Matrix Mode : In the sensor matrix mode, the debounce logic is inhibited. The 8-byte FIFO RAM now acts as 8 * 8 bit memory matrix. The status of the sensor switch matrix is fed directly to sensor RAM matrix. Thus the sensor RAM bits contains the row-wise and column wise status of the sensors in the sensor matrix.

• The IRQ line goes high, if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU. The IRQ line is reset by the first data read operation, if AI = 0, otherwise, by issuing the end interrupt command. AI is a bit in read sensor RAM word.

Keyboard Modes.


• There are various options of data display. For example, the command number of characters can be 8 or 16, with each character organised as single 8-bit or dual 4-bit codes. Similarly there are two display formats.

• The first one is known as left entry mode or type writer mode, since in a type writer the first character typed appears at the left-most position, while the subsequent characters appear successively to the right of the first one. The other display format is known as right entry mode, or calculator mode, since in a calculator the first character entered appears at the rightmost position and this character is shifted one position left when the next characters is entered.

Display Modes (cont..)


• Thus all the previously entered characters are shifted left by one position when a new characters is entered.

i. Left Entry Mode : In the left entry mode, the data is entered from left side of the display unit. Address 0 of the display RAM contains the leftmost display characters and address 15 of the RAM contains the right most display characters. It is just like writing in our address is automatically updated with successive reads or writes. The first entry is displayed on the leftmost display and the sixteenth entry on the rightmost display. The seventeenth entry is again displayed at the leftmost display position.

Display Modes (cont..)


ii. Right Entry Mode : In this right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position. The leftmost characters is shifted out of that display at the seventeenth entry and is lost, i.e. it is pushed out of the display RAM.

Display Modes


Command Words of 8279 (cont..)

• All the command words or status words are written or read with A0 = 1 and CS = 0 to or from 8279. This section describes the various command available in 8279.

a) Keyboard Display Mode Set – The format of the command word to select different modes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 A0D00 0 D D D K K 1K


D D Display modes

K K K Keyboard modes

0 0

0 1

1 0

1 1

Eight 8-bit character Left entrySixteen 8-bit character left entry

Eight 8-bit character Right entry

Sixteen 8-bit character Right entry

0 0 0 Encoded Scan, 2 key lockout ( Default after reset )0 0 10 1 0

0 1 11 0 0

1 0 1

1 1 0

1 1 1

Decoded Scan, 2 key lockoutEncoded Scan, N- key Roll overDecoded Scan, N- key Roll overEncode Scan, N- key Roll overDecoded Scan, N- key Roll over

Strobed Input Encoded ScanStrobed Input Decoded Scan

Fig:


b) Programmable clock : The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler.

• PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31, decided by the bits of an internal prescaler, PPPPP.

D7 D6 D5 D4 D3 D2 D1 A0D00 0 1 P P P P 1P



c) Read FIFO / Sensor RAM : The format of this command is given below.

• This word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read, in the same sequence, in which the data was entered.

• In sensor matrix mode, the bits AAA select one of the 8 rows of RAM. If AI flag is set, each successive read will be from the subsequent RAM location.



D7 D6 D5 D4 D3 D2 D1 A0D00 1 0 AI X A A 1A

X – don’t care

AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM

Fig


d) Read Display RAM : This command enables a programmer to read the display RAM data. The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA, the 4-bit address points to the 16-byte display RAM that is to be read. If AI=1, the address will be automatically, incremented after each read or write to the Display RAM. The same address counter is used for reading and writing.

D7 D6 D5 D4 D3 D2 D1 A0D00 1 1 AI A A A 1A



e) Write Display RAM :

AI – Auto increment Flag.AAAA – 4 bit address for 16-bit display RAM to be written.

D7 D6 D5 D4 D3 D2 D1 A0D01 0 0 AI A A A 1A



f) Display Write Inhibit/Blanking : The IW ( inhibit write flag ) bits are used to mask the individual nibble as shown in the below command word. The output lines are divided into two nibbles ( OUTA0 – OUTA3 ) and ( OUTB0 – OUTB3 ), those can be masked by setting the corresponding IW bit to 1.

• Once a nibble is masked by setting the corresponding IW bit to 1, the entry to display RAM does not affect the nibble even though it may change the unmasked nibble. The blank display bit flags (BL) are used for blanking A and B nibbles.



• Here D0, D2 corresponds to OUTB0 – OUTB3 while D1 and D3 corresponds to OUTA0-OUTA3 for blanking and masking.

• If the user wants to clear the display, blank (BL) bits are available for each nibble as shown in format. Both BL bits will have to be cleared for blanking both the nibbles.

D7 D6 D5 D4 D3 D2 D1 A0D01 0 1 X IW IW BL 1BL



g) Clear Display RAM : The CD2, CD1, CD0 is a selectable blanking code to clear all the rows of the display RAM as given below. The characters A and B represents the output nibbles.

• CD2 must be 1 for enabling the clear display command. If CD2 = 0, the clear display command is invoked by setting CA=1 and maintaining CD1, CD0 bits exactly same as above. If CF=1, FIFO status is cleared and IRQ line is pulled down.

• Also the sensor RAM pointer is set to row 0. if CA=1, this combines the effect of CD and CF bits. Here, CA represents Clear All and CF as Clear FIFO RAM.



D7 D6 D5 D4 D3 D2 D1 A0D01 1 0 CD2 CD1 CD0 CF 1CA

CD2 CD1 CD0

1 0 X

1 1 0

1 1 1

All zeros ( x don’t care ) AB=00

A3-A0 =2 (0010) and B3-B0=00 (0000)

All ones (AB =FF), i.e. clear RAM

Fig


h) End Interrupt / Error mode Set : For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM. Otherwise, if a change in sensor value is detected, IRQ goes high that inhibits writing in the sensor RAM.

• For N-Key roll over mode, if the E bit is programmed to be ‘1’, the 8279 operates in special Error mode. Details of this mode are described in scanned keyboard special error mode. X- don’t care.

D7 D6 D5 D4 D3 D2 D1 A0D01 1 1 E X X X 1X



8

4

4

8086

8279

INTR

AD0-AD15A16-A19

RDWR

PCLK (from 8284)

Address decoder

8282 (3) Address latch

8259 Interrupt controller

A0L

A1L-A3L

A0L-A19L

INT2Shift

Control Key board matrix

8 columns8 rows

8

3-8 decoder

4-16 decoder

AddressDisplay character data

Blank display

BD

A0-3B0-3CLKA0

CSResetIOWIOR

INT

D0-7

RL0-7

S0-3

5VVDD

Vss 0VScan lines

Return lines

16

4

3

Data bus

Fig

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