rs flipflop
DESCRIPTION
nice bookTRANSCRIPT
SR - LatchBy - Mayank Dixit
0
0
0
0
0
0
Q`=1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
→ 1
→ 1
Now Since one input of SR latch’s both NAND gates is: 0both the gates will be giving 1 as the output, no matter what other inputs are.(so we can skip checking with Q=1 and say:)Since one is Q and other is Q`; but in here these are ‘1’ (both).And this is so not a valid condition;When one is complement of other; both can’t be the same.
This is why
S R Q+
0 0 X (unused)
0
1
0
Q`=1
0
1
0
1 1
0
0
1
0
1
1
0
→1
→1
1
1
0
1
0
1
→1
→1
1
1
0
1
0
1
→1
→1
1
1
1
1
→ 1
0→
• Now it’s clear that this is stable condition; you repeat it again and again but this will give the same output i.e. Q=1 and Q`=0.
• Clearly this is not unstable state since value of Q and Q` is different.
• So S R Q+
0 0 X (unused)
0 1 1
1
0
0
1Q` =1
1
0
0
→ 11
1
0
0
→ 1
→ 0
1 1
S R Q+
0 0 X (unused)
0 1 1
1 0 0
1
1
0
11
0
→ 1
→0
1
1
1
00
1
→ 0
→1
S R Q+
0 0 X (unused)
0 1 1
1 0 0
1 1 Q(if Q = 0; Q` = 0 & if Q = 1; Q` = 1)
Final Table: