rsc mapld 2005/130hodson robert f. hodson 1, kevin somervill 1, john williams 2, neil bergman 2, rob...
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RSCMAPLD 2005/130Hodson
Robert F. Hodson1, Kevin Somervill1, John Williams2, Neil Bergman2, Rob Jones3
1NASA LaRC, 2University of Queensland, 3ASRC Aerospace
An Architecture for Reconfigurable Computing in Space
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RSC Goals & Objectives
• To develop the next generation high performance space-qualified computing system leveraging…– Field Programmable Gate Arrays FPGAs
– Intellectual Property (IP)• Soft cores, processors
– COTS software architectures• Multi-processor
• Specialized
• Meet Strategic Challenges– Reconfigurability
– Modularity
• First step towards the next
generation avionics suite
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Why Reconfigurable Computing with Soft Cores & Custom Logic
Source: R. Lysecky and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning,” Design Automation and Test in Europe (DATE), March 2005
• Soft cores readily available for rad-tolerant FPGAs
• Custom co-processors can improve performance on average by 5.8X
• Power consumption can also be reduced on average by 57%
• Reconfiguration allows many designs without hardware redesign – reducing cost
• Making this approach competitive with current space computing systems
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Scalable Architecture
Multiple interconnected general purpose processing nodes with optimized custom logic attached for special purpose processing.Multiple interconnected general purpose processing nodes with optimized custom logic attached for special purpose processing.
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Physical Concept
Stacks of reconfigurable processing modules (RPMs) similar to a ruggedized version of a PC104+ stack. Modules, which make up a stack will be RPMs, Command Control Module (CCM), Network Module (NM), etc.
Physical design will support launch loads, radiation shielding, and conduction cooling.
STACKS
Modules
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Modular Technology
• Modules will be combined to build RSC systems
• Designs will be based on rugged small form factor modular stackable technology– Allows mixing and matching of
appropriate modules to meet mission requirements
• Planned modules– Reconfigurable Processing
Module (RPM)
– Command/Control Module (CCM)
– Network Module (NM)
– Power Module (PM)
Command Control Module(CCM)
Reconfigurable Processing Module(RPM)
Network Module(NM)
Reconfigurable Processing Module(RPM)
Reconfigurable Processing Module(RPM)
Power Module(PM)
BU
S
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Multiple Interconnected RSC Stacks
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Software Architecture
RSC plans to deliver a complete system with hardware, system software, development software, and a demonstration application.
RSC plans to deliver a complete system with hardware, system software, development software, and a demonstration application.
uCLinux
MPI
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Reconfigurable Processing Module
SDRAM(512 MB)SDRAM(512 MB)
ConfigMemoryConfig
Memory
Config
Mgr
NVR I/FNVR I/F
NVRAM(FLASH or CRAM
32MB min)
NVRAM(FLASH or CRAM
32MB min)
SDRAM I/FSDRAM I/F
SLin
SLou
t
Actel FPGA
Xilinx FPGA (V4FX60)
Bus
SERDES(2.5 Gbps)SERDES(2.5 Gbps)
Parallel IO
Serial IO
Switch
NICNIC
Data Cache
PCI I/FPCI I/F
PCI Bus 33MHz 32/64 Bits
uBCustom Logic Instr
Cache
RPM
Frame BufFrame Buf
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RPM Features
• Xilinx logic is triplicated and scrubbed– Custom cache design (MicroBlaze cache not used)
• Caches will be scrubbed
• SDRAM is SECDED protected and scrubbed.• Rad-Hard NVRAM is an issue • Compressed code image and configuration is stored in
NVRAM. It is copied to SDRAM and decompressed after reset.– If the system has multiple MicroBlaze processors they each
have separate memory space in the same physical memory.
• Custom logic can communicate via FSL or OPB• PCI interface supports Master/Target/DMA
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RSC Protocol Stack
Transport
Application/MPI
Network
datagrams
Data Linkand Physical
packet
message
Internet Protocol
UDP
Buses
SocketsMessageMessage
DataData
PHdrPHdr
PHdrPHdrIPIP
DataData
DataData
PHdrPHdr
PHdrPHdrIPIP
NICNIC
DataData
ReceivingCPU or NMReceivingCPU or NM
MessageMessage
DMA EngineDMA Engine
PCI Address and Size of Datagram
Network ReqNetwork Req
IP A
dd
res
s a
nd
Siz
e o
f D
ata
gra
m
Pull
NICNIC
INTRINTR
INTRINTR
ACKACK
SendingCPU
SendingCPU
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Communication Event Sequence
PCI I/FPCI I/F IP2PCIMappingIP2PCI
Mapping
SDRAM
CPU
Message Buffer
Message Buffer
Controller
Req queue
PCI I/FPCI I/F IP2PCIMappingIP2PCI
Mapping
Controller
Req queue
SDRAM
CPU
Message Buffer
Message Buffer
Source RPM
Destination RPM
1. Datagram is built in memory.
2. Message send request.
Source NIC
Destination NIC
3. IP address is translated to PCI address of destination.
4. PCI Address of message on source RPM sent to destination NIC.
5. Destination NIC pulls (DMAs) message into destination RPM’s memory.
6. Message received interrupt sent to CPU.
8. Destination NIC tells source NIC “message received.”
7. Message processed.
9. Interrupt to source CPU. Buffer can now be released.
PCI Bus
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Command & Control Module
PCI Master/TargetPCI Arbiter
Reset
Power Mgmt
1553 Command I/FSystemReset
PowerGood
Configuration and Code Selects
uController
PCI Backend I/F
Hub
Memory NVRAM
Test port
IO Controller
MemoryController
Discrete IO
PCI
The Command and Control Module (CCM) provides the primary command interface to the system. If also controls the system bus initialization and boot process.
The Command and Control Module (CCM) provides the primary command interface to the system. If also controls the system bus initialization and boot process.
CCM
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Network Module Design
Control
Routing Lookup
Control
Routing Lookup
DMA
SERDES
To Other Link InterfacesFrom LinkInterfaces From Link
Interfaces
LinkI/F
PCII/F
Actel AX2000
To/from other stacks
Additional Link I/Fs
SERDESSERDESSERDES
Network Module (NM) provides an interface to other RSC stacks. It buffers and routes IP packets based on routing information loaded during system initialization. Serialized links provide a high-bandwidth interconnect to other systems.
Network Module (NM) provides an interface to other RSC stacks. It buffers and routes IP packets based on routing information loaded during system initialization. Serialized links provide a high-bandwidth interconnect to other systems.
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RSC Robotic Demonstrator
• Demonstrate reconfigurable technology on a challenging real-time control and processing application
• Tele-operated robot with multiple sensors– Stereo camera
– Omni camera
– IR camera
– X-Ray florescence sensor
– Several others
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RSC Team
• Core Team Members– NASA Langley Research
Center (Lead)
– NASA Goddard Space Flight Center
– The University of Queensland
– ARSC Aerospace
– Jefferson Lab (DoE)
– Starbridge Systems
– Department of Defense
• Affiliate Members– Air Force Research
Laboratory
– SEAKR Engineering
– Imagination Engines