s- band gan lna with oip3>50dbm using parallel
TRANSCRIPT
2018
S- Band GaN LNA with OIP3>50dBm using Parallel
Independently Biased Gates
Kanika Saini1, Amin Ezzeddine2, Waleed Joudeh2, Ho Huang2, Sanjay Raman1
1MICS Group, Dept. of Electrical Eng., Virginia Tech, Arlington, VA2AMCOM Communications Inc., Gaithersburg, MD
2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
Introduction and Motivation
GaN devices have similar noise figures compared
to GaAs, Si, SiGe etc.
LNA linearity is a challenge for radar, satellite
systems, base stations etc.
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F. Schwierz and J. J. Liou, “Semiconductor devices for RF applications: evolution and current status,” Microelectronics
Reliability, vol. 41, no. 2, pp. 145–168, Feb. 2001.
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Introduction and Motivation
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Higher Bandgap for GaN
Makes it capable to withstand higher input power.
Eliminates the need of limiter circuitry.
GaN
LNA
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Introduction and Motivation
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12. K. W. Kobayashi, “An 8-W 250-MHz to 3-GHz Decade-Bandwidth Low-Noise GaN MMIC Feedback Amplifier
With > +51-dBm OIP3,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2316–2326, Oct. 2012.
Objective of this work is to explore techniques to improve LNA linearity performance and to
develop LNA for microwave.
2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
Linearization Approach
Divide a single FET into
multiple gates and bias
them separately.
If one device is biased in
Class AB and other in deep
Class AB then, inter-mods
of both can be adjusted to
be out of phase with each-
other and get cancelled.
As a prototype, two gates
are done.
For more than two gates bias
control can be difficulty.
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2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
GaN Device Technology
0.5 mm GaN HEMT AMCOM Chip
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Bias point
Bias both
devices
individually
Device Picture DC IV Characteristics
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Noise Figure Characterization
Source Pull measurement:
AMCOM 0.5mm GaN HEMT Chip (Die)
■ Using Focus Tuners
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Optimum Source plot
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Circuit Design
Target Specifications
2 – 4 GHz, 40dBm Pout, 50dBm OIP3
3 stage design: First stage stabilized by RC feedback.
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Package
Chip
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Circuit Design
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Cb = 100pF (blocking capacitor), Rf = 220 ohm, Cf = 0.3pF, R1 = 5ohm, R2 = 22ohm
C1 = 1pF, C2 = 2.7pF
W1 = 0.5mm, W2 = 1.25mm, W3 = 2.5mm2 -4GHz LNA , 38dBm Pout
Schematic of circuit on AutoCad
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Small Signal Simulation : CKT 1
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Freq: 2 -4GHz
Gain ~ 43dB, Insertion loss ~7-10dB
NF ~ 2 -2.5dB
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Large Signal simulation :CKT1
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Freq(GHz) SS Gain (dB) Pout(dBm) PAE(%)
2 43 38.63 30.53
2.5 42.62 40.11 34.13
3 41.68 39.84 35.05
3.5 41.52 40.06 36.3
4 43.89 40.37 38.79
Gain
Power
PAE
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Small Signal Simulation : CKT 2
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Freq: 2 - 4GHz
Gain ~ 43dB, Insertion loss ~7-10dB
NF ~ 2 -3dB
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Large Signal Simulation : CKT2
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Freq(GHz) SS Gain (dB) Pout(dBm) PAE(%)
2 40.5 38.25 30.49
2.5 41.06 38.42 29.47
3 42.33 39.29 34.56
3.5 42.8 39.68 33.15
4 44.7 40.36 37.26
Gain
PAE
Power
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Large Signal Simulation : IMD Current
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Computation of IMD Current for both the FET’s AWR microwave office using
foundry model.
Summation of the IMD Current at the output current node.
2018
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Φ difference
Large Signal Simulation
Plot of IMD3 current magnitude &
phase at 2.75GHz
40mA/mm
20mA/mm
60mA/mm
Sum (20_60)
Sum (40_40)
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Large Signal Simulation
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Φ difference
Plot of IMD3 current magnitude &
phase at 3GHz
40mA/mm
20mA/mm
60mA/mm
Sum (20_60)
Sum (40_40)
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Large Signal Simulation
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Φ difference
Plot of IMD3 current magnitude &
phase at 3.25GHz
40mA/mm
20mA/mm
60mA/mm
Sum (20_60)
Sum (40_40)
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Large Signal Simulation
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Φ difference
Plot of IMD3 current magnitude &
phase at 3.5GHz
40mA/mm
20mA/mm
60mA/mm
Sum (20_60)
Sum (40_40)
2018
Large Signal Simulation
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Φ difference
Plot of IMD3 current magnitude &
phase at 3.75GHz
40mA/mm
20mA/mm
60mA/mm
Sum (20_60)
Sum (40_40)
2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
Circuit Design
Picture of the
assembled prototype
circuits
Circuits identical to each
other except for third
stage to include
package parasitics in
the second circuit.
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3.5”
2”
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Measurement Results: Power and Noise
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Ckt1 , Ckt2
Similar power and noise performance
from 2.75 – 3.75 GHz.
Power 35 ~ 38dBm
Noise 1.8 ~ 3.5dB
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Measurement Results
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B. Kim, J.-S. Ko, and K. Lee, “Highly linear CMOS RF MMIC amplifier using multiple gated transistors and its Volterra series
analysis,” in Microwave Symposium Digest, 2001 IEEE MTT-S International, 2001, vol. 1, pp. 515–518 vol.1.
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Measurement Results : OIP3 & FOM
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2.75 GHz 3 GHz
3.25 GHz
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Measurement Results : OIP3 & FOM
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3.5 GHz
3.75 GHz
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Summary of results and comparison
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Case1: when both the devices are biased
at 40 mA/mm (40_40)
Case2: when first FET is biased at
20mA/mm and second FET is biased at
60mA/mm (20_60)
Comparison of results done at
15dBm (Lower power) (solid curves)
33dBm (Higher power) (dotted curves)
2018
SOA Comparison
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High output power and high OIP3 compared with previous designs with similar
noise figure with higher linearity FOM
2018
Introduction and Motivation
Linearization Approach
Circuit Design and Simulation
Measurement Results
Conclusion and Future Works
Outline
2018
Conclusion
Linearization technique demonstrated by biasing a
single FET in two individual FETs.
If one FET is biased in Class AB and other in deep Class
AB, linearity is improved.
■ Attributed to partial phase cancellation
Improvement in linearity upto 9.5dBm and FOM
upto 14
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2018
Future Work
Demonstrate the technique for MMIC
Use of more than two FET’s
Reconfigurable bias circuits.
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2018
References
S. Cha et al., “Wideband AlGaN/GaN HEMT low noise amplifier for highly
survivable receiver electronics,” in 2004 IEEE MTT-S International Microwave
Symposium Digest (IEEE Cat. No.04CH37535), 2004, vol. 2, p. 829–831
Vol.2.
S. E. Shih et al., “Broadband GaN Dual-Gate HEMT Low Noise Amplifier,” in
2007 IEEE Compound Semiconductor Integrated Circuits Symposium, 2007,
pp. 1–4.
K. W. Kobayashi, “An 8-W 250-MHz to 3-GHz Decade-Bandwidth Low-Noise
GaN MMIC Feedback Amplifier With > +51-dBm OIP3,” IEEE J. Solid-State
Circuits, vol. 47, no. 10, pp. 2316–2326, Oct. 2012.
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