sam3a/3u/3x/4e dma controller (dmac)...

SMART ARM-based Microcontrollers

AT07892: SAM3A/3U/3X/4E DMA Controller(DMAC) Driver

APPLICATION NOTE

Introduction

This driver for Atmel® | SMART ARM®-based microcontrollers provides aninterface for the configuration and management of the device's DirectMemory Access DMA Controller (DMAC) functionality.

The DMAC is an AHB-central DMA controller core that transfers data from asource peripheral to a destination peripheral over one or more AMBA buses.This is a driver for the configuration, enabling, disabling, and use of theDMAC peripheral.

Devices from the following series can use this module:• Atmel | SMART SAM3A• Atmel | SMART SAM3U• Atmel | SMART SAM3X• Atmel | SMART SAM4E

The outline of this documentation is as follows:• Prerequisites• Module Overview• Special Considerations• Extra Information• Examples• API Overview

Atmel-42291B-SAM3A-3U-3X-4E-DMA-Controller-DMAC_AT07892_Application Note-07/2015

Table of Contents

Introduction......................................................................................................................1

1. Software License....................................................................................................... 4

2. Prerequisites..............................................................................................................5

3. Module Overview.......................................................................................................6

4. Special Considerations..............................................................................................7

5. Extra Information....................................................................................................... 8

6. Examples...................................................................................................................9

7. API Overview...........................................................................................................107.1. Structure Definitions................................................................................................................... 10

7.1.1. Struct dma_transfer_descriptor_t................................................................................ 107.2. Function Definitions....................................................................................................................10

7.2.1. Function dmac_channel_disable()...............................................................................107.2.2. Function dmac_channel_enable()............................................................................... 107.2.3. Function dmac_channel_get_status()..........................................................................117.2.4. Function dmac_channel_is_enable()........................................................................... 117.2.5. Function dmac_channel_is_transfer_done()............................................................... 127.2.6. Function dmac_channel_keep().................................................................................. 127.2.7. Function dmac_channel_multi_buf_transfer_init().......................................................127.2.8. Function dmac_channel_resume().............................................................................. 137.2.9. Function dmac_channel_set_configuration()...............................................................137.2.10. Function dmac_channel_set_ctrlA()............................................................................ 137.2.11. Function dmac_channel_set_ctrlB()............................................................................ 147.2.12. Function dmac_channel_set_descriptor_addr().......................................................... 147.2.13. Function dmac_channel_set_destination_addr().........................................................147.2.14. Function dmac_channel_set_source_addr()............................................................... 157.2.15. Function dmac_channel_single_buf_transfer_init()..................................................... 157.2.16. Function dmac_channel_stop_transfer()..................................................................... 167.2.17. Function dmac_channel_suspend().............................................................................167.2.18. Function dmac_disable()............................................................................................. 167.2.19. Function dmac_disable_interrupt().............................................................................. 167.2.20. Function dmac_enable().............................................................................................. 177.2.21. Function dmac_enable_interrupt()...............................................................................177.2.22. Function dmac_get_interrupt_mask().......................................................................... 187.2.23. Function dmac_get_status()........................................................................................ 197.2.24. Function dmac_get_writeprotect_status()....................................................................197.2.25. Function dmac_init().................................................................................................... 197.2.26. Function dmac_set_priority_mode()............................................................................ 197.2.27. Function dmac_set_writeprotect()............................................................................... 207.2.28. Function dmac_soft_chunk_transfer_request()........................................................... 20

Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]Atmel-42291B-SAM3A-3U-3X-4E-DMA-Controller-DMAC_AT07892_Application Note-07/2015

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7.2.29. Function dmac_soft_set_last_transfer_flag()...............................................................207.2.30. Function dmac_soft_single_transfer_request()........................................................... 21

7.3. Enumeration Definitions............................................................................................................. 217.3.1. Enum dmac_priority_mode_t.......................................................................................21

8. Extra Information for Direct Memory Access Controller Driver................................ 228.1. Acronyms....................................................................................................................................228.2. Dependencies.............................................................................................................................228.3. Errata..........................................................................................................................................228.4. Module History............................................................................................................................22

9. Examples for Direct Memory Access Controller Driver............................................239.1. Quick Start Guide for the DMAC driver...................................................................................... 23

9.1.1. Use Cases................................................................................................................... 239.1.2. DMAC Basic Usage..................................................................................................... 239.1.3. Setup Steps................................................................................................................. 239.1.4. Usage Steps................................................................................................................ 24

9.2. SAM Direct Memory Access Controller - Example Memory to Memory Transfer.......................259.2.1. Purpose....................................................................................................................... 259.2.2. Requirements.............................................................................................................. 259.2.3. Description...................................................................................................................259.2.4. Main Files.................................................................................................................... 259.2.5. Compilation Information...............................................................................................259.2.6. Usage.......................................................................................................................... 25

10. Document Revision History..................................................................................... 27


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1. Software LicenseRedistribution and use in source and binary forms, with or without modification, are permitted providedthat the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and thefollowing disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and thefollowing disclaimer in the documentation and/or other materials provided with the distribution.

3. The name of Atmel may not be used to endorse or promote products derived from this software withoutspecific prior written permission.

4. This software may only be redistributed and used in connection with an Atmel microcontroller product.

THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND SPECIFICALLYDISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ORBUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISINGIN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OFSUCH DAMAGE.


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2. PrerequisitesThere are no prerequisites for this module.


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3. Module OverviewThe DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a sourceperipheral to a destination peripheral over one or more AMBA buses. One channel is required for eachsource/destination pair. In the most basic configuration, the DMAC has one master interface and onechannel. The master interface reads the data from a source and writes it to a destination. Two AMBAtransfers are required for each DMAC data transfer. This is also known as a dual-access transfer.


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4. Special ConsiderationsThere are no special considerations for this module.


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5. Extra InformationFor extra information, see Extra Information for Direct Memory Access Controller Driver. This includes:

• Acronyms• Dependencies• Errata• Module History


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6. ExamplesFor a list of examples related to this driver, see Examples for Direct Memory Access Controller Driver.


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7. API Overview

7.1. Structure Definitions

7.1.1. Struct dma_transfer_descriptor_t

DMA transfer descriptor structure, otherwise known as a Linked List Item (LLI).

Table 7-1 Members

Type Name Description

uint32_t ul_ctrlA Control A register settings

uint32_t ul_ctrlB Control B register settings

uint32_t ul_descriptor_addr Next descriptor address

uint32_t ul_destination_addr Destination buffer address

uint32_t ul_source_addr Source buffer address

7.2. Function Definitions

7.2.1. Function dmac_channel_disable()

Disable the specified DMA Channel.

void dmac_channel_disable( Dmac * p_dmac, uint32_t ul_num)

Table 7-2 Parameters

Data direction Parameter name Description

[out] p_dmac Module hardware register base address pointer

[in] ul_num DMA Channel number (range 0 to 3)

7.2.2. Function dmac_channel_enable()

Enable the specified DMA Channel.

void dmac_channel_enable( Dmac * p_dmac, uint32_t ul_num)


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7.2.3. Function dmac_channel_get_status()

Get the DMAC Channel handler status.

uint32_t dmac_channel_get_status( Dmac * p_dmac)



[in] p_dmac Module hardware register base address pointer

ReturnsDMAC Channel handler status register. Refer to the section called "DMAC Channel Handler StatusRegister" in the device-specific datasheet for more information.

7.2.4. Function dmac_channel_is_enable()

Check if the specified DMA Channel is enabled.

uint32_t dmac_channel_is_enable( Dmac * p_dmac, uint32_t ul_num)





ReturnsThe DMA Channel's enable/disable status.

Table 7-6 Return Values

Return value Description

0 DMA Channel is disabled

1 DMA Channel is enabled


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7.2.5. Function dmac_channel_is_transfer_done()

Check if the data transfer occurring on the specified DMA Channel is complete.

uint32_t dmac_channel_is_transfer_done( Dmac * p_dmac, uint32_t ul_num)

Note: This function is used in polling mode.





ReturnsThe data transfer status.

Table 7-8 Return Values

Return value Description

0 Data is transferring

1 Data transfer complete

7.2.6. Function dmac_channel_keep()

Resume the specified DMA Channel from an automatic stall state.

void dmac_channel_keep( Dmac * p_dmac, uint32_t ul_num)





7.2.7. Function dmac_channel_multi_buf_transfer_init()

Initialize the DMA Channel for a multiple buffer transfer.

void dmac_channel_multi_buf_transfer_init( Dmac * p_dmac, uint32_t ul_num, dma_transfer_descriptor_t * p_desc)


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[in, out] p_dmac Module hardware register base address pointer


[in] p_desc Pointer to a transfer descriptor

7.2.8. Function dmac_channel_resume()

Resume the specified DMA Channel transfer (restoring its context).

void dmac_channel_resume( Dmac * p_dmac, uint32_t ul_num)





7.2.9. Function dmac_channel_set_configuration()

Set the DMAC configuration register of the specified DMA Channel.

void dmac_channel_set_configuration( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_cfg)





[in] ul_cfg Configuration of CFG register

7.2.10. Function dmac_channel_set_ctrlA()

Set the DMA control A of the specified DMA Channel.

void dmac_channel_set_ctrlA( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_ctrlA)


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[in] ul_ctrlA Configuration of control A register

7.2.11. Function dmac_channel_set_ctrlB()

Set the DMA control B of the specified DMA Channel.

void dmac_channel_set_ctrlB( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_ctrlB)





[in] ul_ctrlB Configuration of control B register

7.2.12. Function dmac_channel_set_descriptor_addr()

Set the DMA descriptor address of the specified DMA Channel.

void dmac_channel_set_descriptor_addr( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_desc)





[in] ul_desc Descriptor address

7.2.13. Function dmac_channel_set_destination_addr()

Set the DMA destination address of the specified DMA Channel.

void dmac_channel_set_destination_addr( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_addr)


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[in] ul_addr Destination address

Note: This register must be aligned with the source transfer width.

7.2.14. Function dmac_channel_set_source_addr()

Set the DMA source address of the specified DMA Channel.

void dmac_channel_set_source_addr( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_addr)





[in] ul_addr Source address

Note: This register must be aligned with the source transfer width.

7.2.15. Function dmac_channel_single_buf_transfer_init()

Initialize the DMA Channel for a single buffer transfer.

void dmac_channel_single_buf_transfer_init( Dmac * p_dmac, uint32_t ul_num, dma_transfer_descriptor_t * p_desc)





[in] p_desc Pointer to a transfer descriptor


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7.2.16. Function dmac_channel_stop_transfer()

Stop a DMA transfer occurring on the specified DMA Channel.

void dmac_channel_stop_transfer( Dmac * p_dmac, uint32_t ul_num)

Note: Under normal operation, the hardware disables a channel on transfer completion by clearing theDMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losingdata is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register.





7.2.17. Function dmac_channel_suspend()

Suspend the specified DMA Channel and its current context.

void dmac_channel_suspend( Dmac * p_dmac, uint32_t ul_num)





7.2.18. Function dmac_disable()

Disable the DMA Controller.

void dmac_disable( Dmac * p_dmac)




7.2.19. Function dmac_disable_interrupt()

Disable DMAC interrupts.

void dmac_disable_interrupt( Dmac * p_dmac, uint32_t ul_mask)


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[in] ul_mask A bitmask of interrupts to be disabled

Where input parameter ul_mask is a bitmask containing one or more of the following:

Parameter Value Description

DMAC_EBCIDR_BTC0 Channel 0 Buffer Transfer Completed




DMAC_EBCIDR_CBTC0 Channel 0 Chained Buffer Transfer Completed




DMAC_EBCIDR_ERR0 Channel 0 Access Error




7.2.20. Function dmac_enable()

Enable the DMA Controller.

void dmac_enable( Dmac * p_dmac)




7.2.21. Function dmac_enable_interrupt()

Enable DMAC interrupts.

void dmac_enable_interrupt( Dmac * p_dmac, uint32_t ul_mask)


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[in] ul_mask A bitmask of interrupts to be enabled

Where input parameter ul_mask is a bitmask containing one or more of the following:

Parameter Value Description

DMAC_EBCIER_BTC0 Channel 0 Buffer Transfer Completed




DMAC_EBCIER_CBTC0 Channel 0 Chained Buffer Transfer Completed




DMAC_EBCIER_ERR0 Channel 0 Access Error




7.2.22. Function dmac_get_interrupt_mask()

Get the DMAC Interrupt Mask.

uint32_t dmac_get_interrupt_mask( Dmac * p_dmac)




ReturnsDMAC Interrupt mask.


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7.2.23. Function dmac_get_status()

Get the DMAC transfer status.

uint32_t dmac_get_status( Dmac * p_dmac)




ReturnsDMAC transfer status. Refer to section called "DMAC Error, Buffer Transfer and Chained Buffer TransferStatus Register" in the device-specific datasheet for more information.

7.2.24. Function dmac_get_writeprotect_status()

Get the DMAC register's write protect status.

uint32_t dmac_get_writeprotect_status( Dmac * p_dmac)




ReturnsWrite protect status.

7.2.25. Function dmac_init()

Initialize the DMA controller and disable it.

void dmac_init( Dmac * p_dmac)




7.2.26. Function dmac_set_priority_mode()

Set the DMA priority mode.

void dmac_set_priority_mode( Dmac * p_dmac, dmac_priority_mode_t mode)


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[in] mode Priority mode

7.2.27. Function dmac_set_writeprotect()

Enable/Disable the write protect of DMAC registers.

void dmac_set_writeprotect( Dmac * p_dmac, uint32_t ul_enable)




[in] ul_enable 1 to enable, 0 to disable

7.2.28. Function dmac_soft_chunk_transfer_request()

DMA Channel software chunk request.

void dmac_soft_chunk_transfer_request( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req)





[in] ul_src_req Request a source transfer

[in] ul_dst_req Request a destination transfer

7.2.29. Function dmac_soft_set_last_transfer_flag()

Set the DMA Channel's last transfer flag.

void dmac_soft_set_last_transfer_flag( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_src_flag, uint32_t ul_dst_flag)


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[in] ul_num Channel number

[in] ul_src_flag Last source transfer flag

[in] ul_dst_flag Last destination transfer flag

7.2.30. Function dmac_soft_single_transfer_request()

DMA Channel software single request.

void dmac_soft_single_transfer_request( Dmac * p_dmac, uint32_t ul_num, uint32_t ul_src_req, uint32_t ul_dst_req)





[in] ul_src_req Request a source transfer

[in] ul_dst_req Request a destination transfer

7.3. Enumeration Definitions

7.3.1. Enum dmac_priority_mode_t

Table 7-34 Members

Enum value Description

DMAC_PRIORITY_FIXED Fixed priority arbiter

DMAC_PRIORITY_ROUND_ROBIN Modified round robin arbiter


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8. Extra Information for Direct Memory Access Controller Driver

8.1. AcronymsBelow is a table listing the acronyms used in this module, along with their intended meanings.

Acronym Definition

AHB AMBA High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

FIFO First In First Out

LLI Linked List Item

QSG Quick Start Guide

8.2. DependenciesThis driver has the following dependencies:

• None

8.3. ErrataThere are no errata related to this driver.

8.4. Module HistoryAn overview of the module history is presented in the table below, with details on the enhancements andfixes made to the module since its first release. The current version of this corresponds to the newestversion in the table.

Changelog

Initial document release


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9. Examples for Direct Memory Access Controller DriverThis is a list of the available Quick Start Guides (QSGs) and example applications for SAM3A/3U/3X/4EDMA Controller (DMAC) Driver. QSGs are simple examples with step-by-step instructions to configureand use this driver in a selection of use cases. Note that a QSG can be compiled as a standaloneapplication or be added to the user application.

• Quick Start Guide for the DMAC driver• SAM Direct Memory Access Controller - Example Memory to Memory Transfer

9.1. Quick Start Guide for the DMAC driverThis is the quick start guide for the SAM3A/3U/3X/4E DMA Controller (DMAC) Driver, with step-by-stepinstructions on how to configure and use the driver for a specific use case. The code examples can becopied into the main application loop or any other function that will need to control the DMAC module.

9.1.1. Use Cases

• DMAC Basic Usage

9.1.2. DMAC Basic Usage

This use case will demonstrate how to initialize the DMAC module to perform a single memory to memorytransfer.

9.1.3. Setup Steps

9.1.3.1. Prerequisites

This module requires the following service• System Clock Management (sysclock)

9.1.3.2. Setup Code

Add these macros and global variable to the top of your application's C-file:#define DMA_CH 0

#define DMA_BUF_SIZE 32

uint32_t g_dma_buf[6][DMA_BUF_SIZE];

Add this to the main loop or a setup function:pmc_enable_periph_clk(ID_DMAC);

9.1.3.3. Workflow

1. Define the variables needed, in order to perform a data transfer:uint32_t i;uint32_t cfg;dma_transfer_descriptor_t desc;

2. Prepare the data buffer to be transferred:for (i = 0; i < DMA_BUF_SIZE; i++) { g_dma_buf[0][i] = i;


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g_dma_buf[1][i] = 0;}

3. Initialize the DMAC module:dmac_init(DMAC);

4. Set the priority to round-robin:dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);

5. Enable the DMAC module:dmac_enable(DMAC);

6. Configure the channel for:• Enable stop on done• Enable AHB protection• Set the FIFO so that largest defined length AHB burst is performed

cfg = DMAC_CFG_SOD_ENABLE | DMAC_CFG_AHB_PROT(1) | DMAC_CFG_FIFOCFG_ALAP_CFG; dmac_channel_set_configuration(DMAC, DMA_CH, cfg);

9.1.4. Usage Steps

9.1.4.1. Usage Code

Configure the DMA source and destination buffer addresses:desc.ul_source_addr = (uint32_t) g_dma_buf[0];desc.ul_destination_addr = (uint32_t) g_dma_buf[1];

Configure DMA CTRLA:• Set the buffer transfer size to DMA_BUF_SIZE• Set the source transfer width to 32-bit• Set the destination transfer width to 32-bit

desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;

Configure DMA CTRLB:• Disable source buffer descriptor fetch• Disable destination buffer descriptor Fetch• Enable memory-to-memory transfer• Increment the source address• Increment the destination address

desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE | DMAC_CTRLB_FC_MEM2MEM_DMA_FC | DMAC_CTRLB_SRC_INCR_INCREMENTING | DMAC_CTRLB_DST_INCR_INCREMENTING;


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Initialize the DMA transfer:desc.ul_descriptor_addr = 0;dmac_channel_single_buf_transfer_init(DMAC, DMA_CH, &desc);

Start the DMA transfer:dmac_channel_enable(DMAC, DMA_CH);

Finally, poll for the DMA transfer to complete:while (!dmac_channel_is_transfer_done(DMAC, DMA_CH)) {}

9.2. SAM Direct Memory Access Controller - Example Memory to Memory Transfer

9.2.1. Purpose

This example demonstrates how to configure and use DMAC controller for single and multiple memory tomemory data buffer transfers.

9.2.2. Requirements

This example can be used with SAM evaluation kits that have a DMA Controller.

9.2.3. Description

This example transfers data in one RAM buffer to another RAM buffer. Two transfer modes will be used:1. It uses single buffer transfer with polling mode. After transfer is done, the transferred data will be

verified.2. It uses multiple buffer transfer with interrupt mode. After transfer is done, the transferred data will

be verified.

9.2.4. Main Files

• dmac.c: Direct Memory Access Controller driver• dmac.h: Direct Memory Access Controller driver header file• dmac_example1.c: Direct Memory Access Controller example application

9.2.5. Compilation Information

This software is written for GNU GCC and IAR Embedded Workbench® for Atmel®. Other compilers mayor may not work.

9.2.6. Usage

1. Build the program and download it into the evaluation board.2. On the computer, open and configure a terminal application (e.g., HyperTerminal on Microsoft®

Windows®) with these settings:• 115200 baud• 8 bits of data• No parity• 1 stop bit


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• No flow control3. Start the application.4. In the terminal window, the following text should appear:

* -- DMAC Example --* -- xxxxxx-xx* -- Compiled: xxx xx xxxx xx:xx:xx --** Test single buffer transfer......* > Test OK** Test multiple buffer transfer......* > Test OK.

Note: Values depend on the board and the chip used.


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10. Document Revision HistoryDoc. Rev. Date Comments

42291B 07/2015 Updated title of application note and added list of supported devices

42291A 05/2014 Initial document release


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IntroductionTable of Contents1. Software License2. Prerequisites3. Module Overview4. Special Considerations5. Extra Information6. Examples7. API Overview7.1. Structure Definitions7.1.1. Struct dma_transfer_descriptor_t

7.2. Function Definitions7.2.1. Function dmac_channel_disable()7.2.2. Function dmac_channel_enable()7.2.3. Function dmac_channel_get_status()7.2.4. Function dmac_channel_is_enable()7.2.5. Function dmac_channel_is_transfer_done()7.2.6. Function dmac_channel_keep()7.2.7. Function dmac_channel_multi_buf_transfer_init()7.2.8. Function dmac_channel_resume()7.2.9. Function dmac_channel_set_configuration()7.2.10. Function dmac_channel_set_ctrlA()7.2.11. Function dmac_channel_set_ctrlB()7.2.12. Function dmac_channel_set_descriptor_addr()7.2.13. Function dmac_channel_set_destination_addr()7.2.14. Function dmac_channel_set_source_addr()7.2.15. Function dmac_channel_single_buf_transfer_init()7.2.16. Function dmac_channel_stop_transfer()7.2.17. Function dmac_channel_suspend()7.2.18. Function dmac_disable()7.2.19. Function dmac_disable_interrupt()7.2.20. Function dmac_enable()7.2.21. Function dmac_enable_interrupt()7.2.22. Function dmac_get_interrupt_mask()7.2.23. Function dmac_get_status()7.2.24. Function dmac_get_writeprotect_status()7.2.25. Function dmac_init()7.2.26. Function dmac_set_priority_mode()7.2.27. Function dmac_set_writeprotect()7.2.28. Function dmac_soft_chunk_transfer_request()7.2.29. Function dmac_soft_set_last_transfer_flag()7.2.30. Function dmac_soft_single_transfer_request()

7.3. Enumeration Definitions7.3.1. Enum dmac_priority_mode_t

8. Extra Information for Direct Memory Access Controller Driver8.1. Acronyms8.2. Dependencies8.3. Errata8.4. Module History

9. Examples for Direct Memory Access Controller Driver9.1. Quick Start Guide for the DMAC driver9.1.1. Use Cases9.1.2. DMAC Basic Usage9.1.3. Setup Steps9.1.3.1. Prerequisites9.1.3.2. Setup Code9.1.3.3. Workflow

9.1.4. Usage Steps9.1.4.1. Usage Code

9.2. SAM Direct Memory Access Controller - Example Memory to Memory Transfer9.2.1. Purpose9.2.2. Requirements9.2.3. Description9.2.4. Main Files9.2.5. Compilation Information9.2.6. Usage

10. Document Revision History

sam3a/3u/3x/4e dma controller (dmac)...

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