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Measurement 31 (2002) 187–199www.elsevier.com/ locate /measurement

Sampling clock jitter effects in digital-to-analog convertersa a , a b*Naoki Kurosawa , Haruo Kobayashi , Hideyuki Kogure , Takanori Komuro ,

bHiroshi SakayoriaDepartment of Electronic Engineering, Gunma University, 1-5-1 Tenjin-cho, Kiryu 376-8515, Japan

bAgilent Technologies Japan Ltd., 9-1 Takakura-cho Hachioji, Tokyo 192-8510, Japan

Abstract

This paper describes sampling clock jitter effects in digital-to-analog converters. A formula for the output error power dueto sampling clock jitter for a sinusoidal input is derived and verified by numerical simulations, and its spectrumcharacteristics is shown. Also its effects on DAC SNR is clarified by numerical simulation as follows: (i) When the totalnoise power outside as well as inside the signal band is taken into account, the DAC SNR remains almost constant regardlessof the sampling jitter. (ii) However, when an analog lowpass filter follows the DAC and only the noise power inside thesignal band is considered, the DAC SNR degrades as the jitter increases and the input signal frequency becomes higher. Thusthe sampling clock jitter is serious for the high speed DAC. 2002 Elsevier Science Ltd. All rights reserved.

Keywords: Jitter; Sampling; DAC; Analog circuit; Spread spectrum

1. Introduction numerical simulation verifies the derived formula. InSection 4, the power spectrum characteristics of the

Digital-to-analog converters (DACs) are essential DAC output error due to the sampling jitter iscomponents for measuring instruments (such as discussed, and in Section 5 we clarify by numericalarbitrary waveform signal generators) and communi- simulations that sampling clock jitter degrades sig-cation systems (such as transceivers), and higher nal-to-noise ratio (SNR, one of the important per-sampling speed is being demanded for them [1–3]. formance metrics of the DAC [3]) significantly.For such high sampling speed DACs, their sampling Finally Section 6 provides conclusion.clock jitter effects may be crucial; the clock jittereffects of DACs have not been well investigated,even though those of analog-to-digital converters 2. DAC output error power due to sampling(ADCs) and sampling circuits have been [4–8]. In clock jitterthis paper we analyze their effects theoretically andverify them by numerical simulations. In Section 2, 2.1. Problem formulationthe formula for the DAC output error power due tothe sampling jitter is derived, and in Section 3, Fig. 1 shows a DAC where a digital input V (n) isin

applied with a sampling clock of CLK. Ideally thesampling clock CLK operates with a period of T fors*Corresponding author. Tel.: 181-277-30-1788; fax: 181-277-every cycle, however in reality its timing can fluc-30-1707.

E-mail address: k [email protected] (H. Kobayashi). tuate which is called jitter or phase noise (Fig. 2)]

0263-2241/02/$ – see front matter 2002 Elsevier Science Ltd. All rights reserved.PI I : S0263-2241( 01 )00028-8

188 N. Kurosawa et al. / Measurement 31 (2002) 187 –199

sampling period of T in most of practical situations,s

we assume that

T Ts s] ]2 , e , . (1)n2 2

Also we suppose that the DAC has sufficiently goodFig. 1. A DAC with digital input signal, sampling clock and resolution so that quantization can be neglected, andanalog output signal.

the DAC output V (t) is zero-order hold [3]. Thenout

[9,10]. If we denote jitter as e , then the n-th Fig. 3 shows the DAC outputs with an ideal clockn

sampling timing of CLK is nT 1 e instead of nT . (without jitter) and an actual clock (with jitter) whiles n s

Since the jitter e is sufficiently smaller than the Fig. 4 shows the DAC output error due to jitter.n

Fig. 2. Ideal sampling clock (without jitter) and actual sampling clock (with jitter e ) provided to a DAC.n

Fig. 3. DAC output waveforms with ideal sampling clock (without jitter) and actual sampling clock (with jitter e ).n

N. Kurosawa et al. / Measurement 31 (2002) 187 –199 189

Fig. 4. DAC output error due to sampling clock jitter e .n

2.2. Error power formula due to jitter assumed for the DAC sampling clock; the n-th DACsampling timing is nT 1 D instead of nT , where Ds n s n

The DAC output error power P due to the is a periodic sequence with period M. This probleme

sampling clock jitter is defined as follows: formulation is similar to that for the timing skeweffect in time-interleaved ADC systems [4,13]. In

N211 2 Ref. [12] it is considered that the DAC sampling]P [ lim O e ue u (Time Average)e n nNN→` (2) clock is phase-modulated by a deterministic sinen502 wave and it is given by5 E[e ue u] (Ensemble Average).n n

Here e is the DAC output error due to jitter (see Fig. A cos(v t 1 b sin(v t))n s j4). If the input signal V (t) and the sampling jitterin

are not correlated (which is the case in general), e where v is the nominal DAC clock frequency, v isn s j

and e are independent and we obtain the jitter frequency and b is the modulation index.n

On the contrary, in this paper we consider the case2P 5 E[e ]E[ue u]. (3)e n n that the DAC sampling clock is phase-modulated bya random signal, as described above in this section.

Proposition. When the input V (n) to the DAC is ain

cosine wave

fin 3. Numerical simulation of DAC output error]V (n) 5 A cos 2p n ,S Din f power due to sampling clock jitters

the error power P due to jitter is given bye Example 1. Suppose that the jitter e follows an

uniform distribution whose probability function p(e )f nin2 2 ]P 5 2A sin p n E[ue u].S D is shown in Fig. 5:e fs

1Here f is the input frequency and f is the samplingin s ] (2a # e # a)nfrequency ( f 5 1/T ). p(e ) 5 2as s n 50 (otherwise).Proof of Proposition. See Appendix A.

Note that 0 , a , T /2 according to Eq. (1). Sinces

Remark. The references of [11,12] discuss non- 1]E[ue u] 5 a,uniform sampling effects to DACs, however, our n 2

problem formulation is different from theirs. In Ref.[11], periodic fixed-amount of timing offsets are we obtain


Fig. 5. Probability distribution of the jitter e (uniform distribu-n

tion, 0 , a , T /2).s Fig. 7. Probability distribution of the jitter e (triangular dis-n

tribution, 0 , a , T /2).s

fin2 2 1]P 5 A a sin p . (4)S De ] (a 2 ue u) (2a # e # a)f 2 n ns p(e ) 5 an 5Fig. 6 shows a graph of f /f versus P calculated 0 (otherwise).in s e

numerically from Eq. (4) and a graph obtained froma DAC simulation including jitter, where a 5 T /4s Similarly, we assume 0 , a , T /2 according to Eq.sand A 5 2 are used in both cases. We see that both (1). Sincematch well and hence Eq. (4) is verified by simula-tion.

1]E[ue u] 5 a,n 3Example 2. Suppose that the jitter e follows an

distribution whose probability function p(e ) is inn

triangular shape as shown in Fig. 7: we obtain

Fig. 6. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the uniform distribution with a 5 T /4in s e s

(Fig. 5). The solid line shows numerical calculation results from Eq. (4) while 1 indicates DAC simulation results including jitter.


Fig. 8. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the triangular distribution with a 5 T /4in s e s


f2 in2 2] ]P 5 A a sin p . (5)S De 3 fs

Fig. 8 shows a graph of f /f versus P calculatedin s e

numerically from Eq. (5) and a graph obtained froma DAC simulation including jitter, where a 5 T /4s

and A 5 2 are used in both cases. We see that bothmatch well and Eq. (5) is verified by simulation.

Example 3. Suppose that the jitter e follows an

distribution whose probability function is in cosineFig. 9. Probability distribution of the jitter e (cosine distribution,nshape as shown in Fig. 9: 0 , a , T /2).s

pep n] ]cos (2a # e # a)S D n4a 2ap(e ) 5n H f2 in2 20 (otherwise). ] ]P 5 (p 2 2)A a sin p . (6)S De p fs

Similarly, we assume 0 , a , T /2 according to Eq. Fig. 10 shows a graph of f /f versus P calculateds in s e

(1). Since numerically from Eq. (6) and a graph obtained froma DAC simulation including jitter, where a 5 T /4s

a and A 5 2 are used in both cases. We see that both]E[ue u] 5 (p 2 2),n match well and Eq. (6) is verified by simulation.p

we obtain Example 4. Suppose that the jitter e follows an


Fig. 10. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the cosine distribution with a 5 T /4in s e s


distribution whose probability function is in cosine we obtainsquared shape as shown in Fig. 11:

f1 in2 2 2] ]P 5 (p 2 4)A a sin p . (7)pe1 S De 2n2 fp] ] scos (2a # e # a)S D na 2ap(e ) 5n 5Fig. 12 shows a graph of f /f versus P calculated0 (otherwise). in s e

numerically from Eq. (7) and a graph obtained fromSimilarly, we assume 0 , a , T /2 according to Eq.s a DAC simulation including jitter, where a 5 T /4s(1). Since and A 5 2 are used in both cases. We see that both

a match well and Eq. (7) is verified by simulation.2]]E[ue u] 5 (p 2 4),n 22p

Remark. (i) The numerical simulation results in thissection show the plausibility of ergodic processassumption in Eq. (2); Eqs. (4)–(7) are derived byensemble average while the numerical simulationuses time average, and as Figs. 6, 8, 10 and 12 showthat the equations and the simulation results matchvery well.

(ii) In general the quantization noise (which weneglect in our problem formulation in Section 2) andthe noise due to the sampling jitter in a DAC arestatistically independent. Hence the total error powerwhen both the quantization and the sampling jitterexist is just the simple addition of the error powerdue to quantization and that due to the samplingFig. 11. Probability distribution of the jitter e (cosine squaredn

distribution, 0 , a , T /2). jitter. We have confirmed this fact by numericals


Fig. 12. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the cosine squared distribution (Fig.in s e

11) with a 5 T /4. The solid line shows numerical calculation results from Eq. (7) while 1 indicates DAC simulation results includings

jitter.

simulation; Fig. 13 shows simulation results for jitter power when both jitter and quantization exist is theand quantization effects, where jitter of the uniform addition of the error power when only jitter exists todistribution with a 5 T /800 (Fig. 5) and 6-bit that when only quantization exists. According to ours

quantization are assumed. We see that the error simulation, this fact holds for jitter of other dis-

Fig. 13. Simulation results for jitter and quantization effects, where jitter of the uniform distribution with a 5 T /800 (Fig. 5) and 6-bits

quantization are assumed. We see that the error power when both jitter and quantization exist are the addition of the error power when onlyjitter exists to that when only quantization exists.


tributions and other levels of quantization (e.g. 8-bit be approximated by multiplication of the samplingquantization). impulse by e , where e 5 62A sin(p( f /f ))n n in s

1](iii) According to our experiences, the cosine sin(2p( f /f )(n 2 )). The sampling impulse can bein s 2

squared distribution in Example 4 (Fig. 11) approxi- approximated by Fourier series with a fundamentalmates the actual jitter distribution most accurately. frequency of f . Hence the peak frequencies of thes

DAC error power due to jitter are kf 6 f .s in

4. Power spectrum of DAC output error due to5. Sampling jitter effects on DAC SNRsampling clock jitter

According to Eq. (8), one might ponder as fol-Next we will consider the power spectrum charac-lows: ‘If the input signal f is smaller than Nyquistteristics of the DAC output error due to the jitter. in

frequency f /2 (which is usually the case), kf 6 fSuppose that the input V (n) to the DAC is a cosine s s ininare beyond f /2 for all of k 5 1, 2, 3, . . . (in otherwave s

words these are out of signal band) and hence thefin error peaks can be attenuated by an analog filter]V (n) 5 A cos 2p nS Din fs following the DAC. Therefore the sampling jitter

effects on DACs are not serious.’ However, thisand the DAC suffers from sampling clock jitter ofstatement is not true. Their effects are very seriousthe uniform distribution (Fig. 5). Fig. 14 showsand now we will show their effects to DAC SNR.simulation results of the power spectrum of the error,Fig. 15 shows the power spectrum of a 10-bit idealand we see that their power has peaks atDAC output without jitter for f /f 5 103/512. Sincein s

kf 6 f (k 5 1, 2, 3, . . . ). (8) we consider the case that the DAC output is zero-s in

order hold, the DAC output error due to the zero-Remark. For all of the other jitter distributions order hold output has peaks of the power spectrum atshown in the above examples, the error power due to kf 6 f (k 5 1, 2, 3, . . . ) [3]. Then it follows froms in

the jitter has peaks at the same frequencies. This can Eq. (8) that the DAC output errors due to jitter andbe explained qualitatively as follows: the error can zero-order hold have the peaks of the power spec-

Fig. 14. The power spectrum of DAC output error power due to jitter (whose distribution is shown in Fig. 5 with a 5 T /4) for the inputs

V (n) 5 cos(2p( f /f )n) with f /f 5 103/512. The peaks are located at f k6 f where k 5 1, 2, 3, . . . .in in s in s s in


Fig. 15. The power spectrum of a 10-bit DAC zero-hold output without the sampling clock jitter for f /f 5 103/512.in s

trum at the same frequencies. On the other hand, Fig. jitter. However, in practical situation, the DAC is16 shows the power spectrum of the same DAC with often followed by an analog low filter which suffi-jitter (cosine squared distribution of a 5 T /4 in Fig. ciently attenuates the noise components beyond f /2.s s

11), and we see that the noise floor increases. Figs. In this case we consider that SNR is given by 1017 and 18 show the SNRs of the DAC with and log hsignal powerj / hnoise power between 0 to f /210 s

without jitter, where the whole noise (outside as well (total noise power in the signal band)j [dB], andas inside the signal band f /2) is considered. We see Figs. 19 and 20 show the simulation results of SNRss

that SNR degrades slightly (by a few dB) due to the using the above definition with the sampling clock

Fig. 16. The power spectrum of a 10-bit DAC zero-hold output with the sampling clock jitter of cosine squared distribution of a 5 T /4s

(Fig. 11), for f /f 5 103/512.in s


Fig. 17. Simulation result of SNR versus f /f of a 10-bit DAC with and without jitter of cosine squared distribution of a 5 T /4 (Fig. 11).in s s

Here the total noise power outside as well as inside the signal band is considered.

Fig. 18. Simulation result of SNR versus the jitter a /T of a 10-bit DAC with jitter of cosine squared distribution (Fig. 11) fors

f /f 5 3/512. Here the total noise power outside as well as inside the signal band is considered.in s

jitter; Fig. 19 shows that as the input frequency f power due to the zero-hold output and the jitter hasin

increases for a given jitter, SNR gets worse while the peaks at kf 6 f (k 5 1, 2, 3, . . . ) (which iss in

Fig. 20 shows that as the jitter increases for a given higher than f /2 for all k) and if we consider thes

input frequency f , SNR degrades significantly. whole noise outside as well as inside the signal bandin

These results can be interpreted as follows: the noise f /2, the dominant noises are located at these fre-s


Fig. 19. Simulation result of SNR versus f /f of a 10-bit DAC with and without jitter of cosine squared distribution of a 5 T /4 (Fig. 11).in s s

Here only the noise power inside the signal band f /2 is considered.s

Fig. 20. Simulation result of SNR versus the jitter a /T of a 10-bit DAC with jitter of cosine squared distribution (Fig. 11) for f /f 5 3/512.in s

Here only the noise power inside the signal band f /2 is considered.s

quencies. The sampling clock jitter induces the the total noise power remains almost constant. Hencespread spectrum effects for the peak frequency when the total noise power is considered, the SNR ofnoises (as well as the signal power) and the power at the DAC is almost constant regardless of the sam-these frequencies is widely spread to other frequen- pling jitter. On the other hand, when only the noisecies, and hence the noise floor increases. However, inside the signal band f /2 is taken into account, thes


SNR degrades significantly due to the sampling jitter e 5V (n 2 1) 2V (n)n in in

because the noise floor inside the signal band is f fin in] ]raised by the jitter (in this case the noise peaks at 5 A cos 2p (n 2 1) 2 A cos 2p nS D S Df fs skf 6 f are out of signal band and we do not have tos inf f 1consider them). in in] ] ]S D5 2A sin p sin 2p n 2 .S D S D2f fs s

In case e . 0,n

6. Conclusion e 5V (n) 2V (n 2 1).n in in

In both cases,We have described sampling clock jitter effects in2 2DACs. A formula for the output error power due to e 5 [V (n) 2V (n 2 1)]n in insampling clock jitter is derived and its spectrum

f f 1in in2 2 2characteristics is shown. Also we have investigated ] ] ]S D5 4A sin p sin 2p n 2S D S D2f fits effects on SNR by numerical simulation and s s

found the following: f f 1in in2 2 ] ] ]S D5 2A sin p 1 2 cos 4p n 2 .S DF S DG(i) When the total noise power outside as well as 2f fs sinside the signal band is taken into account, the DACSinceSNR remains almost constant regardless of the

sampling jitter. f 1in] ]S DE cos 4p n 2 5 0,(ii) However, when an analog lowpass filter F S DG2fsfollows the DAC and only the noise power inside the

signal band is considered, the DAC SNR degrades as we obtainthe jitter increases and the input signal frequency fin2 2 2becomes higher. Thus the sampling clock jitter is ]E[e ] 5 2A sin p . (A.1)S Dn fsserious for the high speed DAC.

As another DAC timing non-ideality issue, we are Then it follows from Eqs. (3) and (A.1) thatcurrently investigating the characterization of the

fin2 2glitches which are caused by the timing skew inside ]P 5 2A sin p E[ue u],S De nfsthe DAC [2,3] and this result will be reportedelsewhere. and thus the proposition is proved. (Q.E.D.)

ReferencesAcknowledgements

[1] H. Kobayashi, K. Kobayashi, H. Sakayori, Y. Kimura, ADCWe would like to thank M. Morimura, K. Standard and Testing in Japanese Industr, Computer Stan-

Kobayashi, K. Yamashita and K. Wilkinson for dards & Interfaces, Elsevier Publishers 23(1), pp. 57–64(March 2001).valuable discussions. A part of this work was

[2] M. Gustavsson, J.J. Wikner, N.N. Tan, CMOS Data Conver-performed at Gunma University Satellite Ventureters for Communications, Kluwer Academic Publishers,

Business Laboratory. 2000.[3] B. Razavi, Principles of Data Conversion System Design,

IEEE Press, 1995.[4] H. Kobayashi, M. Morimura, K. Kobayashi, Y. Onaya,

Aperture Jitter Effects on Wideband Sampling Systems,Appendix AProceedings of the Instrumentation and Measurement Tech-nology Conference, pp. 880–885, Venice, Italy (May 1999).

This Appendix gives proof of Proposition in [5] H. Kobayashi, K. Kobayashi, Y. Takahashi, K. Enomoto, H.Section 2. Look at Fig. 4, and in case e # 0, Kogure, Y. Onaya, M. Morimura, Finite Aperture Time andn


Sampling Jitter Effects in Wideband Data Acquisition Sys- Dr. Eng. degree in electrical engineering from Waseda Universitytems, Proceedings of the Automatic RF Techniques Group in 1995. In 1982, he joined Yokogawa Electric Corp. Tokyo,56th Measurement Conference – Metrology and Test for RF Japan, where he was engaged in the research and developmentTelecommunications, pp. 115–121, Boulder, Colorado, USA related to measuring instruments and a mini-supercomputer. From(Dec. 2000). 1994 to 1997 he was involved in the research and development of

[6] S.S. Awad, Analysis of accumulated timing-jitter in the time ultra-high-speed ADCs and DACs at Teratec Corporation. He wasdomain, IEEE Trans. Instrum. Measurem. 47 (1) (1998) also an adjunct lecturer at Waseda University from 1994 to 1997.69–74. In 1997 he joined Gunma University and presently is an Associate

[7] M. Shinagawa, Y. Akazawa, T. Wakimoto, Jitter analysis of Professor in Electronic Engineering Department there. Dr.high-speed sampling systems, IEEE J. Solid-State Circ. 25 Kobayashi received the 1994 Best Paper Award from the Japanese(1) (1990) 220–224. Neural Network Society, and he is a member of the IEEE.

[8] W.L. Gans, The measurement and deconvolution of timejitter in equivalent-time waveform samplers, IEEE Trans. Hideyuki KOGURE received the B.S. degree in electronicInstrument. Measurem. 32 (1) (1983) 126–133. engineering from Gunma University, Japan in 2000, and currently

[9] A. Hajimiri, T. Lee, A general theory of phase noise in he is an M.S. course student there. His research interests includeelectrical oscillators, IEEE J. Solid-State Circ. 33 (2) (1998) analog integrated circuit design.179–193.

[10] B. Razavi, A study of phase noise in CMOS oscillators, Takanori KOMURO received his BSEE degree in electronicIEEE J. Solid-State Circ. 31 (3) (1996) 331–343. engineering from the University of Tokyo, and joined Yokogawa

[11] Y.-C. Jenq, Digital-to-analog (D/A) converters with Electronic Works in 1985. He had developed AD converter fornonuniformly sampled signals, IEEE Trans. Instrument. measurement instruments. From 1991 to 1995, he had joined aMeasurem. 45 (1) (1997) 56–59. consortium called Superconductive Sensor Laboratory, at which

[12] Y.-C. Jenq, Direct digital synthesizer with jittered clock, he took part to develop electronic portion of MEG system. In 1995IEEE Trans. Instrument. Measurem. 46 (3) (1996) 653–655. he joined Kanazawa Institute of Technology as researcher. Then

[13] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, K. he had developed SQUID system. In 1997, he joined AgilentKobayashi, Explicit Analysis of Channel Mismatch Effects Technologies Japan Ltd. And he is now developing measuringin Time-Interleaved ADC Systems, IEEE Trans. Circ. Syst. – sub-system for LSI tester. He is a member of the IEEE.I, 48(3) (March 2001) pp. 261–271.

Hiroshi SAKAYORI received his BSEE degree in electronicengineering from Waseda University, and joined Agilent Tech-Naoki KUROSAWA received the B.S. degree in electronicnologies Japan Ltd. (former Hewlett-Packard Japan Ltd.) in 1972.engineering from Gunma University, Japan in 2000, and currentlyHe has developed LCR meters and related products, and semi-he is an M.S. course student there. His research interests includeconductor parameter analyzer. From 1992 to 1997, he hasanalog integrated circuit design.temporarily left Agilent Technologies and has joined a consortiumcalled Teratec, at which he took part to develop high speed dataHaruo KOBOYASHI received the B.S. and M.S. degrees inconversion technology. He is now responsible for developinginformation physics from University of Tokyo in 1980 and 1982measuring sub-system for mixed-signal LSI tester. He is a memberrespectively, the M.S. degree in electrical engineering fromof the Institute of Electrical Engineers of Japan.University of California, Los Angeles (UCLA) in 1989, and the

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