sar adc’s and delta sigma adc’s - ti training architecture...11001101011010 10101010101010...
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SAR ADC’s and Delta Sigma ADC’s: Different Architectures for Different Applications
1
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments
SAR
ADS7xxx
ADS8xxx
≤ 4 Msps
≤ 1.25 Msps
≤ 16-bit
≤ 18-bit
• Easy to Use
• Zero Latency
• Low Power
Delta-Sigma
ADS10xx/11xx
ADS12xxx
ADS13xxx
ADS16xx
≤ 4 Ksps
≤ 4 Msps
≤ 10 Msps
> 24-bit
≤ 24-bit
≤ 16-bit
• High Resolution
• High Integration
Pipeline
≤ 200 Msps
≤ 250 Msps
≤ 1000 Msps
≤ 16-bit
≤ 14-bit
≤ 12-bit
• Higher Speed
• Higher Power
2
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments
SAR
ADS7xxx
ADS8xxx
≤ 4 Msps
≤ 1.25 Msps
≤ 16-bit
≤ 18-bit
• Easy to Use
• Zero Latency
• Low Power
Delta-Sigma
ADS10xx/11xx
ADS12xxx
ADS13xxx
ADS16xx
≤ 4 Ksps
≤ 4 Msps
≤ 10 Msps
> 24-bit
≤ 24-bit
≤ 16-bit
• High Resolution
• High Integration
Pipeline
≤ 200 Msps
≤ 250 Msps
≤ 1000 Msps
≤ 16-bit
≤ 14-bit
≤ 12-bit
• Higher Speed
• Higher Power
3
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments
SAR
ADS7xxx
ADS8xxx
≤ 4 Msps
≤ 1.25 Msps
≤ 16-bit
≤ 18-bit
• Easy to Use
• Zero Latency
• Low Power
Delta-Sigma
ADS10xx/11xx
ADS12xxx
ADS13xxx
ADS16xx
≤ 4 Ksps
≤ 4 Msps
≤ 10 Msps
> 24-bit
≤ 24-bit
≤ 16-bit
• High Resolution
• High Integration
Pipeline
≤ 200 Msps
≤ 250 Msps
≤ 1000 Msps
≤ 16-bit
≤ 14-bit
≤ 12-bit
• Higher Speed
• Higher Power
4
Selecting ADC Topology
ADC Topology Data Rate Resolution Comments
SAR
ADS7xxx
ADS8xxx
≤ 4 Msps
≤ 1.25 Msps
≤ 16-bit
≤ 18-bit
• Easy to Use
• Zero Latency
• Low Power
Delta-Sigma
ADS10xx/11xx
ADS12xxx
ADS13xxx
ADS16xx
≤ 4 Ksps
≤ 4 Msps
≤ 10 Msps
> 24-bit
≤ 24-bit
≤ 16-bit
• High Resolution
• High Integration
Pipeline
≤ 200 Msps
≤ 250 Msps
≤ 1000 Msps
≤ 16-bit
≤ 14-bit
≤ 12-bit
• Higher Speed
• Higher Power
5
SAR ADC takes “snapshots” Each conversion command captures the
signal level, at that point in time, onto the
sample/hold
ADC calculates an average The signal is sampled continuously
What is the ADC actually converting?
SAR vs. Delta-Sigma
SAR
6
• SAR conversions have Start Conversion Signal
• Delta-Sigma is always sampling/converting
SAR Converter
Start Conversion
Conversion Done
Delta-Sigma Converter
Input Sampling
Conversion Done
How does the ADC control happen?
SAR vs. Delta-Sigma
7
?
How Does a SAR ADC Work?
• Similar to a balance scale
½ ¼ 1
8
How Does a SAR ADC Work?
• Similar to a balance scale
½ ¼ 1
?
9
How Does a SAR ADC Work?
• Similar to a balance scale
½ ¼ 1
?
10
How Does a SAR ADC Work?
• Similar to a balance scale
½ ¼
? MSB
1
1
The MSB is determined first
11
How Does a SAR ADC Work?
• Similar to a balance scale
½
¼
?
MSB
1
1
The test is repeated for each
Binary weighted bit
Mid
0
12
How Does a SAR ADC Work?
• Similar to a balance scale
½
?
MSB
1
1
Mid
0
¼
LSB
1
The LSB is determined last
13
Typical Topology of a SAR ADC
14
SAR ADC Acquisition Phase
COMPARATOR
SAMPLE & HOLD
VIN DAC
C
S1
VIN
S2
N-bit Search
DAC
Data Register
SAR
15
SAR ADC Acquisition Phase
VSH0
VIN
tAQ Time
1/2 LSB
VCSH(t)
t0
COMPARATOR
SAMPLE & HOLD
VIN DAC
C
S1
VIN
S2
N-bit Search
DAC
Data Register
SAR
16
SAR ADC Acquisition Phase
)1()]([)()( 00
t
CSHINCSHCSH etVVtVtV
VSH0
VIN
tAQ Time
1/2 LSB
VCSH(t)
t0
SHS CR 1
COMPARATOR
SAMPLE & HOLD
VIN DAC
17
SAR ADC Conversion Phase
Analog
Input
VD
AC
FS
0
1/4FS
1/2FS
3/4FS
TEST
MSB
TEST
MSB -1
TEST
LSB
TEST
MSB -2
Bit = 1
Bit = 0
Bit = 1 Bit = 0
Digital Output Code = 10100
Time
Bit = 0
TEST
MSB -3
DAC Output 18
SAR ADCs
• Very Popular Topology
• Attractive in “Point in Time” or Multiplexed Measurements
• Advantages
– “no latency”
• input is sampled once
• “balancing” done internally
– good tradeoff between speed, resolution and power
• Speed: DC to 4MSPS
• Resolution: 8 to 18 bits; and moving towards higher resolutions
• TI Part Numbers:
– ADS7xxx
– ADS8xxx
SAR ADC
19
Delta Sigma Topology
Delta-Sigma Modulator
Analog Input
Digital Filter
Decimator
Digital Output
Digital Decimating Filter
20
Delta Sigma
Modulator
Digital
Filter Decimator
Delta Sigma Topology (2)
Delta-Sigma Modulator
Analog Input
Digital Filter
Decimator
Digital Output
Digital Decimating Filter
SAMPLING RATE (Fs)
21
Delta Sigma
Modulator
Digital
Filter Decimator
High frequency, 1 bit PCM data stream
(Samples at High Frequency)
Delta Sigma Topology (3)
Delta-Sigma Modulator
Analog Input
Digital Filter
Decimator
Digital Output
Digital Decimating Filter
SAMPLING RATE (Fs)
DATA RATE (Fd)
22
Delta Sigma
Modulator
Digital
Filter Decimator
High frequency, 1 bit PCM data stream
Lower data rate, very high
resolution digital output
Input Oversampling
23
Oversampling (1)
fs/2 fs
Power
Average Noise energy distributed from DC to
fs/2
Ideal N-Bit ADC SNR= 6.02 N + 1.76 dB
DC
Input Signal
Average Noise Floor
24
Oversampling (2)
– On a Delta-Sigma Converter, the analog input is sampled at a Frequency much higher than the Nyquist rate
fs/2 fs
Power
Average Noise energy distributed from DC to
fs/2
Ideal N-Bit ADC SNR= 6.02 N + 1.76 dB
DC
Input Signal
Average Noise Floor
Average Noise Floor
K fs/2 K fs
Power
Average Noise energy distributed over a wider range from DC to K fs/2
SNR= 6.02 N + 1.76 dB +10 log (OSR)
DC
Digital Low Pass filter
Oversampling
Delta Sigma Modulator
25
Delta Sigma
Modulator
Digital
Filter Decimato
r
First Order Delta-Sigma Modulator (1)
Noise Shaping
Integrator
(Low-Pass)
A(f)=1/f
Input
Signal
Xi
∑ +
∑
-
ei
Quantization
Noise
1-Bit
ADC
1-Bit
DAC
Yi
26
First Order Delta-Sigma Modulator (2)
Noise Shaping
Noise
Transfer
Function
Signal
Transfer
Function
Integrator
(Low-Pass)
A(f)=1/f
Input
Signal
Xi
∑ +
∑
-
ei
Quantization
Noise
1-Bit
ADC
1-Bit
DAC
Yi
𝑌 = 𝑋 − 𝑌 𝐴 𝑓 + 𝑒 𝑛 (1)
𝑌 = 𝑒 𝑛𝑓
1 + 𝑓+ 𝑋
1
1 + 𝑓 (2)
27
First Order Delta-Sigma Modulator (3)
Noise Shaping
Signal
Ma
gn
itu
de
Quantization
Noise
Noise
Transfer
Function
Signal
Transfer
Function
Integrator
(Low-Pass)
A(f)=1/f
Input
Signal
Xi
∑ +
∑
-
ei
Quantization
Noise
1-Bit
ADC
1-Bit
DAC
Yi
𝑌 = 𝑋 − 𝑌 𝐴 𝑓 + 𝑒 𝑛 (1)
𝑌 = 𝑒 𝑛𝑓
1 + 𝑓+ 𝑋
1
1 + 𝑓 (2)
28
First Order Delta-Sigma Modulator (4)
Noise Shaping
Modulator Output: TIME DOMAIN
0
1
Believe it or not, the sine wave is in there!
(drawing is approximate)
Sig
nal
29
First Order Delta-Sigma Modulator (5)
Noise Shaping
Modulator Output: TIME DOMAIN
0
1
Believe it or not, the sine wave is in there!
(drawing is approximate)
Sig
nal
30
First Order Delta-Sigma Modulator (6)
Noise Shaping
Modulator Output: TIME DOMAIN
Modulator Output: FREQUENCY DOMAIN
0
1
Believe it or not, the sine wave is in there!
(drawing is approximate)
QUANTIZATION
NOISE
Fs
SIGNAL
Sig
nal
31
Frequency FS
Third Order
Modulator
Second Order
Modulator
First Order
Modulator
Higher Order Delta-Sigma Modulators
32
Delta-Sigma A/D Signal Path
33
Delta Sigma
Modulator
Digital
Filter Decimator
Frequency FS
Modulator Noise Shaping and Digital Filter(1)
34
Modulator
Noise Shaping
Frequency FS
Modulator Noise Shaping and Digital Filter(2)
35
Modulator
Noise Shaping
Frequency FS
Modulator Noise Shaping and Digital Filter(3)
36
Filter set by
Oversampling
Ratio
Modulator
Noise Shaping
37
Digital Filter
• Digital filter architecture determines overall ADC response.
• Common filters: “Sinc” and “Flat Passband”
Sinc Filter Flat Passband Filter
38
Sinc Digital Filter
Sinc filter response
-100
-80
-60
-40
-20
0
0 1 2 3 4 5 6
Frequency (x Fdata)
Att
en
tua
tio
n, d
B
Sinc 1
Sinc 3
Sinc 5
• Typically used for DC measurements, or slow moving signals
Advantages
• Economical silicon area, easy to
implement
– Low cost
– Low power
• Low latency
• Filter notches can target specific
frequencies (ex. 50/60 Hz)
Disadvantages
• Pass band signal droop
• Weak Stop band attenuation for
low-order Sinc filters
Fdata
Sinc Digital Filter Settling
0 1 2 3 0 1 2 3
3 full cycles 3 full cycles
Valid data Valid data
Fdata periods
Analog Inputs
Settling time for an input step change, Sinc3 filter
Need n cycles to settle for a Sincn filter
4 cycles
Uncertainty of Analog Edge
4 Data Cycles
39
• Zero cycle Latency =
– Zero latency
– Single cycle conversion
– Single cycle settling
– No Latency
Analog IN
Data OUT
Single Cycle
Conversion
Data
Invalid
N+0 N+1 N+2 N+3 N-1
N+1 N+2
N+3 N+0
Delta Sigma: Zero Cycle Latency (1)
40
• Zero cycle Latency =
– Zero cycle latency
– Single cycle conversion
– Single cycle settling
– No Latency
Analog IN
Data OUT
Single Cycle
Conversion
Data
Invalid
N+0 N+1 N+2 N+3 N-1
N+1 N+2
N+3 N+0
Delta-Sigma: Zero Cycle Latency (2)
“Hidden Conversions”
41
42
Flat Pass Band Filter
Advantages
• Frequency Response
• Very low ripple pass band
• Sharp Nyquist transition band
• Large stopband attenuation: lower than
-100dB (simplify aliasing requirement)
• Frequency response scalable with master
clock
Disadvantages
• Large area – Costly
• Higher-order / high-tap filter – large latency
100dB stop band
Low Ripple Passband
43
Delta-Sigma: Flat Passband Digital Filter Settling
• The latency of the filter depends on the number of delay blocks used
• Flat Passband filters require a lot delay blocks to maintain desired AC response
• Many Delta-Sigma Converters incorporate filters with programmable settings: – Optimize for lower latency, power consumption or for AC performance/higher resolution
delay delay delay delay delay
Σ
Modulator Data Input
Digital Filter
Output
FIR filter block
topology
ΔΣ ADCs: Simplifying the Signal Chain (1)
CT
Passive Network + Protection
Passive Network + Protection +
R1
R2
In
OutADC Drive Circuitry
Iso
ADCProcessor
MUX
Sensor Signal
Conditioning
and
Protection
Gain Stage Mux ADC Drive ADC
MCU
44
ΔΣ ADCs: Simplifying the Signal Chain (2)
CT
Passive Network + Protection
Passive Network + Protection +
R1
R2
In
OutADC Drive Circuitry
Iso
ADCProcessor
MUX
Sensor Signal
Conditioning
and
Protection
Gain Stage Mux ADC Drive ADC
MCU
Delta-Sigma ADCs integrate many signal chain elements into one device 45
Delta-Sigma ADC’s
• Highest Resolution and High Stability with moderate power consumption
• Incorporate a Digital Filter
• Frequency Response, and Latency dependent on Digital Filter
• Typically Highly Integrated devices:
– Digital Filter, Buffer, PGA, MUX, Vref, Calibration/diagnostics
• Typically Requires Configuration of Registers
46
ΔΣ ADC
SAR ADCs
• Very Popular Topology
• Attractive in “Point in Time” or Multiplexed Measurements
• Advantages
– “no latency”
• input is sampled once
• “balancing” done internally
– good tradeoff between speed, resolution and power
• Speed: DC to 4MSPS
• Resolution: 8 to 18 bits; and moving towards higher resolutions
• TI Part Numbers:
– ADS7xxx
– ADS8xxx
SAR ADC
47
48
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