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Saravanakumar J and Suganya P 1

International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 3, July-2013.

High Resolution Satellite Image EnhancementUsing Transform Techniques

Saravanakumar J and Suganya P

Abstract: Nowadays satellite images are used in manyapplications such as geoscience studies, astronomy, geographicalinformation systems and defense monitoring. The majorproblem of these types of images is their resolution because theresolution of these images varies depends on the instrumentused and the altitude of the satellite's orbit. A new satelliteimage resolution enhancement technique has been proposedbased on the Wrapping technique of Discrete CurveletTransform (DCvT), which represents edges better thanwavelets. In this, an input image is transformed into frequencydomain by applying 2D FFT. The product of image and curveletin frequency domain is obtained and wrapped around theorigin. Finally, the DCvT coefficients are generated by applyingthe inverse 2D FFT to the wrapped data. The proposedtechnique is tested on satellite benchmark images. Thequantitative measures (peak signal-to-noise ratio, mean absoluteerror and mean square error) and visual results show thesuperiority of this technique over the other image resolutionenhancement techniques.

Index Terms- Curvelet Transform, Discrete wavelettransform (DWT), interpolation, Peak signal-to-noise ratio(PSNR), Satellite image resolution enhancement.

I. INTRODUCTION

In many image and video processing applications such asvideo resolution enhancement [8], facial feature extraction[4] [23], image fusion [5] [18] and satellite image resolutionenhancement [6] [9]. Resolution enhancement has alwaysbeen a major issue to extract more information from them.One of the commonly used techniques for image resolutionenhancement is Interpolation [8]. Interpolation in imageprocessing is a method to increase the number of pixels in adigital image. There are three interpolation techniques,nearest neighbour, bilinear, and bicubic. Nearest Neighbourresult in significant edge distortion. Bilinear Interpolationresults in smoother edges but somewhat blurred appearance.Bicubic interpolation is more sophisticated than the other twotechniques having fewer interpolation artifacts and producessmoother edges.

Saravanakumar J, Suganya P are with Dept. of EEE, K.S.R. College ofEngineering, Tiruchengode. Email: [email protected],[email protected]

The 2-D wavelet decomposition of an image is performedby applying the 1-D discrete wavelet transform (DWT) alongthe rows, and then the along the columns. This generates fourdecomposed sub band images [3] low-low (LL), low-high(LH), high-low (HL), and high-high (HH). Wavelet basedimage processing gives low resolution for images withvarying slopes. Wavelet Transform doesn’t handle curvesdiscontinuities well.

Curvelet transform [1] has been developed to overcomethe limitations of wavelet. Though wavelet transform hasbeen explored widely in various branches of imageprocessing, it fails in representing objects having randomlyoriented edges and curves as it is not good at representingline singularities. Curvelets uses only a small number ofcoefficients and handles curve discontinuities well. CurveletTransform can be decomposed with four steps SubbandDecomposition, Smooth Partitioning, Renormalization andRidgelet Analysis [2]. By inversing the step sequence withmathematic revising, it is able to reconstruct the originalimage which is called Inverse Curvelet Transform. FastDiscrete Curvelet transform (FDCT) provides differentfrequency components for analysis and synthesis of digitalimage in multi-resolution analysis. The proposed techniquehas been compared with standard interpolation techniques. Inthis, an input image is transformed into frequency domain byapplying 2D FFT. The product of image and curvelet infrequency domain is obtained and wrapped around the origin.Finally, the DCvT coefficients are generated by applying theinverse 2D FFT to the wrapped data.

II. INTERPOLATION TECHNIQUE

There are many methods available which are used forsatellite image resolution enhancement. In this paper,Wavelet Zero Padding (WZP) [20] [21] and theninterpolation techniques are used for comparison purposes.Interpolation is used to estimate the continuous functionvalues from discrete samples [14] [15]. Interpolation includesmany image processing applications such as imagedecompression, image magnification or reduction, sub-pixelimage registration, image resolution enhancement [7] [11][17] and to correct spatial distortions.

A. Bilinear Interpolation



Bilinear Interpolation determines the grey level value ofthe specified input coordinates from the average of fourclosest pixels and assigns that value to the outputcoordinates. Initially, two linear interpolations are performedin one direction (horizontally) and then another linearinterpolation is performed in the perpendicular direction(vertically). The number of grid points needed to evaluate theinterpolation function for one-dimensional LinearInterpolation, is two and for Bilinear Interpolation (linearinterpolation in two dimensions), it is four. BilinearInterpolation produces an image of smoother appearance thannearest neighbour interpolation, but the grey levels arealtered in the process, results in blurred images.

B. Bicubic interpolation

Bicubic interpolation is sophisticated and producessmoother edges than bilinear interpolation. Thecomputational time of bicubic interpolation is more. A newpixel is a bicubic function of 16 pixels in the nearest 4 x 4neighborhood of the pixel in the original image The image isslightly sharper than that produced by Bilinear Interpolation,and it does not have the disordered appearance produced inNearest Neighbour Interpolation. First, four one-dimensioncubic convolutions are performed in one direction and thenone more one-dimension cubic convolution is performed inthe perpendicular direction. Thus to implement a two-dimension cubic convolution, a one-dimension cubicconvolution is needed.

III. IMAGE RESOLUTION ENHANCEMENTUSING TRANSFORMS

.Resolution is an important parameter in satellite image

processing. Resolution enhancement is used to enlarge theinput image in a way to make the output image looks sharper.Thus, increasing the resolution of an image affects the systemperformance. In image resolution enhancement byinterpolation techniques, the main loss is in high frequencycomponents (edges) which is due to the smoothing caused byinterpolation. Thus, preserving the edges is necessary toincrease the quality of an image. In this paper, DWT [11][14] [16] is used to preserve the high-frequency componentsof the image.

DWT separates the image into different subband images.First by using horizontal filters to obtain L and H subbands,and then by using vertical filters LL, LH, HL, and HH. Highfrequency subbands contains the high frequency componentof the image. Bicubic interpolation is applied to these foursubband images. The low resolution image is obtained bylow-pass filtering of the high resolution image as in [19],[20] and [21]. The low resolution image (LL subband) isused as the input for the proposed resolution enhancementprocess. The low frequency subband image contains less

information than the original input image. Thus, the lowresolution input image is interpolated with half of theinterpolation factor.

To obtain a sharper enhanced image [22], an intermediatestage is proposed in high frequency subband interpolationprocess. The low resolution input satellite image and theinterpolated LL image with factor 2 are highly associated.The difference between the LL subband image and the lowresolution input image are in their high frequencycomponents. Hence, this difference image is used as anintermediate process to correct the estimated high frequencysubbands. The estimation process is performed byinterpolating high frequency subbands by factor 2 with thedifference image (which is high-frequency components onlow-resolution input image) into the estimated high-frequency images, then another interpolation with factor α/2is performed in order to reach the required size for IDWTprocess.

Similarly, LL subband image is used as input for thesecond level. The horizontal and vertical filters are used toobtain the LLLL subband image. The estimated highfrequency subbands from the first level is used to obtain thesharper image by adding the difference image obtainedbetween the LLLL subband image and the low resolutioninput image. The resultant image obtained is much sharperthan the first level.

The curvelet approach of image enhancement is describedas follow: First, apply the curvelet transform to the image.Then according to noise ratio of each subband, enforcesectional nonlinear enhancement to the coefficients. At last,apply the Inverse Curvelet Transform to the coefficients andcome out the image with image enhancement on edge.

V. RESULTS AND DISCUSSIONS

The simulation tool used for processing satellite image isMATLAB and tested on different satellite benchmark imagescollected from satellite imaging corporation and GEOEYE.In order to show the superiority of the proposed method overthe wavelet zero padding, interpolation techniques and DWTfrom visual point of view Figures. 1-2 are included. In thosefigures with low-resolution satellite images, the enhancedimages by using bilinear interpolation, bicubic interpolation,enhanced images by using WZP, enhanced images usingDWT and also the enhanced images obtained by theproposed are shown. Figure 1 is Kutztown University inPennsylvania with resolution 258 X 195 taken by GeoEye-1satellite. Fig 2 is Washington DC image with resolution 256X 256.



(a) (b)

(c) (d)

(e) (f)

Figure 1 original image, (b) bilinear interpolation, (c) bicubic interpolation, (d) WZP output, (e) DWT, (f) DCvT.



(a)

(c)

(b)

(d)

(e) (f)

Figure 2 original image, (b) bilinear interpolation, (c) bicubic interpolation, (d) WZP output, (e) DWT, (f) DCvT.

From above figures, it is evident that the bilinearinterpolation results in blurred appearance and bicubicinterpolation produce an image slightly sharper than bilinear

interpolation. In WZP discontinuities are artificially createdat the borders. The Discrete Wavelet Transform basedscheme generates artifacts due to a DWT shift-variant



property. It is clear that the image, enhanced by using theproposed technique is sharper than the other techniques.Normally, the processed images are looking similar.However, when the image is enlarged, the losses in the imageare obvious, and it will look blocky.

Visual comparisons as well as quantitative comparisonsare confirming the superiority of the proposed method. Peaksignal-to-noise ratio (PSNR) and Mean Square Error (MSE)are calculated to obtain quantitative results for comparison.PSNR can be obtained by using the following formula [12]

2

1 0RP S N R = 1 0 l o g ( )

M S Ewhere R is the maximum fluctuation in the input image.

The higher the PSNR, the better the quality of thereconstructed image. An improvement in the PSNRmagnitude will increase the visual appearance of the image.

The mean square error (MSE) is the MSE between originaland reconstructed image defined as

M-1 N-12

m=0 n=0

(x(m,n)-y(m,1

MSE=M

)N

n)where x (m, n) and y(m, n) represent the original image

and the reconstructed image respectively. The lower thevalue of MSE, the lower the error present in the image.

Table 1 Comparison of PSNR (dB) values

METHODPSNR (dB)

Fig 1 Fig 2

Bilinear 27. 4835 19.4766

Bicubic 31.1228 24.9384

WZP 28.1503 23.3906

DWT 33.5867 33.8008

Proposed Method 35.8503 35.3802

Table 1 is showing the comparison of PSNR (dB) betweenthe proposed method with bilinear, bicubic interpolation,WZP and DWT. Improved PSNR values in Table 1 showsproposed method is improved in quality.

Table 2 is showing the Entropy values. In order to showthe improvement obtained by the proposed satellite imageresolution enhancement from information content point ofview, the entropy of the images are calculated. As expected,highest level of information content is embedded in theoriginal images. Compared to other techniques DCvT hashigher quality of images.

Table 2 Entropy comparison

METHOD / IMAGEENTROPY

Fig 1 Fig 2

Low resolution satelliteimage (8-bit unsigned) 3.1165 5.6022

Original image 7.7368 7.3151

DWT Method 7.5607 6.4708

DCvT Method 7.6913 7.2942

Table 3 is showing the comparison of MSE and MAEbetween the proposed method using Daubechies (db.9)wavelet transform with bilinear and bicubic interpolation bymeans of MSE and MAE

Table 3 comparison of MSE and MAE

METHODMSE MAE

Fig 1 Fig 2 Fig 1 Fig 2

Bilinear 0.5225 0.1068 0.718 0.1262

Bicubic 0.5014 0.0293 0.694 0.0662

DWT 0.0368 0.0197 0.412 0.0364

DCvT 0.0298 0.0034 0.376 0.0249

. The improved MSE and MAE value in Table 3 shows theproposed method has good quality images.

V.CONCLUSION

This paper discusses about improvement in the resolutionof satellite images based on the discrete curvelet transform(DCvT). In this, an input image is transformed intofrequency domain by applying 2D FFT. The product ofimage and curvelet in frequency domain is obtained andwrapped around the origin. Finally, the DCvT coefficientsare generated by applying the inverse 2D FFT to the wrappeddata. In DWT, an image is decomposed into differentsubband images. The input low-resolution image and high-frequency subband images are interpolated by bicubicinterpolation. The input image is interpolated with half of theinterpolation factor used for interpolation of the high-frequency subband images. Then, all these images arecombined using IDWT to generate a more enhanced image.The quantitative metrics (PSNR, MSE, MAE and entropy) ofthe image calculated shows the superiority of this technique.



The results based on PSNR values show that the proposedmethod, in comparison with the interpolation techniques, andDWT show improvement in quality.

REFERENCES

[1] AlZubi, S., Islam, N. and Abbod, M. “Multiresolution AnalysisUsing Wavelet, Ridgelet, and Curvelet Transforms for MedicalImage Segmentation,” in Inter Journal of Biomedical Imaging,May, 2011, pp. 1-18.Ayman, M. T. “Color Restoration of OldPhotos Using the Curvelet Transform,” in IEEE Trans ImageProc, vol. 11, no. 6, pp. 147-153, Dec 2012.

[2] Celik, T. and Tjahjadi, T. “Image Resolution Enhancement UsingDual-Tree Complex Wavelet Transform,” in IEEE Geosci.Remote Sens. Lett.,Vol. 7, NO. 3, July 2010. pp. 554-557.

[3] Celik, T., Direkoglu, C., Ozkaramanli, H., Demirel, H. andUyguroglu, M. “Region-based super-resolution aided facialfeature extraction from low resolution video sequences,” in Proc.IEEE ICASSP, Philadelphia, PA, Mar. 2005, vol. II, pp. 789–792.

[4] Choi, J., Kiyun Yu, K. and Yongil Kim, Y. “A New AdaptiveComponent- Substitution-Based Satellite Image Fusion by UsingPartial Replacement,” in IEEE Trans. Geosci. Remote Sens., Vol.49, no. 1, Jan 2011, pp. 295-309.

[5] Demirel, H. and Anbarjafari, G. “Discrete Wavelet Transform-Based Satellite Image Resolution Enhancement,” in IEEE Trans.Geosci. Remote Sens., Vol. 49, no. 6, June 2011, pp. 1997–2004.

[6] Demirel, H. and Anbarjafari, G. “IMAGE ResolutionEnhancement by Using Discrete and Stationary WaveletDecomposition” IEEE Trans. Image Process., VOL. 20, NO. 5,May 2011, pp. 1458-1460.

[7] Demirel, H. and Anbarjafari, G. “Image super resolution based oninterpolation of wavelet domain high frequency subbands and thespatial domain input image,” ETRI J., vol. 32, no. 3, pp. 390–394,Jun. 2010. pp. 390-394.

[8] Demirel, H. and Anbarjafari, G. “Satellite image resolutionenhancement using complex wavelet transform,” IEEE Geosci.Remote Sens. Lett., vol. 7, no. 1, pp. 123–126, Jan. 2010.

[9] Demirel, H., Anbarjafari, G. and Izadpanahi, S. “Improvedmotion-based localized super resolution technique using discretewavelet transform for low resolution video enhancement,” inProc. 17th EUSIPCO, Edinburgh, U.K., Aug. 2009, pp. 1097–1101.

[10] Gambardella, A. and Migliaccio, M. “On the super resolution ofmicrowave scanning radiometer measurements,” IEEE Geosci.Remote Sens. Lett., vol. 5, no. 4, pp. 796–800, Oct. 2008.

[11] Gonzalez, R. C. and Woods, R. E. Digital Image Processing.Englewood Cliffs, NJ: Prentice-Hall, 2007.

[12] Kim, S., Kang, W., Lee, E. and Paik, J. “Wavelet-Domain ColorImage Enhancement Using Filtered Directional Bases andFrequency-Adaptive Shrinkage,” in IEEE Trans ConsumerElectronics, Vol. 56, No. 2, May 2010 pp. 1063-1069.

[13] Kinebuchi, k , Muresan, D. D. and Parks, T.W. “Imageinterpolation using wavelet based hidden Markov trees,” in Proc.IEEE ICASSP, 2001, vol. 3, pp. 7–11.

[14] Li , X. and Orchard, M. T. “New edge-directed interpolation,”IEEE Trans. Image Process., vol. 10, no. 10, pp. 1521–1527, Oct.2001.

[15] Ozcinar, C., Demirel, H. and Anbarjafari, G. “Satellite ImageContrast Enhancement Using Discrete Wavelet Transform andSingular Value Decomposition,” in IEEE Geosci. Remote Sens.Lett., Vol. 7, no. 2, April 2010. pp. 333-337.

[16] Piao, Y., Shin, L. and Park, H. W. “Image resolutionenhancement using inter-subband correlation in wavelet domain,”in Proc. IEEE ICIP, 2007, vol. 1, pp. 445–448.

[17] Ray, L.A., and Adhami, R. R. “Dual tree discrete wavelettransform with application to image fusion,” in Proc. 38th Southeastern Symp. Syst. Theory, Mar. 5–7, 2006, pp. 430– 433.

[18] Temizel, A. “Image resolution enhancement using waveletdomain hidden Markov tree and coefficient sign estimation,” inProc. ICIP, 2007, vol. 5, pp. 381–384.

[19] Temizel, A. and Vlachos, T. “Wavelet Domain Image ResolutionEnhancement Using Cycle Spinning and Edge Modelling,” IEEEGeosci. Remote Sens. Lett., Vol. 7, no. 5, Feb 2006, pp 796-799.

[20] Temizel, A. and Vlachos, T. “Wavelet domain image resolutionenhancement using cycle-spinning,” Electron. Lett., vol. 41, no. 3,pp. 119–121, Feb. 3, 2005.

[21] Tolpekin, V. and Stein, A. “Quantification of the effects of land-cover class spectral separability on the accuracy of Markov-random-field-based super resolution mapping,” IEEE Trans.Geosci. Remote Sens., vol. 47, no. 9, pp. 3283–3297, Sep. 2009.

[22] Yi-bo, L., Hong, X. and Sen-yue, Z. “The wrinkle generationmethod for facial reconstruction based on extraction of partitionwrinkle line features and fractal interpolation,” in Proc. 4th ICIG,Aug. 22–24, 2007, pp. 933–937.

Saravanakumar pursing Master of Engineering in AppliedElectronics at K.S.R College of Engineering. He presented a paperin an International conference at Muthayammal EngineeringCollege. His research interests include image processing.

Suganya has 13 years experience in teaching and research. She iscurrently doing her PhD. Her research interests include powersystems.

Karthikeyan T and Vinothkumar S 7


Automatic Indian Vehicle License PlateRecognition

Karthikeyan T and Vinothkumar S

ABSTRACT: Automatic Vehicle License PlateRecognition has many applications in traffic systems(highway electronic toll collection, redlight violationenforcement, border and customs checkpoints, etc.Inthis project, a smart and simple algorithm is presentedfor vehicle’s license plate recognition system. Theproposed algorithm consists of Four major parts: ImagePre Processing &Integral Edge Image, License PlateLocalization, segmentation of the characters, recognitionof the characters.

Keywords—Character recognizer, license platerecognition, plateregion extraction, segmentation,smearing, template matching, Matlab

1.INTRODUCTION

The License Plate Recognition (LPR) system is anintegrated hardware and software device, which has theability to detect and read the characters from the licenseplate and convert it into electronic text like ASCIIcharacters. Research has shown that majority of crimes inUnited States are related to vehicles. Thus, the ability ofLPR system to automate the process of identifying vehiclesof interest has revolutionized law enforcement and hasimproved public security. The input to the LPR system is adigital image of the front or the rear end of the vehicle'slicense plate, taken by the sophisticated cameras. Furtherprocessing on this image is carried out for the purpose oflicense plate detection. After the plate information isextracted from the image, it is further segmented to locateindividual characters. There are several methods available inthe market used for recognizing the characters on the platei.e., Character recognition using Feed Forward NeuralNetwork, Template matching, etc. Each segmentedcharacters are identified using one of these algorithms andconverted into electronic data. This data can be used invarious safety and traffic applications like tolling, lawenforcement, and thus useful in fighting crime and fraudthereby improving public safety.

Karthikeyan T , , Assistant Professor, Deptof ECE. Aksheyaa College ofEngineering, Puludivakkam, Kancheepuram, [email protected] S, Associate Professor, Deptof ECE.Aksheyaa College ofEngineering, Puludivakkam, Kancheepuram,[email protected]

Automatic License Plate recognition is one of thetechniques used for vehicle identification purposes. The soleintention of this project is to find the most efficient way torecognize the registration information from the digital image(obtained from the camera). This process usually comprisesof three steps. The proposed algorithm consists of fourmajor parts: Image Pre Processing &Integral Edge Image,License Plate Localization, segmentation of the characters,recognition of the characters. Thus, this project uncovers thefundamental idea of various algorithms required toaccomplish character recognition from the license plateduring Template Matching.

2. PROPOSED SYSTEM

Inthis project, a smart and simple algorithm is presented forvehicle’s license plate recognition system. The proposedalgorithm consists of Four major parts: Image PreProcessing &Integral Edge Image, License PlateLocalization, segmentation of the characters, recognition ofthe characters.

2.1 PRE PROCESSING & INTEGRALEDGE IMAGE

Images are acquire Image can be input to the system bydifferent methods by analog camera, or by digital cameras.The algorithm described here is independent of the type ofcolors in image and relies mainly on the gray level of animage for processing and extracting the requiredinformation. Color components like Red, Green and Bluevalue are not used throughout this algorithm. So, if the inputimage is a colored image represented by 3-dimensionalarray in MATLAB, it is converted to a 2-dimensional grayimage before further processing. The sample of originalinput image and a gray image is shown below:

Fig1.a Original Image Fig.1a Grayscale



License plate can be detected as an area containing rich edgeand textural information. To exploit this property the Sobeloperator for vertical edge detection is used after convertingthe gray image.Experiments show that by detecting onlyvertical edges an accuracy of detection can be improved.Horizontal edges preserve minor edge information in theplate area. On the other hand there are a lot of horizontaledges in the background making the

detection process is less effective. Vertical edge map isbinarized using adaptive threshold based on mean value andstandard deviation of pixel neighborhood. Finally, integraledge image I1 is computed using Matlab7.Highlight DesiredDetails such as Plate Details and vertical edge in theimage.HDD performs AND-AND operation for each twocorresponding pixel values taken from both Verticalresponse and threshold images. The AND-AND procedurefor this process is illustrated in Fig. 2.This scanning processwill start moving from left to right and from top to bottom.After all pixels are scanned, the regions in which the correctLP exists are highlighted as shown in Fig. 3.

Fig2. AND - AND Gate Logic

Fig.3 Highlighted Desired Area

2.2 LICENSE PLATELOCALIZATION

Histogram is a graph representing the values of avariable quantity over a given range. In this Number PlateDetection algorithm, the writer has used horizontal andvertical histogram, which represents the column-wise androw-wise histogram respectively. These histogramsrepresent the sum of differences of gray values betweenneighboring pixels of an image, column-wise and row-wise.In the above step, first the horizontal histogram is

calculated. To find a horizontal histogram, the algorithmtraverses through each column of an image. In each column,the algorithm starts with the second pixel from the top. Thedifference between second and first pixel is calculated. If thedifference exceeds certain threshold, it is added to total sumof differences. Then, algorithm will move downwards tocalculate the difference between the third and second pixels.So on, it moves until the end of a column and calculate thetotal sum of differences between neighboring pixels. At theend, an array containing the column-wise sum is created.The same process is carried out to find the verticalhistogram. In this case, rows are processed instead ofcolumns. Referring to the figures shown below, one can seethat the histogram values changes drastically betweenconsecutive columns and rows. Therefore, to prevent loss ofimportant information in upcoming steps, it is advisable tosmooth out such drastic changes in values of histogram. Forthe same, the histogram is passed through a low-pass digitalfilter. While p performing this step, each histogram value isaveraged out considering the values on it right-hand sideand left-hand side. This step is performed on both thehorizontal histogram as well as the vertical histogram.Below are the figures showing the histogram before passingthrough a low-pass digital filter and after passing through alow-pass digital filter.

Fig 5 Horizontal edge processing histogram

Fig.4 Vertical edge processinghistogram

Once the histograms are passed through a low-passdigital filter, a filter is applied to remove unwanted areasfrom an image. In this case, the unwanted areas are the rowsand columns with low histogram values. A low histogram



value indicates that the part of image contains very littlevariations among neighboring pixels. Since a region with alicense plate contains a plain background with alphanumericcharacters in it, the difference in the neighboring pixels,especially at the edges of characters and number plate, willbe very high. This results in a high histogram value for suchpart of an image. Therefore, a region with probable licenseplate has a high horizontal and vertical histogram values.Areas with less value are thus not required anymore. Suchareas are removed from an image by applying a dynamicthreshold.

In this algorithm, the dynamic threshold is equal tothe average value of a histogram. Both horizontal andvertical histograms are passed through a filter with thisdynamic threshold. The output of this process is histogramshowing regions having high probability of containing anumber plate. The filtered histograms are shown below: Thenext step is to find all the regions in an image that has highprobability of containing a license plate. Co-ordinates of allsuch probable regions are stored in an array. The outputimage displaying the probable license plate regions is shownbelow.

Fig.7Probable License Plate

The output of segmentation process is all theregions that have maximum probability of containing alicense plate. Out of these regions, the one with themaximum histogram value is considered as the mostprobable candidate for number plate. All the regions areprocessed row-wise and column-wise to find a commonregion having maximum horizontal and vertical histogramvalue. This is the region having highest probability ofcontaining a license plate. The image detected license plateis shown below:.

Fig.7a Extracted Plate Fig7.b Detected Plate

2.3 SEGMENTATIONIn the segmentation of plate characters, license

plate is segmented into its constituent parts obtainingthecharacters individually. Firstly, image is filtered forenhancing the image and removing the noises and unwantedspots. Then dilation operation is applied to the image forseparating the characters from each other if the characters

are close to each other. After this operation, horizontal andvertical smearing are applied forfinding the characterregions. The next step is to cut the plate characters. It isdone by finding starting and end points of characters inhorizontal direction.The result of this segmentation is inFigure.

Fig.8 Segmented Characters2.4 CHARACTER RECOGNITION

Before recognition algorithm, the characters arenormalized. Normalization is to refine the characters into ablock containing no extra white spaces (pixels) in all thefour sides of the characters. Then each character is fit toequal size. Fitting approach is necessary for templatematching. For matching the characters with the database,input images must be equal-sized with the databasecharacters. Here the characters are fit to 36 ×18. Theextracted characters cut from plate and the characters ondatabase are now equal-sized. The next step is templatematching. Template matching is an effective algorithm forrecognition of characters. The character image is comparedwith the ones in the database and the best similarity ismeasured.

3. EXPERIMENTAL RESULTS

Experiments have been performed to test the proposedsystem and to measure the accuracy of the system. Thesystem is designed in Matlab 7 for recognition of Indianlicense plates. The images for the input to the system arecolored images with various sizes. The test images weretaken under various illumination conditions. The results ofthe tests are given by Table I.

4. CONCLUSIONIn this paper, we presented application software designedfor the recognition of car license plate. Firstly we extractedthe plate location, then we separated the plate charactersindividually by segmentation and finally applied templatematching with the use of correlation for recognition of platecharacters. This system is designed for the identificationIndian license plates and the system is tested over a largenumber of images. Finally it is proved to be 83% for the

Units of LPRSystem

Number ofAccuracy

Percentage ofAccuracy

Extraction ofPlateRegion

10/12 83%

Segmentation 10/12 83%

Recognition ofCharacters

9/12 75%



extraction of plate region, 83% for the segmentation of thecharactersand 75% for the recognition unit accurate, givingthe overall system performance 80% recognition rates.

REFERENCES[1] Peter Tarabek, “Fast License Plate Detection based on

Edge density and Integral Edge Image”, 10th

International IEEE Jubilee International Symposiumon Applied Machine Intelligence and Information,January 2012

[2] Rob.G.J. Wijnhoven and Peter H.N. de With “IdentifyVerification using Computer Vision for AutomaticGarage Door Opening”, IEEE Transactions onconsumer Electronics vol 57, No.2, May 2011

[3] Hinde ANOUAL, Sanna EL FKIHI, AbdellilahJILBAB, Driss ABOUTAJDINE “Vehicle LicensePlate Detection in Images”,International ConferenceonMultimedia Computing and Systems (ICMCS),2011

[4] A.W. G. C.D Wijetunge and D.A.A.C.Ratnaweera“Real Time Recognition of License Plates of MovingVehicles in Sri Lanka” 2011 6th InternationalConference on Industrial and information Systems,ICIIS 2011, 2011.

[5] Jianyu Zhao, Shujian Ma, WeiminHan , Yang Yangand Xudong Wang “Research and Implementation ofLicense Plate Recognition” ,Control and DecisionConference (CCDC), 2012

[6] ZuwenaMusoromy, Dr.SoodamaniRamalingama ndNicoBekooy “Edge Detection Comparison for LicensePlate Detection” , 11thInt.Conf.Control,Automation,Robotics and Vision, 2010

[7] XiaojunZhai ,FaycalBenssali andSoodamaniRamalingam “License Plate Localisationbased on Morphological Operations” 11thInt.Conf.Control, Automation, Robotics and Vision, 2010

[8] Otsu N. “A Threshold Selection Method for GrayLevel Histograms” IEEE Transactions on System ,Man and Cybernetics , Vol.9, no. 1, PP 62-66, January1979.

Mr.T.Karthikeyan, has completed hisMasters Degree in Elec tronics andcommunications Engineering, , currentlyworking as Assistant Professor in AksheyaaCollege of Engineering,puludivakkam,kancheepuram, Affiliated to AnnaUniversity.He published many papers andjournals both national and international.His

areas of interest in image processing, matlab,digital signalprocessing etc:-.

Mr.Vinoth Kumar.S Has completed hisMasters Degree in Communi cationsystems, undergoing Research scholar inSathyabama university. He is currentlyworking as Associate Professor & Head ofthe Department in Aksheyaa College ofEngineering, puludivakkam,

Kancheepuram, Affiliated to Anna University. His areas ofinterest are Network protocols, IPV4, IPV6, imageprocessing, VOIP, network security, wirelesscommunication. He got certified in MCP, MCSA, Novell,A+, N+, RHCE, ITIL, remote management tools. He is alsocertified in MISSION 10X from WIPRO and ANNAUNIVERSITY. He published many research journals inboth national and international publications.

R. Dinesh kumar and P. Karuppusamy 11


Performance Analysis of Soft Switched SevenLevel Inverter for Photovoltaic System

R.Dinesh kumar and P.Karuppusamy

Abstract — The PV power generation have low efficiency dueto the various constrains. This thesis gives a proposed methodto reduce the THD using soft switching technique. The PV cellis connected to Multi-Level Inverter (MLI).In order to improvethe efficiency. The project proposes an advanced H-bridgemultilevel inverter which varies from the conventional onefrom the number of power devices used. The proposed sevenlevel multilevel inverter has minimum number of powerdevices compare than conventional. MLI have emerged asattractive high power medium voltage converter to the reduceharmonic component in the output current due to filter. Anovel PWM technique is used to generate the PWM signal forinverter switch and to reduce the THD level using softswitching technique.

Keywords — MLI , PWM, PV Array, soft switching, Totalharmonic distortion.

I. INTRODUCTION

The demand for renewable energy has increasedsignificantly over the years because of shortage of fossilfuels and the greenhouse effect. The different types ofrenewable sources such as solar and wind energy arenowadays popular and also it is more demand due toadvancement in power electronics techniques [1]. Photo-Voltaic (PV) sources are used today in many applications asthey have the advantages of being maintenance and it is freefrom pollution. The demand for solar-electric energy isincreased consistently by 20%–25% per annum over the last20 years, which is mainly because of reducing costs. Thisdecline has been driven by the following factors: 1) anincreasing efficiency of solar cells 2) manufacturingtechnology improvements and 3) economics of scale.[2]

Multilevel inverter is the heart of a Photovoltaic system.The DC power which is obtained from PV modules areconverted into AC power with the help of multilevelinverter, then it is fed into the grid.

R.Dinesh kumar is a PG scholar in the Deparment of EEE, BannariAmman Institute of Technology, Erode India.Email: [email protected].

R.Karuppusamy is a Assistant professor in the Deparment of EEE,Bannari Amman Institute of Technology,Erode India.

The harmonic content is reduced by improving the outputwaveform of the inverter, hence, the size of the filter usedand the level of electromagnetic interference (EMI)generated by switching operation of the inverter. In therecent years, multilevel inverters have become more popularfor researchers and manufacturers due to their advantagesover conventional three-level inverters [5] ,They offerimproved output waveforms, smaller filter size, lower EMIand lower total harmonic distortion (THD).

II. PROPOSED SCHEME

Fig 1 . Proposed topology

The proposed single-phase seven-level inverter wasdeveloped from the five-level inverter. It comprises a single-phase the modified H-bridge topology is significantlyadvantages over other topologies, such as less power switch,power diodes, and less capacitors for inverters of the samenumber of levels. Photovoltaic (PV) arrays were connectedto the inverter and the output of inverter applied to the load.Proper switching of the inverter can produce seven output-voltage levels (Vdc, 2Vdc, 3Vdc,0 ,-Vdc,-2Vdc,-3Vdc)from the dc supply Voltage.



Table 1.Comparison table for proposed topology

Compared with the best of the other configurations,it requires only six controlled switches instead of the thirtysix required by the other configurations (83% reduction),only twelve diodes instead of the thirty six required by thecapacitor clamped or the asymmetric cascade configurations(66% reduction), and only three capacitors instead of thenine required by the asymmetric cascade configuration(66% reduction). In the other hand, the proposedconfiguration is at a disadvantage when the required voltageratings are compared: in the new configuration the mainpower switches are required to block one half of the mainsupply voltage and the auxiliary switches one third the mainsupply voltage, as opposed to 1/7 of the main supply voltagein the other configurations.

Table 2.Inverter output voltage during various switchingconditions

III. MODELING OF THE SOLAR CELL

The diode in parallel with current source is simplestequivalent circuit of a solar cell. The light falling on the cellwhich is equal to output of the current source. At the time ofdarkness the solar cell works as a diode. It does not producecurrent and voltage. Then it is connected to an externalsource (large voltage) it generates a current ID, called diode

(D) current or dark current. The diode determines the I-Vcharacteristics of the cell.

Fig 2 .Circuit diagram of the PV model

Increasing sophistication, accuracy and complexity can beintroduced to the model by adding in turn Temperaturedependence of the diode saturation current I0. Temperaturedependence of the photo current IL. Series resistance R s s,which gives a exact shape between the open circuit voltageand maximum power point. At the time of current flow thereis some internal losses. The diode parallel with the shuntresistance Rsh this corresponds to the leakage current to theground and it is commonly neglected. Either allowing thediode quality factor n to become a variable parameter(instead of being fixed at either 1 or 2) or introducing twoparallel diodes with independently set saturation currents.The output current (I) from the PV cell is found by applyingthe Kirchoff’s current law (KCL) on the equivalent circuitis shown.

I=I -Isc d (1)The photon generated current is equal to the short circuitcurrent Isc and Id is the current shunted through the intrinsicdiode.From shockley’s diode equation the diode current Id is givenbelow:

qV /KTdI =I (e -1)d o (2)

Where: Io is the reverse saturation current of diode (A), q isthe electron charge (1.602×10-19 C), Vd is the voltageacross the diode (V), k is the Boltzmann’s constant(1.381×10-23 J/K), T is the junction temperature in Kelvin(K).Replacing Id of the equation (3) by the equation (4) givesthe current-voltage relationship of the PV cell [5].

qV /KTdI =I (e -1)d o (3)

V represents voltage across the Photo voltaic cell, and I isthe output current from the cell.The reverse saturation current of diode (Io) is constant underthe constant temperature and found by setting the open-



circuit condition as shown. Using the equation (5), let I = 0(no output current) and solve for Io.

qV /KTdI =I (e -1)sc o (4)

qV /KTdI =I (e -1)sc o (5)

q V / KTdI = I / (e -1)o sc (6)

To a very good approximation, Isc Which is equal to photongenerated current is directly proportional to the irradiance,the intensity of illumination of Photo voltaic cell; From thedata sheet Isc value is taken, under the standard testcondition, Go=1000W/m2 at the air mass (AM) = 1.5, thenthe photon generated current at any other irradiance, G(W/m2), is given by [5,11]:

Isc Isc 00

GG GG

(7)

The PV cell output is both limited by the cell current and thecell voltage, and it can only produce a power with anycombinations of current and voltage on the I-V curve. It alsoshows that the cell current is proportional to the irradiance.

Then the VI relationship of Photo voltaic cell is writtenas:

q

o

V+IR

I = I I (e -1)-sc

snKT V IRs

Rp

(8)

Since it does not include the effect of parallel resistance(Rp), letting Rp =∞ in the equation (10) gives the equation(11) that describes the current-voltage relationship of the PVcell, and it is shown in equation 9.

o

V+IRq

I=I I (e -1)sc

snKT

(9)

Where: I is the cell current (the same as the module current),V is the cell voltage = {module voltage} ÷ {# of cells inseries},T is the cell temperature in Kelvin (K).

IV. NEW PWM MODULATION

Different types of pulse width modulationtechniques are possible for multilevel inverters (MLI). This

paper uses multi-level triangular wave’s generation asderived in. It can be a useful solution for pulse generationfor this topology. This technique in is called carrierredistribution (CR) technique. This technique is derivedfrom the triangular carrier and has individually the lowestswitching frequency among the multi-level PWM methods.

V. CONTROL ALGORITHM

The proposed inverter utilizes the Incrementalconductance algorithm. Incremental conductance (IC) isgood for conditions of rapidly varying irradiance. However,noise may cause continuous searching so some amount ofnoise reduction may be needed. The incrementalconductance algorithm is based on the fact that the slope ofthe curve power vs. voltage (current) of the PV module iszero at the MPP, positive (negative) on the left of it andnegative (positive) on the right.• ΔV/ΔP = 0(ΔI/ΔP = 0) at the MPP• ΔV/ΔP > 0(ΔI/ΔP < 0) on the left• ΔV/ΔP < 0(ΔI/ΔP > 0) on the right

The output of the MPPT is the duty-cycle function. As thedc-link voltage Vdc was controlled in the dc–ac seven levelPulse Width Modulation inverter, the change of the dutycycle, it will changes the voltage at the output of the PhotoVoltaic panels.

VI. SOFT SWITCHING TECHNIQUE

The multilevel inverter to increasing the levels toreduce the ripples and get better output voltage and withoutincreasing the levels to reduce the THD level that is solutionfor the proposed system. To using the soft switchingtechnique reduced the THD. Turn ON and Turn OFF theswitches at time of zero crossing .and ZVS (zero voltageswitching) and ZCS (zero current switching) these are sometypes of soft switching on that to use ZVS RSI ( zerovoltage switching resonant snubber inverter)soft switchingto reduce the harmonic content of the system

VII. SIMULATION RESULTS

Generally, it is important that the harmoniccomponents of output voltage produced by inverter itselfshould be reduced to alleviate the output current ripple andthe core loss of inductor. For this purpose, simulations areperformed in advance to prove availability of the proposedsingle-phase seven-level PWM inverter. The PWMswitching patterns were generated by comparing threereference signals (Vref1, Vref2, and Vref3) against atriangular carrier signal (see Fig. 2) One leg of the inverteroperated at a high switching rate that was equivalent to thefrequency of the carrier signal, while the other leg operatedat the rate of the fundamental frequency(i.e., 50 Hz).Switches S5 and S6 also operated at the rate of the carriersignal. Fig. 13 shows the simulation result of inverter outputvoltage Vinv.



Fig 3. A Single Phase Version of the Proposed SoftSwitched Inverter

Fig 4.Pulse generation

Fig 5 . Input voltage for proposed system

Fig 6. PWM signal for S1 and S4

Fig 7. PWM signal for S2 and S3

Fig 8. PWM signal for S5




Fig 12 . Simulation result of 7-level Multilevelinverter Output current

Fig 13.Simulation result of 7- Level Multilevel inverteroutput voltage



Fig 14. Voltage THD of 7-level multilevelinverter with soft switching technique

Fig 15. Current THD of 7-level multilevel inverterwith soft switching technique

The THD measurement of the waveform corresponds toseven-level inverter shown and to apply the soft switchingtechnique to reduce the THD level of the system

VIII. EXPERIMENTAL RESULTS

This chapter describe about hardware description of sevenlevel multilevel inverter for PV application .which chapterconsist of controller circuit ,driver circuit, circuit ,invertercircuit ,Soft switching Solar energy is observed by the PVcell. The output of the PV cell is given to multilevelinverter. And soft switching technique also applied to themultilevel inverter. Soft switching to reducing the switchinglosses so THD level will be reduced. The output of the PVcell and soft switching are given to multilevel inverterwhich converts DC to AC. PWM pulses are generated byusing PIC18f4331and it is given to inverter switches.

Fig.16.Hardware Block Diagram for seven levelinverter

Fig17.Experimental prototype of soft switching multilevelinverter

Fig18.Output voltage of soft switching multilevel inverter



Fig19.THD level for Hardware setup

IX. CONCLUSION

This paper has covered conversion of photovoltaicdc voltage to ac voltage by implementing a novel multilevelinverter. A novel PWM technique is used here. The PWMswitching signals are generated by comparing one referencesignal against six triangular wave signals. The proposedmultilevel inverter is to reduce both voltage & current THDof the inverter using soft switching technique .The proposedtopology has minimum number of switches compare thanother configuration .Simulation results indicate that theTHD of the seven-level inverter.

REFERENCES

[1] M. Calais and V. G. Agelidis, “Multilevel converters forsingle-phase grid connected photovoltaic systems—Anoverview,” in Proc. IEEE Int. Symp. Ind. Electron.,1998,vol. 1, pp. 224–229.

[2] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review ofsingle-phase grid onnected inverters forphotovoltaicmodules,” IEEE Trans. Ind. Appl., vol. 41, no. 5,pp. 1292–1306, Sep./Oct. 2005.

[3] Nasrudin A. Rahim, Senior Member, IEEE, and JeyrajSelvaraj Multistring” Five-Level Inverter With Novel PWMControl Scheme for PV Application ,” IEEE Transactions onIndustrial Electronics, Vol. 57, No. 6, June 2010

[4] P. K. Hinga, T. Ohnishi, and T. Suzuki, “A new PWMinverter for photovoltaic power generation system,” in Conf.Rec. IEEE Power Electron. Spec. Conf., 1994, pp. 391–395.

[5] J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters:A survey of topologies, controls, and applications,” IEEETrans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[6] Nasrudin A. Rahim, Senior Member, IEEE, KrismadinataChaniago, Student Member, IEEE, and JeyrajSelvaraj,”Single-Phase Seven-Level Grid-Connected Inverterfor Photovoltaic System,” IEEE Transactions on IndustrialElectronics, Vol. 58, No. 6, June 2011

Rajesh Pingle, P.B.Borole and Sagar Patkar 17


Simulation and Results of Automatic Rationing for PublicDistribution System (PDS) and Technique to Inform

People about Various Facilities Provided by Governmentto Them

Rajesh Pingle, P.B.Borole and Sagar Patkar

Abstract: In a article published in Times of India itwas given that" To prevent the smuggling of goodsprovided under scheme of public distribution system bygovernment to poor people at rationing shop thegovernment launched a scheme. Under this scheme thegroup of rationing shops are formed. For each group ofration shop a committee got appointed. This committeecontains 25 members which include School principal,Social worker, Tasildar, police inspector, postmaster etcof that local region. Under this scheme when governmentsend foods for the people at ration shop simultaneouslysend the message about this to the respective committeemembers. Now committee members job was to keepwatch over distribution so that smuggling to beprevented. Even there was corruption and smuggling ofgoods carried on. "

Now need arise to make the system automated so thathuman intervention and manual work avoided andcreate the transparency in system. In this paper wepropose the concept about to replace manual work inpublic distribution system (rationing distributionsystem) by automated system which will be install at theration shop. In this automated system we replace theconvectional ration card by smart card in which all thedetails about users are provided including their"AADHAR" number which is used for userauthentication. This prompted us to interface smart cardreader (RFID Based) to the microcontroller(AT89V51RD2) and PC via RS232.Government shouldhave control over all transaction happen at ration shop,to involve government in the process we connected thesystem which is at ration shop to the governmentdatabase via GSM module (SIM900D) and RS232.Therewill be a Smart card based ration card which will beused to identify the user by machine placed at rationshop. There are two main objective of this project one isto create the transparency in public distribution systemand second is to inform the people about new schemelaunch by government.

Keywords:

AT COMMANDS , GSM MODULE , RFID READER, SMART CARD.

1. INTRODUCTION

The government having the UID number called "AADHAR"number and all related information such as contact number,bank A/C related information etc of every resident in india.Using the AADHAR number and contact details thegovernment will send a message(SMS) to respective person,before sending the products allotted to him/her in therespective ration shop. The message contains theinformation about the quantity and quality of the productwhich government provided for particular person in theration shop. People who accessing the ration shop forsubsidies rationing products will be given the smart cardbased ration card. This card is RFID based card in which allthe details about the users are given such as AADHARnumber, name of family members ,their profession, age etc.The system which installed at the ration shop having threesubsection i.e smart card interfacing to microcontroller,microcontroller and disply, GSM module interfacing tomicrocontroller as well as government database. The personhave to swap the card on the system placed at ration shop.After that the system will ask for the Password for userauthentication. The user have to enter their respectivePassword and press enter, as soon as the user press enter theGSM module send signal to government database for useridentification. The user will be valid If it's Password getmatch with respective AADHAR number. Once user is validthen respective detail information will be send bygovernment database to the system placed at shop. Thisinformation contains the detail about quality and quantity ofproduct that government allotted for that particular person.In this policy government send product (rice, wheat,kerocin, palm oil etc.) to rationing shop in form of sealpackets instead of the sack. The packet size of1Kg,2Kg,4Kg,8Kg,1Lit,2Lit,4Lit,8Lit etc. If user is validthen shopkeeper provide the product allotted to him/her bygovernment.

The government launches various schemes for the differentcategories people, to serve these schemes and inform aboutthese schemes to people are also a objective of this project.

2. COMPONENT OF AUTOMATEDTHE SYSTEM

The Entire automated system can be divided basically intothree parts:



1. RFID Module2. Microcontroller Unit3. GSM Module

The hardware of this project divided into three parts:

1. The smart card reader interfacing withmicrocontroller(AT89V51RD2) and PC: The RFIDbased smartcard reader is connected to microcontrollerand PC via RS232.

2. Microcontroller system and PC: This is the assemblywhich placed in between smart card reader and GSMmodule.It is used to establish the communicationbetween smart card reader and GSM module.

3. GSM module interfacing with microcontroller:Here theGSM module is used to exchange the information inform of SMS between microcontroller assembly andgovernment database.This exchange of information isrequired for user authentication and for other details.

The software demands of this project are:

1. The smart card reader should send the command tomicrocontroller when there is smartcard detected.

2. On receiving command from smartcard reader themicrocontroller should send command to GSM moduleto send message to the government database.

3. To receive the message from government database andsend to microcontroller using GSM module.

3. BLOCK DIAGRAM ANDSPECIFICATIONS

3.1 BLOCK DIAGRAM

3.2 BLOCK SPECIFICATIONS

1. RFID READER: It is block which detects the RFIDTAG when user present and send the user Password tomicrocontroller module for further processing. The serialinterfacing is setup to transfer the data to microcontrollerunit. When the smart card arrive in vicinity of RFID readermodule the password data will be get saved in the arraydefine in the microcontroller .When all bytes of passwordreceived then further processing gets start.

The RFID READER used having following specification:

Parameters ValueInput voltage 9 to 15 V AC/DC

Data speed(Output) 9600 BPS8 bit dataNo parity bitOne stop bit

Signal level(Output) Level define byRS232

Detection Range 25 to 30 cm.

Tag indication By LED ANDBUZZER

2. RS232: This module provides the required interfacingbetween RFID reader–microcontroller and GSM module-microcontroller.

3. GSM MODULE: It is the block which serves in order toexchange of information betweenmicrocontroller and government database.The GSM MODULE used having following specification:

Parameters ValueDatarate 9600 baud CSD

Service Support GSM data transmisson,SMS

Status indicator 1 LED,Alarm

Antenna Impedance 50 ohms

Digital I/O Output 8 TTL outputs, 8 TTLinputs w. 10K pull-down

Operatingtemperature range

Operating temperaturerange



4.PROCESS FLOW

5. AT COMMANDS FOR GSMMODULEAfter connecting the GSM module to microcontroller, it canbe control by sending instructions to it. The instructionswhich controls the GSM module are called AT commands.Commands are to controlling sending and receiving of SMSmessages.

The following table lists the AT commands that are relatedto sending and writing of message:

AT COMMANDS MEANING

+CMGS Send message+CMSS Send message from

storage+CMGW Write message to

memory

+CMGD Delete message+CNMI SMS alert+CMMS More message to send

6. RFID INTERFACING WITHMICROCONTROLLER

Each transponder tag contains a unique identifier (one of2^40,or 1,099,511,627,776 possible combinations) that isread by the RFID Card Reader and transmitted to the hostvia a simple serial interface. It means no two tags are same.Each tag has different value. This value if read by reader.When the RFID Card Reader is active and a valid RFIDtransponder tag is placed within range of the activatedreader, the unique ID will be transmitted as a 12-byteprintable ASCII string serially to the host in the followingformat:

The start byte and stop byte are used to easily identify that acorrect string has been received from the reader (theycorrespond to a line feed and carriage return characters,respectively). The middle ten bytes are the actual tag'sunique ID.

For example, for a tag with a valid ID of 0F0184F07A, thefollowing ASCII data would be sent 0F0184F07A Samedata in HEX bytes can be interpreted as: 0x0A, 0x30, 0x46,0x30, 0x31, 0x38, 0x34, 0x46, 0x30, 0x37, 0x41, 0x0D.Allcommunication is 8 data bits, no parity, 1 stop bit, and leastsignificant bit first (8N1). The baudrate is configured for9600 bps, a standard communications speed supported bymost any microprocessor or PC, and cannot be changed. TheRFID Card Reader initiates all communication. This allowseasy access to the serial data stream from any programminglanguage that can open a COM port.

6.1 Connecting to PC

Use the supplied serial cable to connect to PC’s serial port.Use Hyperterminal software which comes with WindowsXP or use any other Terminal software with followingsettings.

Data Rate: 9600, Data Bits: 8,Parity: None, Stop Bit: 1,FlowControl: None

7. GSM MODULE INTERFACING WITHMICROCONTROLLER



For interfacing of GSM module with microcontroller onefirst needs to know the GSM modem create an interfacingenvironment between microcontroller and governmentdatabase for exchanging message. The GSM module canaccept GSM network operator SIM card and act just like amobile phone with its own unique phone number. Toconnect GSM module to microcontroller(PC) the RS-232 isrequired.

8.PROJECT PROTOTYPE

9. CONCLUSION AND FUTURE WORKS

Government launches various schemes for those people whoare financially poor. To get the updates of that schemes topeople is the main objective of this paper. A system will bethere which identify the person by their Aadhar (UID)number and then serve them accordingly.

In this paper the identification and reception of usersinformation from database manage by government andplaced at remote distance are explain. This project create thetransparency in public distribution system as much of thework becoming automatic. With help of this it is possible tomake public distribution system efficient.

9.1.FUTURE WORKS:

The same system with existing components can also beused for keeping employees record in multibranchorganizations. It is possible by creating commondatabase for multibranches.

It can be also carried out for various remote securityapplication as hardware requirement is same, thedifference is that some relay and sensors need to beattached.

10.ACKNOWLEDGEMENT

It is with immense pleasure that I present this project, whichhas been a learning experience and an enhancement for mytechnical expertise. I take this opportunity to express mydeep sense of gratitude to my guide Prof.P. B.Borole(Department of Electrical Engineering) for suggesting thisinteresting topic and allowing me to do my dissertation infield of RFID Technology. His constant guidance, support

and encouragement contributed very much in my efforts forcompleting this dissertation.

I am also grateful to Dr.M.S.Panse Head of ElectricalEngineering Department, Director Dr. O. G. Kakde andformer Director Dr.M.C. Deo ,Veermata JijabaiTechnological Institute for providing academics facilitiesand support.

11. REFERENCES:

[1] Z. Zyonar, Karl Kammelander, Peter Jung,"Evolution Towards 3rd GenerationSystems",1988."

[2] Jorg Eberspacher, Hans-Joerg Vogel, ChristianBettstetter," GSM Architecture, Protocols andServices",2008.

[3] RFID Journal ,"Wal-mart begin RFID proce ss.changes".http://www. rfidjournal.com/article/article view/1385.

[4] S.Lahiri,RFID sourcebook,USA:IBM press,2006.[5] http://www.omni-id.com/pdfs/Omni-ID_

Fit_200_datasheet.pdf

Rohit Suneja and Vaibhav Jain 21


Energy Efficient MAC Protocol for WirelessSensor Networks-A Review

Rohit Suneja and Vaibhav Jain

Abstract: Wireless Sensor Networks is having broad area forresearchers due to their wide range of application potential inareas such as target detection and tracking, environmentalmonitoring, industrial process monitoring, and tacticalsystems. In designing of Wireless Sensor Networks MACprotocols, conservation of energy is the main issue. Energyefficiency is a major consideration while designing wirelesssensor network nodes. Lowering the energy consumption mayresult in increase of time delay from end to end in WirelessSensor Network (WSN). To address the tradeoff betweenenergy consumption and time delay, this paper proposes aMAC protocol based on sleep schedule of sensor node dynamicduty cycle. This paper propose that if any node is having datato send to the desired destination, it first checks the idleness ofmedium from where the data is to be sent and then sends anAWAKE signal to wake up the node for data reception. Else,all the nodes are kept in SLEEP state, so that energyconservation is more.

I. Introduction:

Recent advancements in scaling and low-power design putforward to active research in large-scale, highly distributedsystems of small-size, wireless unattended sensors [1][2]. Asensor network consists of minute devices that are capableof probing the environment and reporting the collected data,typically using a radio, to the command center. Sensornetworks can serve many military and civil applicationssuch as disaster management, combat field surveillance andsecurity.

In such applications, the sensors are usually powered usingsmall batteries and replacing sensor’s battery is not possibleor not practical. Such energy constraints limit sensors’lifetime and thus makes it a real challenge for efficientdesigning and management of sensor networks. Therefore, alot of the research related to sensor networks has focused onenergy-awareness and minimization [1] [3] [4]. In this paperwe concentrate on the minimization of energy consumptionat the MAC layer through time-based arbitration of thesensor’s medium access.

Rohit Suneja and Vaibhav Jain, Dep’t. of ECE, Vaish College ofEngineering, Rohtak Email: Email ID: [email protected]

Medium access is a major consumer of sensor energy,especially when the radio receiver is kept on all the time forlong-range transmissions. Energy consumed for radiotransmission is directly proportional to distance squared andcan significantly increase in a noisy environment. Energy-aware routing typically follows multi-hop paths in order tooptimize the energy of transmission [5]. On the other hand,time-based medium access control (MAC) savestransmission energy by limiting the potential for collisionsand minimizes the energy consumed in the receiver byturning the radio off when it is idle [3][4]. Generally, anefficient MAC layer protocol for sensor networks shouldhave the following attributes: The protocol should be scalable since most

applications of sensor networks involve a large set ofsensor nodes.

Collisions among the transmissions of various nodesshould be avoided. Collisions lead to packet drop andthus reduce throughput and cause energy wastage.

Energy consumed by the radio circuit in idle mode isalmost equal to that consumed in active state.Consequently, idle mode of operation andtransmission overhearing among sensors should beminimized.

To limit energy consumption during idle time, thesensors are typically switched to a sleep mode whennot in use. However, active to sleep transitions andvice-versa consume considerable amount of energy.Therefore, an efficient protocol should minimize suchtransitions [4].

Control packets overhead and active sensing of themedium, typically performed by contention-basedprotocols, are inefficient in terms of energyconsumption. So, the protocol should not becontention-based.

Packet drop due to limited buffer capacity should beprevented.

The protocol should adapt to changes in the networktopology and all sensors should have a fair chance oftransmitting.

Unlike contention-based protocols, a Time-Division-Multiple-Access (TDMA) based MAC allowscommunication traffic to flow according to a presetschedule. Time-based MAC can minimize the energyconsumption since the nodes can turn off their transmittersor receivers, unless they are expecting to receive or transmita packet. It has been shown that turning off the radioreceiver significantly reduces energy consumption andextends the life of wireless sensor networks [6] [7]. Also,collision among nodes can be avoided since each node has



its own assigned time slots. However these advantages oftime-based MAC are due to the deterministic operation,which requires communication time slots to be scheduledfor both transmitting and receiving.

A. System ModelThe system architecture for the sensor network is depictedin Fig. 1. In the architecture, all the sensor nodes arecontrolled by a single command node called the sink nodewhich forms a cluster. Every cluster has a gateway node thatmanages sensors in the cluster. Clustering the sensornetwork can be either performed by the command node orcollaboratively among the gateways and is beyond the scopeof this paper [8]. Sensors are having the capability tocommunicate with radio based short-haul communicationand are responsible for probing the clustering environmentto detect a target/event. In this paper, we assume that sensorand sink (gateway) nodes are initially in idle state and allsensors in a cluster are within the communication range ofthe gateway of that cluster. The on-board clocks of thegateway nodes are assumed to be synchronized, e.g. via theuse of GPS.

The sink node interfaces the command node with the sensornetwork through long-haul communication links. Sensorsreceive commands from and send readings to their gatewaynode, which processes these readings and transmits thefused information to the command node. Unlike sensors thegateways are significantly less energy consumption nodes.Hence the gateway is assigned the responsibility oforganizing the sensors and routing generated data. Sensororganization refers to activating a subset of available sensorsin the cluster to probe the environment based on theapplication and the sensor’s capabilities. The gateway setsmulti-hop routes based upon the current state of the networkand sends route updates to the sensors. Route formation willdesignate some sensors to act as relays. The sensors thenadjust their transmit power based upon their next hopneighbor.

Fig. No. 1 WSN ClusterRadios are assumed to have the ability to operate in fourdifferent modes transmit, receive, idle and sleep. The energyconsumed in idle mode is almost equivalent to that inreceive mode [16]. The energy consumed by the radio is:Eradio = Ntx [Ptx (Ton-tx+Tst) +PoutTon-tx] +Nrx [Prx (Ton-rx+Tst)]…… (1)

Where Ntx/rx is the average number of times per second, thetransmitter/receiver is used. Tst is the transition time fromsleep to active mode. Ton-tx/rx is the ON time of thetransmitter/receiver. Pout is the output transmission power.Ptx/rx is the power consumed by the transmitter/receiver [8].

II. Major Issues of Energy Wastage:

1. Idle listeningWhen nodes in the cluster have nothing to transmit orreceive, the nodes still remain in active state and do idlelistening to the network. This process consumes sameamount of energy as in the transmission or receivingprocess, that lead to wastage of energy.

2. Collision or CorruptionNormally collision may occur when neighboring nodesassert for free medium and faulty channel will leads tocorruption of transmitted packets. When either of two caseshappens corrupted packets should be retransmitted, whichincreases energy consumption.

3. OverhearingThis happens when a node receives some packets that areactually sent to other nodes.

4. Control Packet OverheadSome energy is also consumed when there is exchange ofcontrol packets between sender and receiver.

III. S-MAC (Sensor-MAC)

In wireless sensor network, the Sensor S-MAC protocol is acontention based MAC protocol. It is an improved versionof IEEE 802.11 protocol .The sensor node periodically goesto the fixed sleep cycle for the MAC protocol. The timeframe is divided into two part: one for a sleeping sessionand the other for a listening session In SMAC, the sensornode are capable to communicate with additional nodes andthey send some control packets like SYNC,RTS (Request toSend), CTS (Clear to Send) and ACK(Acknowledgement)are only for listen period. By a SYNC packet exchange allnearest nodes can synchronize collectively and usingRTS/CTS switch over the two nodes can communicate witheach other. The Fig. 1 describes the basic s-node schemewhere transmission of data from node 1 to node 2 is shown.Even IF there is no reception/transmission a lot of energy isstill dissipated in this protocol during listen period as thesensor will be in AWAKE state.If node sleep for half second and wake up for other halfsecond so energy saving is 50%.

Schedule Exchanging-:

SYNC packets are exchanged periodically to maintainschedule synchronization.SYNC Packet



Synchronization period: Period for a node to send a SYNCpacket. Receivers will adjust their scheduled countersimmediately after they receive the SYNC packet. Each nodemaintains a schedule table that stores schedules of all itsknown neighbors. For initial schedule: A node first listens tothe medium for a certain amount of time (at least thesynchronization period). If it does not hear a schedule(SYNC packet) from another node, it randomly chooses aschedule and broadcasts its schedule with a SYNC packetimmediately. This node is called a synchronizer. If a nodereceives a schedule from a neighbor before choosing its ownschedule it follows this neighbor’s schedule becomes aFollower. It waits for a random hold time and broadcasts itsschedule to the cluster. Border node having different SYNCpacket from Synchronizer node. It will wake up for allschedules it knows, so it consumes more energy

Overview

The S-MAC protocol is designed with the primary goal ofreducing energy consumption from various methods. It isobtained by periodically putting nodes into a sleep state.Each node sleeps for a specified amount of time, then wakesup and listens to see if any other nodes want tocommunicate. During the sleep time, the node turns off itsradio and sets its timer to wake up. A complete listen andsleep cycle is called a frame. Nodes are free to choose theirown listen and sleep schedules. Nodes announce theirschedules to their neighboring nodes by broadcasting SYNCpackets. A group of nodes following the same scheduleforms a virtual cluster. As shown in Fig. 2, nodes A, B, C, Dand E form a virtual cluster following one schedule, andnodes F,G,H, and E form another virtual cluster followinganother schedule. Node E belongs to two clusters, andfollows two different schedules. It becomes a border nodeand has two listen intervals in a given frame to supportinter-cluster communication. When two neighboring nodesfollow two different schedules where two listen intervals arenot overlapped, they may never find each other. ThePeriodic neighbor discovery (PND) is introduced to solvethis problem. During PND, each node periodically listensfor an entire synchronization period, the period for eachnode to send a SYNC packet. The following rules governeach node when selecting its schedule and creating itsschedule table which stores the schedules of all knownneighboring nodes and its own. Also the AWAKE/SLEEPsignal is introduced in this to set the state of node.

After being deployed, a node listens for at least onesynchronization period to hear the existing schedulesfrom neighboring nodes. If it does not hear anyschedules, it starts its own schedule, announces theschedule by broadcasting

SYNC packets periodically and becomes asynchronizer. If it hears a schedule from its neighboringnode before choosing its own schedule, it follows thereceived schedule and becomes a follower.

After choosing and announcing its own schedule, anode has two choices when it hears a different schedulefrom a neighboring node. If the node has no otherneighboring nodes with different schedules, it discardsits old schedule and follows the new schedule from theneighboring node. If it has one or more neighboringnodes with different schedules, it adopts all schedulesand becomes a border node.

Fig No. 2 Scheduled based networkA border node following multiple schedules has relativelylarge power consumption because it transits into the listenstate more than once in each frame and relays the datapackets between the virtual clusters. It makes border nodesto reduce lifetime. The eventual death of the border nodeceases the communication between neighboring virtualclusters. Therefore, after some time, a sensor networkcovering a wide area and consisting of tens of thousands ofsensor nodes is divided into several isolated virtual clustersdue to the death of border nodes

.

IV. Comparative study of existing MAC Protocols:

Table 1 compares the different MAC protocols by taking parameter scheme used, energy savings, advantages anddisadvantages. [9]

Sender Node ID Next Sleep Time



NAME OF THEPROTOCOL

SCHEME USED ENERGYSAVINGS

ADVANTAGES DISADVANTAGES

SMAC Fixed duty cycle,Virtual Cluster,

CSMA

Power savings overCSMA/CAMAC

Low energyconsumption when

traffic is low

Sleep latency,problem with

broadcastBMAC LPL, Channel

assessment softwareinterface

Better powersavings, latency and

throughput thanSMAC

Low overhead whennetwork is idle,

consumes less power

Overhearing, badperformance at heavy

traffic, longtransmission latency

TMAC Adaptive duty cycle,overhearing, FRTS

Use 20% of energyused in SMAC

Adaptive active time Early sleepingproblem

WISE MAC Minimized preamblesampling, schedule

Better than SMACand low power

listening

Energy consumptionboth at sender andreceiver and at non

target receiverincrease latency at

each hop

Low power for lowtraffic, do not incur

overhead due tosynchronization

TRAMA TDMA Utilization ofclassical TDMA

Higher energyefficiency and

throughput

Time is divided in torandom access period

DMAC Converge castcommunication

Low latency Energy saving andlow latency

Aggregate rate islarger

CMAC Aggressive ack.anycast, convergentpacket forwarding

Consume lessenergy than existing

solutions

High throughput,low latency andconsumes less

energy

Not yet found

Table 1: Comparative study of energy efficient MAC protocols

V. Conclusion:Designing a MAC protocol which can improve energyefficiency to extend network lifetime in Wireless SensorNetworks is a challenging problem. It is mainly due tostringent resource constrains both in sensor nodes andwireless media. Sensor-MAC (SMAC) and theircomparative study with different protocols have beenproposed in this paper. Although there are various MAClayer protocols proposed for sensor networks, there is noprotocol accepted as a standard. One of the reasons behindthis is the MAC protocol choices will, in-general, beapplication dependent, which means that there will not beone standard MAC for WSN’s.

VI. Reference:[1] Woonsik Lee, Minh Viet Nguyen, Arabinda Verma,

“Schedule Unifying Algorithm Extending Network Lifetimein S-MAC-Based Wireless Sensor Networks”, (September,2009) Student Member, IEEE, and Hwang Soo Lee,Member, IEEE.

[2] Ilker Demirkol, Cem Ersoy, and Fatih Alagöz, “MACprotocols for Wireless Sensor Networks- A Survey”,Network Research Laboratory (NETLAB) of the ComputerEngineering Deptt. Of Bogazici University, Istanbul,Turkey.

[3] Ramchand V and D.K. Lobiyal, “Throughput Analysis ofpower control B-MAC protocol in WSN”, (June 2012)School of Systems and Computer Sciences, JawaharLalNehru University, New Delhi, India

[4] Kyung Tae Kimand Hee Yong Youn, “An Energy EfficientMAC protocol Employing Dynamic Threshold for WirelessSensor Networks”, (September 2012) College of Informationand Communication Engineering, SungkyunkwanUniversity, Suwon 440-746, Republic of Korea

[5] Qiang Fan, Jing Fan1, Jie Li, and Xiaofang Wang, “A Multi-hop Energy-Efficient sleeping MAC Protocol based onTDMA scheduling for Wireless Mesh Sensor Networks”,(September 2012) School of Electrical and InformationTechnology, Yunnan University of Nationalities, Kunming,P.R.China

[6] Smriti Joshi & Anant Kr. Jayswal, “Energy-Efficient MACProtocol for Wireless Sensor Networks- A Review”, AmityUniversity, Noida International Journal of Smart Sensors andAd Hoc Networks (IJSSAN) ISSN No. 2248‐9738Volume‐1, Issue‐4, 2012

[7] Ziqiang An, “Medium Access Control Protocol withDynamic Duty Cycle in Wireless Sensor Network”, (June2012), International Journal of Future Computer andCommunication, Vol. 1, No. 1, June 2012

[8] Bhavana Narain, Anuradha Sharma, Sanjay Kumar andVinod Patle, “ENERGY EFFICIENT MAC PROTOCOLSFOR WIRELESS SENSOR NETWORKS: A SURVEY”,International Journal of Computer Science & EngineeringSurvey (IJCSES) Vol.2, No.3, August 2011

[9] Gaurav Jolly and Mohamed Younis’ “An Energy-Efficient,Scalable and Collision-Free MAC layer Protocol for WirelessSensor Networks”, Dept. of Computer Science and Elec.Eng. University of Maryland Baltimore County 1000 HilltopCircle, Baltimore, MD 21250

Prabhjot Kaur and Reena 26


Watermarking Embedding in Spatial Domain

Prabhjot Kaur ReenaECE Deptt. DVIET, Karnal Asst.Prof, DVIET, Karnal

Abstract: Due to improvement in imaging technology and theease with which digital content can be reproduced andmanipulated there is a strong need for a digital copyrightmechanism to be put in place. Digital Watermarking is beingseen as a potential solution to this problem. Digital authenticateit. In spatial domain technique watermarking is a technologywhich embeds a watermark signal into the host image to thewatermark image is embedded into the cover image. The spatialdomain is slightly modifies the pixels of one or two randomlyselected subsets of an image. Modification might includeflipping the low order bit of each pixel It deals with hiding secretbits of information with a digital content as a cover.

Keywords: Spatial domain, least significant bits, most significantbits, watermarked image,

I IntroductionWith the ever-growing expansion of digital multimediaand the internet digitizing of visual data such as imagesand video has become popular .However ,thisadvancement in technology has double impact .Firstimpact is that ,it has permitted faster and more efficientstorage ,transfer and processing lf digital data. The secondimpact is, duplication and manipulation of digital contentshas also become very easy and undetectable ,which allowsfast and error free movement of any unauthorized digitaldata and possibly manipulated copy of such information,grow in popularity in the recent years, security concernsover Copyright protection of digital multimedia data hasalso been increasingly emphasized. One of the mostpromising solutions appears to add author information(watermark) into the visual data as a secondary signal thatis not perceivable and is bonded so well with the originaldata that it is undividable. Techniques to embed andrecover such secondary information or stamps (calledwatermark) is digital watermarking.

II Watermark Embedding and ExtractionA watermarking algorithm embeds a visible or invisible

watermark in a given multimedia object. In thewatermarking embedding scheme

Secrete Key

W WatermarkedOriginal ImageImage

Watermark

“Fig. 1: Watermarking Embedding”

The input to the scheme is watermark, the cover imagedata and optional or secret key. The watermark can be anynature, such as a number, text, an image. The secret orpublic key is used to enforce the securityFor the detection scheme the input is watermarked image,

watermark image and optional or secrete keyand depends upon the original data and originalwatermark.

Key

Watermarked W \WatermarkImage

“Fig. 2: Watermarking Extraction”

The output of the watermark recovery process is either therecovered watermark or some kind of confidence measureindicating how likely it is for the given watermark imageat the input to be present in the data under inspection.

A. Evaluation parameters of a watermarking techniqueMean Square ErrorThe mean square error between the original image f (m, n)and the reconstructed image g (m, n) is given by

MSE= × ∑ ∑ ( f(m, n) − g(m, n) )Here N×M represents the size of the image.The MSE is a very useful measure as it gives an averagevalue of the energy lost in lossy compression of theoriginal image. A human observing two images affectedby the same type of degradation will generally judge theone with smaller MSE to be closer to the original. A verysmall MSE can be taken to mean that the image is verycloser to the original. Original image and reconstructedimage (watermarked image) are the grayscale of the

EmbeddingAlgorithm

ExtractionAlgorithm



images to compare to measure value of the energy lost inlossy compression of the original image.Peak Signal to Noise Ratio

A more subjective qualitative measurement of distortion isthe peak signal to noise ratio. The peak signal to noiseratio (PSNR) is used to evaluate the image quality bycalculating the mean square error (MSE) between theimages to compare.

PSNR=10× log [ ) ]For an 8-bit image, b=8 which gives the PSNR value as

PSNR=10×log [( ) ]The PSNR is expressed in dB. The PSNR evaluationparameter is superior measurement method. It uses aconstant value in which to compare the noise againstinstead of a fluctuating signal. We calculate PSNRbetween original image and watermarked image that weoutput from the embedding process. The higher the PSNRshows the better quality of watermarked image. So, if wehave bigger PSNR, it shows least difference betweenoriginal image and watermarked image that shows morerobustness’ against attacks.

III WATERMARKING IN SPATIAL DOMAIN

In spatial domain technique the watermark image isembedded into the cover image. The spatial domain isslightly modifies the pixels of one or two randomlyselected subsets of an image. Modification might includeflipping the low order bit of each pixel. This concept isused most often when discussing the frequency withwhich image values change that is over how many pixelsdoes a cycle of periodically repeating intensity variationsoccur. One would refer to the number of pixels overwhich a pattern repeats in the spatial domain.

A. LSB-MSB Watermark Embedding Scheme

LSB coding is one of the earliest methods. It can beapplied to any form of watermarking. In this method theLSB of the carrier signal is substituted with thewatermark. The bits are embedded in a sequence whichacts as the key. The watermark encoder first selects asubset of pixel values on which the watermark has to beembedded. The cover image and the watermark image arethe inputs for the watermarking embedding process. LSB-MSB approach of LSB invisible watermarking scheme,uses the least significant bits of the original image ismasked and substituted by the most significant bits of thewatermark image. LSB-MSB watermarking scheme isused to embed invisible watermark in famous test image.These approaches decrease the authentication distortionand increase the efficiency of secure authentication. Soimplementation in this process by embedding data aspixels into the image and then provide authentication bycomparing the original and the embed image. The publickey is used to enforce security if the watermark image isnot to be read by unauthorized parties, a key can be usedto protect the watermark. The output of the watermarkingscheme is converted to watermarked image.

Watermark Image

Cover

Image Watermarked

Image

Public / secret key

“Fig. 3: Watermarking Embedding Scheme “

The figure 3 shows the LSB watermarking embeddingscheme. The cover image, watermark image and thepublic key are the inputs for the watermarking embeddingprocess. The public key is an optional key for the LSBwatermarking embedding scheme. In this process theinvisible watermark is embedded into the standard testimage.

Algorithm for LSB-MSB embedding watermarkingscheme

(1) Read image i.e. cover image.(2) Calculate its size let 1 2*m m .(3) Read watermark image i.e. CS image.(4) Calculate its size let 1 2*n n .

(5) If the (( 1 2*n n ) ≥ ( 1 2*m m ))Print (watermark not fit in to cover image).

Else, follow step number 6 to 10.(6) Reset the content of LSB bit plane in the

cover image...(7) Calculate the value of MSE, PSNR &

Correlation between cover image andwatermark image\

IV SIMULATION OF LSB-MSB ALGORITHMThe famous standard test image: Cameraman (256 256 ) and shown in figure 4.1 is taken as the coverimage or base image to embed a (120 100 ) watermarkimage. N LSB MSB watermarking scheme is used toembed watermark. Where n is the number of bits used. Itis quite obvious that smaller the value of n, lesser is thedeterioration in the quality of the image. As we increasethe number of bits, the image quality further degrades andbecomes more visible to the naked eye n LSB MSBwatermarking scheme is used to embed invisiblewatermark in famous test image. Where n is the numberof bits used. It is quite obvious that smaller the value of n,lesser is the deterioration in the quality of the image. Aswe increase the number of bits, the image quality furtherdegrades and becomes more visible to the naked eye. Bychanging the value of the variable ‘bits’ from 1 to 7, wecalculate the values of PSNR and MSE which shows thequality of the image.

LSBalgorithmforembedding



“Fig. 4.1: (a) Cover Image (Cameraman) “

“Fig 4.1: (b) Watermark”

“Fig. 4.1: (a) Cover Image (Cameraman), (b)Watermark “

CASE-1 Using 1 LSB-MSB algorithm for embeddinginvisible watermarked image

MSE=0.0503, PSNR=61.112db

“Fig. 4.2: Recovered Watermarked Images Using 1LSB-MSB Algorithm”

CASE-2 Using 3 LSB-MSB algorithms for embeddinginvisible watermarked image

MSE=0.788, PSNR=49.164db

“Fig. 4.3: Recovered Watermarked Images Using 3LSB-MSB Algorithms”

CASE-3 Using 7 LSB - MSB algorithm for embeddinginvisible watermarked image

MSE=14.781, PSNR=35.335db

“Fig. 4.4: Recovered Watermarked Images

Using 7 LSB-MSB Algorithms







MSE=0.0503, PSNR=61.112db



MSE=0.788, PSNR=49.164db



MSE=14.781, PSNR=35.335db









MSE=0.0503, PSNR=61.112db



MSE=0.788, PSNR=49.164db



MSE=14.781, PSNR=35.335db





.

“ Table 4.1 Results of LSB-MSB Algorithm”

V CONCLUSION AND RESULTS

The table 4.1 shows that when we use 1 LSB-MSBalgorithm the value of MSE and PSNR is 0.050 and 61.11db for cameraman image. And when we use 2 LSB-MSBalgorithms the value of the MSE and PSNR is 0.201 and55.08 db for the cameraman image. When number ofusing bits increases, the value of PSNR is decreases andthe value of MSE is increase

REFERENCES[1] Yanqun Zhang “Digital Watermarking Technology: AReview” 2009 ETP International Conference on FutureComputer and Communication[2] Houtan Haddad Larijani and Gholamali Rezai Rad “ANew Spatial Domain Algorithm for gray scale imageswatermarking” Proceedings of the InternationalConference on Computerand Communication Engineering 2008 May 13-15, 2008Kuala Lumpur, Malaysia[3] Ibrahim Nasser, Ying Weng, Jianmin Jiang “NovelMultiple Spatial Watermarking Technique In ColorImages “Fifth International Conference on InformationTechnology: New Generations[4] Munesh Chandra “A DWT Domain VisibleWatermarking Techniques for Digital Images”2010International Conference on Electronics and InformationEngineering (ICEIE2010)[5] Vikas Saxena, J.P Gupta “Collusion Attack ResistantWatermarking Scheme for Colored Images using DCT”

IAENG International Journal of Computer Science, 34:2,IJCS_34 _2_02[6] Reza Mortezaei, Mohsen Ebrahimi “A new losslesswatermarking Scheme based on fuzzy integral and DCTdomain”2010 International Conference on Electronics andInformation Engineering (ICEIE 2010)[7] Afzel Noore “An Improved Digital WatermarkingTechnique for Protecting JPEG images” WPM P2.08 0-7803-7721-4/ 03 2003 IEEE[8]Dhruv Arya” A Survey Wavelet Domain of FrequencyandDigital Watermarking Techniques” International Journalof Scientific & Engineering Research, Volume 1, Issue 2,November-2010 1 ISSN 2229-5518[9] Mansi Hasija, Alka Jindal” Contrast of WatermarkingTechniques indifferent domains” IJCSI International Journal ofComputer Science Issues, Vol. 8, Issue 3, No. 2, May2011 ISSN (Online): 1694-0814

Approaches

Cameraman WatermarkedImage

MSE PSNR

1 LSB-MSB 0.050 61.11

2 LSB-MSB 0.201 55.08

3 LSB-MSB 0.788 49.16

4 LSB-MSB 3.446 42.75

5 LSB-MSB

6 LSB-MSB

7 LSB-MSB

11.54

12.11

14.78

37.50

37.29

35.33



Prabhjot Kaur received herB.Tech degree in Electronics and communicationfrom Doon Valley institute of engineering andtechnology under Kurukshetra Universty. At present,she is pursuing her Master in Technology.Herresearch works includes Image Processing.

Er. Reena received herB.Tech degree in Electronics and communicationfrom Doon Valley institute of engineering andtechnology under Kurukshetra Universty. Shereceived her M.Tech degree from UIET,Kurukshetra. She was assistant professor in UIET,Kurukshetra for six months. At present she isworking as an assistant professor in Doon valleyInstitute of engineering and technology from last oneyear and 4 months.

Nidhi Kaushik and Nidhi Mittal 31


Designing and comparative analysis for BER of selection,Equal gain and maximal ratio combining diversity techniques

Nidhi Kaushik and Nidhi Mittal

Abstract: This paper provides a brief introduction to thevarious types of Diversity systems in wireless systems. Steppinginto the new generation of mobile communication it is ofconcern to increase the performance of the mobile terminalsand their antennas to be able to answer to the demand of fasterand more various communicational services. Still, the issue ofsignal fading in a multi-path environment stands as an obstacletoday. The purpose of this work is to introduce diversitytechniques as a promising way of improving the performanceat the mobile terminals. The goal is more profound, dealingwith analysis of the correlation between received signals andthe propagation environments that diversity improvementdepends on, and putting together a repeatable method formeasuring the improvement. The work resulted in simulatedand measured diversity performance for three different,antenna diversity concepts created for the purpose of thiswork. The results confirmed by using Rayleigh fading inAWGN noisy channel and with the BPSK modulation,presented the best diversity technique out of three and alsoprovide a comparison between all. An analytical expression forthe signal-to-bit-error-rate (BER) at the output of a three-diversity technique is given. The three branches are assumed tobe Rayleigh fading, correlated with the BPSK modulation.Measurements of the bit-error-rate with the Eb/N0 afterselection, equal gain combining and maximal ratio combiningwere made in Rayleigh fading channels and compared with theanalytical results.

Keywords: Diversity, fading, selection diversity, maximalratio combining, equal gain diversity, bit error rate, signal to noiseratio.

I. IntroductionModern communication systems have become an importantpart of day-to-day life. The demand for higher data-speed inwireless networks calls for innovative efficientCommunications technologies which are not only spectrally-efficient but also energy efficient. Diversity techniques is tobe effective to overcome the channel fading and exploitbroadcast nature of transmission to provide reliable andbetter links. Diversity is a powerful communication receivertechnique that Provides wireless link improvement at arelatively low cost. Diversity techniques are used in wirelesscommunications systems to improve performance over afading radio channel.In such a system, the receiver is provided with multiplecopies of the same information signal which are transmittedover two or more real or virtual communication channels.Thus the basic idea of diversity is repetition or redundancyof information.

Nidhi Kaushik is pursuing M.Rech and Nidhi Mittal is a AssistantProfessor, ECED, DVIET, Haryana (India),[email protected], [email protected]

In virtually all the applications, the diversity decisions aremade by the receiver and are unknown to the transmitter. Asthe use of multimedia applications grows, there is anincreasing demand for higher data rate and access to suchservices. The diversity techniques have been proven to beeffective for such purpose.

II. Types of diversityFading can be classified into small scale and large scalefading. Small-scale fades are characterized by deep andrapid amplitude fluctuations which occur as the mobilemoves over distances of just a few wavelengths. For narrow-band signals, this typically results in a Rayleigh fadedenvelope.

A. Time Diversity: In this, multiple versions of the samesignal are transmitted at different time instants thisinformation signal is transmitted at regular intervals of time.The separation between the transmit times should be greaterthan the coherence time period. In order to transmit thedesired signal in M different periods of time, i.e., eachsymbol is transmitted M times. The time interval depends onthe fading rate, and increases with the decrease in the rate offading.

f

Δt

t“Figure 1: Time Diversity Scheme”

B. Frequency Diversity: The signal is transmitted usingseveral frequency channels spread over a wide spectrum.The same information signal is transmitted on differentcarriers, each carrier should be separated from the others byat least the coherence bandwidth so that different copies ofthe signal undergo independent fading. To achieve this,modulate the information signal through M differentcarriers.

Δf

t

“Figure 2 : Frequency Diversity”

s(t) s(t)

S(t)

S(t)



C. Space Diversity: In Space diversity, there are multiplereceiving antennas placed at different spatial locations,resulting in different independent received signals, Mantennas are used to receive M copies of the transmittedsignal. The antennae should be spaced far enough apart.Different from frequency diversity, no additional work isrequired on the transmission end, and no additionalbandwidth or transmission time is required.

“Figure 3: Space Diversity”

III. Diversity CombiningTechniques

The aim of diversity is to combine several copies of thetransmitted signal, which undergo independent fading, toincrease the overall received power. There are differenttypes of diversity combining methods.

A. Selection Diversity: In this method, the strongest signalbranch is selected. From the number of antennas, the branchthat receives the signal with the largest signal-to-noise ratiois selected and connected to the demodulator. Larger thenumber of available branches, the higher the probability ofhaving a larger signal-to-noise ratio at the output.

r(t)= A s(t) + Z(t)-s(t) = is the equivalent lowpass of the transmitted signal,

A = is the fading attenuation of branchwhere A= max{ °, ,.. … .., }received signal to noise ratio is given as:

┌ =°

= max{┌°,┌ , ……,┌ }

“Figure 4: BER for selection diversity”

B. Maximal Ratio Combining

Both branches are weighted by their instantaneous voltage-to-noise ratios. Each of the branch signals is weighted with again factor proportional to its own SNR. The branches arethen co-phased and summed in order to insure that allbranches are added in phase for maximum diversity gain.The summed signals are then used as the received signal andconnected to the demodulator. The advantage is thatimprovements can be achieved with this configuration evenwhen both branches are completely correlated. Thedisadvantage of maximal ratio is that it is complicated andrequires accurate estimates of the instantaneous signal leveland average noise power to achieve optimum performancewith this combining scheme. Maximal ratio combining willalways perform better than either selection diversity or equalgain combining because it is an optimum combiner. Theinformation on all channels is used with this technique to geta more reliable received signal.

y(t) = ∑ ( )received signal to noise ratio is given as:

┌ = ∑ = ∑ ┌

“Figure 5: BER for Maximal Ratio Combining”

C. Equal Gain Combining

It is same as that of maximal ratio combining except that ofequal gains. In this scheme the gains of the branches are allset to a single value and are not changed. Both the branchsignals are multiplied by the same branch gain (G) and theresulting signals are co-phased and summed. The resultantoutput signal is connected to the demodulator.

y(t) = ∑ ( ) = (∑ ) ( ) + ∑ (t)

SNR is given by

┌ = (∑ )2

0 5 10 15 20 25 30 3510

-5

10-4

10-3

10-2

10-1

Eb/No, dB

BitErrorRate

BER for BPSK modulation with Selection diveristy in Rayleigh channel

nRx=1 (theory)nRx=1 (sim)nRx=2 (theory)nRx=2 (sim)nRx=3 (sim)

0 5 10 15 20 25 30 3510-5

10-4

10-3

10-2

10-1

Eb/No, dB

BitErrorRate

BER for BPSK modulation with Maximal Ratio Combining in Rayleigh channel


TransmitterReceiver



“Figure 6: BER for Equal Ratio Combining”

IV. Result ComparisonIn the figure below, plots for the SNR with the different no.of antenna for all the three techniques have been shown.This clearly shows that SNR in case of MRC is much thanthat of Equal Gain and selection diversity. It is alsoobserved that as the number of receiver increases SNRincreases gradually. If the no. of antenna is 4 then it can beobserved from the below figure the value of signal to noiseratio is more for Maximal Ratio Combining diversitytechnique as compare to Equal Gain Combining andSelection diversity technique and SNR value for Equal GainCombining is more than the Selection diversity technique.

“Figure 7: BER Comparison”

V. ConclusionFor the receiver diversity we have different diversitytechnique, out of which we used three techniques-selectiondiversity, maximal ratio combining and equal gaincombining for our work. BPSK modulation technique andRayleigh fading is used for checking the performance ofthese techniques. We observed that for the calculation thebit error rate with respect to the ⁄ then again maximalratio combining have lesser value as compare to the equalgain combining and selection diversity. So, we can say thatthe performance of the maximal ratio combining is better ascompare to the equal gain combining and selection

diversity. Other effective techniques are time and frequencydiversity. Time interleaving, together with error correctioncoding, can provide diversity improvement.

VI. References[1] Wireless Communications Principles and Practice, Dr.

Rappaport.[2] Fangming He, Hong Man and Wei Wang, “Maximal

Ratio Diversity Combining Enhanced Security”, IEEECommunications Letters, Vol-15, Issue: 5, pp-509 – 511,May 2011.

[3] Vivek K Dwivedi, G Singh, “Analysis of ChannelCapacity of Generalized -K Fading with Maximal-RatioCombining Diversity Receivers” InternationalConference on Communication Systems and NetworkTechnologies, 2011.

[4] Wireless Communication Technologies, lecture notes,Spring 2005, Dr. Narayan Mandayam, RutgersUniversity.

[5] J. H. Winters, “The diversity gain of transmit diversity inwireless systems with Rayleigh fading,” in Proc. 1994ICC/SUPERCOMM, New Orleans, LA, May 1994, vol.2, pp. 1121–1125.

[6] H.Hourani, “An overview of diversity techniques inwireless communication systems,” IEEE JSAC , pp.1200-5, October 2004.

[7] M. K. Simon and M.-S. Alouini “Digital Communicationover Fading Channels” 1st Ed. New York: Wiley 2000.

Nidhi Kaushik received her B.Tech degree in Electronics andcommunication from Doon Valley institute of engineering andtechnology under Kurukshetra University. At present, she ispursuing her Master in Technology. Her research works includeswireless communication.

0 5 10 15 20 25 30 3510-5

10-4

10-3

10-2

10-1

Eb/No, dB

BitErrorRate

BER for BPSK modulation with Equal Gain Combining in Rayleigh channel


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 510-2

10-1

Eb/No, dB

BitErrorRate

BER for BPSK modulation with all the three techniques in Rayleigh channel

nRx=3 (equal gain)nRx=3 (maximal ratio combining)nRx=3 (selection diversity)

Dr C. M. Jadhao 34


Low Power VLSI CMOS design by DCGTechnique

Dr C. M. Jadhao

Abstract-The demand for power-sensitive design has grownsignificantly in recent years due to tremendous growth inportable applications. Consequently, the need for powerefficient design techniques has grown considerably. Severalefficient design techniques have been proposed to reduce bothdynamic as well as static power in state-of-the-art VLSI circuitapplications. With the scaling of technology and the need forhigher performance and more functionality, power dissipationis becoming a major bottleneck for microprocessor designs.Clock power is significant in high-performance processors.Deterministic Clock Gating (DCG) technique effectivelyreduces the clock power. DCG is based on the key observationthat for many of the pipelined stages of a modern processor,the circuit block usage in the near future is known a few cyclesahead of time. DCG exploits this advance knowledge to clock-gate the unused blocks. Because individual circuit usage varieswithin and across applications, not all the circuits are used allthe time, giving rise to power reduction opportunity. ByANDing the clock with a gate-control signal, clock-gatingessentially disables the clock to a circuit whenever the circuit isnot used, avoiding power dissipation due to unnecessarycharging and discharging of the unused circuits. Results showthat DCG is very effective in reducing clock power. Powerconsumption is reduced by using this method. As high-performance processor pipelines get deeper and powerbecomes a more critical factor, DCG’s effectiveness andsimplicity will continue to be important.

IndexTerms—VLSI, CMOS, DCG, Power reduction, Clockgating.

I. INTRODUCTION

In recent years, the demand for power-sensitive designshas grown significantly. This tremendous demand hasmainly been due to the fast growth of battery-operatedportable applications such as notebook and laptopcomputers, personal digital assistants, cellular phones, andother portable communication devices. Semiconductordevices are aggressively scaled each technology generationto achieve high-performance and high integration density.Due to increased density of transistors in a die and higherfrequencies of operation, the power consumption in a die isincreasing every technology generation. Supply voltage isscaled to maintain the power consumption within limit.

However, scaling of supply voltage is limited by thehigh-performance requirement. Hence, the scaling of supplyvoltage only may not be sufficient to maintain the powerdensity within limit, which is required for power-sensitiveapplications. Circuit technique and system-level techniquesare also required along with supply voltage scaling to achievelow-power designs.

Dr C. M. Jadhao, Principal, Mauli College of Engineering, ShegaonShegaon-444203, India , [email protected]

In the nano-meter regime, a significant portion of the totalpower consumption in high performance digital circuits isdue to leakage currents. Because high-performance systemsare constrained to a predefined power budget, the leakagepower reduces the available power, impacting performance.It also contributes to the power consumption during standbyoperation, reducing battery life. Hence, techniques arenecessary to reduce leakage power while maintaining thehigh performance. Moreover, as different components ofleakage are becoming important with technology scaling,each leakage reduction technique needs reevaluation inscaled technologies where sub-threshold conduction is notthe only leakage mechanism. New low-power circuittechniques are required to reduce total leakage in high-performance nano-scale circuits. A spectrum of circuittechniques including transistor sizing, clock gating, multipleand dynamic supply voltage are there to reduce the dynamicpower. For low-leakage design, different circuit techniquesincluding, dual Vth, forward/reverse bias, dynamicallyvarying the Vthduring run time, sleep transistor, naturalstacking are there.

II. POWER DISSIPATION IN VLSI CIRCUITSThe total power dissipation in a circuit conventionally

consists of two components, namely, the static and dynamicpower dissipation.

A. Dynamic powerFor dynamic power dissipation there are two components

one is switching power due to charging and discharging ofload capacitance. The other is the short circuit power due tothe nonzero rise and fall time of input waveforms. Theswitching power of a single gate can be expressed as

PD = α CL VDD2 f (1)

Where α is the switching activity,f is the operation frequency,CL is the load capacitance,VDD is the supply voltage.

The short circuit power of an unloaded inverter can beapproximately given by

PSC = β (VDD – Vth) 3 τ / 12T (2)Where β is the transistor coefficient,

τ is the rise/fall time,T (1/f) is the delay.

B.Leakage powerThere are three dominant components of leakage in a

MOSFET in the nanometer regime:(1) Sub-threshold leakage, which is the leakage current

from drain to source (Isub).

Dr C. M. Jadhao 35


(2) Direct tunneling gate leakage which is due to thetunneling of electron (or hole) from the bulk silicon throughthe gate oxide potential barrier into the gate.

(3) The source/substrate and drain/substrate reverse-biased p-n junction leakage.

III. DYNAMIC POWER REDUCTION TECHNIQUESThough the leakage power increases significantly in every

generation with technology scaling, the dynamic power stillcontinues to dominate the total power dissipation of thegeneral purpose microprocessors. Effective circuittechniques to reduce the dynamic power consumptioninclude transistor size and interconnect optimization, gatedclock, multiple supply voltages and dynamic control ofsupply voltage. Incorporating the above approaches in thedesign of nano-scale circuits, the dynamic power dissipationcan be reduced significantly. Other techniques such asinstruction set optimization, memory access reduction andlow complexity algorithms are also there to reduce thedynamic power dissipation in both logics and memories.

A. Transistor sizing and interconnect optimizationThe best way to reduce the junction capacitance as well asthe overall gate capacitance is to optimize the transistor sizefor a particular performance. Sizing techniques can bemainly divided into two types.

• Path-based optimization.• Global optimization.

In path-based optimization, gates in the critical paths areupsized to achieve the desired performance, while the gatesin the off critical paths are down sized to reduce powerconsumption.In global optimization, all gates in a circuit are globallyoptimized for a given delay.

B. Clock gatingClock gating is an effective way of reducing the dynamic

power dissipation in digital circuits. In a typical synchronouscircuit such as the general purpose microprocessor, only aportion of the circuit is active at any given time.

Figure1. Single clock, flip-flopbased FSM.Hence, by shutting down the idle portion of the circuit,

the unnecessary power consumption can be prevented. Oneof the ways to achieve this is by masking the clock that goesto the idle portion of the circuit.This prevents unnecessaryswitching of the inputs to the idle circuit block, reducing thedynamic power. The input to the combinational logic comesthrough the registers, which are usually composed ofsequential elements, such as D flip-flops (Fig.1). A gatedclock design can be obtained by modifying the clockingstructure shown in Fig.1. A control signal (fa) is used toselectively stop the local clock (LCLK) when thecombinational block is not used. The local clock is blocked

when fais high. The latch shown in Fig.2 is necessary toprevent any glitches in fafrom propagating to the AND gatewhen the global clock (GCLK) is high. The circuit operatesas follows.

Figure2. Schematic diagram of gated clock designThe signalfa is only valid before the rising edge of the globalclock. When the global clock is low, the latch is transparent,however, fadoes not affect the AND gate. If fais high duringthe low-to-high transition of the global clock, then the globalclock will be blocked by the AND gate and local clock willremain at low. Power saving using gated clock techniquestrongly depends on the efficient synthesis and optimizationof dedicated clock-stopping circuitry. Effective clock gatingrequires a methodology that determines which circuits aregated, when, and for how long. Clock-gating schemes thateither result in frequent toggling of the clock-gated circuitbetween enabled and disabled states, or apply clock gatingto such small blocks that the clock-gating control circuitry isalmost as large as the blocks themselves, incur largeoverhead. This overhead may result in power dissipation tobe higher than that without clock gating.

C. Low-voltage operationSupply voltage scaling was originally developed forswitching power reduction. It is an effective method forswitching power reduction because of the quadraticdependency of switching power on supply voltage.However, since the gate delay increases with decreasingVDD, globally lowering VDDdegrades the overall circuitperformance. To achieve low-power benefits withoutcompromising performance, two ways of lowering supplyvoltage can be employed: static and dynamic supply scaling.In Static supply voltage scaling schemes, higher supplyvoltage is used in the critical paths of the circuit, whilelower supply voltages are used in the off critical paths. InDynamic supply voltage scaling schemes, the highest supplyvoltage delivers the highest performance at the fastestdesigned frequency of operation. When performancedemand is low, supply voltage and clock frequency islowered, just delivering the required performance withsubstantial power reduction.

IV. LEAKAGE POWER REDUCTION TECHNIQUESThe techniques to reduce leakage energy utilizing the

slack without impacting performance can be categorizedbased on when and how they utilize the available timingslack e.g. dual Vthstatically assigns high Vthto sometransistors in non-critical paths at the design time so as toreduce leakage current. The techniques, which utilize theslack in run time, can be divided into two groups dependingon whether they reduce standby leakage or active leakage.Standby leakage reduction techniques put the entire system

Dr C. M. Jadhao 36


in a low leakage mode when computation is not required.Active leakage reduction techniques slow down the systemby dynamically changing the Vthto reduce leakage whenmaximum performance is not needed.

A. Design time techniquesDesign time techniques exploit the delay slack in non-critical paths to reduce leakage. These techniques are static;once it is fixed, it cannot be changed dynamically while thecircuit is operating.

B. Dual threshold CMOS logic:In this logic, a high Vthcan be assigned to some transistors inthe non-critical paths so as to reduce sub-threshold leakagecurrent, while the performance is not sacrificed by using lowVthtransistors in the critical path(s). No additional circuitry isrequired, and both high performance and low leakage can beachieved simultaneously.Different Dual threshold CMOS techniques are

• Changing doping profile.• Higher oxide thickness• Large channel length

C. Run time techniquesStandby leakage reduction techniques place certain sectionsof the circuitry in standby mode (low leakage mode) whenthey are not required.Different Standby leakage reduction techniques are

• Natural transistor stacks.• Sleep transistor (forced stacking).• Forward/reverse body biasing.

Active leakage reduction techniques are intermittently slowsdown the faster circuitry and reduces the leakage powerconsumption as well as the dynamic power consumptionwhen maximum performance is not required. DynamicVthscaling (DVTS) scheme uses body biasing to adaptivelychange Vthbased on the performance demand. The lowestVthis delivered, if the highest performance is required. Whenperformance demand is low, clock frequency is lowered andVthis raised to reduce the run-time leakage power dissipation.In cases when there is no workload at all, the Vthcan beincreased to its upper limit to significantly reduce thestandby leakage power.

D. Cache memoriesCircuit techniques to reduce leakage in cache memories are

• Source biasing scheme.• Forward/reverse body biasing scheme.• Dynamic VDD scheme• Leakage biased scheme• Negative word line scheme

V. Low Power CMOS Logic DesignVLSI designers have different options to reduce the

power dissipation in the various design stages. For example,supply voltage may be reduced through fabricationtechnology, circuit design or dynamically through the systemlevel. Switched load capacitance may be reduced throughtechnology scaling, efficient layout.Circuit design, gate leveloptimization, and system level. Over the last decade,researchers have developed many techniques to reduce powerdissipation in CMOS circuits. The gain obtained from each ofthese techniques depends solely on the application. Some of

this technique may degrade the performance or increase thearea to reduce power. Other techniques may degrade theperformance or increase the area to reduce power. Manymodifications may be applied to the process technology inorder to reduce power dissipation. These modificationsinclude reducing the threshold voltage, reducing minimumgate length, and increasing the number of metal layers.Power dissipation may also reduced by using alternativefabrication technology other than the CMOS process. Thissection reviews low-power CMOS technologies and presentsome of the alternative fabrication technologies for low –power design.

A. Threshold Voltage ReductionUntil recently, the Vth in most CMOS processes has been

set to fairly high potential: 0.7V to 1.0V. For 5V circuitoperation, this has little impact on circuit delay, which isinversely proportional to (Vdd-Vth) 2 andthe main benefit ofsuch a large threshold is that the sub threshold leakage isreduced exponentially. While the total leakage current of achip is still well below the average supply current underoperation, the reduced sub threshold current prolongs theduration the stored charge in dynamic circuits, providingmore robust operation due to longer leakage times. Thus,there have been fewer tendencies to reduce the thresholdsuntil recently, with the decrease of supply voltages to 3.3V,and emphasis on low-power design. The reduction of Vthenables VLSI designers to lower the supply voltage. Thismaintains circuits speed and results in a power reduction.However, the limitation of this technique is that at lowthresholds, the sub threshold currents become significant, ifnot dominant, portion of the average current drawn from thesupply. Previous work has shown the optimal Vth to rangefrom 0.3V down to below 0.1V depending on the conditionsof the circuit operation.

B.Technology ScalingWith every new process generation, the entire lateral and

some of the vertical dimensions of the transistor are scaleddown. This has an immediate impact on reducing powerdissipation, as well as increasing circuit speed. The primaryeffect of process scaling is the reduction of all thecapacitances, which provides a proportional decrease inpower and circuit delays. Device sizes may be reduced tokeep the delay constant over process scaling, which yields aneven larger power reduction. Both gate capacitance andinterconnect capacitance may be expressed as C= W.L (1/tox).The width W, length L, and oxide thickness tox all scalealmost equally by a factor s, so that the total capacitancescales down by the same factor s. Diffusion capacitance is amore complex function of process scaling; however it isreduced by factor between s and s3/2 for a constant supplyvoltage, both the power and circuit delays scale downapproximately by the factor s. Thus, power reduction isaccomplished with no alterations in the circuit design. Asmentioned earlier, not all the vertical dimensions scale down.In particular, the thickness of the interconnect metal isroughly the same across the processes, due to fundamentalprocessing requirements. This increases the fringingcapacitance from the side of the metal to the substrate, andincreases the capacitance between adjacent interconnectsegments. With these secondary effects considered, the

Dr C. M. Jadhao 37


overall capacitance scaling is somewhere below the factor s,and is difficult to accurately characterize without using athree-dimensional simulation model. New technologies fromIBM and Motorola use copper instead of aluminum forinterconnect, because copper has better conductivity andscales down better than aluminum.

C. Increasing Number of Metal LayersFurther power reduction may be achieved by using some

features in today’s more advanced processes; namely, anincreased number of metal layers and a trend towardsallowing stacked vias. If these are used wisely, not only canthe power be reduced, but also the circuit area, and delaytimes. However, utilizing these advancements requiresspecial circuit redesign methodologies. In old fabricationtechnologies with two metal layers, polysilicon has been usedextensively in intercell signal routing, as second-level metalhas been reserved for intercell routing to allow the CAD toolsto perform global routing. In present technologies with moremetal layers, the second-level, and perhaps higher metallayers, can be used for intercell routing. Since the capacitanceper unit area decreases with each higher metal level, usingthe higher metal layers helps reduce the interconnectcapacitance, which already contributes around 30% to theoverall capacitance. That percentage is expected to increasewith future VLSI generations. Also, by allowing stackedvias, the areas of the different gates can be compressed.Moreover, this reduces both the intercell and global routingbecause the terminal connections will be closer.Consequently, most interconnect routes will be reduced inlength. However, condensed routing increases the couplingcapacitance between interconnects, and cancels part of thepower saving previously achieved.

D. Alternative TechnologiesIf the current rate of scaling MOSFET’s were to continue,

devices with lengths of 1nm would be in use in the year2040. A nano-meter of oxide consists of only a few layers ofatoms which approaches fundamental limits. Therefore, somenew device structure will eventually replace the devicesbeing used today. Predictions of when this will happen haveconsistently underestimated the ingenuity of fabricationengineers, and the conclusion is that the end of CMOSscaling is still too far away to accurately predict. However,the limits which are driving current device scaling can givesome insight into what new technology might eventuallyreplace today’s devices. The following technologies seek toaddress the limitations of CMOS MOSFET’s by allowingfurther reductions in the supply voltage and therefore furtherscaling of the device dimension, by providing improvedperformance at same device dimensions, or both.

1) Silicon on Insulator (SOI)The elimination of junction capacitance gives SOI

improved performance at the same device dimensions, andimproved sub threshold slope allows for further deviceScaling. The floating body of SOI devices is a concern forreliability and circuit simulation. It also causes these devicesto have low breakdown voltages which have been a majorroadblock to their use in the past, but as supply voltagescontinue to scale down this may present less of a problem.

2) Multi Threshold Voltage (MTCMOS) Devices

By using low threshold devices for circuits on the criticalpath and high threshold device elsewhere, it may be possibleto achieve high performance, while maintaining reasonableleakage currents. However, very low threshold devices maynot be suitable for the dynamic circuits, which are usuallyused in high speed applications.

3) Low Temperature CMOS (LTCMOS)Reducing the Chip’s operating temperature can enhance

the performance due to improved carrier mobility andreduced wire resistance. It also reduces leakage currentwhich increases exponentially with temperature. This wouldallow technologies to be scaled to smaller dimension. Thedisadvantage is the increased size and cost of the system.

4) Dynamic Substrate BiasingDesigning an on-chip circuit which dynamically varies

the substrate voltage in order to compensate for thresholdvariations helps reduce the leakage current. Dealing withtemperature and process variations across a single die wouldrequire several of these circuits to control isolated substrateregions. In such chips substrate noise would be a majorconcern.

5) New Gate Oxide MaterialReplacing SiO2 with a higher permittivity material would

allow thicker gate oxide films to provide the same control ofthe channel. Fields the oxide layer would be reduced, makingbreakdown less of a concern, and tunneling currents wouldbe reduced. The difficulties with this approach are depositinga very thin very high quality oxide layer rather than simplygrowing a thermal oxide. The Si- SiO2 interface has been thesubject of intensive study for decades and moving to adifferent material would be a very significant change in thefabrication process

VI. CONCLUSION

Deterministic clock-gating (DCG) methodology is basedon the key observation that for many of the stages in amodern pipeline, a circuit block’s usage in a specific cycle inthe near future is deterministically known a few cycles aheadof time. Using this advance information, DCG clock-gatesunused execution units, pipeline latches. Results show thatDCG is very effective in reducing clock power. Powerconsumption is reduced by using this method. As high-performance processor pipelines get deeper and powerbecomes a more critical factor, DCG’s effectiveness andsimplicity will continue to be important. Effective clock-gating, however, requires a methodology that determineswhich circuits are gated, when, and for how long. Care to betaken while designing the clock-gating control circuitry;otherwise the circuitry may become an overhead. Thisoverhead may result in power dissipation to be higher thanthat without clock-gating.

VII. REFERENCES

[1]. Bipul C. Paul, AmitAgarwal, Kaushik Roy, “Low-powerdesign techniques for scaled technologies”, INTEGRATION,the VLSI journal, science direct 39(2006).

[2]. L. Hai, S. Bhunia, Y. Chen, K. Roy, T.N. Vijay Kumar, “ DCG: deterministic clock gating for low-power microprocessordesign ”, IEEE Trans. VLSI Syst. 12 (2004), pp.245-254.

[3]. Yan Luo , Jia Yu , Jun Yang , LaxmiBhuyan, Low powernetwork processor design using clock gating, Proceedings of

Dr C. M. Jadhao 38


the 42nd annual conference on Design automation, June 13-17,2005, San Diego, California, USA.

[4]. Hai Li, SwarupBhunia, Yiran Chen, T. N. Vijaykumar, andKaushik Roy, “Deterministic Clock Gating for MicroprocessorPower Reduction”,1285 EE Building, ECE Department,Purdue University.

[5]. Enoch O. Hwang, “Microprocessor Design Principles andPractices”, Brooks / Cole, 2004.

[6]. Hai Li , Chen-Yong Cher , Kaushik Roy , T. N. Vijaykumar,Combined circuit and architectural level variable supply-voltage scaling for low power, IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, v.13 n.5, p.564-576,May 2005.

[7]. D. Folegnani and A. Gonzalez, “Energy-effective issue logic”,in Proc.28th Int. Symp. Computer Architecture (ISCA), July2001, pp. 230 - 239.

[8]. D. Garrett, M. Stan, A. Dean, “Challenges in clock gating for alow power ASIC methodology”, in International Symposiumon Low Power Electronics and Design, 1999, pp. 176 - 181.

[9]. J. Oh, M. Pedram, “Gated clock routing for low-powermicroprocessor design”, IEEE Trans. Comput. AidedDes.Integr. Circuits Syst. 20 (2001) 715 – 722.

[10]. N. Raghavan, V. Akella, S. Bakshi, “Automatic insertion ofgated clocks at register transfer level”, in: InternationalConference on VLSI Design, 1999, pp. 48 – 54.

[11]. L. Benini, G.D. Micheli, “Automatic synthesis of low powergated clock finite state machines”, IEEE Trans. Comput. AidedDes. Integr. Circuits Syst. 15 (1996) 630 –643.

[12]. R. I. Bahar and S. Manne, “Power and energy reduction viapipeline balancing,” in Proc. 28th Int. Symp. ComputerArchitecture (ISCA), July 2001, pp. 218–229.

[13]. D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: aframework for architectural-level power analysis andoptimizations,” in Proc. 27th Int.Symp. Computer Architecture(ISCA), July 2000, pp. 83–94.

[14]. S. Palacharla, N. P. Jouppi, and J. E. Smith, “Complexity-effective superscalar processors,” in Proc. 24th Annu. Int.Symp. Computer Architecture (ISCA), June 1997, pp. 206–218.

[15]. S. Manne, A. Klauser, and D. Grunwald, “Pipeline gating:speculation control for energy reduction,” in Proc. 25th Int.Symp. Computer Architecture (ISCA), June 1998, pp. 132–141.

[16]. D. Folegnani and A. Gonzalez, “Energy-effective issue logic,”in Proc. 28th Int. Symp. Computer Architecture (ISCA), July2001, pp. 230–239.

[17]. D. Brooks and M. Martonosi, “Value-based clock gating andoperation packing: dynamic strategies for improving processorpower and performance,” ACM Trans. Comput. Syst., vol. 18,no. 2, pp. 89–126, May 2000.

[18]. J. C. Monteiro, “Power optimization using dynamic powermanagement,” in Proc. XII Symp. Integrated Circuits SystemsDesign (ICSD), Sept. 1999, pp. 134–139.

[19]. MassoudPedram “Power Minimization in IC Design:Principles and Applications”, Department of EE-Systems,University of Southern California, Los Angeles CA.

[20]. William M. Johnson “Super-Scalar Processor Design”,Computer Systems Laboratory, Stanford University Stanford,CA, June 1989.

[21]. Ricardo E. Gonzalez “LOW-POWER PROCESSORDESIGN”, Computer Systems Laboratory, Stanford UniversityStanford, CA, June 1997.

[22]. Qing WU “Clock-Gating and Its Application to Low PowerDesign of Sequential Circuits”, Department of ElectricalEngineering-Systems, University of Southern California, LosAngeles, CA, USA.

Dr C M Jadhao, Principal, Mauli Group ofInstitutions College of Engineering andTechnology, Shegaon. 24 years ofTeaching, research and administrativeexperience, Specializations in Fiber optics,VLSI design and Microprocessors.

Sapna Katiyar,Chhavi Tyagi ,Mayank Pratap Tyagi, Deepak Yadav 39


Robot Path Planning In Static Environment Using Ant Colony Optimization

Sapna Katiyar,Chhavi Tyagi, Mayank Pratap Tyagi, Deepak Yadav

Abstract: When a machine or robot moves from one source point to a destination point it is important that it takes an efficient and optimized path. To achieve this goal path planning is done to find an optimized path for a robot which is moving from one point to another. For this, artificial intelligence is used which has various techniques for finding an optimized path. ACO is one of the various techniques from AI which is based on the foraging behavior of the ants. The main motive of path planning is to select an optimized path while moving from source to destination and avoid collision with obstacles (if any) in the path in a static or dynamic environment.

Keywords: Ant Colony Optimization (ACO), Robot Path Planning (RPP).

I. INTRODUCTION Machines are the building blocks of automation. They are

operated by human beings having a control over the machinery systems. But, what if machines can operate and work by themselves. Artificial intelligence made it possible by making machines intelligent that can take decisions by themselves and work even in hazardous and dangerous environment where human intervention is strictly prohibited. So, machines could be an effective option to do work in such kind of environment.

Artificial intelligence made the machines intelligent by implementing some programming in them. The programmed machines can work like the machines used to work under the control of a human. Now, in a working environment a robot has to move from one point to another for any reason for e.g. to transfer material from one point to other etc. So, there are some points necessary for a robot while navigating the route:

1. Direction: in which direction the robot is moving, towards the target or away from it.

2. Path planning: to choose the optimized and efficient path

3. Control over its motion: how the robot is moving towards the destination.

4. Congestion control: to remember what path it has followed and from where it has started.

For the purpose of path planning, ACO is used to develop an algorithm which can be used to find an optimized path for a robot while navigating and to avoid collisions with the obstacles in the path.

ANT COLONY OPTIMIZATION ACO is a heuristic technique which is used to find an

optimized path. It is inspired by the real ants behavior while

searching for food. All ants of a same anthill move along the same path by following one another. This is because every ant releases a substance called “Pheromone” while moving. The other ants sense the intensity of pheromone and follow the path having a higher concentration of pheromone. This is their way to find an optimized path.

Initially the ants wander randomly to find their own way to the destination. Every ant releases pheromone along the path. On their return trip ant senses the pheromone intensity and choose the path having higher intensity of pheromone. The pheromone evaporates with time and hence the concentration of pheromone would be higher along the shortest path as the time taken to cover the shortest path would be minimum as compared to other paths. Hence, almost every ant would be attracted by the higher intensity of pheromone along the shortest path and select the optimized path. This technique can also be applied on the robots to find an optimized path while navigating in an environment.

WORKING ENVIRONMENT There are mainly two types of environment in which a

mobile robot can work: 1. Static environment in which the object does not move

with time i.e. they are static or fixed. 2. Dynamic environment in which the position of object

changes with time i.e. they can move. If the robot has some prior knowledge about its

environment, it is called global path planning and the path can be planned in offline mode even before the robot starts moving.

And if the robot has no prior knowledge about its environment, it is called local path planning. It is done in online mode in which robot has to move in a real world like environment.

ARTIFICIAL ANTS Artificial ants are the mobile robots that are inspired from

the real ants. The movements of the artificial agents are governed by a probabilistic function that depends on heuristic and trail functions. They move in a search space having all possible solutions and generate optimal solutions. Artificial ants prefer paths having higher pheromone concentration. The position of ants and quality of solution is recorded so that better solutions can be obtained in later simulation iterations. METHODOLOGY:

By taking the simplest approach we are solving RPP



problems.

By selecting a 2D grid model ,we are representing here an

environment in which robot has to move from source to destination. It is a map consists of a 100x100 square dimension. The X-axis is divided into 100 equal parts and the Y-axis is also divided into 100 equal parts. Each side of a cell is of unit length. The origin or the source point of the robot is at the coordinate (0, 0) and the target point at coordinate (100,100). An obstacle of rectangular shape is placed at the coordinates (70,70) and (90,90) as diagonal. The mobile robot has to reach the target from the source point by avoiding any collision with the obstacle along the optimized path using Ant Colony Optimization algorithm.

SELECTING A NODE- Initially the robot is at source point and has to move

towards the destination. The robot has to select its proceeding node to move towards the target. The node will be chosen on the basis of a probability formula. The formula includes heuristic equation and pheromone intensity equation.

The heuristic equation: Heuristic= [1/distance between next node and the

intersection point at reference line]*β …(1) where, β= heuristic coefficient The heuristic equation or visibility equation represents the

distance between selected adjacent nodes with intersect point at reference line and the line from that intersection point must be perpendicular to the node i.e. Distance A. A perpendicular is a shortest distance between two points and hence minimum the distance A, the path will get more closer to the reference line and would be the optimized one. For example, let’s take start point (1,1) and goal point(4, 4).the green node(3,2) is a candidate node for which distance has to be calculated.

Distance A=Sin θ*Distance B =Sin θ* sqrt[(y2-y1) ^2+(x2-x1) ^2] = Sin 45* sqrt[(2-2) ^2+(3-2) ^2] = 0.7071*1 = 0.7071 Visibility = [1/0.7071]1 =1.4142 Pheromone or trail equation: Trail= [trail//Σ trail] α …..(2) Where, α=trail coefficient From equations (1) and (2) Probability ij (t) = Heuristic ij(t)*Pheromone ij (t) = (1 / distance between next node and the

intersection point at reference line)β * (trail / Σ trail)α …..(3)

where, the ij is the location of the node under investigation

at time t. LOCAL UPDATING

The pheromone gets evaporated with time. Hence, the pheromone amount will be reduced at all the nodes locally by the given evaporation rate using the formula of update local rules

t ij(new trail) ←(1-ρ)* t ij (old trail) where, ρ=evaporation rate Local updating is important because it prevents the

unlimited accumulation of pheromone on the map and to avoid confusion while selecting a node by sensing the pheromone intensity which could lead to a wrong decision taken by the robot.

GLOBAL UPDATING When an ant reaches the destination, it carries the

information like path cost ant takes to traverse from source to destination, address of the nodes passed while moving. The information carried by the ant is fetched and the intensity of pheromone is updated or increased only on the nodes passed by the ant.

tij ← tij + Σ Δ tijk



where, Δ tijk is the amount of pheromone deposited by an ant on the path it has visited.

Hence, the intensity of pheromone is increased only along

the path travelled by the ant .Which is then used to choose the optimized path from all the available traversed paths by sensing the pheromone intensity.

ANT COLONY OPTIMISATION ALGORITHM: There are so many algorithms which have being proposed

to solve RPP problems since the evolution of path planning in 1980. Here, an algorithm is proposed for robot path planning using the concept of ACO. This algorithm would used to find an optimized path in a static environment while avoiding any collision with the obstacles encountered in the path.

The process is divided in the following steps: 1. Initialize the value of starting and target points. The

robot must know from where to start and where to reach.

2. On the basis of probability function given by eq.(3) select an appropriate node.

3. Now, check if an obstacle has encountered. If yes then select another node to avoid collision. And move to the selected node. Else simply move to the node selected in step 2.

4. The robot must know what path it is taking. For that it has to store the address of every node the robot has gone through in an array.

5. Now, the information about path taken etc by him must be fetched out every time it reaches the goal.

6. Local updating will be done. In local updating the pheromone evaporation will be done as described earlier.

7. Global updating will be done to update the pheromone concentration on the path traversed by the robot.

8. By selecting the best path so far, we can get an optimized path after sufficient iterations

Algorithm pseudo code Do For iteration=1, 2, ….. N Do For ant=1,2, …. K Do For step=1,2, …. M Compute the probability of the kth ant’s next

node. Move to a next node by the computed probability Store the history of past node locations in an array If the current location is equal to the end point End End Obtain the path passed Update the pheromone evaporated on the entire map Compute and update the pheromone amount generated

by the kth ant on the path traversed If there are sufficient iterations has done to get an

optimized path End



IMPLEMENTATION The pseudo code will be converted into the MATLAB code

implemented by using available functions in MATLAB.

II. CONCLUSION After performing a sufficient number of iterations the optimized path is obtained which is effective for path cost reduction, consumes less power and shorten computation time. Hence contribute to the total cost reduction for a robot to work in an environment.ACO comes out to be the most effective technique to find an optimized and effective path without colliding with the obstacles comes into the path.

.

ACKNOWLEDGMENT We take this opportunity to express our sincere thanks and

deep gratitude to all those people who extended their wholehearted co-operation and have helped us in completing this project successfully. Their works and text have been the source of inspirations and guidance to us in the research.

Also we would like to thank all the visible and non visible hands which helped us to complete our research with great success.

REFERENCES

REFERENCES: [1]. Dorigo, M. and Stutzle, T. (2004). Ant Colony Optimization.

Massachusetts Institute of Technology. [2]. Gengqian, Tiejun L, P. Yuqing L, .Xiangdan P, The ant

algorithm forsolving robot path planning problem. in 3rd Int. Conf. on Information Technology and Applications (ICITA). 2005.

[3]. Dorigo, M., L. M. Gambardella, Ant colony system: A CooperativeLearning Approach to the Traveling Salesman Problem(TSP). IEEE Transactions on Evolutionary Computation, 1997.

[4].Buniyamin N., Sariff N., Wan Ngah W.A.J., Mohamad Z., Robot global path planning overview and a variation of ant colony system algorithm, International journal of mathematics and computers in simulation.

[5]. Michael Brand, Michael Masuda, Nicole Wehner, Xiao-Hua Yu, Ant Colony Optimization Algorithm for Robot Path Planning, 2010 International Conference On Computer Design And Appliations (ICCDA 2010)

[6]. Yogita Gigras, Kusum Gupta, Artificial Intelligence in Robot Path Planning, International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-2, May 2012.

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