SATEL in a nutshell

Founded in 1986 by Pekka Aura and two other persons

65 employees (R&D:20, production 30, sales:10)

Revenue aprox 14 M €, 90% export, 20 000...30 000 units / annum

Traditional company: company own its own premises and tools etc.

Mimimal amount of outsourcing: R&D, sales, marketing, production and testing in-house

on a single site.

SATEL is privately owned. PASATEL Oy (Pekka Aura, founder and CEO) and the Tapiola Insurance Company are the main owners, with around 93 % of the shares.

SATEL is an ISO 9001 / 2000and ISO14001 / 2004 certified company

Manufacturer of narrow band radio modems in VHF and UHF bands

Key Application AreasUtilizing differential GPS in surveying and construction worksLand surveying

Fleet management and traffic control

Active traffic light control, traffic sign control, locating vehicles on duty

Agriculture Utilizing differential GPS in Precise farming and irrigation

SCADA applications (distribution networks)

Power networks, fresh and wastewater, oil and gas pipeline management

Alarm systems and automated meter reading Building alarm systems, power meter reading

Logistics Warehouses, harbours, work vehicles maintenance, construction sites

Remote control and reading Weather stations, snowguns, radiation, seismographic, water level meters, windfarms etc.

CASE:SATELLAR Digital System

•New generation of radio modems•Digital radio (400...520 MHz)

•Main feature: long distance narrowband radio links• Data transfer:

•Async data: RS232, RS485, RS422(Radio unit)•Packet data: TCP/UDP IP transer (Ethernet)

• Modular approach:• Radio unit• Central unit • Extension units

SATELLAR radio unit• Stand-alone, digital, UHF radio unit• Carrier frequency: 360….520 MHz (covered by freq variants)• RF tuning range: 45 MHz• Channel spacing: 12.5 kHz / 25 kHz• Modulation method: 2FSK, 4FSK, 8FSK, 16FSK• Data rate : 4800…38400 bps• RF output power: 100 mW…1 W• RF sensitivity: -115 dBm• FEC: OFF / 67% / 50%• Encryption: AES 128-bit, CTR-mode• Network Management System• Over-the-Air software update• Interface: RS-232 / RS-485

SATELLAR Central Unit (CU)

• 200 MHz CPU• 64 MB RAM• 128 MB Flash• Linux OS• Color display and keypad• Ethernet and USB • TCP/IP support:

– IP-routing– Firewall (iptables)– QoS– UDP, SNMP, SSH, http, etc.

Internal construction (radio unit)BB board

RFboard

Interface board

Previous test scenario• Previous products where a lot simpler

and not as modular. • Less demanding packaging

(TQFP, 0603 etc.)

• Verification relies heavily on visual inspection• RF board is tested during a manual operator

driven tuning /alignment procedure (most fails are found and repaired here).

• BB board is tested when flashing the board. • The assembled product is subjected to functional

tests (RF measurements, data transfer tests etc.)

Previous production cycle, 3AS product

Pick & place + soldering

visual inspection

Manual soldering of thru hole components

RF board

ManualRF tuning/alignment

Product assembly

Pick & place + soldering

visual inspection

Manual soldering of thru hole components

BB board

Firmware flashing

Modem to modem data transfer test

Verification of RF parameters

Custom settings / packing + shipment

Reasons for boundary scan• Visual inspection depends on operator alertness

-> unreliable -> should be minimized• Higher density packing (0402, uBGA, CSPs etc.)

BGAs and CSPs => visual inspection impossible• Increased part count/board (statistically more

prone to errors) -> errors should be caught early.• Flexible end product, all HW functions do not have

functions at time of product launch (unit to unit bus) -> functional testing not possible

• Good board level test coverage => less disassembly / repair / rework on assembled products

Production cycle, SATELLAR Radio Unit

Pick & place + soldering

visual inspection

JTAG- Boundary scanJTAG- firmware loading

RF board

AutomaticRF tuning/alignment

Product assembly

Pick & place + soldering

visual inspection

JTAG- Boundary scanJTAG- firmware loading

BB board

Verification of RF parameters

Custom settings / packing + shipment

Block diagram of Radio Unit BB board

FPGA(LATTICE MACHXO)

MCU (ARM ST STR9)

DC/

DC

INTERFACE BOARD(20 PINS, 2MM PITCH)

SATBUS

DSP(ANALOG DEVICES BLACKFIN)

RF/BB INTERFACE(32 PINS 2MM PITCH PIN HEADER)

POWERMANAGER

(LATTICE PWR607)

CA

N-B

US6*BLVDS2*CMOS12*CMOS8....30V

DC

2*SPI

SPI, ”SSI”, DISCRETE SIGNALS ETC.

2*SPI

SPI FLASH

6V, 3.6V

1,2V

1,8V

3,3V

Challenges in test design

• Same test station tests 4 different boards (future boards), changeable test fixtures

• I/O connector interfaces included in testing• LVDS + TTL signals in interfaces• PANEL testing, 4 boards per panel (aprox 70test probes

per board =280 test points / panel.• Testpoints/contacts on both sides of board• STR ARM processor => multichip module (ARM, FLASH,

debugger) treated as a separate board. • 1532 device, no .ISC files

Solving the JTAG Challenges in test design

• ST device is MCM. 3 separate BSDL files. Netlist createdby hand. Once netlist is created very easy to handle in ProVision. MCM becomes just another board in the project.

• Device does have IEEE 1532 registers BUT is not fully compliant.

• No IEEE 1532 extensions in the supplied BSDL file –these were written manually based on the programming manual

• JTAG Technologies created an intel HEX to ISC convertor. After that device is treated as normal 1532 device

STR91xFADevice has 2 different

chain configurations:

• Normal Mode with all 3 devices in chain

• Turbo-mode where ARM core is physically bypassed

• TCK frequencies supported are different between modes

System chain configuration 1

System chain configuration 2

I/O and LVDS Testing

• Normal I/O is tested through DIOS type of connection• LVDS part is tested through Special DIOS with LVDS

capabilities from GEB.• FPGA needs to be programmed with special file into the

SRAM part (volatile)• configured BSDL needs to be created• Special LVDS DIOS is used and the test is a simple

board to board interconnect.• Tests are carried out Single ended and Differential to

improve diagnostic capability. Differential is in effect a functional test.

Test setup in detail

TEST SETUP

AGILENT DMM / CROSS CONNECT MATRIX

TEST PC(PCI JTAG CONTROLLER)

AGILENT DC SOURCE

ETHER

NET / LXI

CHANGEABLE TEST FIXTURE

GEB SIMPLEXJTAG MUX

JTAG POD1 2 3 4

DUT 1

DUT 2

DUT 3

DUT 4

JTAG

CMOS, LVDS IO/TEST SIGNALSTEST POINTS, POWER ETC.

The tester

Check DUTs present Check DUTs present

Measure DC voltages from testpoints and IO connectors

Measure DC voltages from testpoints and IO connectors

JTAG - BSCAN INFRASTRUCTURE TEST

JTAG - BSCAN INFRASTRUCTURE TEST

JTAG - ERASE FPGA AND POWERMANAGER

JTAG - ERASE FPGA AND POWERMANAGER

CYCLE DUT POWERCYCLE DUT POWER

JTAG – BSCAN PULLDOWN AND INTERCONNECT

JTAG – BSCAN PULLDOWN AND INTERCONNECT

TEST CAN BUS INTERFACE (JTAG + DMM)

TEST CAN BUS INTERFACE (JTAG + DMM)

JTAG - INTERCONNECT TEST FOR TTL IO

JTAG - INTERCONNECT TEST FOR TTL IO

TEST SEQUENCE FOR NGUC BOARD

JTAG – PROGRAM FPGA FOR LVDS TEST

JTAG – PROGRAM FPGA FOR LVDS TEST

JTAG – INTERCONNECT FOR LVDS SIGNALS

JTAG – INTERCONNECT FOR LVDS SIGNALS

JTAG – SET STR PROCESSOR TO TURBOMODE

JTAG – SET STR PROCESSOR TO TURBOMODE

CYCLE DUT POWERCYCLE DUT POWER

JTAG – PROGRAM SPI FLASHJTAG – PROGRAM SPI FLASH

JTAG – PROGRAM FPGA FOR STR PROGRAMMING

SUPPORT

JTAG – PROGRAM FPGA FOR STR PROGRAMMING

SUPPORT

JTAG – PROGRAM STR IN TURBOMODE

JTAG – PROGRAM STR IN TURBOMODE

JTAG – PROGRAM PRODUCTION CODE

(FPGA AND POWERMANAGER)

JTAG – PROGRAM PRODUCTION CODE

(FPGA AND POWERMANAGER)

The operator user Interface.

CONCLUSIONS• Benefits:• 1. Created a means to test soldering that can not be

inspected visually• 2. Created a means of flash programming of devices on

the board• 3. Created a means for early rather than late fault

detection in production process• 4. Created a flexible method of testing (4+ units with

same test HW)• 5. Fast, reliable and good test coverage• 6. Same test interface can be used in production and

service

Next steps

• Future SATEL products will be ”JTAG enabled”whenever possible, and will be tested with the same tester

• Improve speed of flash programming • Better test coverage of mixed signals boards (RF boards)

using ”virtual tests”.

CREDITS:• FIXTURE MECHANICS: IT-LINE, SALO FINLAND

http://www.it-line.fi

• LABVIEW PROGRAMMING: TESTHOUSE ENKOhttp://www.enko.fi/

• JTAG TEST VECTORS: JTAG TECHNOLOGIES / JARKKO SALANNEhttp://www.jtag.com/

• PROJECT SPECIFICATION, PLANNING AND SUPERVISION: SATEL OY / KALLE SUOMINENhttp://www.satel.com/

THANK YOUQuestions?