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User Guide

SC15Eval3 Board Kit

PRELIMINARY INFORMATIONRELEASED UNDER NDA ONLY

BD-01996-001_v01

ii BD-01996-001_v01NVIDIA CONFIDENTIAL 9/15/05

SC15 Eval3 Board Kit User GuidePROPRIETARY INFORMATION

Preliminary InformationSC15 Eval3 Board Kit User Guide v01 Provided Under NDA

Contents

Chapter 1 SC15 Evaluation Kit ............................................................................. 1-1

1.1 Introduction ...........................................................................................................................1-1

1.2 Applicable Documentation .....................................................................................................1-1

1.3 SC15 Evaluation Board Kit Contents .......................................................................................1-1

1.4 Evaluation Board Kit Features .................................................................................................1-1

Chapter 2 SC15 Evaluation Board ......................................................................... 2-1

2.1 Introduction ...........................................................................................................................2-1

2.2 SC15 Evaluation Board Features .............................................................................................2-2

2.3 SC15 Evaluation Board Diagrams ...........................................................................................2-2

Chapter 3 Functional Overview ............................................................................ 3-1

3.1 Feature Overview ...................................................................................................................3-13.1.1 Reset .......................................................................................................................3-23.1.2 I2C Source ...............................................................................................................3-23.1.3 Power ......................................................................................................................3-23.1.4 SD ............................................................................................................................3-23.1.5 Camera ....................................................................................................................3-2

Chapter 4 Power Management .............................................................................. 4-1

4.1 SC15 Power Rails ...................................................................................................................4-1

4.2 Software Power Management .................................................................................................4-3

4.3 Software Power Rails Adjustment ...........................................................................................4-3

Chapter 5 Evaluation Board Configuration .......................................................... 5-1

5.1 Hardware Configuration .........................................................................................................5-15.1.1 Switch Bank Configuration Details ............................................................................5-2

5.2 Software Configuration ..........................................................................................................5-55.2.1 I2C/SPB Address Map ...............................................................................................5-55.2.2 Modes Summary ....................................................................................................5-10

5.2.2.1 Manual Mode .........................................................................................5-105.2.2.2 Auto Mode .............................................................................................5-10

5.3 Jumpers ...............................................................................................................................5-11

5.4 Clock Headers ......................................................................................................................5-12

NVIDIA Proprietary and Confidential 3

Preliminary InformationProvided Under NDA SC15 Eval3 Board Kit User Guide v01

Chapter 6 Software Mapping ................................................................................ 6-1

6.1 Software Mapping ..................................................................................................................6-1

Chapter 7 SC15 Module ........................................................................................ 7-1

7.1 Introduction ...........................................................................................................................7-1

7.2 SC15 Module Components .....................................................................................................7-2

7.3 SC15 Module Interface Details ................................................................................................7-3

Chapter 8 LCD Module Description ...................................................................... 8-1

8.1 Introduction ...........................................................................................................................8-1

Appendix A Schematics ...........................................................................................A-1

4 NVIDIA Proprietary and Confidential

Preliminary InformationSC15 Eval3 Board Kit User Guide v01 NDA Required

Revision History

Date Revision Description

09/15/05 Advance v01 First version of document.

NVIDIA Proprietary and Confidential Revision History 5

Preliminary InformationNDA Required Revision History

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6 Revision History NVIDIA Proprietary and Confidential


Chapter 1 SC15 Evaluation Kit

1.1 Introduction

The NVIDIA® SC15 Evaluation Board Kit enables SC15-specific development and evaluation.Its modular design supports all SC15 module variants and legacy interfaces.

1.2 Applicable Documentation

To further support use of the SC15 Evaluation Board Kit, use this document along with

• SC15 Technical Manual and Data Sheet (NVIDIA document DP-01433-001)

1.3 SC15 Evaluation Board Kit Contents• SC15 Evaluation Board• SC15 Module

• 600-80436-0002-100 PCB Assembly for SC15-NM version• 600-80436-0000-100 PCB Assembly for SC15-8ME version• 600-80438-001-000: SC15 with 640KB eSRAM and additional, external DDR

memory

• NVIDIA LCD Module• 600-80431-0000-000 PCB Assembly with Optrex 320 x 240 LCD panel

• Omnivision OV9650 1.3Mpixel camera• PCI32B-BCA5 Standard Windows PC PCI Card

1.4 Evaluation Board Kit Features

Figure 1.1 shows the SC15 Evaluation Board Kit. The main platform is the SC15 EvaluationBoard, used with the SC15 module (which contains an SC15.) Because the SC15 is availablewith different memory configurations, the SC15 module comes with one of the differentconfigurations on it. (Choose the SC15 module corresponding to the version of SC15chosen for your design.) An LCD module completes the kit. The camera module is optional,as the Evaluation Board comes with a camera already mounted on it.

NVIDIA Proprietary and Confidential SC15 Evaluation Kit 1-1

Preliminary InformationNDA Required SC15 Evaluation Kit

tal

t

Figure 1.1: SC15 Evaluation Board Kit Block Diagram

Camera Module

VI Connector

Host_I2C

Stereo

Host Interface

LCD

E433: SC15 Evaluation Board

GPIO/IO

Power I2C/ SYS _CLK

I

Power

Host Bus

LCD

SC15_I2C

I2 C PLL

I2C

SDRAM

mux

SC15_I2C

XTLI2C

EPROM

SC15

SC 15 ModuleCard Connectors

MICTOR

CameraVI Header

Debug Header

Debug Header

Strap_SW

Pow

er H

dr EperimenPowerModule

On-boardSummit

Power SupplyProgrammable PLL

Chrontel 7013B TVout

Encoder

Debug Header

Debug HeaderSTAC9766

AC97

Wolfson8731I2S

IPU Interface (16bit)MUX

MUX

S-Video

MUX

Line In

Line Ou

Mic

I2S

SD Card

1-2 Evaluation Board Kit Features NVIDIA Proprietary and Confidential


Chapter 2 SC15 Evaluation Board

2.1 Introduction

The NVIDIA® SC15 Evaluation Board Kit has been developed for SC15-specific developmentand evaluation purposes. Its modular design supports all SC15 module variants and legacyinterfaces. Basic features of the E433 follow:

Highly configurable operational modes

• Software programmable through I2C• Manual mode through Switches and Jumpers

Host configuration support for

• Type A and Type C interfaces• 32Bit and 16bit interfaces• Indirect and direct addressing modes• IPU interface: 16bit, type C

Peripheral devices and interfaces supported

• I2S Audio using Wolfson WM8731 codec• AC’97 Audio using SigmaTel CODEC • SD Socket with insert detect and write protect• OV 9650 camera module and generic camera interface connector • LCD Interface Connector• JTAG, DSP JTAG• Variable power supply for each rail• SVideo out using Chrontel CH7013B• NTSC and PAL outputs

Modules used with the SC15 Evaluation Board, which enable its use as part of a completekit include the following:

• SC15 Module• 600-80436-0002-100 PCB Assembly for SC15-NM version• 600-80436-0000-100 PCB Assembly for SC15-8ME version• 600-80438-001-000: SC15 with 640KB eSRAM and additional, external DDR

memory

• NVIDIA LCD Module• NVIDIA Camera Module

NVIDIA Proprietary and Confidential SC15 Evaluation Board 2-1

Preliminary InformationNDA Required SC15 Evaluation Board

2.2 SC15 Evaluation Board Features

• Uses PC/PLX PCI card - performance benchmark• SC15 Module connection to support both rapid design change and different revisions

or SKUs of SC15• SC15 peripheral components:

• SDRAM/DDR on board (with optional Mictor)• XTL clock source• External CLK input as primary source (need GFSDK approval) • Power measurement Test Points

• Major components • LCD panel connector • Low profile camera I/F connector

• Audio CODECs (AC’97/I2S) with connectors• Mictor for host and connector for I2S• I2C programmable core & I/O power supplies; and manual control with

external card for bring-up• SD card• SC15 GPIO connector for power control• Host Interface connector (PLX I/O PCI card)• JTAG• I2C PLL OSC as SC15 external clock• NTSC encoder for VGA output• PAL support• Board automation for bus type/width selection

2.3 SC15 Evaluation Board Diagrams

The two figures in this section, Figure 2.1 and Figure 2.2, show the physical layout of theSC15 Evaluation Board from both the top and bottom view, for easy reference.

2-2 SC15 Evaluation Board Features NVIDIA Proprietary and Confidential


P

LC

Mic

Clo

Figure 2.1: SC15 Evaluation Board Top View

LCD/Observation

Bus Analyzer I/F

Configuration

Switch Banks Host Bus

Analyzer I/F

Video Input

Analyzer I/F

SC15Module

Connectors

anel IO

S-VideoTV Out

D ModuleInterface

rophone

Line Out

Line In

JTAG Port

On-BoardCamera

Camera ModuleInterface

JTAG

ExternalInputs

Status LEDsStatus LEDS

NVIDIA Proprietary and Confidential SC15 Evaluation Board Diagrams 2-3

Preliminary InformationNDA Required SC15 Evaluation Board

Figure 2.2: SC15 Evaluation Board Bottom View

2-4 SC15 Evaluation Board Diagrams NVIDIA Proprietary and Confidential


Chapter 3 Functional Overview

3.1 Feature Overview• Host interface• Wireless Media Processor Module Support• Video input

• On-board Camera• Camera Module Connector

• LCD Display Support• TVout• Audio

• I2C Codec• AC97 Coded

I2C Control Bus

• Clocking• Power

• Power Management• Power module

• Debug support• JTAG

• Standard• DSP JTAG

NVIDIA Proprietary and Confidential Functional Overview 3-1

Preliminary InformationNDA Required Functional Overview

3.1.1 Reset

The Maxim 6306UK4.4 is used to generate a 200 ms reset. The reset is triggered threeways:

• Turning on the PCI32B-BCAx • Depressing the SW1 push button• Issued by JTAG debugger• Issued by Host GPIO.

3.1.2 I2C Source

There are two sources for the I2C interface:

• Host I2C• SC15 I2C

The default is the Host system. The User must configure SW3-7 to use the SC15’s I2C.

3.1.3 Power

All power rails of the SC15 are controlled by high-precision voltage regulators (SMB120 orSMB113.)

• The voltage levels can be programmed via I2C• SMB120 and SMB113 are accurate to +/- 50 mV of the programmed voltage value • Core voltage regulators are all controlled by the Summit SMB113, at address 0x84h.• Host and SD card IO voltages are controlled by the SMB120 at address 0x80h• LCD, camera, audio Codec, and DRAM memory IO voltages are controlled by the

SMB113 at address 0x88

3.1.4 SD

Two of SC15’s GPIOs are used in the following configuration:

• SD Detect on SGPO0 of SC15• True = 1• False = 0

• Write Protect SGPO1 of SC15• True = 1• False = 0

3.1.5 Camera

The SC15 Evaluation Board supports an on-board camera, the Omnivision OV96501.3 Mpixel CMOS sensor.

A customer-specific camera board may be installed and tested by using the expansionconnector on the SC15 Evaluation Board.

The SC15 controls the I2C for these two modules.

3-2 Feature Overview NVIDIA Proprietary and Confidential


Chapter 4 Power Management

4.1 SC15 Power Rails

This section highlights the SC15 power rails, adjustment of those rails, and softwarepower management of the SC15.

• SC15 Power Requirements• AOCVDD 1.2*.15=0.18 W• MMCVDD 1.2*.08=0.096 W• VECDD 1.2*.45=0.54 W• TDCVDD 1.2*.3=0.36 W• I/O pads ~ Ave 2.5*.1=0.25 W

Total Power = 1.4 W

• System• CODECS (AC’97) • 3.3*0.1=0.33 W + 5.0*0.08=0.26 W• SD card =3.3*0.1=0.33 W• 100 mW - 400 mW based on camera• MDDR (x32) = 1.8*0.08 = 0.15 W (REF mode)• Display (0.5-1.5 W) BL “ON”• SC15= 1.4 W

Card Operating Power~ 1.4 W+2.65 W = 4.0 W

NVIDIA Proprietary and Confidential Power Management 4-1

Preliminary InformationNDA Required Power Management

Figure 4.1: SC15 Power Rails

VBAT

TDCVDD MMCVDD

AOCVDD

VECVDD

EMVDDEMVDD

EMVDD EMVDDHVDD HVDD

SDVDD

HVDD

VVDD

LVDD

LVDD

HVDD

EMVDDEMVDD

CorePower Supply

AOCVDD

SW1

SW2

SW3

[email protected]

LVDD

SDVDD

EMVDD VVDDHVDD

AVDDOSC

Display SD Card EMC Camera Host I/O Audio

ACVDD

3.3V-2.5V 3.6V-2.7V 3.3V-1.8V 2.5V-1.8V 3.3V-1.8V 3.3V-2.5V

ACVDD

(150mA)

MMCVDD (80mA)

VECDD (450mA)

TDCVDD (300mA)

2mA

4-2 SC15 Power Rails NVIDIA Proprietary and Confidential


4.2 Software Power Management

4.3 Software Power Rails Adjustment

Use the I2C to adjust the following supply voltages.

Table 4.1: Software Power Management Configuration

U30 Control 0 1 DescriptionIO-0.3 AOCVDD ON OFF Main core voltage On/OffIO-0.4 VECVDD ON OFF Video core voltage On/OffIO-0.5 TDVCDD ON OFF 3D core voltage On/OffIO-0.6 MMCVDD ON OFF Embedded memory voltage On/OffIO-0.7 SDVDD ON OFF SD Interface voltage On/OffIO-1.0 VVDD ON OFF Camera Interface voltage On/OffIO-1.1 DPD_ DPD

modeNormal SC15 DPD mode

IO-1.2 POWER_EN Plugged Unplugged

As Input, allows software to read if an SC15 module is plugged onto the Evalua-tion Board.

IO-1.3 LDVDD ON OFF Display Interface voltage On/OffIO-1.4 AVDDOSC ON OSC Crystal oscillator voltage On/OffIO-1.5 AVDDP1 ON OFF PLL0 voltage On/Off

(May use to control EMCVDD on this bit if PLL voltage control is not required.)

IO-1.6 AVDDP2 ON OFF PLL1 voltage On/Off (May use to control EMCVDD on this bit if the PLL voltage control is not required.)

IO-1.7 HVDD OFF ON Host Interface voltage On/Off (should be provided as default by host)

Table 4.2: Software Power Management Configuration

U30 Control DescriptionU67 AOCVDD Main core voltage level controlU66 VECVDD Video core voltage level controlU69 TDVCDD 3D core voltage level controlU71 MMCVDD Embedded memory core voltage level

controlU40 VVDD Camera Interface voltage level controlU36 AVDDP1 PLL0 voltage level controlU37 AVDDP2 PLL1 voltage level control

NVIDIA Proprietary and Confidential Software Power Management 4-3

Preliminary InformationNDA Required Power Management

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4-4 Software Power Rails Adjustment NVIDIA Proprietary and Confidential


Chapter 5 Evaluation Board Configuration

5.1 Hardware Configuration

Configure the Evaluation Board by switch banks and jumper settings detailed in thischapter. Switch banks S2, S3, S4, and S5 are located as shown in Figure 5.1.

Figure 5.1: SC15 Evaluation Board Switch Banks

1 2 3 4 5 6 7 8

ON

1 2 3 4 5 6 7 8

ON

1 2 3 4 5 6 7 8

ON

1 2 3 4 5 6 7 8

ON

S2

S4

S3

S5

NVIDIA Proprietary and Confidential Evaluation Board Configuration 5-1

Preliminary InformationNDA Required Evaluation Board Configuration

5.1.1 Switch Bank Configuration Details

Configure the Evaluation Board using switch banks S1, S2, S3, and S4. Details for doing sofollow. In each table, shaded cells indicate default configuration settings.

Table 5.1: Switch Bank S2: Auto and Manual Configuration

Name Configuration Description Switch Function1 AUTO / MANUAL

OVERRIDEON = Normal All SC15 and board control sig-

nals are controlled by switch S3.

Auto Override of board configura-tion: If this switch is set to OFF, the controls are configured by software only using SPB.OFF = Override All SC15 and board control sig-

nals are controlled by SPB GPIO expander. This switch position overrides other switches of S2.

2 MODE(partial auto mode)

ON = Manual MOD pins controlled by SW4 SC15 MOD pins HW or SW config-uration: This switch has effect only when S2-1 is ON

OFF = Auto MOD pins controlled by SPB GPIO expander

3 BUS WIDTH 16 / 32(partial auto mode)

ON = Manual 16-bit/32-bit Host I/F con-trolled by SW4

16bit or 32bit Host I/F HW or SW configuration: This switch has effect only if S2-1 is ONOFF = Auto 16-bit/32-bit Host I/F con-

trolled by SPB GPIO expander4 BUS TYPE C

EMULATION(partial auto mode)

ON = Manual Type C controlled by SW4 Type C HW or SW configurationThis switch has effect only if S2-1 is ON.

OFF = Auto Type C controlled by SPB GPIO expander

5 VARIABLE LATENCY(partial auto mode)

ON = Manual Variable latency controlled by S3. Only supported in certain Host platforms. Please refer to schematics for more details.

Variable latency HW or SW config-uration: This switch has effect only if S2-1 is ON.

OFF = Auto Variable latency controlled by SPB GPIO expander

6 SPARE ON = GND N/A Programmable I/O. Defaults as input pulled low.OFF = Pull up N/A

7 No Function N/A N/A N/A - No Function8 INDIRECT

ADDRESSING REMAPON = LSB SC15-A[3:2] address bits are

controlled by Host A[3:2]In Indirect mode configuration SC15 address bits A2 and A3 can be shifted to higher bits for easier address and data mapping by the software

OFF = MSB SC15-A[3:2] address bits are controlled by Host A[22:21]

5-2 Hardware Configuration NVIDIA Proprietary and Confidential


Table 3.2 details the settings of switch bank S3 for setting various host mode controlconfigurations.

Table 5.2: Switch Bank S3: Host Mode Configurations

Name Configuration Description Switch Function1 MODE BIT 0 ON = Low MOD0 = 0 SC15 MOD0 pin HW control

This switch has effect only if S2-1 and S2-2 are ON

OFF = High MOD0 = 1

2 MODE BIT 1 ON = Low MOD1 = 0 SC15 MOD1 pin HW controlThis switch has effect only if S2-1 and S2-2 are ON

OFF = High MOD1 = 1

3 MODE BIT 2 ON = Low MOD2 = 0 SC15 MOD2 pin HW controlThis switch has effect only if S2-1 and S2-2 are ON.

OFF = High MOD2 = 1

4 MODE BIT 3 ON = Low MOD3 = 0 SC15 MOD3 pin HW controlThis switch has effect only if S2-1 and S2-2 are ON.

OFF = High MOD3 = 1

5 BUS 16/32 ON = 16Bit MOD4 = 0 SC15 Host I/F bus width configu-ration.This switch has effect only if S2-1 and S2-3 are ON

OFF = 32Bit MOD4 = 1

6 BUS TYPE CEmulation

ON = Type C Host I/F emulates Type C SC15 Host I/F type configuration This switch has effect only if S2-1 and S2-4 are ON.

OFF = Type A Host I/F emulates Type A

7 VAR LAT WRITE ON = Dedicated Dedicated WR2n signal for vari-able latency

Allows using a dedicated Write signal for variable latency (avail-able only on some platforms).Usually the same WRn signal is used for fixed and variable latency (let switch to OFF).This switch has effect only if S2-1 and S2-4 are ON

OFF = Standard Single WRn signal for fixed and variable latency

8 INDIRECT ADDR/DATA CON-TROL

ON = A1 Host A1 is the address/data control

SC15-A2 configuration in indirect mode.It can be controlled by Host A1 or A2.

OFF = A2 Host A2 is the address/data control

NVIDIA Proprietary and Confidential Hardware Configuration 5-3


Generic Input states are controlled through switch bank S4, shown in Figure 5.1.

Use switch bank S5 to configure host bus address mapping, deep power down (DPD_), andvoltage control states for HVDD and video.

Table 5.3: Switch Bank S4: Generic Switch IOs

Name Configuration Description Switch Function1 INPUT SWITCH 1 ON = High U520 bit 1.4 = 1 General Input Switch HW control

This switch has an effect only if U520-1.4 is configured as an input.

OFF = Low U520 bit 1.4 = 0

2 INPUT SWITCH 2 ON = High U520 bit 1.5 = 1 General Input Switch HW controlThis switch has an effect only if U520-1.5 is configured as an input.

OFF = Low U520 bit 1.5 = 0


OFF = Low U520 bit 1.6 = 0


OFF = Low U520 bit 1.7 = 0

5 NOT USED N/A6 NOT USED N/A7 NOT USED N/A8 NOT USED N/A

Table 5.4: Switch Bank S5: Miscellaneous Control

Name Configuration Description Switch Function1 ADDR MAP CTRL 0 ON = No Remap Host A23 remains A23 Used to control address mapping

from PCI adapter.This switch has an effect only if U518 interface 0 is disabled as an output.

OFF = Remap Host Interface A23 is set to 0 and A23 is passed to A25.

2 ADDR MAP CTRL 1 ON = No Remap Host A24 remains A24 Used to control address mapping from PCI adapter.This switch has an effect only if U518 interface 0 is disabled as an output.

OFF = Remap Host Interface A24 is set to 0.

3 ADDR MAP CTRL 2 ON = No Remap U520 bit 1.6 = 1 Used to control address mapping from PCI adapter.This switch has an effect only if U518 interface 0 is disabled as an output.

OFF = Remap U520 bit 1.6 = 0

4 DPD_ DISABLE ON = Enabled N/A Used to put the chip in Deep Power Down This switch has an effect only if U518 interface 0 is disabled as an output.

OFF = Disabled

5 CTRL HVDD ON = Disable PCI Board HVDD power

Turns Host power (from the PCI board) On and Off

This switch has an effect only if U518 interface 0 is disabled as an output.

OFF = Enable PCI Board HVDD power

6 VIDEO POWER ENABLE

N/A TBD, Not used yet This switch has an effect only if U518 interface 0 is disabled as an output.

7 NOT USED N/A8 NOT USED N/A

5-4 Hardware Configuration NVIDIA Proprietary and Confidential


5.2 Software Configuration

Software configuration and control of the SC15 Evaluation Board is implemented primarilyover the I2C bus.

5.2.1 I2C/SPB Address Map

Table 5.5 gives the I2C Address Mapping. (I2C is sometimes also called SPB in other SC15documentation.) The following tables give details for specific I2C address locations.

Table 5.5: SPB Address Map

SPB Address

Function Device Reference

0x36h I2S Audio Wolfson WM8731 CODEC U5260x40h Host modes and LEDs PCA9555 I2C Expander U5200x44h Video Control and GPIOs PCA9555 I2C Expander U5070x46h Address Remap and Miscellaneous

Power ControlsPCA9555 I2C Expander U518

0x60h Onboard camera Omnivision 9650 J190x80h IO and Auxiliary Power Controller Summit SMB120 U5050x84h Core Power Controller Summit SMB113 U260x88h IO Power Controller Summit SMB113 U5040xA0h SC15 WMP Module ID EEPROM Microchip 24LC024 WMP Module0xA2h EVAL3 Module ID EEPROM Microchip 24LC024 U150xAEh LCD Module ID EEPROM Microchip 24LC024 LCD Module0xB0h Sysclk PLL AMI FS7140 U70xEAh PC to TV Encoder Chrontel CH7013B U3TBD Generic Camera Module TBD TBD

NVIDIA Proprietary and Confidential Software Configuration 5-5


Table 5.6: 0x40h: Host Mode Details

0x40h Name Direction Description I/O FunctionPort 0

P0-0 MODE BIT 0 Output Set inverted value of SC15 MD0 pin.This control has effect only if S2-1 and S2-2 are OFF

1 = Active Low Handshake0 = Active High Handshake


1 = No Handshake Mode0 = Handshake Mode


1 = Direct Addressing0 = Indirect Addressing


1 = Asynchronous Mode0 = Synchronous Mode

P0-4 HOST BUS WIDTH Output Set host interface bus controls for appropriate bus width.This control has effect only if S2-1 and S2-2 are OFF

1 = 16Bit Addressing0 = 32Bit Addressing

P0-5 HOST BUS TYPE Output Set host interface bus controls for appropriate bus type.This control has effect only if S2-1 and S2-2 are OFF.

1 = Type C Host Bus0 = Type A Host Bus

P0-6 WRITE SELECT Output Select Write Enable from one of two host interface pins.This control has effect only if S2-1 and S2-2 are OFF.

1 = Set WE_ to Pin 32 of Host interface connector.0 = Set WE_ to Pin 22 of Host interface connector.

P0-7 SYSTEM RESET Output Create a 10 ms system reset.This control has effect only if S2-1 and S2-2 are OFF

1 = Re-arm Reset Trigger0 = Generate Reset Pulse

Table 5.7: 0x40h: LED Status and Switch Details


P1-0 STATUS LED 0 Output Control LED DS4 1 = LED Off0 = LED On




P1-4 INPUT SWITCH 1 Input Read value of S4-SW1 1 = SW Input On0 = SW Input Off




5-6 Software Configuration NVIDIA Proprietary and Confidential


Table 5.8: 0x44h: Video GPIO Details


P0-0 VGP0 Input/Output User Defined I/O passed to Generic Cam-era Connector J30

1 = Logical High 0 = Logical Low















Table 5.9: 0x44h: Miscellaneous GPIOs and Video Control Details


P1-0 MGPIO0 Input/Output User Defined I/O passed to Test point TP9 for miscellaneous control applications.








P1-4 MGPIO4 Input/Output User Defined I/O passed to Test point TP11 for miscellaneous control applications




P1-6 Video Shut-ter

Output Shutter control output that is passed to Generic Camera Interface J30.


P1-7 Video Reset Output Video Reset control output that is passed to Generic Camera Interface J30.




0x

P0-03

P0-13

P0-2

P0-3

P0-4

P0-5

P0-6

P0-7

** Default Condition:

• AM2 = 0• AM1 = X• AM0 = 1• A25 = 0• A24 = 0• A23 = 0

Table 5.10: 0x46h: Address Mapping and Miscellaneous Power

46h Name Direction Description I/O FunctionPort 0

ADDR MAP CTRL 0(AM0)

Output Remap A23, A24 and A25.This control has effect only if S4-1 is set to OFF

ADDR CTRL **AM2 AM1 AM0 A25 A24 A2

ADDR MAP CTRL 1 (AM1)


0 X 0 0 0 0X X 1 A25 A24 A2

ADDR MAP CTRL 2 (AM2)


1 X 0 A23 0 0

DPD_ Output Set DPD Mode On or OffThis control has effect only if S4-4 is set to OFF

1 = Disables DPD_0 = Enables DPD_

CONTROL HVDD Output This control has effect only if S4-5 is set to OFF

1 = Enables PCI board regulator

0 = Disables PCI board regulatorVIDEO I/O ENABLE Output Enable the Camera Module Video IO voltage

This control has effect only if S4-6 is set to OFF

1 = Enables Voltage0 = Disables Voltage

SPARE Input Takes input from S5.7 1 = Switch On0 = Switch Off

SPARE Input Takes input from S5.7 1 = Switch On0 = Switch Off



0

P1

P1

P1

P1

P1

P1

P1

P1

UIO l

IO l

IO l

IO l

IO

IO

IO

IO

Table 5.11: 0x46h: Address Mapping and Miscellaneous Power

x46h Name Direction Description I/O FunctionPort 1

-0 SUMMIT POWER ENABLE 1

Output Generic Power Enable for Summit Core Voltage

1 = Logical High0 = Logical Low

-1 SUMMIT POWER ENABLE 2

Output Generic Power Enable for Summit Core Voltage


-2 PWR GPIO 0 Input/Output User-defined I/O passed to Power Module 1 = Logical High0 = Logical Low

-3 PWR GPIO 1 Input/Output User-defined I/O passed to Power Module 1 = Logical High0 = Logical Low

-4 POWER HEALTHY Input Power good indication from the power subsystem.

1 = Power Good0 = Power Fault

-5 AC’97 AUDIO RESET

Output Resets the AC97 Audio CODEC. 1 = Normal Operation0 = Resets Audio

-6 EXT HVDD OFF Input Indicates if external HVDD is present. 1 = External HVDD Off0 = External HVDD On

-7 EFUSE BURN TRIG-GER

Output Trigger signal passed to SC15 module to trigger EFUSE burn sequence.


Table 5.12: 0x40h: Miscellaneous Control

27 Name Configuration Description Bit Function-0.0 CRTL_MD0 0 MD0 = 0 SC15 MOD0 pin is under software contro

Set S2-1 to OFF1 MD0 = 1 0.1 CRTL_MD1 0 MD1 = 0 SC15 MOD1 pin is under software contro

Set S2-1 to OFF1 MD1 = 1 0/2 CRTL_MD2 0 MD2= 0 SC15 MOD2 pin is under software contro

Set S2-1 to OFF1 MD2 = 1 0.3 CRTL_MD3 0 MD3 = 0 SC15 MOD3 pin is under software contro

Set S2-1 to OFF1 MD3 = 1 0.4 CTRL_32_16 0 Host I/F is 16bit mode SC15 Host I/F bus width configuration

Set S2-1 to OFF1 Host I/F is 32bit mode 0.5 CTRL_TYPE_C 0 Host I/F is Type C Emulation SC15 Host I/F Type configuration

Set S2-1 to OFF1 Host I/F is Type A Emulation 0.6 CTRL_WR_LAT 0 Dedicated WR_ signal for variable

latencyAllows using a dedicated Write signal forvariable latency (available only on some platforms).Usually the same WRn signal is used for fixed and variable latency (let switch to OFF).Set S2-1 to OFF

1 SIngle WR_ signal for fixed and variable latency

0.7 I2C_RESET Falling edge Create a low pulse reset on SC15 SW Reset of the board



Use specific U30 bits to control the Evaluation board when plugged on to the NVIDIA PCIboard (PCI32B-BCA2), which provides only 24 address bits. The address MSB (A23) getsshifted to access the complete SC15 mapping, which requires 26 address bits.

5.2.2 Modes Summary

This section summarizes the manual and auto modes.

5.2.2.1 Manual Mode

In manual mode, use the switch positions for SW3 and SW4 shown in Table 5.14 fordifferent host I/F modes.

5.2.2.2 Auto Mode

Use the swtich positions of SW3 and outputs of U27 (the GPIO expander) in Table 5.15 forthe different host I/F modes when using Auto Mode.

Table 5.13: U30 Bits for Configuration to Old PCI Board

PCI BoardU30

DescriptionIO_0.0 IO_0.1 IO_0.2

“Old” PCI32B-BCA2 0 1 0 A23 from Host is shifted to A25 of SC15, A[24:23] on SC15 are switched to ground

Current PCI32B-BCA5

1 X 1 Complete address mapping is managed by the Host (A[25:0])


Latency Switch Mode PositionSW3-1 OnSW3-2 OnSW3-3 OnSW3-4 On

Fixed SW4-1 OnSW4-2 On

Ready Low SW4-1 OnSW4-2 Off

Ready High SW4-1 OffSW4-2 OffSW4-3 Direct On

Indirect OffSW4-4 Asynchronous On

Synchronous OffSW4-5 16 Bit On

32 Bit OffSW4-6 Type A Off

Type C On



5.3 Jumpers


Latency Switch/Bit Mode Position/OutputSW3-1 Off OnSW3-2 X OffSW3-3 X OffSW3-4 X Off

Fixed U27_0.0 0U27_0.1 0

Ready Low U27_0.0 0U27_0.1 1

Ready High U27_0.0 1U27_0.1 1U27_0.2 Direct 0

Indirect 1U27_0.3 Asynchronous 0

Synchronous 1U27_0.4 16 Bit 0

32 Bit 1U27_0.5 Type A 1

Type C 0

Table 5.16: Clock Source Selection Jumper Configurations

Jumper Control Position DescriptionJ7 Refclk1 Source 1 - 4 I2C clock generator U29

2 - 5 Oscillator 13 MHz3 - 6 Chrontel pixel clock

J16 SC15 External Clock sources:Sysclk and Refclk0

1 - 2 I2C Clock Generator (U29)2 - 3 Oscillator

(13 MHz)Open (No Jumper)

Use only when a 3.6864 MHz crystal is mounted on the SC15 Module.

J17 Camera Master Clock

1 - 2 SC15 (VSMCLK) generates the camera clock

2 - 3 Oscillator socket

Table 5.17: I2S/AC’97 Selection Jumper Configurations

Jumper Control Position DescriptionJ14/J15 Line in select 1 - 2 I2C

2 - 3 AC’97J10/J11 Microphone select 1 - 2 I2S

2 - 3 AC’97J9/8 Line out select 1 - 2 I2S

2 - 3 AC’97J16/J17/J18 Codec interface

select1 - 2 I2S2 - 3 AC’97

NVIDIA Proprietary and Confidential Jumpers 5-11


5.4 Clock Headers

Table 5.18: SRCLOCK Frequency Select

Jumper Control Position DescriptionJ40 SRCLK_GEN 1 - 2 SRCLK_GEN source: S0 of ICS661 (U28)J42 SRCLK_GEN 1 - 2 SRCLK_GEN source: S1 of ICS661 (U28)J44 SRCLK_GEN 1 - 2 SRCLK_GEN source: S2 of ICS661 (U28)J46 SRCLK_GEN 1 - 2 SRCLK_GEN source: S3 of ICS661 (U28)

Table 5.19: Clock Headers

Jumper Control Position DescriptionJP1 REFCLK0 1 Header for oscillatorJP2 NC 1 Header for oscillatorJP3 CLK 1 Header for oscillatorJP4 HGPIO5 1 Header for oscillatorJP5 HGPIO6 1 Header for oscillator

5-12 Clock Headers NVIDIA Proprietary and Confidential


Chapter 6 Software Mapping

6.1 Software Mapping

Table 6.1 gives I2C addresses for different devices.

Note: Digital potentiometer devices cannot be read back on I2C.

Table 6.1: I2C Mapping for Different Devices

Device Type ReferenceI2C

AddressDescription

PCA9555 GPIO Expander U520 0100000 Modes, LEDs, SwitchesU518 0100001 Aux Controls, DPDn, Address RemapU507 0111000 Spare GPIO for the camera board

FS7140 Clock generator U7 1011000 SC15 external clock (OSCFO), usually 13 MHz from BasebandJ16 must be on 1-2 position to use this clock on SC15

24LC024 EEPROM U14 1010001 Remote inventory (Board configuration summary)

SMB120 Voltage regulator TBD 1000000 SC15 IO powerSMB113 Voltage regulator TBD 1000010 SC15 Core power

TBD 1000100 SC15 IO powerCH7013 SVideo out TBD 1110101 Wolfson I2S Codec24LC024 TBD SC15 Module EEProm24IC024 TBD LCD Module EEProm

NVIDIA Proprietary and Confidential Software Mapping 6-1

Preliminary InformationNDA Required Software Mapping


6-2 Software Mapping NVIDIA Proprietary and Confidential


Chapter 7 SC15 Module

7.1 Introduction

The SC15 Module holds the SC15, external components, and headers for routing SC15signals to the Evaluation Board.

The key components on the module are

• SC15• No additional memory• 2MB additional memory• 8MB additional memory

• SC15 BGA 0.5mm pitch socket (optional for initial lab/software development)• Crystal for the SC15 clock.• Samtec 0.5mm Headers

• all SC15 I/O signals to applicable boards (such as the Evaluation Board) • no signals going through these headers go to the memory interface.

• I2C PROM for module identification, can be interrogated by the Host I2C• Test Points to monitor rail voltages• MICTOR on memory I/F for Debug (option for 2MB and 8MB memories configurations)

NVIDIA part numbers

• 600-80436-0002-100 PCB Assembly for SC15-NM Modules• 600-80436-0000-100 PCB Assembly for SC15-8ME modules• 600-80438-001-000: SC15 with 640KB eSRAM and additional, external DDR memory

Figure 7.1 depicts the SC15-NM module.

NVIDIA Proprietary and Confidential SC15 Module 7-1

Preliminary InformationNDA Required SC15 Module

Figure 7.1: SC15-NM Module Block Diagram

7.2 SC15 Module Components

The SC15Wireless Media Processor (WMP) has the following key features:

• Camera interface with support for 8bit ITU-R BT656 YUV or 10/12 bit RAW data format up to 96MHz data rate (3M Pix sensor @ 15fps).

• Host interface• direct and indirect interface • x16 and x32 bit data bus

• LCD FP interface with support up to 18bit RGB or 1or 2 channel serial interface• External X32 bit Mobile SDRAM or mobile DDR SDRAM interface• SD card interface• Audio I2S or AC’97 interface support• I2C serial interface used to communicate with camera for adjustments• GPIOs• Separate I/O Power and isolated core power

SC15 With Socket

VI (Camera)

SD CARD

JTAG

JTAG

DISPLAY

POWERCLOCK

I2S

SDRAM/DDR

XTL

BOOT STRAP

POWER

ISP (touch Screen)

SC15 I2C

CLKHOSTHost

I2C+5V

I2C Mux

Power FBnetwork

Camera/Display/SD/Power and Clock connector

Host Connector

I2S/JTAG/I2C/Power connection

Touch Screen

SC15 I2C

7-2 SC15 Module Components NVIDIA Proprietary and Confidential


7.3 SC15 Module Interface Details

The module contains the SC15 with all interfaces routed to headers with the exception ofthe crystal clock pins and SDRAM/DDSDRAM, where appropriate.

Interfaces supported by SC15 family of devices

• HostThe host interface functional block in the SC15 has the following features

• Type A or Type C host interfacing with fixed or variable latency• 16Bit or 32bit data bus width• Asynchronous and synchronous support• Direct and Indirect address mapping supported along with

• fixed cycle • ready handshake • wait handshake access

• SC15 reset is supplied by the Eval Board as a system reset

• SDRAM/DDR• The modules support either

• No external memory (Internal RAM only)• 2MB External Memory• 8MB External Memory

• SD• SD and SDIO support• The SD detect pin connection TBD and may be routed on the base board to the

Host GPIO.

• I2S/AC’97• Full-duplex synchronous serial channel interface to an external codec.• Support for AC'97 and I2S.• Programmable FSYNC and SCLK polarity, stop value, direction• FSYNC dividers up to 256

• Video input• Interface supports YUV or Bayer • Designed to interface to camera modules • Maximum clock/data rate (interface): 96 MHz • I2C control interface for camera control and configuration:

If used on the base board to drive I2C and the LCD, may require a voltage translator, depending on design criteria and rail voltages.

• I2C• Bus master I2C interface - • Used to configure the camera and the I2S codec• Additional circuitry may be required on the base boards if I2C is routed to

other devices with different rail voltages

• Video Output - LCD Interface• Support for VGA and QVGA panels.• Backward compatible interface with existing panel modules.• Forward compatible interface for new SC15-based panel interface signaling.

• Oscillator• On-board crystal or• Clock sourced from base board• Jumper configuration switches between the two

NVIDIA Proprietary and Confidential SC15 Module Interface Details 7-3


• Power Supply• I/O supply tolerance to be better than +/-10%, respective to rail voltage• The regulation tolerance between any of the core power supplies to be better

or equal to +/-5% • Core power to be adjustable in <20 mV steps particularly for the Eval/bring-up

phase• Power supply feed back (FB signals) are routed to the headers for tight control

of the power tolerance and control on the base board• All power supplies on the modules to be de-coupled adequately to minimize

impedance, improve transient response and suppress power supply noise.

• Boot Strap Pins• SC15 Host type select and bus width support select pins routed to the

headers. The base board must tie these pins to the appropriate logic level - see SC15 data sheet for option.

• E2PROM• E2PROM on the module is connected to the Host I2C to provide module

configuration data.

• GPIO• Test points on all GPIO pins as well as all GPIOs routed to the header to the

base board

Figure 7.2 depicts the SC15 connections to external peripheral devices. All I/O, power, andcontrol (except the memory interface) are routed through the headers to the base card.

7-4 SC15 Module Interface Details NVIDIA Proprietary and Confidential


Figure 7.2: SC15-NM Module I/Os Block Diagram

D32:0

Host

ADD[26:2]

BE[3:0]

CSn

WRn

RDn

RSTn

GPIO0/MSEL0[Host_type]

GPIO1/MSEL1[Host_type]

GPIO2/Fast_INT/STAT

GPIO3/INT/STAT

GPIO4/RDY

GPIO[6:5]

StarpHost_type

Fast_INT

INT_OUT

GPIO

OSCF1OSCFO CLK

Host I/O PwrPOWER

72

3

SUSP

VD[11:0]

VCLKVSNCLK_VGP0

VGP4:1

SDASCA

VHSYNC

VVSYNC

VGP[15:5]

VI

LD[17:0]

SPI

Cnt[15:0]

LCD

Calibration

OSCFR

JTAG

13

MA[12:0]

32

MDQ [31:0]

2

MBA[1:0]

MDQS[3:0]

4

MCSn MDQ[3:0]

1 4

CLK

2

MCOMPU

2

SD8

I2S6

GND

43

Power

34

I2C

SYS_CLK

NVIDIA Proprietary and Confidential SC15 Module Interface Details 7-5



7-6 SC15 Module Interface Details NVIDIA Proprietary and Confidential


Chapter 8 LCD Module Description

8.1 Introduction

The SC15 LCD Module enables the designer to view 2D and 3D graphics while evaluatingthe SC15 in design. Figure 8.1 shows the location of the module on the evaluation board;Figure 8.2 gives signal pin-out information.

Figure 8.1: LCD Module on the Evaluation Board

IPU Interface (16bit)

Host Connectormtg mtg

SC15 Platform Board 5.1" x 5.3"

LCD

Pan

el C

onne

ctor

3.5" LCD

mtg

mtg

LCD

mtg

NVIDIA Proprietary and Confidential LCD Module Description 8-1

Preliminary InformationNDA Required LCD Module Description

D

3.3 V3.3 V3.3 V3.3 VSeriaSerial

SeSerSeSer

P

Ex

SeSeria

Ex

Main paSub pa

Serial Register lEx l

Main panel back l (legacy)ExEx name change?ExExExEx 6 or FGP8

anel switch

GPIO/Parallel Reg ce. Name change?ExEx5 V5 V5 V5 V

Figure 8.2: LCD Module Connector Pin-to-signal Configuration

escription/notes Description/Notes

SC15 Signal SC15 I/O Name Conn Pin Name Pin # Power Blade Pin# Conn Pin Name SC15 I/O Name SC15 Signal

from system supply D3V3 D3V3 D3V3 1 GND 2 SPCK - - from system supply D3V3 D3V3 D3V3 3 B1-B5 4 SPMOSI - - from system supply D3V3 D3V3 D3V3 5 GND 6 SPMISO - - from system supply D3V3 D3V3 D3V3 7 GND 8 SPSSn - -l interface diff clock - SC* LD0 SC* 9 GND 10 LD18 LHP1 LD18 LCD Data I/O interface diff clock + SC LD1 SC 11 GND 12 LD19 LHP2 LD19 LCD Data I/Orial interface Data0 - SD0* LD2 SD0* 13 GND 14 LD0 LD0 LD0 LCD Data I/Oial interface Data0 + SD0 LD3 SD0 15 GND 16 LD1 LD1 LD1 LCD Data I/Orial interface Data1 - SD1* LD4 SD1* 17 GND 18 LD2 LD2 LD2 LCD Data I/Oial interface Data1 + SD1 LD5 SD1 19 GND 20 LD3 LD3 LD3 LCD Data I/O

Backlight Anode - - BKLT+ 21 GND 22 LD4 LD4 LD4 LCD Data I/Oanel Control enable LPW2 LPW2 LPW2 23 GND 24 LD5 LD5 LD5 LCD Data I/O

Backlight Cathode - - BKLT- 25 GND 26 NC26 - -STH LD6 STH 27 GND 28 LD20 LVP1 LD20 LCD Data I/O

Same Dot indication SDT LD7 SDT 29 GND 30 LD21 LM1 LD21 LCD Data I/Opansion for panel IO - - PNLIO0 31 GND 32 LD6 LD6 LD6 LCD Data I/O

- - TSINT 33 GND 34 LD7 LD7 LD7 LCD Data I/OSTP LD8 STP 35 B1-B5 36 LD8 LD8 LD8 LCD Data I/O

rial interface Data2 - SD2* LD9 SD2* 37 GND 38 LD9 LD9 LD9 LCD Data I/Ol interface Data02 + SD2 LD10 SD2 39 B6-B10 40 LD10 LD10 LD10 LCD Data I/OPanel VDD enable LPW0 LPW0 LPW0 41 FVDD 42 LD11 LD11 LD11 LCD Data I/OPanel VEE enable LPW1 LPW1 LPW1 43 FVDD 44 NC44 - -

Main Display Reset M_RST LHP2 M_RST 45 FVDD 46 LD22 LDI LD22 LCD Data I/ODisplay enable LSC1 LSC1 LDE 47 FVDD 48 LD23 LPP LD23 LCD Data I/O

pansion for panel IO - - PNLIO1 49 FVDD 50 LD12 LD12 LD12 LCD Data I/OHorizantal Pulse 0 LHP0 LHP0 LHP0 51 FVDD 52 LD13 LD13 LD13 LCD Data I/OHorizantal Pulse 1 LHP1 LHP1 LHP1 53 FVDD 54 LD14 LD14 LD14 LCD Data I/O

nel serial chip select MSCS LCS* MSCS 55 FVDD 56 LD15 LD15 LD15 LCD Data I/Onel serial chip select SSCS LDI SSCS 57 FVDD 58 LD16 LD16 LD16 LCD Data I/O

LVP1 LVP1 LVP1 59 FVDD 60 LD17 LD17 LD17 LCD Data I/OData and Command SRS_DC LDC SRS_DC 61 FVDD 62 PWM0 LPW2 PWM0 Sub panel backlight contropansion for panel IO - - PNLIO2 63 FVDD 64 PWM1 LM1 PWM1 Main panel backlight controlight control (legacy) PWM0/PWM1 LPW2/LM1 PWM0/PWM1 65 FVDD 66 PWM2 LM1 PWM1 Main panel backlight contropansion for panel IO - - PNLIO3 67 FVDD 68 NC68 - -pansion for panel IO - - PNLIO4 69 FVDD 70 CSBO LHP1 - Currently Sub Parallel CS. pansion for panel IO - - PNLIO5 71 FVDD 72 SDAO LSDA LSDA Serial data signal (bidi)pansion for panel IO - - PNLIO6 73 FVDD 74 SDAI - -pansion for panel IO - - PNLIO7 75 B6-B10 76 SCLO LSCK LSCK Serial clockpansion for panel IO - - PNLIO8 77 GND 78 GCS1 LHP2 FGP6 See pin 95 Should be FGP

PWM clock LPP LPP LPP 79 B11-B15 80 GCS2 - -System GPIO - - SGPIO0 81 GND 82 LDI LDI LDI LCD Data Inversion

Touchscreen X- - - TSX- 83 GND 84 M_RST LHP2 M_RST Main Panel ResetTouchscreen X+ - - TSX+ 85 GND 86 SGPIO1 - - System GPIOTouchscreen Y- - - TSY- 87 GND 88 S_RST LVP0 S_RST Sub Panel ResetTouchscreen Y+ - - TSY+ 89 GND 90 SGPIO2 - - System GPIO

General Purpose IO FGP12 LSPI LGPIO0 91 GND 92 LGPIO11 - - Assign an FGP here?General Purpose IO FGP10 LPW0 LGPIO1 93 GND 94 LSC0 LSC0 LSC0General Purpose IO FGP8 LHP2 LGPIO2 95 GND 96 LDE LSC1 LDE/LSC1General Purpose IO FGP7 LPP LGPIO3 97 GND 98 PNLIO_RST - - Expansion for reset from p

GPIO/Tear Enable TE LDC LGPIO4 99 GND 100 PNLIO11 - - Expansion for panel IOister Data/Command RS_DC LVP1 LGPIO5 101 GND 102 LM0 LM0 LM0 Main CS for parallel interfapansion for panel IO - - PNLIO9 103 GND 104 LM1 LM1 LM1pansion for panel IO - - PNLIO10 105 GND 106 PNLIO12 - - Expansion for panel IO from system supply D5V D5V D5V 107 GND 108 LVS LVS LVS Vertical sync from system supply D5V D5V D5V 109 GND 110 LHS LHS LHS Horizontal Sync from system supply D5V D5V D5V 111 B11-B15 112 SCL - - from system supply D5V D5V D5V 113 GND 114 SDA - -

SC15

New LCD Connector

8-2 Introduction NVIDIA Proprietary and Confidential

A-1

Appendix A Schematics

NOTE: The schematics in this appendix fit pages sized 11” x 17” and can be printed on paper that size for easier viewing.

PRELIMINARY

Cover PageBASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL

jcihlae433

600-80433-0000-000

18-Apr-2005

1 OF 20

Mictor

SVIDEO JACK

LCD Connector

LCD to TV Video

Converter

E433 SC15 Evaluation MainBoard

Freescale Connector

OmniVision Conn

SDCARD

WMP LCD & VI

WMP Host Conn

Mictor

Camera Module

Generic Camera Connector

SC15 DUT card

Plug in Connectors

E434-SC12 ModuleE436 SC15-NM Module

E437 SC15-XT Inapac ModuleE438 SC15-XT Samsung DDR Module

Host Connector

Mictor

WMP Pwr

Mictor

SMB113

Summit SWREG

Summit SWREG

SMB113

Power Jumpers Connectors

AC97 Codec

I2S Codec

Summit SWREG

SMB120

1

5

4

3

2

F G H

PAGEDATE

SANTA CLARA, CA 95050, USA

2701 SAN TOMAS EXPRESSWAY

NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL

CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALLALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY

IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.

B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARYCON_MICTOR_38LD<0>

LD<1> 3638

SMD

J25

COMMON

3432302826242220181614

8

1210

373533312927

LD<2>LD<3>LD<4>

LD<12>LD<11>LD<8>LD<9>LD<7>LD<6>LD<5>

LD<10>

MOD_LHP0

MOD_LHSMOD_LHP2MOD_LHP1

LD<17>

LD<16>LD<15>LD<14>LD<13>

MOD_LM0 252321191715

97

1311

21

65

43

4039

MOD_LPW1MOD_LPW2

MOD_LVS

MOD_LM1MOD_LSC1

MOD_LVP0MOD_LVP1

MOD_LPW0MOD_LSC0

01

2.2B> LD<17..0>

2.3A>

2.3E>

2.3E> 2.3A>

3.2B<

3.3G<

3.3B< 3.2B<

234567981112101314

1615

176.3C<

3.3G< 3.3B< 3.3G<

3.3G< 2.3A>

2.3E> 2.3A>

2.3E> 2.3E>

2.3A> 2.3A>

2.3E> 2.3E>

2.3A>

3.2B< 3.2B< 3.3G< 3.2B<

3.3B< 3.3G<

3.3B< 3.2B<

3.3G<

3.3B< 6.3C< 3.3B<

6.3C<

3.3G< 3.3G<

434241

GND

SOC_SDPUSH_IN_OUT

13

9

J507

COMMON

1

3

2

6

4

5

15

12

GND

2 OF 2018-Apr-2005

600-80433-0000-000

10

11

7

8

14

e433jcihla

SDVDD

R21

5%100K

0402COMMON

R17100K

04025%

COMMON

R42

COMMON04025%100K

SD_D<0>

SD_D<1>

SDVDD

SD_D<2>

COMMON

R41

04025%100K

COMMON

R40100K5%0402

SD_D<3>

SD_D<3>

SD_D<2>

SD_SCLK

SD_SCMD

22UF

10VN/A

C37

COMMON

TAN

SMA

N/AN/A

GND

SD_D<0>

SD_D<1>

NO STUFF0

5%0402R18

BASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL

14.3D<>

2.2E>

04025%100KR22

COMMON

6.2C< 3.2B<

12.5F<> 12.3G> 12.3C<> 8.2A<>

4.2A<

4.2D<

7.4B<>

3.2B< 6.2C<

7.2A<>

2.2B>

6.2C<>

2.1F<

5.3F<> 18.5D<>

4.4A<>

COMMONJ32

VCLK_VGP13

VD<13..0>11VD<11>10VD<10>

89

7654321VD<1>

VD<3>VD<4>

VD<2>

VD<5>VD<6>VD<7>VD<8>VD<9>

VD<0> 0

LD<23..0>

15.4A<> 3.4F<>

232221

SYS_SDA

LD<20>LD<21>LD<22>LD<23>

20

1819

1716

151413

LD<18>LD<19>

LD<17>LD<16>

LD<15>LD<14>LD<13>

2

10

68

4

M_LCD

MALE

12

20181614

22

30282624

BRD_TO_BRD_CONNECTOR

CON_QTH_SMT_2X60_P050GND

32

40383634

42

5250484644

60585654

62646668

3.3G<

3.3G<

3.3G< 6.3C<

6.3C<

17.4G<

3.2B<

3.3B<

3.2B<

3.3B< 3.3G<

3.3G<

3.3B<

2.2G<

2.2G<

2.2G<

2.2G<

2.2G<

3.3G<

14.3F<

3.3B<

2.2G< 2.2G<

2

3

MOD_LSDA

S_LVDD_FB

MOD_LSPI

MOD_LVP1

MOD_LVS

MOD_LHSMOD_LHP1

MOD_LSC1

MOD_LM1

MOD_LPW1

SD_D(3..0)

0

1

HVDD

HDR_1M2

2.54MMMALE

J48

SD_C_WR_PROTECT

0COMMON5%

21

0

COMMONNORM

MHGP5

0402R15SD_C_DETECTS

R14 R20

5.3H<

100K

04025%

COMMON

100K5%0402COMMON

LCD/Camera/SD Connector and SDCARD Interfaace

31

15.3H<

COMMON0

5%

SD_D<1>

0603R61

12LD<12>

LVDDSC12_FGP13

SD_D<3>

14.3F< S_SDVDD_FB

SD_C_DETECTSSD_C_WR_PROTECT

GND

70

74

7876

72

80

86

8284

889092

9698

94

100102104106108110112114116118120

122124126128

SDVDD

16V

X5R

.1UF

10%

C534

0402COMMON

SDVDD

.1UFC525

16V

X5R10%

16V10%X5R

.1UFC533

0402 0402COMMON

GND

COMMON

SDVDD

135

97

11

19

1513

17

2123252729

ICSDA_VGP2ICSCK_VGP1

S_VVDD_FB

VSNCLK_VGP0

VVSYNCVHSYNC

VGP5

VGP3VGP4

VGP6 31

39373533

41

5149474543

LD<11>

LD<8>LD<9>LD<10>

59

5553

57

61636567

LD<7>

LD<5>

LD<6>

LD<4>

LD<2>LD<3>

LD<1>

SYS_SCL

11109

LD<23..0>

876

5

1

432

4.2A< 4.2A<

4.2D<> 4.2D<

14.3F<

4.2A< 4.2A<

4.2A<

4.2D>

3.4F<

4.2A<

17.3G<

12.2D< 12.2D<

M_VVDD

12.5C<> 12.4C<

0COMMON

2.1F<

4.4A< 15.4A< 18.5D<

5.3H<

SC12_FGP2

2.2E>

6.2C<

6.2C< 3.2B<

7.2A< 7.4B< 8.2A<

5%R5580603

MOD_LPW2

14.3D< 12.4F< 12.3C< 12.2G>

69

737577

71

79

85

81

87

83

MOD_LVP0

LD<0>

89

97

919395

99101103105107

MOD_LSCKMOD_LHP2

MOD_LDCLCSn

SD_D<0>

SC12_FLCLK1

0

LVDD

0SD_D<2>2 109

113115

111

117119

121123125127

GND

SDVDD

SD_SCMD

SD_SCLK

0COMMON5%0603

R563

LCSnCOMMON0

5%0402R557

.1UF

X5R10%16V

C52322UF

10VN/A

C532

COMMON

.1UF

0402X5R10%16V

C537

TAN 0402COMMONCOMMON

GND

SMAN/AN/A

LVDD

N/A

N/A10VTAN

22UFC536

COMMON.1UF

0402X5R10%16V

C521

COMMON

SMAN/A

GND

M_VVDD

GND

MOD_MSCS_LCSn

22UFC531

COMMON

MOD_LPW2MOD_LPW0

MOD_LDI

MOD_LM0

MOD_LSC0

MOD_LPP

MOD_LVP0

MOD_LHP1

MOD_LSCK

MOD_LHP0MOD_LHP2

MOD_LDC

3.2B< 2.2G< 3.2B< 2.2G<

3.3G< 3.3B<

3.3G< 2.2G<

3.3G< 2.2G<

3.3B<

2.3A> 2.2G<

3.3G< 2.3A> 3.3B< 2.3A>

3.2B< 2.2G< 2.3A> 2.2G<

SD_D(3..0)

3.3B<

3.3B< 3.3B<

2.3A>

3.2B<

2.3A>

6.3C< 3.3G<

3.3G<

3.3G< 3.3B<

3.3B<

3.3G< 2.3A> 2.2G<

TAN10VN/A

N/A

SMAN/A

NOTE: Debug Connector is Pinned Out for SC15

Observation Bus and must be descrambled

LCD Debug and Observation BUS Mictor

STANDARD SDCARD

LCD/CAMERA/SD CONNECTOR AND SDCARD INTERFACESE433 SC15 Evaluation MainBoard

LCD/CAMERA/SD CONNECTOR IN

INININ

IN

IN

ININININ

IN

ININ

ININ

GNDGNDGND

A2-3A2-2

CLK0

A0-1

A3-7A3-6A3-5A3-4A3-3A3-2

A2-4

A2-1A2-0

A0-3A0-4A0-5

A0-7A1-0A1-1A1-2A1-3A1-4

CLK1

NCNC

NCNC

A2-5A2-6

A1-6A1-7

A3-0A2-7

A3-1

A0-6

A1-5

A0-2

A0-0

GNDGND

GND_EMI3

C_WR_PROTECT

GND_EMI1

DATA2

CD_DATA3

CMD

VDD

GND

CLK

C_DETECT

GND

DATA1

DATA0

COMMON

GND_EMI2

IN

OUT

OUT

BI

OUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUTOUT

OUTBIOUT

OUTOUT

OUT

IN

OUT

V1.0

V1.0Male LCD

GNDVSNCLK

VVDD_FBVVDD

NC

VGP3

VHSYNCVVDDVVDDVVDD

VVSYNC

VGP1VGP2

VGP4

NC

NC

VGP5VGP6

HOST_SCLH_LSDAH_LCS*H_INTR*

LD11LD10

LD7LD6

LD8LD9

NCLD5

LD4LD3

NC

LD2LD1LD0

LM0

LPW0LPW2LSC0LVP0

NC

NC

LDILPP

LDC

LVDDLVDD

LHP0LHP2LSCK

LCS*

GND

SDD0

SDCLKSDVDDSDVDD

SDCMDSDD2

LVDD

GNDGNDGNDGND

VCLKGNDVD13

VD3VD4VD5

VD12VD11VD10VD9VD8VD7VD6

GND

VD2

VD0

HOST_SDAH_LCLK

H_LDC

LD23

VD1

NC

NC

LD22LD21LD20LD19LD18LD17LD16

NCLD15LD14LD13LD12

LPW1

LSC1LVP1LM1

NC

NC

LVSLHS

LHP1

LSDALSPI

LVDDLVDD

NCNC

NC

NC

LVDD_FBSDD1SDD3SDGP0SDGP1SDGP2SDGP3

SDVDD_FB

GND

GNDGND

GND

OUTOUT

OUTOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

3.3B< 2.3E> 2.2G<

MOD_LM1MOD_LM1

MOD_LPW2

MOD_LHP1

LD<23..0>5.4A< 5.4A<

5.4C< 5.4C<

0

0COMMON

COMMON5%

5%

0603

0603R694

R7330

0

COMMON

3.3B<

14.3D<>

3 OF 2018-Apr-2005

600-80433-0000-000

LD<23>

LD<21>

LD<20>

LD<19>

LD<22>

LD<18>

COMMON

COMMON0

0

0

5%

5%

COMMON

COMMON

COMMON

COMMON0

05%

5%

5%0

5%

e433jcihla

3.2B<

6.3C<

3.3B<

3.2B<

14.3D<

6.3C<

6.3C<

12.5F<>

2.3A>

3.3B<

2.3A>

2.2G<

2.3A>

2.2G<

2.3A>

2.3E>

2.3E>

2.3E>

2.3E> 2.3A>

2.3A> 2.2G<

2.2G<

2.2G< 2.2G<

2.2G<

2.3E> 2.2G<

12.4F<

12.3C<> 12.3G>

12.3C<

8.2A<>

12.2G>

7.4B<>

8.2A<

MOD_LSC1

MOD_LVS

MOD_LM1

MOD_LHP2

MOD_LHS

MOD_LM0

MOD_LSC0

MOD_LDI

MOD_LSDA

MOD_LSCK

MOD_LVP0

MOD_LHP2

7.4B<

7.2A<>

0

0

0

0

0

0

0

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

5%

5%0603

0603

5%0603

R685

R687

R688

R689

0

0COMMON

COMMON

0

COMMON

COMMON

0603 5%

5%0603

5%0603

R682

R683

R713

COMMON0

COMMON0

0 5%0603 COMMON

7.2A< 6.2C<

5.3F<> 6.2C<>

5.3H<

18.5D<> 4.4A<>

18.5D< 15.4A< 4.4A< 2.2B<

2.2D<> 15.4A<>

COMMON

0402

0402

R739

R738

R737

MOD_LHP2

MOD_LVP1

MOD_LHP1

0402

0402R736

R7320402

R7340402

MOD_LM1

MOD_LDI

MOD_LPP


5%

5%

5%

5%

5%

5%

5%

5%

1819

2120

543210

SPSSnSPMISO

LD<18>

LD<21>

LD<19>

LD<20>

LD<5>LD<4>LD<3>LD<2>LD<1>LD<0>

SPCKSPMOSI

LD<6> 6

2322

1110

987

12

0603

R690

R722

1716151413

PWM1_LM1_B

LHP1_A

PWM1_LM1_APWM0_LPW2

LD<11>LD<10>

LD<9>

LD<22>

LD<13>LD<12>LD<23>

LD<17>LD<16>LD<15>LD<14>

LD<7>LD<8>

8

4

10

2

6

121416182022

26

30

24

28

32343638

40

4442

50

4648

5254565860

666462

6870

M_LCD1

21.21MMSAM_MIT_06

COMMON

MALE

J5

975

13

11

2729

1719

1315

2325

21

D3V3

LD<0>0LD<1>1

LD<5>LD<4>

LD<6>LD<7>

LPW2

LD<2>LD<3>3

2

54

67

PNLIO0 31333537

39

49

454341

47

57

61

65

6967

63

55

59

5351

LD<10>

TSINTn

LD<9>LD<8>8

9

10

MSCS_LCSn

PNLIO1

PNLIO4

LHP0

LPW1MRST_LHP2_A

LPW0

PNLIO3

SRS_DC_LDC

LDE_LSC1_B

PWM0_PWM1

SSCS_LDI

PNLIO2

LVP1

LHP1_B

0COMMON

0

0

0

0

0COMMON

COMMON

COMMON

COMMON

COMMON

5%

0603

0603R696

R729

COMMON

COMMON0

0

5%

5%

5%0603

0603

0603 5%

R693

R724

R726

COMMON

COMMON0

0

COMMON

COMMON0

0

0603

0603R672

R686

0603

0603

R718

0603R684

0603R712

LSDALGP12

LGP6_LHP2

LSCK

MRST_LHP2_BLDI

LVS

SGPIO1

LM1

SRST_LVP0

PNLIO12

LM0

LSC0

PNLIO11PNLIO_RSTLDE_LSC1_A

LHS R7140603

SYS_SCL

SYS_SDA

78

767472

80

86

8284

8890

9896

9294

100

106

102104

108110

114112

J5SAM_MIT_06

COMMON

MALEM_LCD1

21.21MM

LCD Module Interface Connectors

I209

87

8385

81

77

757371

79

89

103105

1019997959391

107109

113111

115116117

LGP8_LHP2LGP10_LPW0LGP12_LSPI

TE_LDCRS_DC_LVP1

LVDD

TSYn

PNLIO10

PNLIO7PNLIO6PNLIO5

LGP7_LPP

PNLIO9

TSXpTSXnSGPIO0LPPPNLIO8

TSYp20.3C< 20.3E< 20.3C<

20.3E<

0

0

0COMMON

COMMON

COMMON

NO STUFF0

0COMMON

5%

5%0603

0603

5%0603R716

R720

R7350

0COMMON

COMMON0COMMON

D5V0

119118

120121122

125

124123

126

128127

129

22UFC1

COMMON

SMD_4X6.3

ALE

20%10V

1.8R80MA@105C

GND

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

0603R728

LD<23..0>

MOD_LPW2

0603

0603R692

R740

0603

0603R691

R725

0603

0603R695

R723

MOD_LPW0

MOD_LHP2MOD_LPW1

TSINTn

MOD_LSC1

MOD_LM1

MOD_LDIMOD_MSCS_LCSn

MOD_LDC

MOD_LHP0MOD_LHP1

MOD_LVP1

3.3B< 2.3A> 2.2G<

6.2C< 2.2E> 2.2B> 2.1F<

2.2G<

2.2G< 2.2G<

3.2B>

2.2G<

2.3A>

2.3A> 2.3E>

5.4A<

2.3E>

2.2G<

2.3A> 2.4A>

2.3A>

2.2G< 2.2G<

2.2G<

2.3E>

3.3G<

3.3B<

2.3A> 2.3E>

2.3E>

3.3G<

3.3B<

3.3B<

3.3G<

3.3G<

3.3B<

3.2B>

3.3G<

5.4A<

0603R727

R7210603

0603R717

R719

0603

0603R715

MOD_LPW2

MOD_LPP

MOD_LSPI

MOD_LHP2

MOD_LDC

MOD_LPW0

MOD_LPP

MOD_LVP1

2.3A> 2.2G<

3.3B< 2.3A>

2.3E>

2.2G<

2.3A>

2.2G<

2.3A>

2.2G<

2.3A>

3.3B<

2.3A>

3.3B<

2.3E>

3.2B<

3.2B< 3.2B<

3.3B<

3.3G<

D5V0

PNLIO5PNLIO3PNLIO1

PNLIO7PNLIO9PNLIO11PNLIO_RSTSGPIO1

GND

864

20

2

1816141210

HDR_2X10

2.54MMMALE

J6

NORM90

COMMON

531

79

151311

1719

SGPIO0PNLIO12

PNLIO6

PNLIO0

PNLIO10PNLIO8

PNLIO4PNLIO2

D3V3

GND

PLACE NEAR J3 LD PINS

NEAR J3 PINSPLACE ALL Rs TOPSIDE

LCD MODULE INTERFACE CONNECTOR

TOP SIDE

PLACE ALL Rs TOPSIDE


NEAR J3 PINS

PLACE AS GROUP NEAR J3

IN

IN

IN

IN

IN

IN

ININ

ININ

ININ

ININ

INOUT

IN

BI

1/2 LCD CON

SPCK

LD0

LD2

LD19LD18

LD1

SPSSnSPMISOSPMOSI

LD3LD4LD5

NC26LD20LD21

LD7LD6

LD8LD9

NC44LD22

LD10LD11

LD23LD12LD13LD14LD15LD16

PWM1

LD17

PWM2

PWM0

NC68

SCLOSDAI

CSBOSDAO

LDELSC0

GCS1GCS2LDI

SGPIO2S_RST

SGPIO1M_RST1

LGPIO11

LHS

SDASCL

LVS

LM1LM0

PNLIO_RSTPNLIO11

PNLIO12

D3V3D3V3D3V3

SD0n

SD1n

D3V3

SCnSC

SD0

TSINTn

BKLT+LPW2

PNLIO0

SD2n

BKLT-

SD1

STHSDT

STP

PNLIO1

M_RST0LPW1LPW0

LHP1MSCS

LHP0

LDE

SD2

SSCS

PNLIO4

LVP1

PNLIO5PNLIO6PNLIO7

PNLIO2SRS_DC

PNLIO3PWM1/PWM0

TSY-TSY+LGPIO0

PNLIO8

TSX+TSX-SGPIO0

LGPIO2LGPIO1

LPP

PNLIO10PNLIO9

LGPIO4LGPIO5

LGPIO3

D5VD5V

D5V

D5V

OUTOUTOUTOUT

CON2/2

LCD

GND

GNDGND

GND

FVDDFVDDFVDD

GND

GNDGND

FVDDFVDD

GNDGNDGND

IN

IN

OUT

ININ

ININ

ININININ

IN

ININ

IN

IN

IN

ININ

IN

ININ

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARYDVVDD

AVVDD

C5510UF

COMMON

6.3V

0805

20%X5R

NO STUFF

R530-500K

10%SMD_31

2

GND

3

1%15.0R5940.1UF

10%16V

C560

AVDD_P

0.1UF

10%X5R0402

16V

C561

0402

95.3K

100K

0402

R577

R581

COMMON

COMMON

NO STUFF U18

R5780

04025%

LT1763VREF=1.22V

1%.001UF50V10%X7R

C551

1%

GND

COMMON0402DVVDD_ADJ

DVVDD_BYP

1

4

2

10VN/A

C43

3.3uH

22UFCOMMON

COMMON1008L1

S8S8

COMMON

DVVDD_IN_PWR

5

8

376

GND

VVDD

0402X5R

25

MOLEX_52437FFC_FPC_1X24J19

COMMON

COMMON

1

0402COMMON

DOVDD

COMMON

C553

10%X5R0402

16V

234567

91011

8

VD<9> 1213

17

1516

14

181920

2221

VD<8>

VD<7>PCLK


9

8

7

62534

COMMON33

5%

26

4 OF 20dd-mon-year

600-80433-0000-000

2423

GND

VD<0>VD<1>

01

e433jcihla

0.1UF

COMMON

TAN

SMA

N/AN/A

C50

10VN/A

TAN

SMA

N/AN/A

3.3uH

22UFCOMMON

COMMON1008L2

VCLK_VGP13

VHSYNC

VSNCLK_VGP0

VGP3VVSYNCCAMERA0_RESETICSCK_VGP1

ICSDA_VGP2

0402R587

16V

0402

10%X5R

0.1UFC45

COMMON

DVDD

0.1UF16V10%

0402X5R

C554

COMMON

GND0R590

10%16V

X5R0402

0.1UFC556

COMMON

30R@100MHz

22UF

N/AN/A

10VN/A

TAN

SMA

C46

NO STUFF

COMMON

COMMON0

5%

5%

2

COMMON

0402

0402R591

1

VD(9..0)

GND


D5V0

DVVDD_SHDN

BEAD_0805LB501

0402

R582

COMMON

D3V3

05%

8.33MM

FFEMALE

CON_QSS_RAJ30

COMMON

0402

100KR588

COMMON

1%51525354555657

I179

58

.1UFC524

COMMON

10%

0402X5R

16V

M_VVDD

N/ATAN

22UF

10VN/A

C522

COMMON

N/A

GND

SMA

12.5C<> 12.2D< 12.4C< 12.2D<

14.3D< 10.3F< 10.3F<> 10.3D>

2.2B<> 2.2B>

5.2F<

2.2B< 2.2E<

VSNCLK_VGP0VD<11..0>

VGPIO<7..0>ICSDA_VGP2ICSCK_VGP1

PURn

M_VVDD

7

D5V0

PUR

VGP5

0.1UF16V10%X5R0402

C557

COMMON

GND

DVVDD

CON_MICTOR_38SMD

J29

COMMON

343638

3230282624222018161412108

373533312927252321191715131197

5

321

6

4

414039

4243

GND

Camera Connector and Module Interface

VHSYNCVVSYNC

VD<11>VD<10>

VSNCLK_VGP0VCLK_VGP13

VGPIO6VGPIO5VGPIO4VGPIO3VGPIO2

VGPIO_SHUTTER

VGPIO0VGPIO1

ICSCK_VGP1ICSDA_VGP2

VGPIO_RESET

VCLK_VGP13VSNCLK_VGP0

VID_PWR_ENn

VGP5VGP6

VGP4VGP3

VD<3>VD<4>VD<5>

VD<0>VD<1>VD<2>

VD<6>

VD<9>

VD<7>VD<8>

VGPIO<7..0>

10

TP8TESTPOINT2

1

SCHMOOCOMMON

TESTPOINT2

TESTPOINT2

SCHMOO

TP11

COMMON

SCHMOOCOMMON

TP7

1

1

1

TESTPOINT2SCHMOO

TP10

COMMON

COMMONSCHMOOTESTPOINT2TP6

1

SCHMOOTESTPOINT2TP9

COMMON

1

234

65

7

VGPIO7

VGPIO7

VGPIO3

VGPIO5

VGPIO_RESET

VGPIO0

MGPIO1MGPIO2MGPIO3

MGPIO5

VGPIO1

VGPIO6

MGPIO4

MGPIO0

VGPIO4

VGPIO2

VGPIO_SHUTTER

CON_QSS_RAJ30

8.33MM

GND

0123

54VD<4>

VD<3>VD<2>

VD<5>

VD<1>VD<0>5

31

7

111315

9

VD<6> 617

87

109

11VD<11>VD<10>

VD<8>VD<7>

VD<9>

19212325272931333537394143454749

FEMALEFCOMMON

8642

16141210

GND

18

50484644424038363432302826242220

VGPIO6VGPIO5

VGPIO2

VGPIO0

VGPIO3VGPIO4

VGPIO1

VCLK_VGP13

VGPIO_RESET

VVSYNCVHSYNC

VGP4

VGP5

VGP3

VGP6

0

21

3

54

6

D3V3

VGPIO<7..0>

VGPIO_SHUTTER

VID_PWR_ENn

VVDDO

PUR10.3D>

2.2E>

2.2B>

2.2B> 2.2B> 2.2B>

2.2B> 2.2B>

7.3H> 15.3B<

54

I178

2.54MM

HDR_1M3MALE

0

J26

321

NORM

PCA9555SOP24

U507

COMMON

24

COMMON

D3V3

67891011

1314151617181920

2322

1

12

32

21

SYS_SCLSYS_SDA

GND

I2C_VGIO_A1I2C_VGIO_A0

I2C_VGIO_A2

M_VVDD

.1UF

COMMON

COMMON0

N/A1206R574

VVDD

COMMON

VVDDO

0N/A1206

R573

16V10%X7R0402

C75

GND

2.2B<

0R70

5%

0

04025%

0402

R71

NO STUFF

COMMON

12.3C< 3.4F<

12.4F< 5.3H<

R74

D3V314.3D<

6.2C<

05%0402

04025%

R73

NO STUFF

COMMON

0

GND

15.4A< 7.2A<

0402

0402

R67

R72

NO STUFF

COMMON

0

18.5D< 7.4B< 8.2A<

5%

05%

12.2G>

DVVDD Set to 1.8V

DVVDD Core Power

OMNIVISION CAMERA CONNECTOR AND FILTERS


I2C ADDR: 0b0111000

CAMERA MODULE INTERFACE

CAMERA CONNECTOR AND MODULE INTERFACE

OUT

ADJ

BYP

IN

GND2

SHDN*

GND1

GND3

CGNDMECH_PAD1

MECH_PAD2

CON_1x24

NCAGNDSIO_DAVDD

RESETSIO_C

VSYNC

DOVDDDVDDHREFPWDN

Y9

Y8

Y7PCLK

DGND

XCLK1

Y5

Y4Y3

Y2Y6

Y0Y1

CGNDCGNDCGND

CGND

2/2 CONCNTR PLANE

GNDGND

GND

GND

GNDGND

GNDGND

OUTIN

INBI

IN

GNDGNDGND

A2-3A2-2

CLK0

A0-1

A3-7A3-6A3-5A3-4A3-3A3-2

A2-4

A2-1A2-0

A0-3A0-4A0-5

A0-7A1-0A1-1A1-2A1-3A1-4

CLK1

NCNC

NCNC

A2-5A2-6

A1-6A1-7

A3-0A2-7

A3-1

A0-6

A1-5

A0-2

A0-0

GNDGND

IN

INININ

ININ

ININ

ININ

STD Camera CONN1/2 CON Signals

GNDVSNCLK

VD0

VD2VD3

VD1

VD8VD9

VD4VD5

VD7VD6

VD10

VGPIO7VVDD

VVDDVVDD

AFVDD

SCL

PURn

SDA

VD11

AFVDDD5V0D5V0

GNDVCLK

VVSYNC

VGPIO0

RESET1

SHUTTERFLASH

VGPIO1

PWRDN2PWRDN1RESET2

VHSYNC

VGPIO2

VGPIO6VVDDO

VGPIO5VGPIO4VGPIO3

PWRIOENPURVVDDOVVDDO

FLVDDD3V3D3V3

IO_0_0IO_0_1

IO_0_7IO_0_6IO_0_5IO_0_4

IO_0_2IO_0_3

IO_1_0

IO_1_4IO_1_3IO_1_2IO_1_1

IO_1_5IO_1_6IO_1_7

VDD

INT

SDASCL

GND

A2A1A0

INBI

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY 20.5G>

7.2E>

20.3C>

PLL1_IN_CLK

SYS_REFCLK0

5.2C> 13.4H> 13.4H>

11.5F>

GND

NO STUFF

NO STUFF0

0

5%

5%

REFCLK0COMMON0

5%

BE3n_A1

0603

0603

0603R553

R556

R552

J37

MALE

BE2n

WRn

CS1nCS3n

RDn1210

18

1416

24

86

20

14.3F<

20.3E>

15.1H<

11.3E>

11.2H>

18.5D<

D<31..0>

A<31..0>

15.4A<

HVDD

28

24

30

26

2022

18

1416

12

810

46

20

D<30>HOST_RDYn

D<12>D<10>

D<14>

D<18>

D<28>D<26>D<24>

D<16>

D<20>D<22>

22242628303234363840

D<8>D<6>D<4>D<2>D<0>

54

5856

424446485052

S_HVDD_FB60

302826

22201816

D5V0

1214

10

68

4

0A2_SW_IND

A<28>A<30>

A<16>A<18>A<20>A<22>SC_A24A<26>

A<10>A<12>A<14>

6264666870727476

A<8>A<6>A<4>

A<0>

9694

7880828486889092

M_HOSTCON_QTH_SMT_2X60_P050


COMMONGND

13

75

911

17

1315

SYS_CLK

INTRn0

BE1nBE0n

CS0nCSn

13.2H>

20.2C<

13.3H>

1921232527293133353739

53

5755

414345474951

59

6163656769717375

9593

7779818385878991

A3_SW_IND

A<11>

A<5>

D<13>D<11>

A<7>

D<3>D<1>

D<7>D<5>

D<9>

D<15>D<17>D<19>

D<23>D<21>

D<25>D<27>D<29>

A<1>

A<9>

A<13>A<15>A<17>A<19>A<21>SC_A23SC_A25A<27>A<29>A<31>

D<31>2931

2725232119171513119

57

31

HVDDPURn

D<31..0>

2931

27

211917

111315

975

1

A<31..0>

D5V012.3C<>

12.3C< 12.2G> 8.2A< 8.2A<>

14.1H<>

14.3D<

7.3E>

12.4F< 7.4B< 7.2A< 4.4A< 3.4F<

9.2A<

14.3D< 14.5F<

PLL2_IN_CLK

AUD_SMCLK1

SYS_REFCLK1

2.5E>

6.2C< 2.2B<

8.3H>

7.2G>

100KR510

NO STUFF

NO STUFF

NO STUFF

COMMON

COMMON0R514

0

0

5%

5%

5%R515

0603

0603

0603R513

REFCLK1

MHGP5

SYS_SCL

D3V3

MD1

DPDn

116

108

100102104106

98

114112110

118120

126124122

128

POWER_ENn

5%0402

PLL1_IN_CLK

VBAT

1%0603

51.1R530

GND

GND

GND

1

23

45

dd-mon-year

5 OF 20

600-80433-0000-000

51.1R502

NO STUFF

1%0603

BGP0

GND

GND

231

54

e433jcihla

CON_SMA_TH_ST

CON_SMA_TH_ST

115

109107

99101103105

97

113111

117

127125123121

119

SMA_TH

J39

COMMON

GND

51.1

0603

R522

NO STUFF

1%

GND

PLL2_IN_CLK

SYS_SDAMD3_BGP0

MD2MD0

BGP0COMMON

8.4H> 8.3H>

05%

D3V3

9.4A< 9.2A<

6.2C<> 2.2D<>

0603R521EFUSE_BURN

7.4B<> 7.2A<> 4.4A<> 3.4F<>

31

2

4

GND

5

CON_SMA_TH_STJ41SMA_THCOMMON

SMA_TH

J47

COMMON


11.2D>

18.5D<> 15.4A<> 12.3G>

11.3C> 11.4H>

COMMON

7.1E>

.1UFC502

D5V0

22UFC503

.1UFC516

HVDD

C51422UF

16V 16VCOMMONCOMMON

4.3D< 10.3D> 10.3F<>

COMMON

10%X5R0402

10.3F<

12.5F<>

2.54MM

HDR_1M2

COMMON

J45MALE

NORM0

14.3D<>

12

MD3

GND

14.3D<

N/AN/A

N/A10VTAN

SMA

0402COMMON

X5R10%

SMA

TAN10VN/A

N/AN/A

GND

CSn

8.5H> 9.5A<

NO STUFF

NO STUFF

COMMON

05%

0

0

05%

5%

0402

0402

0402R51

R47

R44

R43

20.5E<

11.5C< 20.3C> 5.2H<

13.4B< 13.3A<

CS3n

CS2n

CS1n

CS0n

20.3C>

11.5C<

7.5E>

COMMON0

5%

0R5125%0603

AUXVDD

0603R507

SMDCON_MICTOR_38J38

COMMON

HOST_RDYn 38HOST_WRn 36

343230282624222018

A<19>A<20>

A<18>

BE1nBE0n

CSn

BE2nBE3n_A1

RDn

5% NO STUFF

18

2019

A<21>21 1614121083735333129

A<24>A<25>

A<23>A<22>

A<3>A<2>

A<6>A<5>A<4>

A<7> 27252321191715131197

A<10>A<11>A<12>A<13>A<14>A<15>A<16>A<17>

A<8>A<9>

22232425234567891011121314151617

1

65

2

43

3940

434241

GND

A<31..0>

HOST_REFCLK0

Host Interface and Connectors

0402

CON_MICTOR_38

D<16> 38

SMD

J31

COMMON

D<17> 36

182022242628303234D<18>

D<20>D<19>

D<21>D<22>

D<24>D<23>

D<25>D<26>D<27> 16

29313335378

101214

D<29>

D<31>D<30>

D<28>

D<0>

D<3>

D<1>

D<4>

D<2>

D<5> 27

79

1113151719212325

D<7>

D<9>D<8>

D<6>

D<10>D<11>D<12>D<13>D<14>D<15>

16171819

2120

2223242526

HVDD

100K5%

R69

272829303101234

7.3H>

56789101112131415

COMMON0402

4321

39

65

40

434241

GND

D<31..0>

16V10%X5R0402

.1UFC61

COMMON

EXT_HVDD

D<31..0>

12.3D<

3.2F< 3.2F<

HOST_REFCLK0

CS3nCS1n

VAR_L_WRn

HOST_BE3nHOST_BE1n

0COMMON5%

R320402

RDn

2

68

4

22

10

24

20

1412

2628

1618

30

10

24

HOST_WRn

2830

26

22

1820

161412

864

INTRn0

D<26>

D<30>D<28>

D<24>D<22>

D<16>D<18>D<20>

D<14>D<12>

D<4>D<6>

D<10>D<8>

D<2> 2

A<31..0>

30

24

20

0

26

22

1618

14

1012

68

02

28

4

A<26>

D<0>A<30>A<28>

A<24>A<22>A<20>A<18>A<16>A<14>A<12>A<10>A<8>A<6>

A<2>A<0>

A<4>

32

3638

40424446

34

485052545658606264666870727476

7880828486

104106

889092949698100102

SAM_MIT_06J504

COMMON

MALEM_CPU

21.21MM

1357

1311

15

9

17

2321

2527

19HOST_BE2n

HOST_RDYn

HOST_BE0n

CS2n

13.3B< 13.2A<

2931

3537

33

3941434547

55535149

57

65636159

D<29>D<31>

D<25>D<27>

25272931

23 D<23>D<21>D<19>D<17>D<15>D<13>

D<9>D<7>D<5>

D<11>

2119171513119753 D<3> 67

75737169

8583817977

9593918987

1019997

103105

A<27>A<29>

A<23>

A<19>

D<1>

A<21>

A<25>

A<31>

A<17>

1312927

2523211917

A<15>A<13>A<11>A<9>A<7>

A<3>A<5>

A<1>

15131197

135

CS0n

D<31..0>20.2C<>

A<31..0>

EXT_HVDD

11.2B<

SPMOSI

EXT_HVDD

D5V0

SPCK

HOST_SCL

CTRL_HVDD

2.54MM

HDR_1M2

0

MALE

NORM

J33

COMMON

21

D5V0

118120122124

116

108110112114

126

134132130

142144

136138140

128

146148150152

GND

22UF

TAN10VN/A

N/A

C60

COMMON

N/ASMA

GND

COMMON

C62.1UF16V10%X5R0402

GND

N/AN/A

N/A10VTAN

SMA

22UFC65

COMMON

MALE21.21MM

M_CPU

SAM_MIT_06J504

COMMON

107109111113

115

123121119117

125

133131129127

135

141143

139137

145147149151

156155154153

GND

COMMON5%0

PRE_PRCLK

H_RESETn

SPMISOSPSSnTSINTnHOST_SDA

0402R65

COMMON

D5V0

0R635%0402

3.2B> 3.2F< 3.2F>

PRCLK

10.4A< 12.3D<

7.3A<

EFUSE_PWR_ENABLE15.2B<

HOST_RDYn

159160

157

158

161162

163164165166167

168169170171172

GND

13.1A<

WMP HOST CONNECTOR

E433 SC15 Evaluation MainBoardHOST INTERFACE AND CONNECTOR

HOST INTERFACE CONNECTOR

IN

IN

IN

ININ

ININ

OUT

IN

IN

ININ

OUT

ININ

IN

IN

IN

IN

OUT

IN

IN

IN

IN

V1.0

V1.0Male Host

GNDSYS_CLK

BE0*

OE*

D31D29D27

NCINTR0*

BE1*

CS0*CS2*SUSPEND

D17D19

D23D21

D25

D15

D7D9

D13D11

D5D3D1

A31

HVDD

RST*HVDDHVDD

A29

A21A23A25A27

A19

A11A13A15A17

A9A7A5A3

D5VA1

D5VHOST_SDAMHGP6MHGP4MHGP2

NCNC

NC

MHGP0

H_GPIO1H_GPIO3

D3V3D3V3

GND

GNDGNDGND

RESET_OUT*

GNDREFCLK0

BE2*

D30

WR*

CS1*

RDYINTR1*

D28D26

RD*BE3*

CS3*

D22D20

D16

D12D10

D14

D18

D24

D6D8

D4

A30

HVDD_FBHVDDHVDDNCD0D2

A28A26A24

A12A10

A14A16A18A20A22

A8

MHGP3

D5VD5V

HOST_SCL

MHGP5

A6A4A2A0

NC

MHGP1

DPD

D3V3

H_GPIO4H_GPIO2

POWER_EN*

NC

GNDGNDGNDGND

IN

BI

IN

IN

IN

IN

OUT

IN

IN

GNDGNDGND

A2-3A2-2

CLK0

A0-1

A3-7A3-6A3-5A3-4A3-3A3-2

A2-4

A2-1A2-0

A0-3A0-4A0-5

A0-7A1-0A1-1A1-2A1-3A1-4

CLK1

NCNC

NCNC

A2-5A2-6

A1-6A1-7

A3-0A2-7

A3-1

A0-6

A1-5

A0-2

A0-0

GNDGND

OUT

GNDGNDGND

A2-3A2-2

CLK0

A0-1

A3-7A3-6A3-5A3-4A3-3A3-2

A2-4

A2-1A2-0

A0-3A0-4A0-5

A0-7A1-0A1-1A1-2A1-3A1-4

CLK1

NCNC

NCNC

A2-5A2-6

A1-6A1-7

A3-0A2-7

A3-1

A0-6

A1-5

A0-2

A0-0

GNDGND

OUTOUT

OUTOUT

OUT

OUTOUT

BI

IN

ININ

OUT

1/2 CPU CON

BE3*

FLLDA

GND_1

NC_4

SDRAS

SDCLKGND_3

SDCKE*

BE1*OE*

WE*RUN

CS1*CS3*

PDWN*

IRIN0*PMCLKBSEL0

SDWE*

D <30>

D <26>

D <14>D <16>D <18>D <20>D <22>D <24>

D <28>

D <12>

A <30>D <0>D <2>D <4>D <6>D <8>

D <10>

A <28>A <26>

A <8>A <10>A <12>A <14>A <16>A <18>A <20>A <22>A <24>

A <6>A <4>

BVDD

BVDD

BVDDBVDD

BVDDBVDD

A <2>A <0>

D5VD5VD5VD5VD5V

I2CA2I2CA0

SPMOSI

XBEN*SPSCK

SCL

SGPIO4SGPIO2

SGPIO6SGPIO8

SGPIO0NC_9

NC_7PUR*

NC_2

SDCAS*NC_3

SDCS*NC_5

NC_1GND_2FLCK

BE2*

IRIN1*SDA10

CS0*

CS4*CS2*

WKUP*

BE0*FLAADV

BSEL1

RDY

D <21>D <19>D <17>D <15>

D <31>D <29>D <27>

D <23>D <25>

D <13>D <11>D <9>D <7>D <5>

A <31>D <1>D <3>

A <27>A <29>

A <23>

A <19>

A <15>

A <11>

A <17>

A <21>

A <13>

A <25>

A <9>A <7>

BVDD

BVDDBVDDBVDD

BVDDBVDD_11A <1>A <3>A <5>

PRCLK

SPMISOSPSS*TSINT*

I2CA1

D5V

D5VD5VD5V

D5V

SDA

SGPIO7SGPIO5SGPIO3SGPIO1

SGPIO9NC_6RESET*

NC_8

ININ

INBIOUT

OUT

OUT

CONCPU2/2

GNDGNDGNDGNDGND

GNDGNDGND

GNDGND

GNDGND

GNDGNDGND

GNDGNDGNDGNDGND

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY0402

5%0R642

COMMON

+/-50PPM14.31818MHZ

COMMON

XTAL

HC49SMDY501

1

D3V3

2.54MM

NORM

MALEHDR_1M3J15

COMMON

032

50V

NPO5%

0402

22PFC593

COMMON

YO

3

21

30V

200MA

COMMON

SOT23

D2

BAT54SLT1

+/-50PPM14.31818MHZ

NO STUFF

XTAL

HC49SMDY1

33PFC6180402 50V

270PF

0402C0G5%50V

C620

COMMON

1.8uH

C0G+/-5%

COMMON

COMMON0603L514

100PF

COMMON

C616

50V5%

0402C0G

3

6

12

CON_MINIDIN_4_SPRINGSVHS

J4

COMMON

8

5

1110

6 OF 2013-SEP-2004

600-80433-0000-000e433jcihla

CO

2

3

1

BAT54SLT1

SOT23

30V

200MA

D1

COMMON

1.8uH

33PFC61750V0402+/-5%C0GCOMMON

COMMON0603L513

C615

270PF

5%C0G0402

50V

C619

COMMON

100PF

COMMON

5%50V

0402C0G


COMMON

R681

5%0402

0

COMMON

123

22PFC614

5%50V

NPO0402

0

J7MALE

HDR_1M3

2.54MM

NORMCOMMON

TVO_XITVO_XO

COMMON

R701751%0402

NO STUFF0

5%

0402

0402R679

R675

COMMON

751%

TVO_C

TVO_Y

TVO_CVBS

36

35

34

23

22

24

PCtoTV Encoder3.3V

CH7013BLQFP-48

-40..85C

U3

COMMON

9764321484746

10

R_MOD_LVS

R_MOD_LSC0R_MOD_LHS

43

45

41

44

29

1716151411

30

39

32

COMMON

1

45

23

6

10

87

9

11

1615

1314

17

05%0603

R645

TVO_ADDR

0

0

10K

COMMON

COMMON5%

5%

0603

0603

R643

R644

R646

100K

R700

COMMON

75

04021%

38

28

26

21

40

31

208

GND

TV Encoder and Connector

42

37

25

13

12

33

185

27

19

TVO_RSET

301R680

1%0402COMMON

GND

TO_DVDD

0.1UFC603

COMMON

16V

0402X7R10%

0.1UF

COMMON

C604

10%

0402X7R

16V

TVO_CSYNC

0402

16V

X7R0402

10%

0.1UFC596

R699

COMMON

COMMON

75

GND

1%

GND

NO STUFF5%0402COMMON

0.1UFC611

COMMON

X7R0402

10%16V

10UFC606

20%X5R0805

6.3V

COMMON

TO_AVDD

0.1UFC602

16V

X7R10%

0402COMMON

0.1UF

COMMON

C608

16V10%

0402X7R

120R@100MHz

6.3V20%

0805X5R

10UFC610

COMMON

COMMONBEAD_0603LB508

MOD_LSC0

SYS_SDASYS_SCL

MOD_LHSMOD_LVS

120R@100MHz

LD<17..0>2.1F< 2.2B>

15.4A< 2.2B<

D3V3

R651

2.2G<

2.2G< 2.2G<

2.3A>

15.4A<> 2.2D<>

18.5D< 3.4F<

2.3E> 2.3E>

3.3G<

18.5D<> 4.4A<> 3.4F<>

5.3H< 4.4A<

3.3G< 3.3G<

5.3F<> 7.2A<

2.2E>

12.3C<> 8.2A<> 7.4B<> 7.2A<> 12.3C< 12.2G> 8.2A< 7.4B<

3.2B<

12.3G> 12.4F<

14.3D<> 12.5F<> 14.3D<

5%0402

D3V3

COMMONBEAD_0603LB509

14.31818 Mhz for NTSC

E433 SC15 Evaluation MainBoardTVOUT ENCODER AND CONNECTOR

17.xxxx Mhz for PAL

Y

Y_GND

C

C_GND

XI

XO_FIN

C

Y

VDD

AGND

CVBS

AVDD

GND2

GND1

DGND4

DGND3

DGND1

DGND2

D5

D8

D12D11

D13D14D15

CLOCKDATA

D10

D7D6

D9

D1

D4D3D2

D0

ADDR

DVDD3

DVDD4

DVDD2

DVDD1

NC4

NC3

NC2

NC1

RSET

CSYNC

POUTBCO

XCLKHV

IN

BIIN

INININ

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

7.3H> 5.4D> CTRL_HVDD

D3V3

11.4F<

11.4E<

11.4C<

5.3H<

11.3A<

VID_PWR_ENn 4.3A<

SINGLE-3V3

COMMON

U84

DCK3

5

GND

D3V3

2

16

15

14

13

12

9

11

10

7 OF 2013-SEP-2004

600-80433-0000-000

SUMMITS_HEALTHY

0

0

0COMMON

COMMON0603 5%

5%0603

5%0603 COMMON

e433jcihla

0COMMON5%0603

SOICDIPSWITCH8

R529

R531

R534

R619

S5

COMMON

1

2

3

4

A23_REMAPn

A24_REMAPn

A23_GNDn

DPDn

CTRL_HVDD 5

8

7

6

10K5%0603COMMON

R620

PWR_VID_IO_EN

5%0603

10KR616

COMMON0603

10KR614

COMMON

5%

R610

COMMON

10K5%0603

COMMON

10K5%0603

R60810K5%0603

R604

COMMON

COREVDD_HEALTHY

AUXIOVDD_HEALTHY

POWERGOOD

GND

14.4F<

15.3B>

14.3D>

IOVDD_HEALTHY17.3A>

16.3A>

14.3D<> 14.3D<>

14.4E<

17.3A<

SMT3_PWREN0

PWR_GPIO0PWR_GPIO1

COMMON0

5%

EXT_HVDD_ONn


SCHMOOTESTPOINT

5%10K

0603

R596

TP2

COMMON

COMMON

1

TP502TESTPOINT2

1

SCHMOOCOMMON

5.1H<

5.1F<

SYS_REFCLK0

SYS_CLK

CLK_TP

5.3H< SYS_REFCLK1

TESTPOINT2SCHMOO

SCHMOOTESTPOINT2

TP501

COMMON

COMMON

COMMON

COMMON0402X5R10%10V.1UFC57

COMMON

HVDD

GND8

SOICICS83026I01U509

COMMON

D3V3

10402

R569

COMMON

1%1K

7

435%

43

0603

25V5%

56PFC56

R55

COMMON5%

COMMON

NPO0402

GND

0603

25V

NPO0402

56PFC59

R56

COMMON

5%

6

5

GNDGND

HVDD

TP1

1

435%

COMMON43

5%

0603R583

0603

X5R0402

.1UF10V10%

C52

R579

COMMON

GND

7

8

5

6

4

3

2

0402

R568

COMMON

1K1%

D3V3

GND

SOICICS83026I01U510

COMMON

1KR584

1%0402

2

1

3

4

COMMON

1KR580

1% C547 C552

R593

COMMON

5%10K

0603

1

TESTPOINTTP3SCHMOOCOMMON

1

R750603

SINGLE-3V3

4

DCK

U10

COMMON

5

3

GND

D3V3

14.3G<

5.3F<

19.3F<

14.4F<

HVDD

SMT1_PWREN0

EFUSE_BURN

AC97_AUD_RESETn

SMT2_PWREN0

SUMMITS_HEALTHY

10K

06035%

R617

R25COMMON

2

0603

10K

COMMON

5%

GND

Programmable Oscillator and Auxillary GPIOs

56PF

0402NPO

25V

COMMON

5%

GND

56PF

0402COMMON

5%NPO

25V

GNDGND

COMMON0402

7654

PCA9555SOP24

U518

COMMON

2019181716151413

111098

GND

GND

24

2322

1

12

32

21

HDR_1M3

2.54MM

.1UFC550

COMMON

COMMON

10V10%

0402

.1UF

X5R

C58

COMMON

GND

COMMON06035%

R6250

D3V3

10%X5R0402

.1UF10V

C540

SYS_REF_CLK

COMMON

J24

0

MALE

NORM

GND

1

32

VARIABLE_CLK

C51

10%10V.1UF

X5R0402COMMON

GND

43COMMON5%0603

R19VCLKR

R63205%0603COMMON

iprg

16

15

814

9

114

NO STUFF0

GND

5%0603R49

D3V3

PRCLK

GND

32.768MHZ

0402

1K1%

R624

COMMON

SSOPFS7140U7

PS_XIN

6

5

12

COMMON

73

12

1310

C23

5%50V22PF

PO_XOUT

0603C0G

COMMONSYS_SCLSYS_SDA

R13 R23100K

COMMON

5%0402

Y5TXC-6N32700095

5.3A>

100K

COMMON

5%0402D3V3

24.576MHZ+/-30PPM

1MCOMMON

COMMON

5%

XTALY3

CER_SMD

0402

C0G5%50V22PFC24

R16

15.4A<> 12.5F<> 12.3C<> 7.4B<>

6.2C<>

3.4F<> 2.2D<>

0603COMMON

GND4.4A<>

12.3G> 8.2A<>

18.5D<> 14.3D<>

5.3F<>

10VC4710%

0402X5R

GND

D3V3

.1UF16V

X7R0402

10%

C34

COMMON

GND

NO STUFF

COMMON

0

05%

5%R450603

R460603

SYS_OSC_OUT

4

3

D3V3

8

SYS_OSC_OUT

D3V3

5

15.4A<> 14.3D<> 18.5D< SYS_SCLSYS_SDA

I2C_INTn8.2A>

18.5D<> 12.5F<>

8.2A<>

5.3F<> 2.2D<>

AUX_GIO_A2AUX_GIO_A1AUX_GIO_A0

12.3C<>

6.2C<> 3.4F<>

NO STUFF

R26

04025%

COMMON

0

12.3G>

7.2A<> 4.4A<>

04025%0R36

COMMON

R280

04025%

NO STUFF

5%0

0402

R31

2.2B< 12.2G> 3.4F<

5%0

0402

R27

NO STUFF

04025%0R29

COMMON

GND

12.3C< 4.4A<

+/- 50 PPMSMDCOMMON

1

2

SKT_4PIN_TH

1108800

N/A

J506

NO STUFF

1

GND

.01UF

0402X7R10%16V

COMMON

GND

.01UF

0402X7R10%16V

C41

COMMON

4

GND

GND

15.4A< 14.3D< 12.4F< 8.2A< 7.2A< 6.2C< 5.3H<

PROGRAMMABLE OSCILLATOR

AUXILIARY GPIO CONTROLSControls Address Mapping, Deep Power Down, Etc


OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUTOUT

OUT

OUT

OUT

OUT

ICS83026I-01

Q0

VDDO

Q1

GND

VDD

CLK

OE

CLK*

OUTOUT

OUT

OUT

ICS83026I-01

Q0

VDDO

Q1

GND

VDD

CLK

OE

CLK*

IO_0_0IO_0_1

IO_0_7IO_0_6IO_0_5IO_0_4

IO_0_2IO_0_3

IO_1_0

IO_1_4IO_1_3IO_1_2IO_1_1

IO_1_5IO_1_6IO_1_7

VDD

INT

SDASCL

GND

A2A1A0

PLL_CLKFS7140-01

CLKN

CLKP

VDDVDD

VSSVSS

IPRG

REF

XOUT

XIN

NCNC

SCLSDA

ADDR0ADDR1

IN

BIIN

INBI

OUT

VCC

OUTGND

EN

VCC

OUT

EN

GND

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY 13.2C< 11.5D< BUS_TYPE_C

C587

HVDD

.1UF

11.5C<

13.5E<

WR_LATC

SWT_32_16

5.3F< 9.2A<

MD0

.1UFC598

COMMON

16V10%X7R0402COMMON

GND

9

6

4

HVDD

16V10%X7R0402

9

6

4

TDFN_12PI5A3158

PI5A3158TDFN_12

U524

COMMON

COMMON

U6

.1UF

X7R10%16V

0402

C589

COMMON

HVDD

12

3

1

2

TDFN_12PI5A3158U6

COMMON

10

11CTRL_TYPE_C

DIP_CTRL_TYPE_C

CTRL_A_M_TYPE_C

7

8

5

X7R0402

10%16V.1UFC515

COMMON

HVDD

GND

9

4

7

8

5

CTRL_A_M_MD

CTRL_MD0

DIP_CTRL_MD0

GND

6

COMMON

TDFN_12PI5A3158

COMMON

8

5

U5

CTRL_A_M_WR_LATC

DIP_CTRL_LATC

CTRL_WR_LATC

CTRL_32_16

DIP_CTRL_32_16

7

16V.1UFC613

10%

5%0

0402R674

0402X7R

COMMON

GND

SINGLE-3V3U530

COMMON

HVDD

CTRL_A_M_32_16

4

DCK

5

3

2

5.3H< 9.2A<

MD1

5.3F< 9.4A<

MD2

.1UF

.1UFC599

C601

COMMON

COMMON

HVDD

GND

10%

0402

16V

X7R

12

3

1

HVDD

GND

10%X7R

16V

0402

12

3

1

5.3E< 9.5A<

MD3

8 OF 20dd-mon-year

600-80433-0000-000

.1UFC600

COMMON

16V

HVDD

GND

910%

0402X7R

4

6

e433jcihla

GND

TDFN_12PI5A3158

TDFN_12PI5A3158

PI5A3158TDFN_12

U524

U525

U525

COMMON

COMMON

COMMON

CTRL_MD1

10

11

2

CTRL_A_M_MD

DIP_CTRL_MD1

10

11

2DIP_CTRL_MD2

CTRL_A_M_MD

CTRL_MD2COMMON

0COMMON

GND

0402 5%R669

0402X7R

16V10%

.1UFC595

COMMON

05%0402

R647

GND

DCKSINGLE-3V3U521

COMMON

HVDD

45

3

2

5

7

8

CTRL_A_M_MD

DIP_CTRL_MD3

CTRL_MD30COMMON

GND

0402X7R

16V10%

.1UF

COMMON

C597

5%0402R667


GND

SINGLE-3V3

SINGLE-3V3

10%X7R0402

16V.1UFC607

U522

U528

COMMON

COMMON

COMMON

D3V3

68R621

DS1 21

20MA

GREEN2.2V

0805

LED_SMD_0805

COMMON

5%

D3V3

CTRL_MD0n

DIPSWITCH8SOIC

0603

S4

COMMON

COMMON

15

16

12

13

14

1

2

3

4

5

9

11

10

8

7

6

R653

COMMON

5%0603

10K

68

06035%

R618

COMMON

D3V3

DS2 21

GREEN

20MA2.2V

0805

LED_SMD_0805

COMMON

R615

D3V3

DS3 2

68

1

GREEN

20MA2.2V

0805COMMON

LED_SMD_0805

R611

D3V3

DS4 2

68

1

GREEN

COMMON0805

20MA2.2V

LED_SMD_0805

0603

100K5%

R626

COMMON

R633100K5%0603COMMON

5%5%

COMMON0603

R64010K

06035%

COMMON

10K5%0603

R635

COMMON

R62710K

0603COMMON

5%

COMMON0603

CTRL_MD3n

CTRL_MD1nCTRL_MD2n

CTRL_MD0n

10.3A<

HVDD

GND

4

DCK

5

3

2

GND

HVDD

CTRL_MD1n

CTRL_MD2n

5

DCK

4

3

GND

2CTRL_MD3n

NO STUFF0

5%

GND

Host Interface Control and I2C Bus Expansion

11.2E<

11.2E<

GND

DIP_CTRL_MD0

DIP_CTRL_MD1

DIP_CTRL_SW_A1_A2

DIP_CTRL_MD2

DIP_CTRL_LATC

DIP_CTRL_TYPE_C

DIP_CTRL_32_16

DIP_CTRL_MD3

100K

06035%

R661

COMMON

R659 R660100K

06035%

COMMON

100K

06035%

COMMON

D3V3

R7310402

CTRL_A_M_TYPE_C

CTRL_AUX1

CTRL_A_M_WR_LATC

CTRL_A_M_32_16

CTRL_A_M_MD

CTRL_I2C_SW 12.3D<

11.2B< INDIRECT_SW

100K

06035%

R730

COMMON

100K

0603

R707

COMMON

5%

HVDD

100K

0603

R706

COMMON

D3V3

R637100K5%0603COMMON

R639100K

COMMON06035%

CTRL_WR_LATC

CTRL_LED1CTRL_LED0

I2C_RESETn

CTRL_32_16CTRL_TYPE_C

654

7

1413

11

8910

CTRL_LED215

GNRLIO_SW3GNRLIO_SW2GNRLIO_SW1

CTRL_LED3GNRLIO_SW0

20

16171819

PCA9555SOP24

U520

COMMON

24

1

2223

32

12

21

GND

SYS_SCLSYS_SDA

I2C_INTn

I2C_GIO_A1I2C_GIO_A2

I2C_GIO_A0

D3V3

.1UF

10%16V

X7R0402

C22

COMMON

GND

12.2G> 2.2B<

7.4B>

12.3C<

6.2C< 3.4F<

12.4F<

7.2A< 4.4A<

5%0402

R12

7.4B< 5.3H<

0

NO STUFF

04025%

R11

COMMON

0

14.3D<

0402

0402

R664

R665

NO STUFF

COMMON

D3V3

5%0

15.4A<

15.4A<> 12.5F<>

R663

18.5D<

7.4B<>

6.2C<>

4.4A<> 2.2D<>

0402

05%

18.5D<> 14.3D<>

12.3G>

12.3C<>

7.2A<>

5.3F<> 3.4F<>

NO STUFF

1

5%0

2

R662

COMMON

1

0402

05%

2

GND

R657 R658100K

06035%

COMMON

100K

0603COMMON

5%

R655 R656100K

06035%

COMMON

100K

06035%

COMMON

HVDD

R654

COMMON

5%0603

100K

16

15

14

13

12

11

10

9

5%100K

0603

R705

COMMON

5%100K

0603

R704

COMMON

5%100K

0603

R703

COMMON

5%100K

0603

R702

COMMON

5%

16

15

11

12

13

14

10

GND

9

DIPSWITCH8

DIPSWITCH8

1

SOIC

S3

COMMON

2

6

5

4

3

7

8

GND

COMMON

S2

SOIC

1

2

6

5

4

3

7

8

GND

HOST INTERFACE CONTROL LOGIC AND I2C GPIOE433 SC15 Evaluation MainBoard

OUT

OUT

OUT

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

VVC_1

A1

GND_1

0B1

1B1

S1

VVC_1

A1

GND_1

0B1

1B1

S1

OUT

OUT

OUT

VVC_1

A1

GND_1

0B1

1B1

S1

VVC_0

A0

GND_0

0B0

1B0

S0

VVC_0

A0

GND_0

0B0

1B0

S0

VVC_1

A1

GND_1

0B1

1B1

S1

OUT

OUT

OUT

OUT

IO_0_0IO_0_1

IO_0_7IO_0_6IO_0_5IO_0_4

IO_0_2IO_0_3

IO_1_0

IO_1_4IO_1_3IO_1_2IO_1_1

IO_1_5IO_1_6IO_1_7

VDD

INT

SDASCL

GND

A2A1A0

IN

OUT

BI

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

5.3E< 8.5H> MD3

5.3F< 8.4H> MD2

GND

3

2

C512

COMMON

.1UF

10%16V

X7R0402 5

COMMON

U27

SC70_5NC7SV17

24 MD3_LEDDS11

080520MA

COMMONGREEN2.2V

1 MD3_LRLED_SMD_0805

R5160603 5% COMMON

68

D3V3

GND

2

3

24 MD2_LED

COMMON

C507

0402X7R

16V10%

.1UF

5

D3V3

GND

COMMON

U29NC7SV17SC70_5

DS12

20MA0805 COMMON

2.2V GREEN

1 MD2_LR R5060603 5% COMMON

68LED_SMD_0805

5.3H< 8.3H> MD1

5.3F< 8.3H> MD0

2

3

COMMON

C501.1UF

10%16V

X7R0402 5

COMMON

U31

SC70_5NC7SV17

24 MD1_LED

D3V3

GND

COMMON

2

3

24 MD0_LEDDS14

DS13

080520MA

20MA0805

COMMONGREEN2.2V

1 MD1_LRLED_SMD_0805

R5050603 5% COMMON

68

2.2V

1COMMON

LED_SMD_0805

GREEN

MD0_LR R5040603 5% COMMON

68

16V

X7R0402

C506

10%

.1UF

5

D3V3

COMMON

U30NC7SV17SC70_5

GND

GND

GND

GND

VVDD

Mode and Voltage LEDs

COMMON

3

2

GND

4

0402 5

C113

X7R

16V10%

.1UF

GND

D3V3

COMMON

U503NC7SV17SC70_5

DS8

080520MA

2COMMON

2.2V GREEN

1LED_SMD_0805

R5270603 5% COMMON

68

HVDD

LVDD

COMMON

3

2

0402

C129.1UF

10%16V

X7R

5

COMMON

U501NC7SV17SC70_5

4

COMMON

X7R0402

35

2

GND

D3V3

COMMON

4

DS10

DS9

0805

080520MA

2COMMON

2.2V GREEN

1LED_SMD_0805

R5250603 5% COMMON

68

20MA

2COMMON

2.2V GREEN

1LED_SMD_0805

R5260603 5% COMMON

68

10%

C118

16V.1UF

D3V3

U502NC7SV17SC70_5


GND

GND

jcihlae433

600-80433-0000-000

dd-mon-year

9 OF 20

GND

LED_SMD_0805

0805GREEN

COMMON

1

04025%300R533

COMMON

GND

COMMON

GREEN0805

5%

1

COMMON

R535

0402

100

COMMON

GREEN0805 1

GND

COMMON

R541

5%0402

200

2.2V2.2V2.2V

DS7

20MA

2

D5V0

DS6LED_SMD_0805

20MA

2

D3V3

LED_SMD_0805DS5

20MA

2

VBAT

E433 SC15 Evaluation MainBoardMODE and VOLTAGE LEDS

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

IN

IN

IN

IN

PRELIMINARY

SDVDD

C3922UF

TAN

N/A

N/AN/A

10V

SMA

COMMON

D3V3

R351200.1%0603

0.1%200

0603

R34

COMMON

COMMON

GND

SDVDD

GND

42

GOI,IGOI,TO263

LM1086CS-ADJ

TO263

N/A

COMMON

U13

1

100UF

3

D5V0

C30

10V

SMD

20%

TANTAL

80MOHM662

COMMON

GND

24

81012

6

14161820

2.54MM

NORM

HDR_2X10

COMMON

J36MALE

90

13

975

1917151311

GND

GND

8642

141210

HDR_2X7J12

GND

MALE

NORM

2.54MM

COMMON

0

31

975

1113

COMMON0

10 OF 20dd-mon-year

600-80433-0000-000e433jcihla

SDVDD

5%

100K5%

R673

0402COMMON

5%100KR638

100K5%

R648

0402COMMON

04025%

100KR668

COMMON

GND

0402COMMON

0402R649R_RESET_OUT

TDOTCK

TDI

TRSTn0NO STUFF5%0402

R636PURn

TCK

TDITMS

TDOPURn

C16

0402

.1UF

COMMON

X5R10%10V

GND

SDVDDD3V3

1

24

5

FXLP34SC70_5

U523

COMMON

GND

TRSTn

04025%

100KR650

COMMON

TMS10.4F>

GND

3

14.2F< 10.4F>


RESET_OUT

14.2F<

4.3D<

14.2F< 14.1F<

14.1F<

14.1F> 4.3D<

15.3B< 4.3A< PUR

SINGLE-3V3

4

DCK

U4

COMMON

5

3

2COMMON

D3V3

C605

04025%10KR670

10V10%X5R0402

.1UF

COMMON

14.3D< 10.3F< 10.3D> 5.2F<

14.3D< 10.3F<> 10.3D> 5.2F<

C17.1UF

0402X5R10%10V

COMMON

GND

14.3D< 10.3F< 10.3F<>

RESET, JTAG and 3V3 Power

5.2F< 4.3D< PURn

GND

HOST_RESETnCOMMON0

5%0603R677

GND

GND

COMP_HOST_RESETn

MAX6306

D3V3

U2

5%0

0402

R671

COMMON

D5V0

0

04025%0R678

R2

NO STUFF

I2CR_PU SOT23_5

1

2

3

COMMON

4

5

X7R0402

10%16V.1UFC609

COMMON

.1UF

X5R0402

10%10V

C612

D3V3D3V3

5%

MAX_VCC

47K

0402

R697

COMMON

COMMON

5%0402

5%47KR1

0402

SW_RESET

3

2

SMD_4SW_SPST_PB

SW_KT11P2SMS1

COMMON

COMMON

C50402

4

1

GND

H_RESETn_3V3

X5R

.1UF

10%10V

0402

C7

COMMON

74LVC1G11

COMMON

GND

4

DBV_6

U1

COMMON

51

3

2

6

GND

PWR_RESETn

RESET_OUTnNO STUFF

0COMMON

0

0402

.1UFC13

COMMON

10V

X5R10%

COMMON

SINGLE-3V3

4

GND

U527

DCK

GND

GND

D3V3

GND

5%

1UF

X5R10%6.3V

5%

COMMON

D3V3

I2C_RESETn8.2C>

HVDD

SC70_5FXLP34U529

COMMON

1 5

4

3

COMMON

.1UF10V

C6

0402X5R10%5%

GND

2H_RESETn

47K

0402

R559

COMMON

5.4A>

0603R698

0603R676PMOD_RESETn

SUMMIT_RESETn

GND

5

3

2RESET_OUT

14.3F>

15.4C>

D3V3 Set to 3.3V @ 500 mA

3V Regulator

Reset, JTAG and 3.3V Power


RESET CIRCUIT

From Host

OUTTAB

GND/ADJ

IN

OUTBI

OUTOUT

ININ

OUT

OUT

OUTRST*

GND

MR*RST_IN

MAX6306

VCC

IN

IN

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

20.3E> 5.3H<

.1UFC97

COMMON

10%X7R0402

16V

A2_SW_IND

GND

HVDD

9

4

TDFN_12PI5A3158U11

COMMON

8

5

67

A2_SW_IND

A<1>

.1UF

COMMON

C541

16V10%X7R0402

5.3F<

16V10%X7R

.1UFC542

HVDD

90402

SC_A25COMMON

GND

6

4

11 OF 2012-JUL-2004

600-80433-0000-000e433jcihla

A23_GND 5

TDFN_12PI5A3158U20

COMMON

7

8

A23_REMAPn

A<25>

.1UFC545

COMMON

16V

0402X7R10%

HVDD

12

1

7.2G> 11.3A<

GND

3

WRn 5.2H<

GND

HVDD


.1UF

10%16V

0402X7R

C555

COMMON

9

4

U22PI5A3158TDFN_12COMMON

8

5

7 6

DIP_CTRL_SW_A1_A2

INDIRECT_SW

A<22>

A<2>

11.2B< 8.5D>

8.4D>

5.3F<

.1UFC544

COMMON

16V

X7R0402

10%

HVDD

12

A3_SW_IND1

GND

3

TDFN_12PI5A3158U20

COMMON

11

2

A<23>

10A23_GNDn

5.3H<

10%

COMMON

C543.1UF

0402X7R

16V

7.2G>

HVDD

9

4

GND

6

TDFN_12PI5A3158U17

COMMON13.4B< 13.3B< 13.3A< 13.2A<

8

5

7

GND

BUS_TYPE_C

Host Interface Address and CType Mode Controls

GND

HVDD

8.1H>

SC_A24

9

4

PI5A3158TDFN_12

U21

COMMON

8

5

67

0402

0402

R571

R572

NO STUFF

NO STUFF

HVDD

5%0

A<24>

1K1%

GND

A24_REMAPn7.2G>

SW_WRn0402X7R10%16V.1UF

COMMON

C559

13.2C<

HVDD

GND

12

1

U17

TDFN_12PI5A3158

COMMON

11

2

10 3

TDFN_12PI5A3158U22

COMMON

11

2

A<3>

A<21>

10INDIRECT_SW

A<25..0>5.3A<

8.5D> 11.2E<

13.1A<

5.3F<

HVDD

10%

0402X7R

16V

COMMON

C546.1UF

GND

SC_A23

12

1

PI5A3158TDFN_12COMMON

11

2

U21

10 3

VAR_L_WRn

HOST_WRn

5.2C>

5.2C>

WR_LATC8.2H>

A23_REMAPn

A<23>

7.2G> 11.4F<

SC15 Address Remap

TYPE C VARIABLE LATENCY CONTROL

(Remaps to Higher Addr space to support autoincrementing buses)

Indirect Addressing Remap(Writes to 0xXX40_0000 control A2, Writes to 0xXX20_0000 control A3)

SC15 Address Remap

HOST INTERFACE ADDRESS AND CTYPE CONTROLS


SC15 Address Remap

OUT

VVC_1

A1

GND_1

0B1

1B1

S1

OUT

VVC_1

A1

GND_1

0B1

1B1

S1IN

OUT

VVC_1

A1

GND_1

0B1

1B1

S1IN

IN

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

OUT

IN

VVC_1

A1

GND_1

0B1

1B1

S1IN

VVC_1

A1

GND_1

0B1

1B1

S1IN

OUTVVC_0

A0

GND_0

0B0

1B0

S0

VVC_0

A0

GND_0

0B0

1B0

S0

IN

IN

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

IN

IN

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

15.4A< 14.3D< 12.4F< 12.3C< 8.2A< 7.4B< 7.2A< 6.2C< 5.3H< 4.4A< 3.4F<

10%16V

0402X7R

.1UFC538

COMMON

SYS_SCL 2.2B< 18.5D<

16V.1UFC535

D3V3

GND

D3V3

12

TDFN_12PI5A3158U24

COMMON

11

2

1

310

PI5A3158TDFN_12

U24

COMMON10%

18.5D<> 12.5F<> 12.3C<> 8.2A<> 7.4B<> 7.2A<> 6.2C<> 5.3F<> 4.4A<>

12 OF 20dd-mon-year

600-80433-0000-000e433jcihla

15.4A<> 3.4F<>

14.3D<> 2.2D<> SYS_SDA

COMMON0402X7R

R10

D3V3

R9

GND

9

6

4

7

8

5

4.7K4.7K

0402COMMON

5%

SYS_SCL

COMMON04025%

SYS_SDA

2.2B<

15.4A<> 2.2D<>

15.4A< 3.4F<

18.5D<> 4.4A<> 3.4F<>

18.5D< 4.4A<


5.3F<>

5.3H<

VGP_SCL_3V3

.1UFC572

16V

COMMON0402

10%X7R

GND7

8

6 4.7KR62

VGP_SDA_3V3

COMMON5%0402

1

2

GND

D3V3

D3V3

U508

COMMONSOT23-8

MAX3373

3

5

4ICSDA_VGP2

ICSCK_VGP1

C530

VVDD

.1UF

X7R10%16V

0402COMMON

GND

HVDD

CTRL_I2C_SW8.5D>

2.2B<>

2.2B>

12.5C<> 4.2D<>

12.4C< 4.2D<

3V3_HOST_SCL

3V3_HOST_SDA

4.7KCOMMON

10%

0402

16V

X7R

.1UFC526

COMMON

GND7

5%0402R66

8

6

1

2

GND

SOT23-8MAX3373

U25

COMMON

3

4

5

8.2A<> 7.4B<> 7.2A<> 6.2C<>

12.2G> 8.2A< 7.4B< 7.2A< 6.2C<

12.3C<>

12.3C<

12.3G>

14.3D<

14.3D<>

0COMMON

COMMON0

5%

5%

IDPROM and I2C Mux Controls

10%

0402

16V

X7R

.1UFC527

COMMON

GND

12.5F<> 14.3D<

12.3G> 8.2A<> 12.4F<

HOST_SCL

HOST_SDA

R5864.7K

04025%

COMMON

7.4B<> 12.2G>

5.4C>

5.4A<>

18.5D<> 7.2A<> 6.2C<> 5.3F<> 4.4A<>

8.2A< 7.4B< 7.2A< 6.2C< 5.3H<

VVDD

4.7K5%0402

R585

COMMON

0402

0402R575

R576ICSDA_VGP2

ICSCK_VGP1

15.4A<> 3.4F<>

4.4A<

2.2B<>

2.2B>

D3V3

10V10%

.1UF

0402X5R

C564

COMMON

GNDU15

0402

100KR597

NO STUFF

5%100KR605

NO STUFF

5%0402

100KR609

COMMON04025%

D3V3

COMMON

R598100K

04025%

24LC02SN

14.3D<> 2.2D<>

18.5D< 15.4A< 3.4F< 2.2B<

SYS_SDASYS_SCL

GND

8

56

4

SO8COMMON

1

7

23I2C_A2

R5950

0402COMMON

5%

12.2D< 4.2D<>

12.2D< 4.2D<

I2C_A0I2C_A1

I2C_WP

R600

COMMON

R606005%0402

NO STUFF04025%

NO STUFF

R5990

04025%

GND

CPU vs GPU I2C Control

I2C and IDPROM


I2C ID Memory

I2C ADDR: 0b1010001

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

OUT

VVC_1

A1

GND_1

0B1

1B1

S1

BI

IN

I2C TranslatorMAX3372

IOVL1

VL

IOVL2

VCC

IOVCC1

TSn

GND

IOVCC2

IN

IN

IN


IOVL1

VL

IOVL2

VCC

IOVCC1

TSn

GND

IOVCC2

IN

IN

IN

BI

INBI

VCC

SCLSDA

GND

WP

A0A1A2

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

BE0n 5.2F<

HVDD

0402COMMON

C549.1UF16V10%X7R

GND

12

3

1

BE1n 5.2F<

BE2n 5.2H<

BE3n_A1 5.2H<

.1UF

0402

C548

COMMON

HVDD

16V10%X7R

GND

4

9

6

.1UF16V10%X7R

C588

HVDD

12

0402COMMON

GND

3

1

PI5A3158TDFN_12

TDFN_12PI5A3158

COMMON

U19

COMMON

10

11

2

IPU_ENABLE

BUF_IPU_WRn

BE0n_WR0n

20.4F>

20.3C>

C581

HVDD

.1UF

X7R

COMMON

10%

0402

16V

GND

HVDD

PI5A3158TDFN_12

U9

12

3

1

COMMON

10

11

2

U9

PI5A3158TDFN_12COMMON

U19

8

5

7IPU_ENABLE

IPU_WRn

BE1n_WR1n

20.2C>

A<1> 2

U5

BE3n_WR3n 11

10SWT_32_168.2H>

10%

0402X7R

16V.1UFC580

COMMON

GND

.1UFC565

COMMON

16V

X7R0402

10%

HVDD

9

4

6

PI5A3158TDFN_12

8

5COMMON

7

3

1

12

PI5A3158TDFN_12

U14

COMMON

10

11

2

X7R

16V10%

0402

.1UFC563

HVDD

COMMON

GND

GND

9

PI5A3158TDFN_12

8

5

U14

COMMON

4

67

BUS_TYPE_C

BUS_TYPE_C

HOST_BE3n

BUS_TYPE_C

HOST_BE1n

HOST_BE0n

C_WR0n

8.1H> 11.5D<

HVDD

0402

10%

.1UF16V

X7R

C578

COMMON

GND 5 U519

4NC7SV32

SC70_5COMMON

3

HVDD

GND

2

1

.1UF

0402X5R10%10V

C569

A<31..0>5.3A<

HOST_BE0n

SW_WRn

5.2A>

11.5D> 13.3A<

11.2B<

13.4B< 13.3B<

HOST_BE2n

BUS_TYPE_C

C_WR1n

C_WR2nNC7SV32

4NC7SV32

SC70_5

U516

COMMON

5

3

GND

HVDD

GND

2

1

COMMON

U5145

4SC70_5COMMON

3

GND

2

1

.1UF

0402X5R10%10V

C562

COMMON

GND

C_WR3nNC7SV32

HVDD

4SC70_5

U513

COMMON

5

2

1

.1UFC558

COMMON

10V

0402

10%X5R

GND

3

GND

HOST_BE1n

SW_WRn

5.2C>

11.5D>

HOST_BE2n

SW_WRn

5.2A>

13.2A< 11.5D> 13.3A<

13.2A<

13.4B<

13.4B< 13.3B<

HOST_BE3n

SW_WRn

5.2C>

13.2A< 11.5D> 13.3A< 13.3B<

18-Jun-2005

13 OF 20

600-80433-0000-000e433jcihla

BASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINALHost Bus Mode C Control Logic

TYPE C BUS MUX CONTROLS


OUT

OUT

OUT

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

IN

IN

VVC_0

A0

GND_0

0B0

1B0

S0

VVC_1

A1

GND_1

0B1

1B1

S1

IN

VVC_0

A0

GND_0

0B0

1B0

S0IN

VVC_1

A1

GND_1

0B1

1B1

S1

VVC_0

A0

GND_0

0B0

1B0

S0

VVC_1

A1

GND_1

0B1

1B1

S1

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

17.3A<

5.4H< AUD_SMCLK1

18.4H> 18.1H>

NO STUFF0

5%0603R628

AUD_SRCLK2

MALE

M_NAME

J43COMMON

4

19.2F<

18.5B<> 18.5B<>

18.4H<>

18.4H< 18.5B>

18.3D< 18.4H> 18.4H<> 18.4H<> 18.4D<

R1CVDD

ACVDD

MMCVDD

TDCVDD

MMCVDD_FB

AUD_SOUTAUD_SINAUD_SFSYNCAUD_SCLKAUD_SMCLK

68101214

22201816

24

32302826

34

42403836

TDCVDD_FB44

S_R1CVDD_FB

52504846

54

605856

6264

GND


CON_QTH_SMT_2X30_P050

1TCK10.3F> 3

11

579

131517192123252729313335373941434547495153

595755

6361

GND

AOCVDD1AOCVDD2

AOCVDD0

TMSTRSTn

TDOTDI

0

0COMMON

COMMON5%

5%

0603

0603

VECVDD

AOCVDD_FB

10.3F> 10.4F>

10.3F< 10.3F>

R117

R5190COMMON5%

R5240603

VECVDD_FB

EMVDD_FB

EMVDD

17.2G< 14.3A>

17.3G< 2.2B>

17.4G< 2.3E> 15.1H< 5.2H>

COREVDD_ENABLE 16.2A<

74LVC1G11

10V10%

0402X5R

.1UFC32

U515

COMMON

COMMON

D3V3

GND

4

DBV_6

51

3

2

6

10%X5R

10V.1UFC33

0

0

0402COMMON

COMMON

COMMON

GND

R335%

5%0603

0603R37

GND

10V.1UFC48

D3V3

.1UFC49

10V10% 10%

15.2B<

14 OF 2005-Jun-2005

IOVDD_ENABLE

600-80433-0000-000

0402X5R

COMMON

GND

4

U51274LVC1G11DBV_6COMMON

GND

5

2

6

3

1

POWER_EN

COMMON

COMMON

X5R0402

05%

e433jcihla

GND

D3V3

SINGLE-3V3

04025%47KR39

U511

COMMON

COMMON

SMT1_PWREN0

POWER_EN

7.4E>

D3V3

R58947K

15.2B<

10.4A<

15.2H< 15.3H< 2.4D>

AUXIOVDD_ENABLE

.1UF

COMMON

C77

10V10%X5R0402

4

DBV_674LVC1G11U506

COMMON

5%

0603R592

542

SMT2_PWREN0

POWER_ENn

COREVDD_HEALTHY

COMMON0402

DCK3

GND

7.4E>

7.5G<

14.3D< 5.4H>

17.3A< 16.3A>

GND

AOCVDD


MALEHDR_1M2J27

21

NORMNO STUFF

2.54MM0

S_ACVDD_FB

S_VVDD_FB

S_LVDD_FBS_HVDD_FB

COMMON

R520

BRD_HVDD

N/A12062.54MM

NORM

MALEHDR_1M2J20

NO STUFF

21

0R50

N/A

01206COMMON

J503

8642

1210

SSW-115-22

NO STUFF

0

FEMALE

NORM

2.54MM

D3V3

1357

119

D5V0

EXT_HVDDHVDDEMVDD

ACVDD

VECVDD

S_AUXVDD_FBS_SDVDD_FB

D3V3

PMOD_RESETn

D3V3

5

2

3

1

6

10%X5R

.1UF

0402

10V

C528

COMMON

COMMON

COMMON

R555

COMMON

47K5%0402

GND

0

05%

5%

0603

0603R551

R554COREVDD_HEALTHY

302826242220181614

GND

131517192123252729

GND

POWER_EN

SMT3_PWREN07.5F>

GND

HDR_1M2_FAN

2.54MM

HDR_1M3

COMMON

COMMON

J35

NORM

MALE2.5MM0

21

R550

J34MALE

NORM0

321

GNDNO STUFF

N/A0

1206

PWR_GPIO0

DAUXIN

Expansion Power Interface

POWERGOOD

SYS_SDA

PWR_GPIO1

SYS_SCL

POWER_ENn

PURn

7.4F>

4.3D<

7.5G<

2.2D<>

7.5F>

5.4H>

5.2F<

15.4A<> 3.4F<> 14.5F<

10.3D> 10.3F<>

18.5D<> 4.4A<>

10.3F<

7.4B<> 7.2A<> 6.2C<> 5.3F<>

AUXVDD

SDVDD

D5V0

R549

1206

0

COMMON

N/A

VBAT

TDCVDD

8.2A<>

AOCVDD

MMCVDD

MMCVDD_FB

VECVDD_FB

TDCVDD_FB

AOCVDD_FB

EMVDD_FB

ACVDD_FB

COMMON

COMMON0

05%

5%0COMMON

COMMON

COMMON

COMMON

0

05%

5%

5%0

5%0603

0603

0603

0603

0603

0603R119

R121

R123

R126

R127

R129

J501

8642

1210

TSM-115-01

NO STUFF

2.54MMMALE

0NORM

302826242220181614

1

11

3579

171513

192123252729

S_MMCVDDS_AOCVDD

S_MMCVDD_FB

S_AOCVDD_FB

S_VECVDD_FB

S_EMVDD_FB

S_ACVDD_FB

S_TDCVDD_FB

16.3H<

16.1G<

16.4H<

16.2H<

17.1G<

14.3F< 17.2G<

S_VECVDD

S_TDCVDDS_ACVDD

S_EMVDD

12.5F<> 12.3G> 12.3C<>

LVDD

R1CVDD

VVDD

BRD_HVDD

GND

COMMON

COMMON

COMMON0

0

0

5%

5%

5%0

COMMON

COMMON

COMMON

0

0

5%

5%

5%

0603

0603

0603

0603

0603

0603R118

R120

R122

R124

R125

R128GND

0

0

0

0COMMON

COMMON

COMMON

5%

5%

5%0603

0603

0603R79

R81

R82

R84

S_HVDD

VBAT

GND

0

0

TSM-115-01J502

COMMON

COMMON

COMMON

5%

5%

5%

MALE

246

1412108

NORM

2.54MM

NO STUFF

0

31

5

97

0603

0603

0603

1311

R86

R88

1615

24222018

26283029

272523211917

VBAT

GND

S_VVDD

S_R1CVDD

S_LVDDS_SDVDD

S_AUXVDD

MODULE POWER CONNECTOR

From Host

From Host

Connect to Battery, AC/DC Supply

or Alternate Source

VBAT Select: 1-2 DAUXIN, 2-3 D5V0

Auxilliary Power for VBAT

HVDD SELECTION JUMPERS

IO FEEDBACK and MISC CONNECTOR

VBAT SELECTION JUMPERS

Power To Board

EXPANSION POWER INTERFACE

EXPANSION POWER INTERFACE, JTAG, RESETE433 SC15 Evaluation MainBoard

Power To Board

CORE POWER CONNECTORPower From Summit Supply

IO POWER CONNECTOR

Power From Summit Supply

BI

OUTBIBI

OUTBI

IN

Rev 1.0

NC

TCKTDITDOTMSTRST*

NC

NCVECVDD

AOCVDDAOCVDDAOCVDDAOCVDDAOCVDDAOCVDD

AOCVDD_FB

VECVDD

NC

VECVDDVECVDD

RES1_3RES1_2RES1_1

VECVDD_FBVECVDDVECVDD

RES1_4

RES1_FBRES1_6RES1_5

GNDGND

SCLK

SRCLKSMCLK

SOUT

SFSYNCSIN

NC

TDCVDD

MMCVDDMMCVDDMMCVDDMMCVDDMMCVDDMMCVDD

MMCVDD_FBNC

TDCVDD

TDCVDDTDCVDD

TDCVDDTDCVDD

RES2_3RES2_2RES2_1

TDCVDD_FBNC

RES2_4

RES2_FBRES2_6RES2_5

GNDGND

IN

OUTIN

ININ

OUT

OUT

IN

OUT

IN

IN

IN

ININININ

ININ

OUT

IN

INBIBIINBI

OUTIN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY 5.2H>

S_HVDD

14.3F< S_HVDD_FB

0402

1001%

R78

COMMON

L507

6.3V20%

22UF

1210X5R

C91

COMMON

S_AUXVDD_FB 14.3F<

S_AUXVDD1%0402

100

20%6.3V

X5R

22UF

1210

C96

R89

COMMON

COMMON

GND

SMD_6_6x4_45mm

6.8uHCOMMON

L512

SMD_6_6x4_45mm

6.8uHCOMMON

FDC6333C_N/F

FDC6333C_N/F

FDC6333C_N/F

FDC6333C_N/F

470PF

470PF

COMMON

COMMONX7R

50V10%

0402C901K

COMMON1%0402R100C87

040250V5%C0G

22PF

COMMON

4470PFC89

SSOT6

Q507

Q507

COMMON2

6

SSOT6COMMON

5

Q1(N)

3

1

X7R10%50V0402

C66

SSOT6

Q512

Q512

COMMON2

4

6

1K

Q1(N)

COMMON1%0402R68

3

33.2K

33.2KCOMMON

COMMON1%0402R101

X7R10%50V

COMMON

0402

C690402

C0G

22PF50V5%

COMMON

1%0402R64470PF

50V

COMMONX7R10%

0402C67

SSOT6

S_SDVDD

14.3F< 2.4D> S_SDVDD_FB

1001%0402

R87

COMMON

22UF

1210X5R20%6.3V

C95

COMMON

GND

GND

L511

SMD_6_6x4_45mm

6.8uHCOMMON

S_R1CVDD

S_R1CVDD_FB

20%

1210X5R

6.3V22UFC93

COMMON

15 OF 2005-Jun-2005

600-80433-0000-000

GND

6.8uHCOMMON

0402

100

SMD_6_6x4_45mm

R83

COMMON

1%

L509

e433jcihla

FDC6333C_N/F

FDC6333C_N/F

FDC6333C_N/F

FDC6333C_N/F

470PF

470PF

COMMON

COMMON

COMMON5

50V10%X7R

0402C741K

COMMON

1

1%0402R90

SSOT6

Q511

Q511

COMMON

4

2

6

SSOT6COMMON

5

Q1(N)

3

1

33.2KCOMMON

C720402

22PF50V5%C0G

COMMON

1%0402R77470PF

X7R10%50V

COMMON

0402C71

50V10%X7R

0402C78

SSOT6

Q509

Q509

COMMON

4

2

6

1K

Q1(N)

COMMON1%0402R93

3

SSOT6COMMON

51

18.2KCOMMON

C840402

5%50V

22PF

C0GCOMMON

1%0402R97470PF

50V

COMMON

10%X7R

0402C85


COMP1_CH4

HSDRV_CH4

COMP2_CH4

LSDRV_CH4

HSDRV_CH5

COMP1_CH5

COMP2_CH5

LSDRV_CH5

0402

16V.1UF

10%X7R

C79

COMMON

GND

COMP2_CH5

LSDRV_CH5

LSDRV_CH4

COMP1_CH4COMP2_CH4HSDRV_CH4

COMP1_CH5

HSDRV_CH5

D3V3_STDBY

41

QFN

VR_1VSMB120N

QFN

U505

COMMON

40

D5V0

59

161312

61

6460

43

484445

27

322928

55

5354

4950

51

38373533

39

10

2526

11

46

42

24

GND

5%

R543

0402

47K

COMMON

62

52

14

36

4

COMP1_CH6

HSDRV_CH6

COMP2_CH6

LSDRV_CH6

COMP2_CH7HSDRV_CH7LSDRV_CH7

COMP1_CH7

LSDRV_CH6

COMP2_CH6HSDRV_CH6

COMP1_CH6

VBAT

COMP2_CH7

LSDRV_CH7

HSDRV_CH7

COMP1_CH7

Summit 120 and IO Power Rails

23

34

2122

1718

19

7

3

56

12

1563

GND

3157

47

89

3020

56

TP

58

10.4A<

GND

17.3B<> 16.3B<>

16.3B< 17.3B<

PWREN_CH1

PWREN_CH0

SMT_SDA

SUMMIT_RESETn

10UFC529

10V10%

0805X5R

COMMON

GND

SMT_VBAT

.1UFC73

16V10%X7R0402

C76

COMMON

1N4148COMMON31

D4SOT23

VBAT

.1UF

S0_VREF

S0_VDDCAP

.1UFC80

16V

10%16V

X7R

COMMON0402

.1UF

X7R10%

0402

16V

C70

COMMON

NO STUFF

COMMON

COMMON

0402X7R10%

0

05%

5%

0COMMON5%0402

0402

0603R546

R98

R99IOVDD_ENABLE

AUXIOVDD_ENABLE

GNDEFUSE_PWR_ENABLE

0805

10UFC68

COMMON

10%X5R

10V

14.4F>

5.4A>

14.4H> 17.3A<

SMT_VBAT

47K

04025%

R564

COMMON

COMMON

COMMON

COMMON

47K

47K

47K

47K

1N4148COMMON31

SH_SCLSH_SDA

SOT23D3

COMMON

COMMON47K

8642

10

2.54MM

HTSS-105-01

COMMON

MALE

NORM0

J28

SMT_DONG_D3V3

5%

5%

5%

5%

5%

97531

SMT_VBAT

R910402

0402

0402

R547

R92

R76

R960402

0402

NO STUFF0

5%

COMMON0

5%

SMT_VBAT

0603

0603R562

R561

7.5G<

47K5%

0402

R560

COMMON

GND

PUR4.3A<

AUXIOVDD_HEALTHY

10.3D>

NORM02.54MMMALEHDR_1M3

0NORM

2.54MMMALEHDR_1M3J21

J22

COMMON

COMMON

321

NO STUFF

1

32

47K

0402

R565

COMMON

5%

SMT1_SCLSMT2_SCL

SMT_VBAT

0402

47KR566

COMMON

5%

R567

COMMON

47K5%0402

HDR_2M3MALE2.54MM

J23

0

SMT0_SCL

642

LVDSCOMMON

00402 5%

R570

SYS_SDA

SYS_SCL

14.3D<

12.2G>

6.2C< 2.2B<

18.5D<>

12.3G>

7.4B<>

5.3F<> 2.2D<>

0402

.1UF

COMMON

C539

16V10%X7R

GND

18.5D<

12.3C<

3.4F<> 6.2C<>

8.2A<>

12.5F<>

3.4F< 4.4A< 7.2A< 7.4B<

12.4F<

8.2A<

4.4A<> 7.2A<>

12.3C<>

14.3D<>

5.3H<

135

NO STUFF0

0

SMT_SCL

5%0402R60

R590402 5% NO STUFF

0NO STUFF5%0402

R58

IO AND AUX POWER SUPPLY RAILSE433 SC15 Evaluation MainBoard

IN

IN

Q2(P)D

SG

D

SG

Q2(P)D

SG

IN

IN

D

SG

Q2(P)D

SG

D

SG

Q2(P)D

SG

D

SG

INVERTER

LDO_OUTPUT

BOOST CHANNELS

BUCK CHANNELS

SMB120

COMP1_CH0COMP2_CH0LSDRV_CH0

PCHSEQ_CH1

VSTANDBY

LSDRV_CH3

PCHSEQ_CH3

COMP2_CH3COMP1_CH3

LSDRV_CH2COMP2_CH2COMP1_CH2

PCHSEQ_CH2

COMP1_CH1

VM_CH4COMP1_CH4

LSDRV_CH1COMP2_CH1

COMP2_CH4

HVSUP6

COMP1_CH6

HSDRV_CH6

HVSUP5

HSDRV_CH5

COMP1_CH5

HSDRV_CH4

VM_CH6

LSDRV_CH4HVSUP4

COMP2_CH6

LSDRV_CH5

COMP2_CH5

VM_CH5

LSDRV_CH6

DRVGNDDRVGND

HVSUP7

DRVGND

COMP2_CH7HSDRV_CH7LSDRV_CH7

VM_CH7

BULK_GND

DRVGND

COMP1_CH7

LDO_SUPPLY

VBATTVBATT

VREF_OUT

DOCK_DC

DC_IN

VREF

VDDCAP

SCLSDA

HEALTHY

POWER_FAIL

nBATT_FAULT

PWREN0

PWREN1

THERMPAD

DGNDAGND

nRESETHOST_RESET

OUT

OUT

OUTOUT

OUT

IN

IN

IN

IN

OUT

IN

BI

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY14.2A> S_AOCVDD

14.3A>

S_VECVDD

S_VECVDD_FB

S_AOCVDD_FB

0402

100

22UF

1210X5R20%6.3V22UFC117

C127

R508

R518

COMMON

COMMON

COMMON

COMMON

1001%0402

6.8uHL501

50V

X7R10%

470PF

COMMON

0402

4

C106COMMON1K

1%0402

6.3V

1210X5R20%

GND

SMD_6_6x4_45mmCOMMON

1%

SMD_6_6x4_45mm

6.8uHL506

COMMON

FDC6333C_N/F

FDC6333C_N/F

COMMON

COMMONSSOT6

SSOT6

2

5

6Q503

Q503

Q1(N)

3

1

470PF50V10%X7RCOMMON

C810402

4Q506

FDC6333C_N/F

FDC6333C_N/F

COMMON

COMMON2SSOT6

Q506SSOT6

6

5

Q1(N)

1KCOMMON1%0402

R94

3

1

14.2A>

S_MMCVDD

14.2A>

16 OF 2005-Jun-2005

600-80433-0000-000

S_TDCVDD

e433jcihla

S_TDCVDD_FB

S_MMCVDD_FB

0402

100

0402

100

20%

22UF

1210X5R

6.3V

6.3V

1210X5R20%

22UFC121

C128

R509

R520

COMMON

COMMON

COMMON

COMMON

GND

1%

6.8uHL502

COMMON

GND

SMD_6_6x4_45mm


C980402

4

1KCOMMON1%0402

R103

Q504FDC6333C_N/F

FDC6333C_N/F

COMMON

COMMON

2SSOT6

6Q504

SSOT6

5

Q1(N)

3

1

1%

SMD_6_6x4_45mm

6.8uHL504

COMMON

GND

470PF

10%X7R

50V

COMMON

C1070402

4Q502

FDC6333C_N/F

FDC6333C_N/F

COMMON

COMMON2SSOT6

6Q502

SSOT6

5

Q1(N)

1KCOMMON1%0402

R108

3

1


R107

33.2K

C1020402

5%50V

22PF

C0G

R105

COMMON

470PFC101

COMP2_CH8COMP1_CH8

LSDRV_CH8

HSDRV_CH8

1% COMMON040210%

COMMONX7R

50V

33.2K

0402C83

COMMON

5%50V

C0G

1%0402

22PF

R95

COMMON

470PF50V0402

C82

X7R10%

COMMON

0402

COMP1_CH9COMP2_CH9

HSDRV_CH9LSDRV_CH9

VBAT

31

32

15

43

22

14

19

10

1213

8

9

29

23

17

18

25

20

28

21

33.2K

0402C88

50V5%

C0G

22PF

R102

COMMON

470PFC861%040250V0402 COMMON

COMMON

10%X7R

COMP2_CH10HSDRV_CH10

LSDRV_CH10

COMP1_CH10

33.2K

0402C104

COMMON

5%50V

C0G

1%0402

22PF

R109

COMMON


C105


LSDRV_CH11

COMP1_CH11

Summit 113 and Primary Core Power Rails

2427

SMB113NVR_1VQFNQFN

U26

COMMON

15

26

16

112

67

10UFC517

COMMON

X5R10%10V16V

.1UF

10%X7R

C519

SMT1_VDDCAP

0402 0805COMMON

0

COMMON

COMMON

05%

5%

GND

47K

0402

R548

COMMON

5%

R539

0603

0603

R542

SMT_SDASMT1_SCL

47K5%0402

R540

COMMON

C518

10V10%X5R

10UF

SMT_VBAT

C520

X7R10%16V.1UF

0402 0805COMMON

17.3B<> 15.4C> 15.5C>

COREVDD_HEALTHY

COREVDD_ENABLE

COMMON

GND

7.5G< 14.4F<

14.3H>

17.3A<

30TP

GND

PRIMARY CORE POWER SUPPLY


IN

IN

Q2(P)D

SG

D

SG

Q2(P)D

SG

D

SG

IN

IN

Q2(P)D

SG

D

SG

Q2(P)D

SG

D

SG

BIIN

IN

OUT

SMB113

VM_CH0HSDRV_CH0LSDRV_CH0COMP1_CH0COMP2_CH0


HSDRV_CH1

HVSUP1

VM_CH1

HVSUP0

COMP2_CH2COMP1_CH2LSDRV_CH2HSDRV_CH2

HVSUP2

VM_CH2

VM_CH3

COMP2_CH3COMP1_CH3

HSDRV_CH3LSDRV_CH3

HVSUP3

VBATTVDDCAP

PWREN0

HEALTHYHOST_RESET

SDA

THERMPADGND

SCL

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARYS_EMVDD14.3A>

14.3F<

S_ACVDD

14.3A>

S_EMVDD_FB

R511

COMMON

1001%0402

50V470PF

0402C1231K

COMMON10%

22UFC122

6.3V

COMMON

20%

1210X5R

SMD_6_6x4_45mm

6.8uHL503

COMMON

GND

S_ACVDD_FB

100

0402

R517

COMMON

1%

6.3V22UFC116

SMD_6_6x4_45mm

6.8uHL505

COMMON

FDC6333C_N/F

FDC6333C_N/F

X7RCOMMON

SSOT6COMMON

2

4Q501

SSOT6COMMON

5

6Q501

Q1(N)

470PF50V10%

COMMONX7R

FDC6333C_N/F

COMMON

0402C125

COMMON1K

2

4

SSOT6

Q505

Q1(N)

3

20%

S_VVDD

14.3F< 2.2B>

17 OF 2005-Jun-2005

600-80433-0000-000

S_LVDD

14.3F< 2.3E>

e433jcihla

COMMON1210X5R

GND

S_VVDD_FB

100

0402

R80

COMMON

1%

6.3V22UFC92

20%X5R1210COMMON

GND

SMD_6_6x4_45mm

6.8uHL508

COMMON

50V470PF

FDC6333C_N/F

COMMON

Q505SSOT6

6

51

0402C1081K

COMMON10%X7RCOMMON

FDC6333C_N/F

FDC6333C_N/F

COMMON

COMMON2

4

SSOT6

Q508

3

Q1(N)

Q508SSOT6

6

51

S_LVDD_FB

100

0402

R85

COMMON

1%

6.3V20%

22UFC94

SMD_6_6x4_45mm

6.8uHL510

COMMON

X5R1210COMMON

GND


FDC6333C_N/F

COMMON

0402C991K

COMMON

Q5104

SSOT6

2

Q1(N)

3

6

FDC6333C_N/F

COMMON

Q510SSOT6

51


1%

1%

1%

3

1

1%0402R113

0402C11922PF

50V5%

33.2KCOMMON1%0402

C0G

R115

COMMON

R1140402

33.2K

0402C120

COMMON

50V5%

22PF

1%

C0G

0402R116

COMMON

50V10%X7R

470PF

470PF

COMMON

COMMON

50V10%X7R

0402C124

0402C126

COMP1_CH12


HSDRV_CH13


LSDRV_CH12

VBAT

5131

14

32

10

1312

43

8

22

17

18

19

2021

9

0402R110

0402C111

50V22PF

5%

33.2KCOMMON

C0G

1%0402R111

COMMON

50V10%X7R

470PF

COMMON

0402C112

R1060402

33.2K

0402C103

COMMON

50V5%

22PF

C0G

1%0402R104

COMMON

50V10%X7R

470PF

COMMON

0402C100

LSDRV_CH15

HSDRV_CH15COMP2_CH15

COMP2_CH14

COMP1_CH15

COMP1_CH14

HSDRV_CH14

LSDRV_CH14

Additional IO Power Supply Rails

29

23

24

25

2728

COMMON

U504

QFNVR_1V

QFN

SMB113N

1615

26

112

10UFC109

COMMON

SMT2_VDDCAP

X5R10%10V

0805

.1UF

0402X7R10%16V

COMMON

C114

COMMON

COMMON0

0

5%

5%

0603

0603R532

R537

47K

0402

R536

COMMON

5%

GND

PWREN0

47K

04025%

R544

COMMON

SMT_VBAT

10UFC110

COMMON

10V10%X5R0805

COMMON

COMMON

0

05%

5%

IOVDD_HEALTHY

0603

0603R538

R545

COMMON

C115

10%X7R

16V.1UF

0402

GND

7.5G<

COREVDD_HEALTHY

IOVDD_ENABLE

7.5G< 16.3A> 14.4F<

15.2B< 14.4H>

67

TP30

GND

SMT2_SCLSMT_SDA

15.5C> 16.3B<> 15.4C>

ADDITIONAL IO POWER SUPPLY RAILSE433 SC15 Evaluation MainBoard

IN

IN

Q2(P)D

SG

D

SG

Q2(P)D

SG

IN

IN

D

SG

Q2(P)D

SG

D

SG

Q2(P)D

SG

D

SG

OUT

IN

IN

SMB113

VM_CH0HSDRV_CH0LSDRV_CH0COMP1_CH0COMP2_CH0


HSDRV_CH1

HVSUP1

VM_CH1

HVSUP0

COMP2_CH2COMP1_CH2LSDRV_CH2HSDRV_CH2

HVSUP2

VM_CH2

VM_CH3

COMP2_CH3COMP1_CH3

HSDRV_CH3LSDRV_CH3

HVSUP3

VBATTVDDCAP

PWREN0

HEALTHYHOST_RESET

SDA

THERMPADGND

SCLBIIN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY18.4H> 14.1H> AUD_SRCLK

.1UF16V

C130

10%

0COMMON

X5R0402COMMON

GND

5%0402

2.54MM

HDR_1M3

COMMON

J9

NORM0

MALE

J8HDR_1M3

2.54MM

COMMON

MALE

0NORM

1

123

23

I2S_RLINEOUTCON_RLINEOUT

I2S_LLINEOUTCON_LLINEOUT

AC97_RLINEOUT

AC97_LLINEOUT

NO STUFF0

5%

19.3H>

19.3H>

I2S_RLINEOUT

ACVDD

SC70_5FXLP34

100

0603R503

R501

COMMON

4

5

U32

1

2

D3V3

10%16V.1UF

0402X5R

C131

COMMON

GND

GND

3

ACVDD

0402X5R

16V10%

.1UFC12

COMMON

R709I2S_ROUT_DCBL

GND

ACVDD

C2

22UFCOMMON

C8

N/A10VTAN

SMAN/AN/A

.1UF

COMMON

10%16V

X5R

C21

0402

DVVDD

C15

N/A

22UF

TAN

N/A

SMA

N/A

10V

COMMON

22UFI2S_ROUT

DVVDD

GND

13

271

CON_STEREO_JACK_Fcon_audioCOMMON

2

1

J2

5

4

3

19.2F<

18.4D<

18.5B> 18.3D<

18.5B<> 18.5B<>

18.1H>

GND

14.1H> 14.1H<>

14.2H> 14.2H<

14.1H<> 14.2H<>

CON_RLINEOUT

CON_LLINEOUT

I2S_LLINEOUT

AUD_SRCLKAUD_SMCLK

AUD_SINAUD_SOUT

AUD_SCLKAUD_SFSYNC

1J5082HDR_1M6

6543

02.54MM

NORM

MALE

COMMON

18 OF 2019-MAY-2005

600-80433-0000-000e433jcihla

100

COMMON

COMMON

5%

5%0402

0402

R710

R71147K

06035%

COMMON

GND

I2S_LOUT_DCBL

47K

06035%

R708

COMMON

SMA

SMAC322UF

N/A10VTANN/A

COMMONN/AN/ATAN

N/A10V

I2S_LOUT

N/ACOMMON

12

10

GND

1128

9


COMMON

TESTPOINTTP12SCHMOO

1

COMMON

0402

.01UFC508

COMMON

16V.01UF16V

C510

10% 10%

0402X7R X7R

COMMON

C509.01UF16V10%

COMMON0402X7R

ACLK_REFGND

COMMON33

I2S_AVDD

16V

C10.1UF

X5R0402

10%

22UF

10VN/A

TANN/AN/ASMA

C9

COMMON

COMMON

.1UFC11

16V

0402X5R10%

WM8731SSOP28

150-220R@100MHz

U526

COMMON

21LB1COMMONBEAD_0805

.1UF16V10%X5R0402

C4

COMMON

D3V3

GND

168

4

14

I2S_AVDD

AUD_SOUT

16V.1UF

10%X5R0402

C19

COMMON

5%

16V10%

0402X7R

.01UFC513

COMMON

1UF10V

C511

20%

0402R528

X7R0603COMMON

REF_CLK

D3V3

23

15

1114

U28ICS661COMMONTSSOP16

4

810

7

1

2 RP501

ACLK_S1ACLK_S0

ACLK_S2

FREE_AUD_CLK

ACLK_S3

COMMON

4.7K

0402X47

5%

16 9 SRCLK_GEN

12

GND

VMID

22UFC18

COMMONN/A

GND

N/AN/ATAN10V

SMA

14.2H< 18.4H<

1365

GND

D3V3

.1UF

0402

C505

COMMON

16V

X5R10%

19.2F<

.01UFC504

16V

COMMON

X7R0402

10%

GND

5376

1920

1817

23

2221

24

I2S_AUD_SFSYNC2

I2S_AUD_SFSYNCI2S_AUD_SCLK

I2S_MICINI2S_MICBIAS

I2S_LLINEIN_DCBI2S_RLINEIN_DCB

I2S_AUD_SIN0COMMON

I2S_CSB

2

26

25

15

GND

COMMON0

5%0402R652

0NO STUFF

16V.1UFC573

10%

COMMON0402X5R

GND

ACVDD

3

5

4

I2S_XTI

I2S_XTO

Analog Audio IO I2S

5%

15PFC591

COMMON

0402R4

NPO

50V5%

+/-10PPMCOMMON

0603

5%0402R641

GND

AUD_SMCLK

11.2896MHZXTAL

Y2HC49SMD

NPO

50V15PF

5%

C592

0603COMMON

0402

0402NO STUFF

COMMON

R8

ACVDD

05%

.47UF10V10%X5R

10%

.47UF10V

X5RCOMMON

COMMON

C5940603

C5900603

R705%

GND

I2S_MICIN

18.4H<> 14.1H<>

3.3KCOMMON

I2S_MICBIAS

5%0402R3

MAX3373U12

SOT23-8COMMON

D3V3

R384.7K

SYS_SDA

7

6

8

COMMON

5%0402

2

1

GND

SYS_SCL

.1UF16V

C64

10%

12.3G> 2.2D<>

0402X5R

COMMON

GND

12.5F<> 3.4F<>

14.3D<> 4.4A<>

2.2B< 3.4F< 12.2G>

4.4A< 5.3H< 12.3C< 12.4F<

MIC_DCB

I2S_LLINEIN_FILT

I2S_RLINEIN_FILT

15.4A<> 5.3F<>

14.3D< 6.2C<

RP501

COMMON

3

D3V3

RP501

6COMMON

5%4.7K

0402X4COMMON

4.7K

0402X45%

41 RP501

50402X4

4.7K5%

COMMON82

1

21

HDR_1M2MALE

2.54MM

NORM0

HDR_1M2MALE

2.54MM

J40

J42

COMMON

225%0402

R112R_AUD_CLK

4

3

GND

SMD

OSC_4PIN

+/-10 PPM27MHZ

Y6

COMMON

21

21

2.54MMMALE

HDR_1M2

HDR_1M2

2.54MM0

MALE

NORM

NORM0

J44

J46

COMMON

COMMON

0NORM

COMMON

D3V3

10K5%0402

R523

COMMON

2

1

GND

OSC27_EN

CON_RLINEIN

4

3

2

1

GND

19.3A<

19.3A< AC97_LLINEIN

AC97_RLINEIN

CON_LLINEIN

I2S_RLINEINCON_RLINEIN

3

5

12

I2S_LLINEINCON_LLINEIN

123

CON_STEREO_JACK_Fcon_audio

J1

COMMON

0NORM

HDR_1M3

2.54MMMALE

J14

COMMON

0NORM

MALE2.54MM

HDR_1M3J13

COMMON

COMMON

R666

0402

47K5%

R63447K

04025%

GND

30R@100MHz

30R@100MHz

COMMON

COMMON

COMMON

680R5

16V10%

1UF

COMMON

COMMON5%

0603C14

X5R

GND

47.5K

0402

0402

COMMON

1%

R6220PF

0402

C20

COG

50V5%

I2S_MIC_SIGIN

I2S_LLINEIN

I2S_RLINEIN

I2S_VREFOUT

BEAD_0603

BEAD_0603LB506

LB507

7.2A<> 6.2C<> 7.4B<>

COMMON

GND

8.2A<>

2.54MM0

MALEHDR_1M3J18

NORM

15.4A< 7.4B< 7.2A< 8.2A<

NORM0

HDR_1M3

2.54MMMALE

HDR_1M3MALE

J16

J17

COMMON

COMMON

2.54MM

NORM0

COMMON

12.3C<>

321

I2S_AUD_SCLK

AC97_AUD_SCLKAUD_SCLK

321

21

3

I2S_AUD_SIN

I2S_AUD_SFSYNC

AC97_AUD_SINAUD_SIN

AC97_AUD_SFSYNCAUD_SFSYNC

19.2F<> 14.1H<>

19.2F> 14.2H>

19.3F<> 14.2H<>

19.2A<

19.2A<

MIC_VREF

1

2

3

GND

AC97_MIC_SIGIN

MIC_SIGIN

I2S_MIC_SIGIN

R_AC97_VREFOUT

I2S_VREFOUT

MIC_SIGIN

5

4

321

MIC_VREF321

CON_STEREO_JACK_Fcon_audio

J3

COMMON

02.54MMMALE

HDR_1M3J10

NORM

MALEHDR_1M3

2.54MM

NORM0

J11

COMMON

COMMON

18.4H<>

18.4H>

18.4H<>

DVVDD Set to 1.8V

Line Output

Place between Audio Codecs and J11

Analog Audio IO I2S

E433 SC15 Evaluation MainBoardI2S AUDIO

Wolfson WM8731

I2S Audio Codec

Audio Sample Clock

0000 - 8.192 Mhz0001 - 11.2896 Mhz

1111 - 73.728 Mhz1110 - 36.864 Mhz1101 - 33.8688 Mhz

0101 - 16.9344 Mhz0110 - 18.432 Mhz0111 - 36.384 Mhz

0011 - 24.576 Mhz

0110 - 18.432 Mhz

0010 - 12.288 Mhz

1000 - 16.384 Mhz

1011 - 49.152 Mhz1001 - 22.5792 Mhz

J20, J10, J9, J8

Line Input

Microphone Input

J28 Install Pin 2 - 3


I2C Port on HOST FPGA


Audio Jumper Selection

I2S Audio Input/Output



AC97 Audio Input/Output


J17 Install Pin 2 - 3J18 Install Pin 2 - 3


Audio Control

I2C Port on HOST Connector




OUT

IN

IN

OUTBIBIBI

OUTIN

ICS661AUDIO_CLK

VDD1VDD2VDDOVDDR

REF

SELIN

CLK

S3

S0S1S2

GND3GND2GND1

X1X2

U_AUDIO_WM8731

DBVDDDCVDD

ROUT

LOUT

HPGNDDGND

HPROUT

HPLOUT

ADCLRCADCDAT

RLINEINLINEIN

BCLKDACLRCDACDAT

AVDDHPVDDVMID

MODE

CLKOUT

SDINSCLK

AGND

MICBIASMICIN

CSB

XTO

XTI

IN

IN


IOVL1

VL

IOVL2

VCC

IOVCC1

TSn

GND

IOVCC2

BI

IN

VCC

OUTGND

EN

IN

IN

BIBI

BI

OUTOUT

BI

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARYAC97_AVDD

18.3H<

.1UF

COMMON

C40

16V10%X5R0402TAN

22UF

10VN/A

SMA

N/AN/A

C31

COMMON

X5R10%

0402

16V.1UFC28

COMMON

AC97_LLINEOUT45R@100MHz

150-220R@100MHz

COMMON

COMMON

LB2

D3V3

BEAD_0805

COMMON

.1UF16V

C29

10%

0402X5R

GND

16V.1UF

X5R0402

10%

C38

COMMON

BEAD_0805LB503

18.4H<

AC97_LLINEOUT_DCB

18.3D<

18.5B<>

18.5B<>

N/A

C26

SMAN/AN/ATAN10V

22UFCOMMON

14.2H<

18.5B>

7.5E>

SMAC570

TAN

N/AN/A

N/A22UF

10V

AC97_RLINEOUT 18.2H<

19 OF 2010-Jun-2005

600-80433-0000-000e433jcihla

45R@100MHzCOMMONBEAD_0805

LB502

47K5%0603

R613

COMMON0603

1000PFC571

COMMON

10%10V

X7R

R607

COMMON

47K

06035%

AC97_RLINEOUT_DCB

1000PF

SMAC567

10%X7R

COMMON

C566

10V

0603

24.576000MHZ

27PFC568

COMMON

N/A22UF

TAN

COMMON

10V

N/AN/A

COMMON

COMMON1M

5%

50V10%

0603NPO

+/-30PPMCOMMON

AC97_LLINEOUT_IC

AC97_AUD_SCLK

AC97_AUD_SIN

AC97_AUD_SFSYNC

AC97_AUD_RESETn

AC97_RLINEOUT_IC


XTAL

27PFC574

COMMON

D3V3

AC97_AVDD

25

38

AUD_SOUT5

8

6

1

9

10

11

35

34

47

12

STAC9767TQFP48

U517

COMMON

13

15

14

17

16

18

20

19

22

21

23

UNUSED_ACGND

C25

AC97_LLINEIN_DCB

MIC2

AC97_MIC1

COMMON

X7R

.1UF

0603

10%16V

GND

.1UF

10%16V0603

C584

X7RCOMMON

0402R612AC97_XTL_OUT

AC97_XTL_IN

Y4SMD

10%50V

NPO0603

COMMON

R603

04025%27K

3

2

40

37

36

48

44

43

42

26

GND

7

4

24

45

46

30

29

27

33

32

31

28

41

39

AC97_VREFOUT

AC97_VREF

Analog Audio IO AC97

AC97_CAP2

AC97_AFILT1

AC97_CID1

AC97_AFILT2

AC97_RLINEIN_DCB

AC97_CID0

10%X7R

16V

0603

.1UFC27

COMMON

.1UF

10%

0603X7R

16V

C36

COMMON

10V1UF

0603

20%X7R

C35

COMMON0603

820PF

1K

1K

C576

NO STUFF

NO STUFF

COMMON

5%

5%

0603

0603R602

R601

X7R10%25V

820PFC577

COMMON

X7R10%25V

0603

GND

D3V3

R622

AC97_MIC1

AC97_VREFOUT

3300PF

COMMON

510COMMON5%0402

R24

50V

C585

10%

0603X7R

AC97_LLINEIN_DCB

AC97_RLINEIN_DCB

GND

10%

10%

.47UF10V

10V.47UF

X7R

0603

X7R

0603

4.7UF10V

0805X5R10%

1.8K5%0402

C579

C582

C583

NO STUFF

COMMON

COMMON

COMMON

10%25V.100UF

0603

X7RCOMMON

C586AC97_MIC_DCB

AC97_RLINEIN_FER

AC97_LLINEIN_FER

3.3K

2K

30R@100MHz

30R@100MHzCOMMON

COMMON

COMMON

COMMON5%

5%

0402

0402R623

R631

R_AC97_VREFOUT

AC97_MIC_SIGIN

BEAD_0603

BEAD_0603

LB505

LB504

AC97_LLINEIN

AC97_RLINEIN

18.4B<

18.3B<

18.2B<

18.4B<

5%0402

47KR629

COMMON

GND

47K

0402

R630

COMMON

5%

AC97 AUDIO

AC97 Audio Codec

SIGMATEL 9767


Microphone Network

Line Input Network

OUT

IN

BI

OUT

BI

IN

OUT

AC97 CODECSIGMATEL STAC9766

AVDD1

AVDD2

DVDD1

DVDD2

SDATA_OUT

BIT_CLK

SDATA_IN

EAPD

NC

SYNC

RESET*

LINE_OUT_L

LINE_OUT_R

MONO_OUT

XTL_IN

XTL_OUT

HP_COMM

GPIO0

AVSS1

SPDIF

AVSS2

GPIO1

DVSS2

DVSS1

PC_BEEP

VIDEO_R

PHONE

AUX_R

VIDEO_L

AUX_L

CD_L

CD_R

CD_GND

MIC1

MIC2

LINE_IN_L

AFILT1

CID0

LINE_IN_R

CID1

AFILT2

VREF

CAP2

NC

NC

HP_OUT_R

VREFOUT

HP_OUT_L

IN

IN

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

PRELIMINARY

20 OF 2020-06-05

600-80433-0000-000

5.1H<

e433jcihla

.1UFC575

COMMON

BUF_IPU_WRn 13.2E<

HVDD

10%X7R

16V

REFCLK0

12

3

1

0603

GNDGND

PI5A3158TDFN_12

U11

COMMON

10

11

2R_BUF_IPU_BCLK

IPU_ENABLE

HOST_REFCLK0


NC7SV17SC70_5

10COMMON

COMMON

11.2H> 5.3H<

TESTPOINTSCHMOOCOMMON

TP4

1

.1UF

COMMON

C54

16V10%X7R0603

1024

8

14

GF_INTAIPU_MCLK

D<4>D<2>

D<8>D<10>

A2_SW_INDD<14>

GND

GF_INTA

GF_INTB

HVDD

NO STUFF

0

0

COMMONR57

5%0402

R540402 5%

1

11

3579

1315171921

CON_ERNI_50

2

FEMALE6.2MM

F

J505

COMMON

1012

468

1416182022

INTRn0

D<15..0>

5.2F>

D<15>

D<9>

D<3>D<11>

D<5>IPU_HSYNC

GF_INTB

IPU_WRn

TESTPOINTSCHMOO

TP5

COMMON

1COMMON

100KR48

04025%

53119

15

HVDD

U23

5

COMMON

C63.1UF

X5R10%10V

0402

4

3

2

GND

IPU_WRn

HVDD

.1UF

COMMON

D5V0

C44

16V

0603X7R10%

3.3D> 3.3D>

12

06

D<12>D<6>D<0>

GND

GND

5%0402R30BUF_IPU_BCLK

5.1D>

NC7SV17

COMMON

U16

SC70_5

4

GND

5

10V10%X5R0402

.1UFC42

COMMON

GND

2

3

IPU_BCLK

IPU Interface

TSXpTSYp

2325272931333537394143

494745

2426283032343638404244

I97

464850

GND

CSn

RDn

D<7>D<13>

D<1>

IPU_VBOOSTIPU_ENABLE

TSYnTSXn

IPU_BCLK

3.3D>

1713

0603

.1UF

X7R10%16V

C53

COMMON

3.3D>

GND

HVDD

5.2A<>

13.3E<

5.3D<

5.2C>

13.2E<

5.2H<

E433 SC15 Evaluation MainBoardIPU INTERFACE AND MISC CIRCUITS

OUT

OUT

VVC_0

A0

GND_0

0B0

1B0

S0

OUT

IN

ININ

IN

31

5

97

1113151719

2321

25

3331

2729

3537394143454749

246

1214

108

16

2018

222426

34323028

363840

4442

464850

ININ

BI

OUT

OUTOUT

OUT

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

This page intentionally blank

D<31..0>

0123456789

1011121314151617181920

222324

262728293031

21

25

SC15-NMU1

BGA284_100_100

D<28>

D<30>D<29>

D<26>D<27>

D<31>

D<25>

D<22>D<21>D<20>

D<18>D<17>D<16>

D<23>D<24>

D<19>

N4M4N5M5N6L5M6L6U2

U3V2

V3

N8V4T4U4

D<15>M7D<14>

D<5>D<6>D<7>D<8>D<9>D<10>D<11>D<12>D<13>

D<0>D<1>D<2>D<3>D<4>

M8N10L7N9

N11U5U6U7

U8V8

U9V9V10U10U11

COMMON

U13M12

K13L12N12M13

M14

M11U12L13N14

V14

T16R16V15U15

U16

R17U18U17V17

T18

N17M17

J16H16

J15L16

L17K16

K14

N15

D5V0

0.2A

1.0A

0.2A HVDD

HVDD_C

1 OF 5dd-mon-year

600-f0ppp-00ss-vvve436manoharc

D3V31.0A

5V

5V

10V

5V

MD3

INTRn0

RDY

MHGP5

MD0MD1MD2

H14M15M16N16

J14

L14

L15

HVDD_C

HVDD

D5V0

L18

J18

K18

R15

H15

N18

D3V3

C10

COMMON

0.1UF16V

0402

10%X5R

HVDD

C8C9

10%

0.1UF16V

X5R0402COMMON

GND

N/A

22UF

TAN16V

N/A

COMMON

N/ASMB


A<22>A<23>A<24>A<25>

A<20>A<21>

25

2324

22

2021

19 A<19>A<18>A<17>A<16>A<15>A<14>

A<10>A<11>

A<13>A<12>

1718

1516

141312

1011

A<25..2>

9 A<9>A<8>A<7>A<6>A<5>A<4>

BE2n

A<3>

BE3n

A<2>

78

56

4

23

RSTn

RDnWRn

BE0n

CS2n

BE1n

2

SMD_310%0-500K

COMMON

R5AOCVDD

HVDD

COMMON

2.54MM

NORM

MALE

0J4

HDR_1M2

21

HVDD

D<31..0>

BE2nBE3nRDnWRnSNN_31SNN_32SNN_33

262830

24

2022

1816

D<22>D<20>

RDYD<30>D<28>

D<18>D<16>

D<24>D<26>

D<14> 14

HVDD_C

A<25..2>

1012

86420

D<6>D<8>

D<12>D<10>

D<4>

D<0>D<2>

24222018

SNN_530SNN_35SNN_34

A<24>

A<20>A<22>

A<18>

OSCFR_1

OSCFO_1

OSCFI

DPD

C0G0603

5%50V33PFC7

200KCOMMON

3

1M

0.1%0603R7

1

R8COMMON5%

COMMON

5%

0 COMMON

0603

R10

3.6864MHZ+/-50PPM

0603

COMMON

XTALY1

HC49SMD

0603C0G5%

C633PF50V

COMMON

GND

SYS_CLK

REFCLK00

TESTPOINT

0COMMON5%

SCHMOO

0603R54

TP4

COMMON

1

REFCLK1

REFCLK0

.1UF

X7R10%16V

C5

D3V3

C4

10%

.1UF16V

X7R04020402COMMONCOMMON

GND

Host Connector and SC15 Host block

5%

COMMON

10K

R6

0402

GND

D5V0

D3V3

1416

12

810

2

64

SNN_36

A<8>

A<16>A<14>A<12>A<10>

A<6>A<4>A<2>

DPD

MHGP5SNN_400MD1SNN_38

REFCLK1SNN_401

HSCLSNN_37

RSTn

D5V0

.1UF16V10%X7R

C3C2

X7R

16V10%

.1UF

04020402COMMONCOMMON

GND

REFCLK0


F_HOST

FEMALECON_QSH_SMT_2X60_P050

J1COMMON

642

8

1614

1012

182022

2624

28

36343230

38

46444240

48

54

5856

5250

6462

60

6668707274

1357

1513

911

17

25232119

27

35333129

CS2n

BE0n

D<23>

D<17>

D<25>D<27>D<29>D<31>SNN_49INTRn0SNN_50

SNN_51

D<19>D<21>

SYS_CLK

BE1nSNN_70

31

2729

25

2123

191715 D<15> 37

45434139

47

5149

5557

53

59

6163

7371696765

D<13>

RSTnD<1>D<3>D<5>D<7>D<9>D<11>

SNN_47

A<25>

A<19>

A<23>A<21>

SNN_48

1113

79

5

13

A272523

1921

D<31..0>

A<25..2>

HVDD_C


TP5

1

7678

848280

86

94929088

96

10098

104102

106108110112114116

120118

122

128

124126

GND

8381797775

85

918987

939597

10310199

105

111113

107109

MD2

SNN_42SNN_43

A<15>A<17>

A<13>A<11>A<9>A<7>

A<3>SNN_45

MD3HSDA

A<5>

SNN_510

MD0

SNN_44

1517

13

911

753

GPIO3SNN_39 115

119117

121123125127

HSDAHSCL

D3V3

0402

6.3V.1UF

X5R10%

C1

COMMON

GND

8

56

AT24C02AN_10SC-1.8

COMMON

1

U2SO8

7

123

WP

A0

4

SCHMOOTESTPOINT

TESTPOINT

TP6

COMMON

D5V0TESTPOINT

1

SCHMOO

TP1

COMMON

D3V3TESTPOINTCOMMON

TP2SCHMOO

TP26TESTPOINT

1

COMMONSCHMOO

COMMON

TP3SCHMOO

1

1

100K

COMMON

0402

5%

R3

D3V3

100K

NO STUFF

5%

R1

0402

COMMON

5%0

0402

R2

E436 SC15-NM BoardHost Connector and SC15 Host block

Short near the SC12 HVDD pin

TOP-SIDE

2-50MHZ CLK INPUT

CLOSE TO SC15

WMP MODULE HOST CONNECTOR

Module E2PROM

NM - 1/7 - HOST

D27D26D25

D28D29D30D31

D24D23D22

D20D21

D19

D15D16D17D18

D14

D10D11D12D13

D9

D5D6D7D8

D4

D0D1D2D3

MHGP0/MD0MHGP1/MD1MHGP2/MD2MHGP6/MD3

MHGP3/INT_

MHGP4/RDY

MHGP5

A22

A19A20A21

A23

A25A24

A18

A14A15A16A17

A13

A9A10A11A12

A8

BE3_/A1BE2_

A2A3A4A5A6A7

BE1_

WR_RD_

OSCFR

OSCFO

OSCFI

BE0_

RST_

CS_

DPD

REFCLK1

REFCLK0

V1.0

V1.0Female Host

REFCLK0GNDBE2*

CS3*CS1*

BE3*

D28

INTR1*RDY

D26

D30

WR*RD*

D6D8

D24

D20D22

D12D10

D14D16D18

D4D2D0NC

A30

HVDD_FBHVDDHVDD

A28

A10A12

A24

A20A22

A26

A18A16A14

A8

A0A2

A6A4

NCHOST_SCL

D5VD5V

MHGP3MHGP5

NCMHGP1

H_GPIO2H_GPIO4

DPD

D3V3POWER_EN

GNDGNDGNDGND

RESET_OUT*

SYS_CLKGNDBE0*BE1*

CS2*CS0*INTR0*

SUSPENDOE*

D29D27

NCD31

D17D19

D23D21

D25

D15

D7D9D11D13

D5

RST*

HVDDHVDD

HVDD

D3D1

A31A29

A21A23A25A27

A19

A15

A11A13

A17

A9

MHGP2

HOST_SDA

MHGP4MHGP6

A7A5A3

D5VA1

D5V

H_GPIO1H_GPIO3

MHGP0

D3V3D3V3

NCNC

NC

GNDGNDGNDGND

VCC

SCLSDA

GND

WP

A0A1A2

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

VI_SCL

VI_SDA

VGP3

VGP4

VGP5

VGP6

SC15-NMBGA284_100_100

U1

COMMON

B13

B17

A16

B12

B16

B15

A14

C12D13

D14C14D15C15D16F17

F15F16

D17C17

C18

VD<6>VD<7>

VD<8>VD<9>VD<10>VD<11>

VD<5>VD<4>

VSNCLK_1

VCLK

VD<3>VD<2>

VD<0>VD<1>

VHSYNC C16

SC15-NMBGA284_100_100

U1

COMMON

B14VVSYNC

LHP1

LDI

LDC

LHP0

LHP2

LM0

LHS

LPP

LM1

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

0

05%

22

22

COMMON

5%

5%

5%

0402R13

R14

0402

0402

0402R15

R16

22R17

22

05%

5%

5%

22

05%

5%

R19

R180402

0402

0402

0402

0402R20

R21

LPW00R22

LSC1

LPW2

LPW1

LSC0

LSCK

LSDA

LVS

LVP1

LVP0

LSPI

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

0

05%

5%

5%22

225%

5%

R24

R230402

0402

0402

0402

0402R12

R25

22R26

0

05%

5%

5%

0

0

05%

5%

R28

R270402

0402

0402

R31

R30

R290402

0402

2 OF 5dd-mon-year


5%0402 COMMON

LHP_0

LDI_1

LHP_1

LDC_1H5

L2

K3

J5

LHP_2M2

LHS_1

LM_0

LM1_1

LPP_0

N2

L4

L3

N3

LPW0_1M3

LPW1_1

LSC1_1

LPW2_1

LSC0_1

T1

H6

K5

R1

LSCK_1T2

LVS_1

LVP0_1

LSPI_1

LSDA_1

LVP1_1

R2

J6

T3

K6

R3

H2

J3

H4

L1

K1

K2

J2

H3

G6

LD<16>

LD<15>

LD<14>

LD<17>17

14

15

16

13 LD<13>

LD<12>

LD<11>

LD<10>

LD<9>

11

12

9

10

8 LD<8> G5

G4

G1

G3

G2

F5

F3

F1

F2

J4

LD<7>

LD<6>

LD<4>

LD<5>

6

7

4

5

3 LD<3>

LCS_1

LD<0>

LD<1>

LD<2>2

1

0

VVDD_1

LVDD0.2A

LVDD_10.2A5V

VVDD

5V

0.2A

0.2A

LVDD

LVDD_1

5V

5V

VVDD

VVDD_1

SDVDDSDVDD

SDVD_10.2A

0.2A

5v

5V

SDVD_1

01234567

891011


COMMON

COMMON

225%0402

R9

VD<11..0>

VSNCLK

LD<17..0>

VD<11..0>

VCLK

SNN_90SNN_918

246

10

GND

LD<17..0>

1011

789

2

456

3

VD<8>VD<7>

VD<11>VD<10>VD<9>


1VD<1>0

SNN_96

SNN_94

SNN_92SNN_93

SNN_95

SNN_97SNN_98

VD<0>

28

1214161820222426

3032

44

34

4648

36

42

3840

SNN_9950

1716

15

SNN_100

LD<15>

LD<17>

LD<14>

LD<16>

SNN_103

SNN_101SNN_102

14

1213LD<13>

LD<12>

SNN_201

SNN_104

LM1

LHSLVS

LVP1LSC1

LPW1

62

5254565860

6466

72

76

84

8078

74

82

86

6870

0R11LCS

5%0402

C16

COMMON

4.7UF6.3V10%X5R0603

SDVDD

LCD and VI Camera Interface

LVDD

J7

COMMON

NORM

HDR_1M2

MALE

2.54MM

2

0

1

LVDD_1

3.2G<>

3.2G<> 3.2G<>

3.2G<>

SNN_500

SNN_106

SNN_121LHP1

SNN_200

LSDALSPI

SDD1

SNN_109SNN_108SDGP1

SDD3SDGP0

88

100

94

90

106104102

9896

92

108

120118116114112110

122124126128

C22 C23

0402X7R10%16V.1UF

COMMONCOMMON

.1UF

X7R10%16V

0402

LVDD

C21

0402X7R10%16V.1UF

COMMON

GND

X7R10%16V.1UF

0402

C20

COMMON

C19.1UF

COMMON

10%16V

X7R0402

CON_QSH_SMT_2X60_P050

10%X7R0402

.1UF16V

C18

COMMON

FEMALEBRD_TO_BRD_CONNECTOR

F_LCDCOMMONJ2

7

135

VSNCLKVVDDVVDD_1

HDR_1M2

0 NORM

COMMON

2.54MM

MALE

9

15

1113

17192123252729

37353331

3941

474543

49

555351

5759

616365

6967

7375

71

7977

818385

SNN_83SNN_84

SNN_82

VGP6VGP5VGP4

LD<1>

LPW0

LSC0LVP0

SNN_81

SNN_120

VI_SDAVI_SCL

VGP3

SNN_87

SNN_80VVSYNCVHSYNC

LD<0>

LD<2>LD<3>

LD<5>

LD<6>LD<7>LD<8>LD<9>LD<10>LD<11>SNN_86SNN_85

LPW2

LD<4>

SNN_88

1011

LD<17..0>

2

9876

5

34

210

LDI

LM0

1J5

VVDD

9193

87

95

89

9799

105103101

107

119117

109111

115

121

113

123

GND

125127

SDCLK

SDCMDSDD2SDD0

LHP2LSCK

SNN_89LHP0

TESTPOINT

LPP

LDCLCS

LVDD_1

3.2G>

3.2G> 3.2G<> 3.2G<>

SDVD_1

1

TP7

COMMONSCHMOO

SDVDD

C154.7UF

COMMON0603X5R10%6.3V

GND

C11

COMMON

6.3V10%X5R0603

4.7UF16V10%X7R0402

.1UFC14

COMMON

VVDD

C13

0402

16V10%X7R

.1UF

COMMON

GND

X7R

.1UF16V10%

0402

C12

COMMON

HDR_1M2

2.54MM

COMMON

0 NORM

MALE

21J6SDVDD

SC15 VI/Camera Interface

SC15 LCD Block

LCD/VI Connector and SC15 blocksE436 SC15-NM Board

SD detectSD write Protected

WMP MODULE LCD CONNECTOR

NM - 3/7 - VIDEO

ICSDA/VGP2

ICSCK/VGP1

VGP3

VGP4

VGP5

VGP6

VHSYNC/VGP14

VVSYNC/VGP15

VD11VD10VD9VD8

VD7VD6VD5VD4VD3VD2

VSNCLK/VGP0

VD1VD0

VCLK/VGP13

NM - 2/7 - LCD

LHP1

LHP0

LDI

LDC

LPP

LM1

LM0

LHS

LHP2

LSC1

LSC0

LPW2

LPW1

LPW0

LVP1

LVP0

LSPI

LSDA

LSCK

LVS

LD17

LD16

LD15

LD14

LD13

LD12

LD11

LD10

LD9

LD8

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

LCS_

BIBI

BIBI

V1.0

V1.0Female LCD

VCLKGNDVD13

VD10VD11VD12

VD7VD8VD9

VD6VD5VD4VD3

NC

NCH_LDC

LD23

VD2VD1VD0

HOST_SDAH_LCLK

GND

LD22

NC


LD15

NC

NC

LD14LD13LD12

LPW1

LSC1LVP1LM1LVS

NCNC

NC

NCLVDDLVDD

LHS

LHP1

LSDALSPI

SDD3SDD1

SDGP3SDVDD_FB

SDGP0SDGP1SDGP2

LVDD_FB

GND

GNDGND

GND

VSNCLKGNDVVDD_FB

VHSYNCVVSYNC

VGP1

VVDDVVDDVVDDVVDD

VGP3VGP2

NC

LD11

H_LSDA

H_INTR*H_LCS*

HOST_SCL

VGP6VGP5VGP4

NC

NC

LD10

LD8LD9

LD7LD6NC

LD4

LD5

LD3

LPW0LPW2LSC0LVP0

NCLD0

LD2LD1

LM0NC

LVDDLVDD

LHP0LHP2LSCK

LCS*

NC

LDILPP

LDC

SDVDDSDVDD

LVDD

SDD2SDCMD

SDCLK

SDD0

GND

GND

GNDGNDGND

BIBI

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

2.3B<>

2.3D<>

2.3B<

2.3B<

2.3D<>

2.3D<>

2.3B<>

SDD2

SDD3

SDD1

SDCLK

SDCMD

SDD0

SDGP0

22COMMON

SDGP1 2.3D<>

5%R410402

SDCLK_1

B3

B2

B7

C4

C5

B1

C3

C1

3 OF 5dd-mon-year


SNN_19SNN_20SNN_21SNN_22

SNN_16SNN_17SNN_18

SNN_23

SNN_25

SNN_27SNN_28

SNN_24

SNN_26

F13F12F11

F6

H13H12G8G13G12G11F9F8F7

SNN_29H7

SCHMOOTESTPOINTTP13

COMMON

1

SNN_30

TESTPOINT

J13

1

COMMON

TP12SCHMOO

TESTPOINTSCHMOO

TP24

COMMON

1

TESTPOINTSCHMOO

TP21

COMMON

1


TESTPOINTSCHMOO

TESTPOINTSCHMOO

TESTPOINT

TP10

TP18

COMMON

COMMON

HVDD

BGA284_100_100SC15-NMU1

COMMON

G14

B5

B4

B6

A3

G16

G15

TP8SCHMOO

1

COMMON

VBOTST_1

VTST R14U14R6

TDI

TDO

TCK

TMS

TRSTn

TESTMODE_1

EFUSESRC_1

COMMON

COMMON

5%

0402

NO STUFF

4.1B>

4.1B>

10K

10K

NO STUFF

5%

0402

R35

4.1B<

4.1B<

4.1B> R34

COMMON0

5%0

0

05%

5%0402

0402R36

R38COMMON0

5%0402R37

COMMON5%

GND

0402R32

R330402

GND

4.1C<>

4.2C< 4.1C>

4.1C<>

4.1C<> 4.1C>

SOUT

SIN

SCLKSRCLK

SFSYNC

SMCLKCOMMON

COMMON22

5%

225%0402

R39

R400402

BGA284_100_100SC15-NM

COMMON

T9R10A2

U1

B10

D7D12D11D10C9C8

C11C10B8

D8

1

SCHMOOTESTPOINTTP9

COMMON

F10D9

1TP7

SNN_15

SNN_10

SNN_1SNN_2SNN_3SNN_4SNN_5SNN_6SNN_7SNN_8

SNN_11SNN_12SNN_13

SNN_9

SNN_14

SNN_0

1

SCHMOOTESTPOINTTP15

COMMON

TP5TP4

TP6

1TP3TP2TP1TP0

Audio, SDcard & Interfaces

TESTPOINTSCHMOO

TP25

COMMON


TP22

11

TESTPOINTCOMMON

TP23SCHMOO

1

SCHMOOTESTPOINTTP20

COMMON

TESTPOINTSCHMOO

TP17

COMMON

11

TP7

RAS_T

TP6

TP4TP3

TP1TP0

CAS_T

CKE_TCLK_T

CS_T

LOAD

TP2

TP5

VB1

WE_T

TESTPOINT

TESTPOINT

SCLK_1

SMCLK_1D4

C7D5D6

D3D2

SC15-NMBGA284_100_100

SC15-NMBGA284_100_100

U1

COMMON

U1

COMMON

T13R13T12

T6R7T7T8

T15

T10

R12

R11T11

R9R8

T5

VSR5T14

SCHMOO

TP19

COMMON

TESTPOINTSCHMOO

TP16

COMMON

11

COMMON

TP14SCHMOO

1

TESTPOINTCOMMON

TP11SCHMOO

RAS_TCAS_T

CS_TWE_T

1

VSVB1

CKE_TLOAD

CLK_T

SC15 JTAG & SDCARD

E436 SC15-NM BoardAudio SDCARD & Test Interfaces

SC15 Stached Chip Test header

SC15 Audio I2S & AC97

BI

BI

BI

BI

OUT

OUT

BI

BI

NM - 4/7 - JTAG/TEST/SD

SDD3

SDD2

SDD1

SDD0

SDGP1

SDGP0

SDCMD

SDCLK

TMS

TDI

TCK

TDO

TESTMODE

TRST_

EFUSESRC

GND/TESTGND/VB0GND/VTST

IN

IN

OUT

IN

OUT

BIINBI

OUT

BIIN

NM - 7/7 - NON CONNECTS

NC_F6NC_F7NC_F8NC_F9

NC_F11

NC_F13NC_F12

NC_G11

NC_G8

NC_G12NC_G13

NC_H7NC_J13

NC_H13NC_H12

NC_B8NC_B10

NC_C10NC_C11

NC_R10NC_T9

NC_A2

NC_C8NC_C9

NC_D7NC_D8NC_D9

NC_D10NC_D11NC_D12

NC_F10

NM - 5/7 - I2C/AC97

SINSMCLK

SFSYNC

SOUTSRCLKSCLK

NM - TEST

TDQ0TDQ1TDQ2TDQ3TDQ4TDQ5TDQ6TDQ7

RAS_TCAS_T

CKE_TCLK_T

CS_T

LOAD

WE_T

VB1VS

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

AVDDP1

COMMON10

AVDDP2

AVDDOSC

COMMON10

EMVDD

COMMON102

R45

1%

1%

1%

0402

.1UF

10%X5R

R55

C68

6.3V

0402

.1UF6.3V10%X5R

COMMON

R56

C69

0402

AVDDP1_I

.001UF

X7R

50V10%

C65

AVDDP2_I

X7R10%50V

.001UF

0402

C66

COMMON

04020402

10402

COMMON

COMMON

R47

C70

0402

.001UF

X7R10%50V

5%

0402

COMMON

AVDD_OSC

.1UF16V10%

0402X7R

C67

COMMON

COMMON

0R44

COMMON

COMMON

SDVDD

VVDD

D18A17

A4

BGA284_100_100

U1

COMMON

SC15-NM

M9M10L9

L10

J11J12

05%

R420402

ACVDD

AGND_1

D1

H17H18

G18

05%

AGND_OSC

0402R43AGND_2

J17

G17

K17

A11

V5V13A9A7A6A13A12

K12K11

H10G9

G10

H9

J7

K8K7J8

V16V12R18

V7

N1J1

1.02K

06031%

COMMON

1.02KR46

COMMON06031%

GND

.001UF

0402

50V10%X7R

C76

GND

EMVREF

COMMON

GND

.01UFC81

10V

0402X5R10%

COMMON

.1UF

0402

C57

COMMON

ACVDD

.1UFC56

10V10V

X5R10%

0402COMMON

X5R10%

4 OF 5dd-mon-year

GND

600-f0ppp-00ss-vvv

4.7UFC80

6.3V

0603

10%X5R

COMMON

.1UF

COMMON

C44.01UF

VVDD

C79

10V 16V10%

0402X7R

COMMON

10%X5R0402

e436manoharc

GND

GND

.1UF

COMMON

M1L8L11K9K4K15K10J9J10

M18

V6V11U1T17R4N7N13

GND

A8A5

A15A10

B11B18B9

C13C2C6

F14F18F4G7H1

H8H11

C42

16V

0402X7R10%

22UFC41

COMMON.1UFC40

16V

SMA

TAN

N/A10V

N/AN/ACOMMON

10%

0402X7R

SDVDD

GND

.1UFC39

16V

0402

10%X7R

COMMON

4.7UFC78

.1UFC37

6.3V16V

COMMON

10%X5R0603

COMMON0402X7R10%

VECVDD

MMCVDD

AOCVDD

TDCVDD


COMMON

HVDD

LVDD

RESERVE_2

.1UFC51

0.5A3.3v

16V.1UF16V

C50

RESERVE_2

3.2D<> 3.2D<

3.2D<> 10%10%

ACVDD

0402COMMON

X7R

COMMON0402X7R

GND

NORM

MALE

2.54MM

HDR_1M2

J13

COMMON

RESERVE_2

0

21

NORM

2.54MM

MALE

0 COMMON

HDR_1M2

J14

TDCVDD

MMCVDD

TDCVDD

3.2D>

COMMON

3.2D< 3.2D<>

NORM

HDR_1M2

2.54MM

MALE

J11

0

21HDR_1M2

COMMON

NORM

2.54MM

MALE

0J12

21

ACV_1

RES_2

21

NO STUFF

NO STUFF

C75

0402

.1UF

10%X5R

16V

GND

RESERVE_1

10%10V1UF

0603X5R

C74

NO STUFF

NO STUFF

100PF50V5%C0G

C73

0402NO STUFF

1%

0603

NO STUFF

1%

NO STUFF0

.05R0603R50

R51

196

187R52

0603

LVDD

.1UFC36

.1UFC35

16V16V10%X7R0402

COMMON

10%

0402X7R

C27.1UF

COMMON

X7R10%

0402

16V

GND

.1UF

0402

C26

COMMON

HVDD

C25.1UF

16V

X7R10%

COMMON

X7R10%16V

0402

.01UF

COMMON

C77

10%10V

X5R0402

GND

Power supplies and Bypassing

0.1UF

RESE_1

ADJ

1

4

2

LT1763VREF=1.22VS8S8

U3

NO STUFF

BYP

5

8

673

.1UF

0402

C72

COMMON

16V10%X5R

10V

X5R0603

10%

1UFC71

COMMON

D3V3

10K

5%

0402

R48

NO STUFF

100

5%

0402

R49

GND

C640.1UFC63

16V16V

X7R

COMMON

10%

0402COMMON

10%

0402X7R

0.1UF

COMMON

C620.1UFC61

16V16V

X7R0402

10%

COMMON

10%

0402X7R

EMVDD

GND

0.1UFC60

0.1UFC59

16V16V

COMMON0402X7R10%

COMMON

X7R0402

10%

0.1UFC58

16V

COMMON0402X7R10%

MMCV_1

MMCVDD

SMCLKSRCLK

SCLK

246



F_NAME

FEMALE

J3COMMON

531

TDITCK

TDO7 8

SNN_300SOUT

SFSYNCSIN

TDC_1

SNN_64

SNN_65

1614

1012

1820222426283032343638

46

404244

48505254565860

6462

43413937353331

9

45

29

1311

27252321191715

TRSTn

AVDDP1

SNN_60

TMS

SNN_61

SNN_67

SNN_66

47

595755535149

6361

AOC_1

EMV_1

1A

EMVDD

AOC_1

AVDDP2

AVDDP1

3.2E>

3.2E< 3.2E<

3.2E< 3.2E>

AVDDP2AVDDOSC

AVDDOSC

COMMON

VEC_1

NORM

COMMON

NORM

2.54MM

0MALE

HDR_1M2

J8

HDR_1M2

2.54MM21

MALE

0J9

21

NORM

MALE

HDR_1M2

2.54MM

J10

COMMON

2.0V

VEC_1

AOC_1

0

21

AOCVDD

VECVDD

0.5A

EMVDD

AOCVDD

2.0V

VECVDD

AOCVDD

MMCVDDGNDVEC_1

RES_2

EMV_1

MMCV_1

TDC_1

ACV_1

22UFC34

COMMONN/A10V

.1UFC31

10%16V

X7R

10V10%

.1UFC55

4.7UF

10%6.3V

C54

X5R0402COMMONCOMMON

X5R0603

MMCVDD

GND

.01UF

0402X5R10%10V

C53

COMMON

4.7UF6.3V

C52

10%

.01UFC49

N/ASMA

N/ATAN

COMMON0402

TDCVDD

10%10V

.1UFC48

10V10%

0603X5R

COMMON0402COMMON

X5R

GND

0402COMMON

X5R

1A

0.5A

.1UF

.1UF

10%X7R0402

16V

C30

COMMON

COMMON

1.0A

1A

1.0A

3.3V

2.0V

2.0V

3.3V

1A

2.0V

3.3V

TDC_1

MMCV_1

RES_2

ACV_1

EMV_1

VECVDD

TDCVDD

RESE_1

MMCVDD

RESERVE_1

ACVDD

EMVDD

.1UFC29

16V10%

AOCVDD

C28

16V.1UF

10%

.01UF

10%10V

C38

0.5A

0.5A

1A

0.5A

0.5A

0.5A

0.5A

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3VRESE_1

EMVDD

MMCVDD

TDCVDD

ACVDD

RESERVE_1

C33

10V10%

.1UF4.7UF

10%6.3V

C24

X5RX5R X7RX7RX5R

COMMON0402

10%10V

C47.01UF10V10%

C46

EMVDD

4.7UF

COMMON0402

COMMON

GND

0402

6.3V10%

C45.1UF

10%10V

C43

X5R0402

COMMON

X5R0402

GND

COMMON

X5R06030402

X5R

COMMON

COMMON04020603

COMMON

VECVDD

10V10%

.01UFC32

6.3V10%

4.7UFC17

0402X5R

COMMONCOMMON0603X5R

GND

Place close to SC15

PLace Close to SC15

Place Close to SC15

SC15 Power pins

place close to SC15

IO Bypass Caps

E436 SC15-NM BoardPower Connector & Bypass Caps

Alternate Regulator

TOP SIDE

Internal Memory Bypass Caps

WMP MODULE POWER CONNECTOR

Place 0.01uF & 0.1uF As Close to the SC!5 as possible or under the chip

Place 0.1uF and 0.1uF as close to SC15 as possible

Core Voltage Bypass Caps

NM - 6/7 - POWER

VVDD_02VVDD_01

SDVDD

AVDDP2AVDDP1

AGNDP1

ACVDD

AGNDP2

AVDDOSC

AGNDOSC

EMVDD_1EMVDD_2EMVDD_3EMVDD_4EMVDD_5EMVDD_6EMVDD_7

EMVREF

GND_18GND_19GND_20GND_21GND_22GND_23GND_24GND_25GND_26GND_27GND_28GND_29GND_30GND_31GND_32GND_33GND_34

AOCVDD_1AOCVDD_2AOCVDD_3AOCVDD_4

MMCVDD_1MMCVDD_2MMCVDD_3MMCVDD_4

VECVDD_1VECVDD_2VECVDD_3VECVDD_4

TDCVDD_4TDCVDD_3TDCVDD_2TDCVDD_1

LVDD_2LVDD_1

HVDD_2HVDD_3HVDD_4

HVDD_1

GND_02GND_03GND_04GND_05GND_06GND_07GND_08GND_09GND_10

GND_01

GND_11GND_12GND_13GND_14GND_15GND_16GND_17

OUT

ADJ

BYP

IN

GND2

SHDN*

GND1

GND3

BIOUTIN

OUTBIBI

OUTIN

INOUTOUT

Rev 1.0SRCLK

SCLK

SINSFSYNC

SOUT

SMCLK

NC

NC

MMCVDDMMCVDD

MMCVDD

MMCVDDMMCVDD_FB

TDCVDD

MMCVDD

MMCVDD

TDCVDD

NCRES2_1RES2_2

TDCVDD

TDCVDDTDCVDD

TDCVDDTDCVDD_FB

RES2_3RES2_4

RES2_6RES2_FB

RES2_5

GNDGND

TRST*

TCKTDITDO

NC

TMS

NC

AOCVDD_FB

AOCVDD

AOCVDDAOCVDD

AOCVDDAOCVDD

AOCVDD

VECVDDNC

VECVDD

RES1_2RES1_1

RES1_3

VECVDD

VECVDDVECVDD

VECVDDVECVDD_FBNC

RES1_4RES1_5RES1_6RES1_FB

GNDGND

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

<edit here to insert page detail>BASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL

manoharce436

600-f0ppp-00ss-vvv

dd-mon-year

5 OF 5

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

D<31..0>

0123456789

10111213141516171819202122232425262728293031

SC15-XTU1

BGA288_100_120

D<26>

D<31>D<30>D<29>D<28>D<27>

D<25>

D<16>D<17>D<18>D<19>D<20>D<21>D<22>D<23>D<24>

R5R6T6T5R7R8N8M8U3

V4V3

U4

U6V5T4U5

D<15>T8

D<5>D<6>D<7>D<8>D<9>D<10>D<11>D<12>D<13>D<14>

D<0>D<1>D<2>

D<4>D<3>

N10N9R9T9

R10U7T7U8

U9V8

V9U10V10T10U11

COMMON

T11N11

T15T13N12T12

N14

R11R12T16R15

U12

V13R14T14R13

U13

V15U16U14V14

V17

T18P18

L15M15

M14N16

M16M17

N15

M12

D5V01.0A

0.2A HVDD

0.2A HVDD_C

1 OF 5dd-mon-year


D3V31.0A5.00000

10.0000

5.00000

5.00000

MD0MD1MD2

INTRn0

RDY

MHGP5

MD3M13R17L14M11

U17

U18

R16

HVDD_C

HVDD

D5V0

L18

J18

K18

U15

N17

N18

D3V3

C10

COMMON

0.1UF

X5R10%

0402

16V

HVDD

C8C9

10%

0.1UF16V

X5R0402COMMON

GND

N/A

22UF

16V

N/ATAN

COMMON

SMBN/A


A<25>A<24>A<23>A<22>A<21>A<20>

25242322

2021

19 A<19>A<18>A<17>

A<15>A<16>

A<14>A<13>

A<10>A<11>A<12>

1718

1516

14

1213

1011

A<25..2>

9 A<9>A<8>A<7>A<6>A<5>A<4>

BE3nBE2n

A<3>A<2>

78

56

4

23

CS2n

RDn

RSTn

BE1n

WRn

BE0n

2

0-500K10%SMD_3COMMON

R5

AOCVDD

HVDD

HVDD

COMMON

NORM

2.54MM

MALE

0J4

HDR_1M2

21

A<25..2>

D<31..0>SNN_31

BE3n

WRn

SNN_32

RDn

BE2n

SNN_33

30282624

2022

1618

D<26>

D<22>

RDY

D<16>

D<20>

D<28>

D<18>

D<24>

D<30>

14D<14>

HVDD_C

18202224

1012

68

4

02

D<12>

D<8>D<10>

D<6>D<4>

D<0>D<2>

A<20>

SNN_504SNN_502

A<18>

A<22>A<24>SNN_505

DPD

OSCFO_1

OSCFI

OSCFR_1

C0G0603

5%50V33PFC7

200KCOMMON

3

1M

0.1%0603R7

1

R8COMMON5%

COMMON

5%

0 COMMON

0603

R10

+/-50PPM3.6864MHZ

0603

COMMON

XTALY1

HC49SMD

33PF

0603C0G

C6

50V5%

COMMON

GND

SYS_CLK

REFCLK0_R

TESTPOINT

0COMMON5%

SCHMOO

0603R54

TP4

COMMON

1

REFCLK1

REFCLK0

.1UF

X7R

16V10%

C5

D3V3

C4

X7R

16V.1UF

10%


GND

Host Connector and SC15 Host block

10K

COMMON

5%

R6

0402

D5V0

D3V3

810121416

46

2SNN_36A<2>A<4>

A<12>

A<8>A<6>

A<16>

A<10>

A<14>

DPD

MHGP5

REFCLK1

SNN_38MD1

SNN_509

SNN_400

SNN_37HSCL

RSTn

D5V0

.1UF16V10%X7R

C3C2.1UF16V10%X7R


GND

REFCLK0


BRD_TO_BRD_CONNECTORFEMALE

F_HOST

J1COMMON

642

8

1614

1012

182022

2624

28

36343230

38

46444240

48

54

5856

5250

6462

60

6668707274

1357

1513

911

17

25232119

27

35333129

CS2n

D<17>

INTRn0

SNN_51

D<27>

SNN_49D<31>

D<25>

SNN_70BE1nBE0n

D<21>

D<29>

D<19>

SYS_CLK

SNN_50

D<23>

31

2729

25

2123

1719

15 D<15> 37

45434139

47

5149

5557

53

59

6163

7371696765

D<11>D<13>

SNN_503SNN_506

SNN_501

D<1>RSTn

D<3>

D<7>D<9>

D<5>

1113

79

5

13

D<31..0>

A<21>A<19>

A<23>A<25>

HVDD_C

212325

19

A<25..2>

7678

848280

86

94929088

96

10098

104102

106108110112114116

120118

122

128

124126

GND

8381797775

85

918987

939597

10310199

105

111113

107109

SNN_45

HSDA

MD0

MD3

SNN_43SNN_42

MD2SNN_44

SNN_507GPIO3

GPIO_TIMER 115

119117

121123125127

HSCLHSDA

D3V3

0402X5R10%6.3V.1UFC1

COMMON

GND

8

56

AT24C02AN_10SC-1.8

COMMON

1

U2SO8

7

123

WP

A0

4

TESTPOINTSCHMOO

TESTPOINT

TP6

COMMON

A<17>

A<3>

A<7>A<9>

A<5>

A<13>A<15>

A<11>

TESTPOINTTP5SCHMOOCOMMON

1

357911131517

TESTPOINT

D5V0

COMMON

TP8SCHMOO

1

D3V3

SCHMOO

TP3

COMMON

1

TESTPOINTSCHMOO

TESTPOINT

COMMON

1

SCHMOO

TP1

COMMON

TP2

1

100K

COMMON

0402

5%

R3

D3V3

100K

NO STUFF

5%

R1

0402

COMMON

5%0

0402

R2

E438 SC15-XT-DDR BoardHost Connector and SC15 Host block

Short near the SC12 HVDD pin

TOP-SIDE

2-50MHZ CLK INPUT

WMP MODULE HOST CONNECTOR

Module E2PROM

XT - 1/7 - HOST

D27D26D25

D28D29D30D31

D24D23D22

D20D21

D19

D15D16D17D18

D14

D10D11D12D13

D9

D5D6D7D8

D4

D0D1D2D3

MHGP0/MD0MHGP1/MD1MHGP2/MD2MHGP6/MD3

MHGP3/INT_

MHGP4/RDY

MHGP5

A23A22A21A20A19

A25A24

A18A17A16A15A14A13A12A11

A9A10

A8

BE3_/A1BE2_

A2A3

A5A4

A6A7

BE1_

WR_RD_

OSCFO

OSCFI

DPD

BE0_

RST_

OSCFR

CS_

REFCLK1

REFCLK0

V1.0

V1.0Female Host

REFCLK0GNDBE2*

CS3*CS1*

BE3*

D28

INTR1*RDY

D26

D30

WR*RD*

D6D8

D24

D20D22

D12D10

D14D16D18

D4D2D0NC

A30

HVDD_FBHVDDHVDD

A28

A10A12

A24

A20A22

A26

A18A16A14

A8

A0A2

A6A4

NCHOST_SCL

D5VD5V

MHGP3MHGP5

NCMHGP1

H_GPIO2H_GPIO4

DPD

D3V3POWER_EN

GNDGNDGNDGND

RESET_OUT*

SYS_CLKGNDBE0*BE1*

CS2*CS0*INTR0*

SUSPENDOE*

D29D27

NCD31

D17D19

D23D21

D25

D15

D7D9D11D13

D5

RST*

HVDDHVDD

HVDD

D3D1

A31A29

A21A23A25A27

A19

A15

A11A13

A17

A9

MHGP2

HOST_SDA

MHGP4MHGP6

A7A5A3

D5VA1

D5V

H_GPIO1H_GPIO3

MHGP0

D3V3D3V3

NCNC

NC

GNDGNDGNDGND

VCC

SCLSDA

GND

WP

A0A1A2

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

VGP6

VGP5

VGP4

VGP3

VI_SDA

VI_SCL

BGA288_100_120SC15-XTU1

COMMON

J15

L12

K13

K14

H15

H16

A16

C16G16

F16D16F17D17B16G17E18C17

C18

VD<7>

VD<9>VD<8>

VD<6>VD<5>VD<4>

VSNCLK_1

VD<2>VD<1>VD<0>

VCLK

VD<3>

VHSYNC B17

SC15-XTBGA288_100_120

U1

COMMON

J16VVSYNC

LHP1

LHP0

LDC

LDI

LHP2

LHS

LPP

LM1

LM0

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

0

05%

22

22

COMMON

5%

5%

5%

0402R13

R14

0402

0402

0402R15

R16

22R17

22

05%

5%

5%

22

05%

5%

R19

R180402

0402

0402

0402

0402R20

R21

LPW00R22

LPW1

LSC0

LPW2

LSC1

LSCK

LSPI

LVP0

LVP1

LVS

LSDA

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

COMMON

0

05%

5%

5%22

225%

5%

R24

R230402

0402

0402

0402

0402R12

R25

22R26

0

05%

5%

5%

0

0

05%

5%

R28

R270402

0402

0402

R31

R30

R290402

0402

2 OF 5dd-mon-year


0402 5% COMMON

LDC_1

LDI_1

LHP_0

LHP_1

M2

T1

M3

N3

LHP_2R2

LPP_0

LHS_1

LM_0

LM1_1

M4

L6

T2

R3

LPW0_1N4

LSC1_1

LPW1_1

LPW2_1

LSC0_1

T3

U2

V2

M5

LSCK_1L5

LVS_1

LVP1_1

LVP0_1

LSPI_1

LSDA_1

L7

M6

N6

M7

N5

K5

P1

K6

N2

L4

L2

L3

K3

K1

LD<14>

LD<15>

LD<16>

LD<17>17

14

15

16

13 LD<13>

LD<9>

LD<12>

LD<10>

LD<11>11

12

9

10

8 LD<8> L1

J4

K2

H4

J2

J3

H3

H2

G1

R1

LD<7>

LD<6>

LD<4>

LD<5>

6

7

4

5

3 LD<3>

LCS_1

LD<0>

LD<1>

LD<2>2

1

0

VVDD_1

VVDD

5.000000.2A LVDD_1

5.00000 0.2A LVDDLVDD

LVDD_1

0.2A

0.2A

5.00000

5.00000VVDD

VVDD_1

SDVDD

SDVD_1

SDVDD

0.2A

0.2A

5.00000

5.00000

SDVD_1

01234567

89


COMMON

COMMON

225%0402

R9VSNCLK

VD<9..0>

LD<17..0>

VD<9..0>SNN_91

VCLK

SNN_9068

24

10

GND

LD<17..0>

789

23456

SNN_511SNN_510

VD<7>VD<8>VD<9>

VD<5>

VD<2>

VD<6>

VD<3>VD<4>

1VD<1>0

SNN_96SNN_97

SNN_94SNN_93SNN_92VD<0>

SNN_98

SNN_95

28

1214161820222426

3032

44

34

4648

36

42

3840

SNN_9950

1716

15

SNN_101

LD<16>LD<17>SNN_102

LD<14>LD<15>

SNN_100

SNN_103

14

1213

LSC1LVP1

LVS

LD<13>

LM1

LPW1SNN_104

SNN_201

LHS

LD<12>

62

5254565860

6466

72

76

84

8078

74

82

86

6870

0R11LCS0402 5%

C16

COMMON

4.7UF6.3V10%X5R0603

SDVDD

LCD and VI Camera Interface

LVDD

J7

COMMON

2.54MM

NORM

HDR_1M2

MALE

2

0

1

LVDD_1

3.2G<>

3.2G<>

3.2G<>

3.2G<>

SNN_121

LSPISNN_106

SNN_200

LSDA

LHP1SNN_500

SDD1

SDGP0

SNN_109SNN_108SDGP1

SDD3

88

100

94

90

106104102

9896

92

108

120118116114112110

122124126128

C22 C23.1UF16V10%X7R0402COMMONCOMMON

.1UF

X7R10%16V

0402

LVDD

C21

0402X7R10%16V.1UF

COMMON

GND

0402

.1UF16V10%X7R

C20

COMMON

C19.1UF

COMMON

10%16V

X7R0402


16V.1UF

0402X7R10%

C18

COMMON

F_LCD


COMMONJ2

7

135

VSNCLKVVDDVVDD_1

HDR_1M2

NORM

0 COMMON

2.54MM

MALE

9

15

1113

17192123252729

37353331

3941

474543

49

555351

5759

616365

6967

7375

71

7977

818385

SNN_85SNN_86LD<11>LD<10>LD<9>LD<8>LD<7>LD<6>

LD<5>

LD<3>LD<2>

LD<0>

VHSYNCVVSYNCSNN_80

SNN_87

VGP3

VI_SCL

SNN_120

SNN_81

VGP5VGP6

SNN_82SNN_83

SNN_88

LD<1>

LPW2LSC0LVP0

LPW0

VI_SDA

LD<4>

SNN_84

VGP4

1011

LD<17..0>

2

9876

5

34

210

LM0

LDI

1J5

VVDD

9193

87

95

89

9799

105103101

107

119117

109111

115

121

113

123

GND

125127

LHP0SNN_89

LSCKLHP2

SDD0SDD2SDCMD

SDCLK

TESTPOINT

LCSLDC

LPP

LVDD_1

3.2G<> 3.2G<> 3.2G>

3.2G>

SDVD_1

1

TP7

COMMONSCHMOO

SDVDD

C154.7UF

COMMON

6.3V10%X5R0603

GND

C11

COMMON

6.3V10%X5R0603

4.7UF.1UF

0402X7R10%16V

C14

COMMON

VVDD

C13.1UF

X7R10%16V

0402COMMON

GND

0402

10%16V.1UF

X7R

C12

COMMON

2.54MM

HDR_1M2

COMMON

0 NORM

MALE

21J6SDVDD

SC15 VI/Camera Interface

SC15 LCD Block

E438 SC15-XT-DDR BoardLCD/VI Connector and SC15 blocks

SD write ProtectedSD detect

WMP MODULE LCD CONNECTOR

XT - 3/7 - VIDEO

ICSDA/VGP2

ICSCK/VGP1

VGP3

VGP4

VGP5

VGP6

VHSYNC/VGP14

VVSYNC/VGP15

VD6VD5VD4VD3

VD7

VD9VD8

VD2

VSNCLK/VGP0

VD1VD0

VCLK/VGP13

XT - 2/7 - LCD

LHP1

LHP0

LDI

LDC

LPP

LM1

LM0

LHS

LHP2

LSC1

LSC0

LPW2

LPW1

LPW0

LVP1

LVP0

LSPI

LSDA

LSCK

LVS

LD17

LD16

LD15

LD14

LD9

LD13

LD12

LD11

LD10

LD8

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

LCS_

BIBI

BIBI

V1.0

V1.0Female LCD

VCLKGNDVD13

VD10VD11VD12

VD7VD8VD9

VD6VD5VD4VD3

NC

NCH_LDC

LD23

VD2VD1VD0

HOST_SDAH_LCLK

GND

LD22

NC


LD15

NC

NC

LD14LD13LD12

LPW1

LSC1LVP1LM1LVS

NCNC

NC

NCLVDDLVDD

LHS

LHP1

LSDALSPI

SDD3SDD1

SDGP3SDVDD_FB

SDGP0SDGP1SDGP2

LVDD_FB

GND

GNDGND

GND

VSNCLKGNDVVDD_FB

VHSYNCVVSYNC

VGP1

VVDDVVDDVVDDVVDD

VGP3VGP2

NC

LD11

H_LSDA

H_INTR*H_LCS*

HOST_SCL

VGP6VGP5VGP4

NC

NC

LD10

LD8LD9

LD7LD6NC

LD4

LD5

LD3

LPW0LPW2LSC0LVP0

NCLD0

LD2LD1

LM0NC

LVDDLVDD

LHP0LHP2LSCK

LCS*

NC

LDILPP

LDC

SDVDDSDVDD

LVDD

SDD2SDCMD

SDCLK

SDD0

GND

GND

GNDGNDGND

BIBI

IN

IN

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

2.3D<>

2.3B<>

2.3B<

2.3D<>

2.3D<>

2.3B<

2.3B<>

SDD3

SDD2

SDD1

SDCLK

SDD0

SDCMD

SDGP0

22COMMON

SDGP1 2.3D<>

5%R410402

SDCLK_1

B1

B2

B3

D3

C1

D2

C3

F4

3 OF 5dd-mon-year


BASE LEVEL GENERIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINALAudio, SDcard, JTAG Interfaces & SDRAM Debug Logic analyzer

HVDD

BGA288_100_120SC15-XTU1

COMMON

TMS

TRSTn

TDO

TCK

TDI

L13

D4

C4

A3

A2

K16

L16TESTMODE_1

EFUSESRC_1

5%

0402

NO STUFF

4.1B>

4.1B>

10K

10K

NO STUFF

5%

0402

R35

4.1B>

4.1B<

4.1B<

R34

COMMON0

5%0COMMON5%

0402R32

R330402

GND

4.1C<>

4.1C<>

4.1C>

4.1C> 4.1C<>

4.2C< SOUT

SIN

SCLK

SMCLK

SRCLK

SFSYNC

COMMON

COMMON5%22

225%0402

R39

R400402

SMCLK_1

SCLK_1

G2

E1F2F3

F1G3

BGA288_100_120SC15-XT

COMMON

U1

E438 SC15-XT-DDR Board

SC15 JTAG & SDCARD

Audio SDCARD & JTAG Interfaces

SC15 Audio I2S & AC97

BI

BI

BI

BI

OUT

OUT

BI

BI

XT - 4/7 - JTAG/TEST/SD

SDD3

SDD2

SDD1

SDD0

SDGP1

SDGP0

SDCMD

SDCLK

TMS

TDI

TCK

TDO

TRST_

TESTMODE

EFUSESRC

IN

IN

OUT

IN

OUTBIINBI

OUT

BIIN

XT - 5/7 - I2C/AC97

SMCLKSIN

SFSYNC

SOUTSRCLKSCLK

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

AVDDP1

AVDDP2

AVDDOSC

.1UF

COMMON

C68

6.3V

0402X5R10%

.1UF

COMMON

C69

6.3V

0402

10%X5R

10R47COMMON21%

100

COMMON

1%

EMVDD

04021

.001UF

COMMON

10%

C70

50V

X7R0402

COMMON

5%

0402

GND

AVDD_OSC

0R44

0402

.001UF50V

X7R10%

C65

COMMON

0402X7R10%50V

C66

COMMON

.001UF

COMMON0

0

5%0402R42

R43AGND_2

AGND_1

5%0402 COMMON

.1UF16V10%

0402X7R

C67

COMMON

GND

AGND_OSC

VVDD

SDVDD

D18A17

A4

BGA288_100_120

U1

COMMON

SC15-XT

M9M10L9

L10

J11J12

ACVDD

D1

J17H18

G18

K17

H17

L17

A12A6A8A9

A10

K12K11

H10G9

G10

H9

J7

K8K7J8

V16V12R18

V7

N1J1

0603

R45

COMMON

100

1%

0603

R46

.001UF

COMMON

50V10%

C76

0402X7R

GNDGND

EMVREF

.01UFC81

10V10%X5R0402COMMON

0402

.1UFC57

COMMON

ACVDD

.1UFC56

10V10V

X5R10%

0402COMMON

10%X5R

4 OF 5dd-mon-year

GND

600-f0ppp-00ss-vvv

4.7UFC80

6.3V

X5R10%

0603COMMON

.1UF

COMMON

C44.01UF

VVDD

C79

10V 16V

X7R0402

10%

COMMON

10%X5R0402

e438manoharc

GND

.1UF

COMMON

N13M18M1L8L11K9K4K15K10

N7

V6V11U1T17R4

GND

B18B15B11A5

C2C6C9

D13F18F7

G14G4H1

H11H8

J9J10

C42

16V10%X7R0402

22UFC41

COMMON.1UFC40

16V

N/AN/A

10VN/A

TAN

SMA

COMMON

X7R0402

10%

SDVDD

GND

.1UFC39

16V

X7R10%

0402COMMON

4.7UFC78

.1UFC37

6.3V16V

COMMON

10%X5R0603

COMMON0402X7R10%

AOCVDD

MMCVDD

VECVDD

TDCVDD


COMMON

HVDD

LVDD

RESERVE_2

.1UFC51

3.300000.5A

16V.1UF16V

C50

RESERVE_2

3.2D<>

3.2D< 3.2D<>

10%10%

ACVDD

0402COMMON

X7R

COMMON

X7R0402

GND

2.54MM

HDR_1M2

NORM

MALE

J13

COMMON

RESERVE_2

0

21

NORM

02.54MM

MALE

COMMON

HDR_1M2

J14

TDCVDD

TDCVDD

MMCVDD

3.2D>

COMMON

3.2D<> 3.2D<

NORM

MALE

2.54MM

HDR_1M2

J11

0

21HDR_1M2

COMMON

NORM

2.54MM

0MALE

J12

21

ACV_1

RES_2

21

GND

LVDD

.1UFC36

.1UFC35

16V16V

0402X7R10%

COMMON

X7R0402

10%

C27.1UF

COMMON

X7R10%

0402

16V

GND

.1UF

0402

C26

COMMON

HVDD

C25.1UF

16V10%X7R

COMMON

X7R10%16V

0402

.01UF

COMMON

C77

10%X5R0402

10V

GND

Power supplies and Bypassing

0.1UFC64

0.1UFC63

16V16V10%

COMMON0402X7R

COMMON0402X7R10%

0.1UF

COMMON

C620.1UFC61

16V16V

0402

10%X7R

COMMON

10%X7R0402

EMVDD

GND

0.1UFC60

0.1UFC59

16V16V

COMMON0402X7R10%

COMMON

X7R0402

10%

0.1UFC58

16V

COMMON0402X7R10%

MMCVDD

MMCV_1

SCLK

SRCLKSMCLK

246



F_NAME

J3COMMON

531

TDOTDITCK

7 8

SNN_300SOUT

SFSYNCSIN

TDC_1

SNN_64

SNN_65

1614

1012

1820222426283032343638

46

404244

48505254565860

6462

43413937353331

9

45

29

1311

27252321191715

SNN_61

TRSTnTMS

AVDDP1

SNN_60

SNN_66

SNN_6747

595755535149

6361

AOC_1

VECVDD

EMV_1

EMVDD

1A

AVDDP2

AVDDP1

AOC_1

3.2E< 3.2E< 3.2E> 3.2E< 3.2E>

AVDDP2AVDDOSC

AVDDOSC

COMMON

VEC_1

NORM

COMMON

2.54MM

NORM

0MALE

HDR_1M2

J8

HDR_1M2

2.54MM21

0MALE

J9

21HDR_1M2

2.54MM

NORM

MALE

J10

COMMON

2.00000AOC_1

VEC_1

0

21

AOCVDD

AOCVDD

VECVDD

EMVDD

0.5A2.00000

VECVDD

AOCVDD

GNDVEC_1

TDC_1

ACV_1

EMV_1

MMCV_1

RES_2

22UFC34

COMMONN/A10V

.1UFC31

10%16V

X7R

.1UF

10%10V

C554.7UF

6.3V10%

C54

0402X5R

COMMONCOMMON0603X5R

MMCVDD

GND

10V10%X5R0402

.01UFC53

COMMON

6.3V4.7UFC52

10%

.01UFC49

N/ASMA

N/ATAN

COMMON0402

TDCVDD

10V10%

.1UFC48

10%10V

X5R0603COMMON

0402COMMON

X5R

GND

0402COMMON

X5R

0.5A

1A

.1UF

X7R10%

.1UF16V

0402

C30

COMMON

COMMON

1.0A

1.0A

1A

2.00000

2.00000

3.30000

3.30000

1A3.30000

2.00000

MMCV_1

TDC_1

ACV_1

RES_2

EMV_1

VECVDD

TDCVDD

MMCVDD

EMVDD

ACVDD

.1UFC29

16V10%

AOCVDD

C28.1UF16V10%

.01UF

10%10V

C38

0.5A

0.5A

0.5A

0.5A

0.5A

3.30000

3.30000

3.30000

3.30000

3.30000

EMVDD

MMCVDD

TDCVDD

ACVDD

C33

10%10V.1UF4.7UF

6.3V10%

C24

X5RX5R X7RX7RX5R

COMMON0402

10%10V

C47.01UF

10%10V

C46

EMVDD

4.7UF

COMMON0402

COMMON

GND

0402

10%6.3V

C45

10V10%

.1UFC43

X5R0402

COMMON0402X5R

GND

COMMON0603X5RX5R

0402COMMON

COMMON04020603

COMMON

VECVDD

.01UF

10%10V

C324.7UF

10%6.3V

C17

0402X5R

COMMONCOMMON

X5R0603

GND

SC15 Power pins

IO Bypass Caps


NOTE 1

1) All the POWER pins need 0.1 cap to be placed near U1 (SC15)

Power Connector & Bypass Caps

Internal Memory Bypass Caps

WMP MODULE POWER CONNECTOR

Core Voltage Bypass Caps

XT - 6/7 - POWER

SDVDD

VVDD_01VVDD_02

ACVDD

AGNDP1

AVDDP1AVDDP2

AGNDP2

EMVDD_2EMVDD_3EMVDD_4

EMVREF

EMVDD_1

AVDDOSC

AGNDOSC

GND_27GND_26GND_25GND_24GND_23GND_22GND_21GND_20GND_19GND_18

GND_28GND_29GND_30GND_31GND_32

MMCVDD_2MMCVDD_1

AOCVDD_3AOCVDD_2AOCVDD_1

AOCVDD_4

VECVDD_4VECVDD_3VECVDD_2VECVDD_1

MMCVDD_4MMCVDD_3

TDCVDD_1TDCVDD_2TDCVDD_3TDCVDD_4

LVDD_2LVDD_1

HVDD_4HVDD_3HVDD_2HVDD_1

GND_10GND_09GND_08GND_07GND_06GND_05GND_04GND_03GND_02GND_01

GND_11

GND_16GND_15GND_14GND_13GND_12

GND_17

BIOUTIN

OUTBIBI

OUTIN

INOUTOUT

Rev 1.0SRCLK

SCLK

SINSFSYNC

SOUT

SMCLK

NC

NC

MMCVDDMMCVDD

MMCVDD

MMCVDDMMCVDD_FB

TDCVDD

MMCVDD

MMCVDD

TDCVDD

NCRES2_1RES2_2

TDCVDD

TDCVDDTDCVDD

TDCVDDTDCVDD_FB

RES2_3RES2_4

RES2_6RES2_FB

RES2_5

GNDGND

TRST*

TCKTDITDO

NC

TMS

NC

AOCVDD_FB

AOCVDD

AOCVDDAOCVDD

AOCVDDAOCVDD

AOCVDD

VECVDDNC

VECVDD

RES1_2RES1_1

RES1_3

VECVDD

VECVDDVECVDD

VECVDDVECVDD_FBNC

RES1_4RES1_5RES1_6RES1_FB

GNDGND

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

3.4E< SDRAM_DQM<3..0>3

2

01

3.3A<>

3130292827262524

SDRAM_DQ<27>

SDRAM_DQ<31>SDRAM_DQ<30>SDRAM_DQ<29>SDRAM_DQ<28>

SDRAM_DQ<24>

SDRAM_DQ<26>SDRAM_DQ<25>

J5G5H5B4F5B5G6H6

181716

9101112131415

8

2322212019

76

3.4E<

345

210

DDR_DQS<3..0>

SDRAM_DQM<3>SDRAM_DQM<2>SDRAM_DQM<1>

SDRAM_DQ<9>

SDRAM_DQ<7>

SDRAM_DQ<15>

SDRAM_DQ<3>

SDRAM_DQ<14>

SDRAM_DQ<8>

SDRAM_DQ<23>

SDRAM_DQ<10>

SDRAM_DQ<12>

SDRAM_DQ<16>



SDRAM_DQ<17>

SDRAM_DQ<11>

SDRAM_DQ<18>

SDRAM_DQ<13>


SDRAM_DQ<0>

SDRAM_DQ<2>

SDRAM_DQ<4>

SDRAM_DQM<0>

SDRAM_DQ<1>

A13G13

F14

F6D6B6G7B7H7A7B8

B12H12D12G12F13H14

B14

10

32

DDR_DQS<0>DDR_DQS<1>DDR_DQS<2>DDR_DQS<3>D5

D7C13C14

C5C7B13D14

F15C15G15D15A14A15

5 OF 5dd-mon-year


SDRAM_DQ<31..0>


BGA288_100_120SC15-XT

COMMON

U1

D8

G8

D9G11

H13

D11

F10J13SDRAM_A<11>

SDRAM_A<9>SDRAM_A<10>

SDRAM_A<7>

SDRAM_A<5>

SDRAM_A<8>

SDRAM_A<12>

SDRAM_A<6>

121110

89

765

SDRAM_A<12..0>

F9

F8

C8J6

J14

C11C10

B9

C12

F11

D10

B10

A11

F12SDRAM_CKE

SDRAM_CLK

SDRAM_BA0

SDRAM_CLKn

SDRAM_A<0>

SDRAM_A<2>SDRAM_A<1>

SDRAM_WEn

SDRAM_A<4>

SDRAM_CSn

SDRAM_CASnSDRAM_RASn

SDRAM_BA1

SDRAM_A<3>34

2

01

0*.05R

R690603

3.4F<

3.4F<

3.4F<

3.4F< 3.4F<

3.4F<

0*.05R

R710603

3.4F<

SDRAM_CLK_RSDRAM_CLKn_R

3.3E<

COMMON

.1UF

0402

10%16V

X5R

C86

SDR_CVDD

.1UF

COMMON

C73

16V10%

0402X5R

.1UF

0402

10%X5R

16V

C72

COMMON

012

6543

7

1211

98

10

151413

GND

SDRAM Interface

SDR_CVDD

1716

2221201918

.1UF

0402

10%X5R

16V

C87

COMMON

.1UF

COMMON

16V

C75

X5R10%

0402

2726252423

31302928

SDR_CVDD

GND

.1UF

1UF

0603

10%10V

X5R

C85

COMMON

COMMON

COMMON

1%

100PF

0402

5%50V

C0G

C84

COMMON

0603

1%

*196

0COMMON.05R

R58

374

ADJ_SDRCVDD

0603R57SDR_CVDD_11

4

2

COMMON

U4LT1763

S8S8

VREF=1.22V

R59

0603

16V

C71

10%

0402X5R

BYP_SDRCVDD

K9F9A9

SDRAM_DQ<0>

SDRAM_DQ<6>


SDRAM_DQ<3>SDRAM_DQ<4>SDRAM_DQ<5>



SDRAM_DQ<11>


SDRAM_DQ<10>

E7D8D7C8C7

A8B7B8

A2B3B2C3C2D3D2E3

BGA60K4X56163PE

COMMON

U3

A7B1C9D1E9

G7

G9

H7G8

K7J9J8

H3H2J7H1J3J2J1K3K2K8

EMVDD

SDRAM_RASn

SDRAM_WEnSDRAM_CSnSDRAM_CASn

D3V3

8

37

5

6

.1UF

COMMON

10%

C83

16V

X5R0402

1UF

0603

10%X5R

10V

C82

COMMON

10K

COMMON

5%

0402

R55

100

COMMON

5%

0402

R56

EMVDD

GND

SDRAM_A<12..0>

121110

012

43

5

76

98

GND

D9C1B9A3

E1

K1F1A1

.1UF

0402

10%16V

X5R

C74

COMMON

SDRAM_DQ<16>

SDRAM_DQ<22>



K9F9A9

D8D7C8C7

A8B7B8

E2F2

G1

G3G2

H9H8

F8

F7

E8

F3

BGA60K4X56163PE

COMMON

U5

D1C9

A7B1

E9

G7

G9

H7G8

J9J8

SDRAM_DQ<26>


SDRAM_DQ<27>



A2B3B2C3C2D3D2E3E7

C1B9A3

D9

GND

E1

K1F1A1

H2J7H1J3J2J1K3K2K8K7

H3

E2

G1

G3G2

H9H8

F2

F7F3

F8E8

SDRAM_CLKn_RSDRAM_CLK_R

SDRAM_CLKn_RSDRAM_CLK_R

SDRAM_WEn

SDRAM_DQM<1>

SDRAM_CKE

SDRAM_BA0SDRAM_BA1

DDR_DQS<1>

DDR_DQS<0>SDRAM_DQM<0>

SDRAM_RASn

SDRAM_DQM<3>

SDRAM_CKE

SDRAM_BA0SDRAM_BA1

DDR_DQS<3>

DDR_DQS<2>SDRAM_DQM<2>

SDRAM_CSnSDRAM_CASn

COMMON200

EMVDD

0.1%R4

0603

10

COMMON200

0.1%

121110

32

4

65

87

9

R360603

NOTE 2

1) SDRAM CLK , SDRAM DATA TRACE LENGTH SHOULD MATCH +-5%2) SDRAM CLK, SDRAM CTRL TRACE LENGTH SHOULD MATCH - +-10%


1) RESISTORS ON CLK, CLKn on TOP SIDENOTE 3

2) R71 & R69 near U1(SC15)

Place R4 or R36 on TOP SIDE(One of the resistors)

Place R4 near U3

Place R36 near U5

OUT

BI

OUT

XT - 7/7 - MEM

MD30MD31

MD29MD28MD27

MD25MD26

MD24

MD23MD22MD21MD20MD19MD18MD17MD16

MD15

MD11

MD14MD13MD12

MD10MD9MD8

MD7MD6MD5MD4MD3MD2MD1

MDM1MDM0

MDQS3MDQS2

MDM3

MD0

MDM2

MDQS0MDQS1

MA10MA11MA12

MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0

MBA1MBA0

MRAS_

MWE_MCAS_

MCS_

MCLK_MCLK

MCKE

OUTOUT

OUTOUTOUTOUT

OUT

OUT

OUT

ADJ

BYP

IN

GND2

SHDN*

GND1

GND3

1/2

DQ<1>DQ<0>

VDDVDDVDD

DQ<2>

DQ<6>

DQ<3>

DQ<11>DQ<10>DQ<9>DQ<8>DQ<7>

DQ<5>DQ<4>

DQ<12>DQ<13>DQ<14>DQ<15>

VSSQVSSQVSSQ

VSSQVSSQ

VSS

VSSVSS

VDDQ

VDDQ

CAS*

VDDQVDDQ

RAS*

VDDQ

CS*

A<6>A<5>

A<3>A<2>A<1>A<0>

A<4>

WE*

A<7>

BA<1>BA<0>A<12>A<11>A<10>/APA<9>A<8>

CKECK

LDQS

UDQS

CK*

UDM

NCNC

LDM

1/2

DQ<1>DQ<0>

VDDVDDVDD

DQ<2>

DQ<6>

DQ<3>

DQ<11>DQ<10>DQ<9>DQ<8>DQ<7>

DQ<5>DQ<4>

DQ<12>DQ<13>DQ<14>DQ<15>

VSSQVSSQVSSQ

VSSQVSSQ

VSS

VSSVSS

VDDQ

VDDQ

CAS*

VDDQVDDQ

RAS*

VDDQ

CS*

A<6>A<5>

A<3>A<2>A<1>A<0>

A<4>

WE*

A<7>

BA<1>BA<0>A<12>A<11>A<10>/APA<9>A<8>

CKECK

LDQS

UDQS

CK*

UDM

NCNC

LDM

1

5

4

3

2

F G H

PAGEDATE



NVIDIA CORPORATION

NV_PN

IDNAME

ED

ASSEMBLYPAGE DETAIL



B C

2

A

1

3

4

5

E GD F HCA B

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