scan chain and lock up latch

www.ednmag.com February 17, 2000 | edn 67

AS GATE COUNTS INCREASE AT AN ENORMOUS RATE, THE

SCAN-DESIGN METHODOLOGY IS BECOMING NECESSARY TO

PRODUCE HIGH-QUALITY CHIPS.

Although scan-design methodologies haveexisted for several years, many companies arejust starting to explore the use of scan, particu-

larly as these companies create more complex, sys-tem-on-chip (SOC) designs. With gate counts in-creasing at an enormous rate, producing high-fault-coverage production tests without using scantechniques becomes increasingly difficult. Scan is be-coming a necessary design methodology to producehigh-quality chips.

If you’re just starting out in scan design, this two-part series provides useful design tips to ensure suc-cessful adoption of scan-design methodologies with-in your company or design group. Part one reviewsthe scan methodology and techniques. Part two pres-ents the tips. By adhering to these tips, you can pro-duce chips that current automatic-test-pattern-gen-eration (ATPG) tools can process to generatescan-based test vectors providing high fault coverage.

Before starting your project, research scan-designmethodologies and read as much as you can. In ad-dition to this series, references 1 and 2 are great in-troductions to scan. (You can also download “Sim-ple case study” from EDN’s Web site, www.ednmag.com/ednmag/reg/2000/02172000/04ms604.htm.) Don’t expect just the “scan expert” ofthe project to learn scan techniques. Geteveryone involved. The more the designers know, theeasier it is for them to produce scan-friendly designs.(See sidebar “Glossary” for a list of definitions andacronyms.)

Also, don’t underestimate the amount of time ittakes to produce a scan design. If your company isjust starting out, scan design will require a largeamount of time. You may encounter many pitfallsand unexpected problems.Your managers may wantto send the chip to the fab without allowing youmuch time to simulate the test patterns produced bythe ATPG tools. But if you don’t run back-annotat-ed simulations of the test patterns, then don’t expect

the patterns to work. These simulations will alert youto timing problems, tool problems, and functionalproblems.

WHY IS SCAN IMPORTANT?

Designers create functional simulations to verifythe proper operation of their designs. For example,a designer of a memory controller creates simula-tions to verify that the design operates correctlywithin the system. This approach is fine for the vir-tual world, in which the chip is only bits and piecesof HDL coding. However, you ultimately want tomanufacturer a real chip and verify that it worksproperly. Production tests can verify that the man-ufacturer correctly implemented the design and thatthe design is free from flaws, such as power andground shorts, open interconnections due to dustparticles, and others. In short, production testing en-sures that the customer receives high-quality partswith low failure rates.

In the past, you could use functional simulationsto generate test vectors, which you could then useto verify newly manufactured chips on a tester. Butbecause of the high gate counts and extreme com-

10 tips for successful scan design: part one

D

C

B

A

STUCK AT 0

For a simple circuit, you can manually create test vectors toverify that each node is not stuck high or low. However, thisapproach isn’t feasible for more complicated designs.

F igure 1

designfeature By Ken Jaramillo and Subbu Meiyappan, Philips Semiconductors

designfeature Scan design

68 edn | February 17, 2000 www.ednmag.com

plexity of today’s SOC designs, these pro-duction-test techniques are quick-ly running out of steam. You canstill use functional simulations to verifythe operation of a design, but producingenough simulations to provide high faultcoverage is becoming more difficult. Forexample, consider a 500,000-gate designthat contains an embedded ARM proces-sor, an embedded DSP mP, a complexmemory controller, and several high-gate-count peripherals. Although designteams can produce enough functionalsimulations to verify the chip, these func-tional simulations would probably pro-vide only about 80% fault coverage if youused them to produce production-testvectors. The amount of effort necessaryto create additional simulations that re-sult in high fault coverage, 95% for ex-ample, would be difficult and time con-suming.

With the advent of scan-design tech-niques and ATPG tools, however, you cantake this same design and quickly pro-duce several thousand production-testvectors that provide high fault coverage.The use of scan-design techniques sim-plifies the problem of test-pattern gener-ation by reducing the design, or sectionsof a design, into purely combinationallogic. Then you can make use of fast andefficient algorithms in ATPG tools—al-gorithms that the tool designer devel-oped for combinational logic—to gener-ate high-fault-coverage vectors.

WHAT IS SCAN?

The goal of any production-testingscheme is to verify that the chip is man-ufactured correctly. Consider the simplecircuit in Figure 1. If you want to verifythat node A is not stuck at 0, due to amanufacturing flaw that shorts this nodeto ground, you can create the vector(A51, B50, C50). Setting B and C lowallows modifications of A to directly con-trol the output at D. If A is stuck at 0, thenD will be 0, no matter what value drivesA. Similarly, you can create other vectorsto verify that each node is not stuck highor low. You can manually create thesesimple test vectors with little effort. How-ever, if the design is complicated andcontains thousands of flip-flops andhundreds of thousands of combination-al logic gates, manually creating these testvectors is laborious.

The use of scan-design techniques al-lows you to use all of the flip-flops in adesign as a big shift register during scantesting. Thus, you can shift patterns intothe chip, for example to drive the inputsof Figure 1’s circuit with A51, B50, andC50. The flip-flops capture the func-tional data that results from the test pat-tern, for example to capture the value atD, which is 1, and you can shift out theresults. This internal scan increases thecontrollability and observability of in-ternal nodes by connecting storage cellsinto a long shift register, or scan chain,and by enhancing the logic of these cellsto support a scan-shift mode that allowsfor serial loading and unloading of scanchain’s contents.

In normal operational mode, the scanchain does not affect system operation.When you select scan mode, however, the

outputs of each storage cell in the scandesign become primary inputs to thecombinational logic, which increasescontrollability. The inputs of each scanstorage cell allow registering of the out-puts of the combinational logic, whichincreases observability. ATPG tools areproficient at generating test patterns toprovide high fault coverage for combi-national logic. Scan allows the tools tohave easy access to all the combinationallogic in the design.

Figure 2a shows a simple circuit with-out any scan circuitry. The circuit con-tains three flip-flops and some combina-tional logic. This circuit could representa simple state machine with a registeredoutput. You add scan to this design tocreate the design in Figure 2b. You needto add only three additional pins, or pads,for scan testing: a scan-input pin for se-

For an example design that contains three flip-flops and some combinational logic, which couldrepresent a simple state machine with a registered output (a), adding scan testing requires justthree additional pins (b).

(a)

FUNCTIONALINPUTS

(b)

FUNCTIONALINPUTS

SCAN INPUT 0

1

0

1

0

1

1

2

3

SCANOUTPUT

SCAN ENABLE

F igure 2


rial data input, a scan-output pin for se-rial data output, and a scan-enable pinfor scan-mode control. This design sharesthe scan clock with the system clock. Youcan often use multiplexers to combinethese pads with system-operation pads,which reduces the I/O overhead. This ex-ample forms a serial scan chain from thescan-input pad, connecting each flip-flopinto a scan register that is 3 bits long. Theoutput of the final flip-flop con-nects to the scan-output pad. Eachof the flip-flops in Figure 2b is now a flip-flop with a multiplexed input. The scan-enable signal selects between the normalfunctional-data input, which comes fromthe combinational-logic clouds, and thescan data, which comes from the scan in-put or the previous flip-flop. The scan-chain ordering is from flip-flop 1 to flip-flop 3.

Figure 3 illustrates the timing for scantesting of Figure 2b’s circuit. The timingsequence consists of three stages: firstscan mode, then normal system mode,then scan mode again. Scan enable51 se-lects the scan mode, during which dataserially loads into the scan chain from thescan-input signal. When the scan chainis fully loaded, which requires onescan clock for each storage cell inthe scan chain, scan enable50 selects thenormal system mode. In this mode, thesystem applies one system clock, appliesdata at the primary inputs of the chip,and observes data at the primary outputsof the chip. This procedure captures datafrom the combinational-logic elementsof the design into the scan-storage cells.The system asserts and deasserts thescan-enable signal on the falling edge ofthe clock, which helps ease timing, espe-cially the hold-time constraints. In thelast and third part of the sequence, thesystem again selects scan mode with scanenable51 and uses the scan clock to un-load the scan chain through the scan out-put. The tester then checks this outputdata against expected values. While cap-tured data shifts out of the scan chain,the system can load input data from thenext scan-test pattern into the scanchain.

Figure 4 shows a circuit with two clockdomains and with the scan circuit inplace. The upper portion of the figureshows clock domain 1 using clk1 andconsists of two flip-flops and some com-

A scan sequence involves three stages, which the scan-enable input controls.

SCAN CLOCK

SCAN INPUT

SHIFT IN FIRST VECTOR NORMALMODE

SHIFT OUT RESULT OF FIRST VECTOR AND SHIFT

IN SECOND VECTOR

SCAN ENABLE

SCAN OUTPUT X X X X C1 C2 C3

S1 S2 S3 X S4 S5 S6

NOTES:S1, S2, S3=SCAN DATA FOR THE FIRST TEST VECTOR.S4, S5, S6=SCAN DATA FOR THE SECOND TEST VECTOR.C1, C2, C3=CAPTURE DATA FROM THE FIRST TEST VECTOR.

F igure 3

When a circuit uses two clock domains, the scan design involves two scan chains, one for eachclock domain.

FUNCTIONALINPUTS

0

1

0

0

1

1

2

1

SCAN OUTPUT 1

CLK1

CLK1

CLK2

SCAN INPUT 1

FUNCTIONAL OUTPUTS

FUNCTIONALINPUTS

0

1

0

1

4

3

CLK2

CLK2

SCAN INPUT 2

FUNCTIONAL OUTPUTS

5

SCAN ENABLE SCAN OUTPUT 2

A

F igure 4



binational logic. The bottom portion ofthe figure shows clock domain 2 usingclk2; it consists of three flip-flops andsome combinational logic.You can thinkof the circuit as two state machines witha shared communication signal, A, thatflip-flop 5 synchronizes to clk2. This ex-ample includes two scan chains, one foreach clock domain. The first scan chainstarts with scan input 1 going throughflip-flops 1 and 2 to scan output 1. Thesecond scan chain starts with scan input2 going through flip-flops 3, 4, and 5 toscan output 2. The circuit has only onescan-enable signal, even though there aretwo scan chains. Because the two scanchains interact—via the functional pathfrom flip-flop 1 to flip- flop 5—you haveto be careful when you assert the clocksduring the capture cycle, or you couldend up with a hold-time violation at flip-flop 5.

Figure 5 illustrates the timing for scantesting of this circuit. Similar to the tim-ing diagram in Figure 3, this sequencehas three stages. During scan mode,

when scan enable51, data loads seriallyinto the scan chains from scan input 1and scan input 2. Each of the two scanchains loads in parallel. The length of thelongest scan chain determines the lengthof the scan-shift operation. Scan chain 2is three flip-flops long. Therefore, thescan-shift operation takes three clocks.Scan chain 1 is only two flip-flops long.However, you can still shift three datavalues into this chain as long as the firstvalue is a “don’t care.”

As in Figure 3, when the scan chainsare loaded, scan enable50 selects normalmode: The system applies one clock, ap-plies data at the primary inputs of thechip, and observes the data at the pri-mary outputs of the chip. As before, thisaction captures data from the combina-tion-logic elements of the design into thescan-storage cells. However, the capturecycle in Figure 5 differs from the cyclein Figure 3, which has only one clock do-main. Because two clock domains existand interact, the capture cycle must stag-ger the assertion of the clocks. Stagger-

As in Figure 3, the scan operation for multiple scan chains involves three stages. In this case, how-ever, the capture cycle uses staggered clocks for the two clock domains.

SCAN ENABLE

CLK1

X S1_1 S1_2 X X

S2_1 S2_2 S2_3 X S2_4

X X X C2_1 C2_2

X X X C1_1 C1_2

SHIFT IN FIRST VECTOR CAPTURECYCLE

SHIFT OUT RESULT OF

FIRST VECTOR AND SHIFT IN

SECOND VECTOR

SCAN INPUT 1

SCAN OUTPUT 1

CLK2

SCAN INPUT 2

SCAN OUTPUT 2

NOTES:S2_1, S2_2, S2_3=SCAN CHAIN 2 DATA FOR THE FIRST TEST VECTOR.S1_1, S1_2=SCAN CHAIN 1 DATA FOR THE FIRST TEST VECTOR.C2_1, C2_2, C2_3=SCAN CHAIN 2 CAPTURE DATA FOR THE FIRST TEST VECTOR.C1_1, C1_2=SCAN CHAIN 1 CAPTURE DATA FOR THE FIRST TEST VECTOR.S2_4, S2_5, S2_6=SCAN CHAIN 2 DATA FOR THE SECOND TEST VECTOR.S1_3, S1_4=SCAN CHAIN 1 DATA FOR THE SECOND TEST VECTOR. F igure 5

Circle 4 or visit www.ednmag.com/infoaccess.asp


ing the clocks prevents any timing prob-lems with the data crossing the clock do-mains. The capture cycle first clocks datainto scan chain 1, at the first clock afterscan enable goes low, to capture datainto the clk1-based flops. The capturecycle then clocks data into scan chain 2,at the second clock after scan enable goeslow, to capture data into the clk2 basedflops. After capture data latches into theflip-flops on scan chain 1, the function-al input to flip-flop 5 of the second scanchain will change. Only sequential-basedATPG tools can handle this situation.Purely combinational-based ATPG toolscannot. If you’re using a combinationalATPG tool, you should tell the tool to as-sert only one of the clocks during thecapture cycle. The tool then asserts clk1or clk2 only during the capture cycle,which results in a higher number of pat-terns for the same level of fault coverage.

Finally, the cycle again selects scanmode, and the system uses the scanclocks to unload the scan chains throughthe scan-output pins. While capture datashifts out of the scan chains, input datafrom the next scan-test pattern can be-gin loading. Note that Figure 5 shows thefirst cycle of the shift.

SCAN TECHNIQUES AND ELEMENTS

All of the examples so far use flip-flopswith multiplexed inputs for the scan-storage elements. These multiplexed flip-flops are only one type of scan-storageelement. The other types of scan ele-ments are clocked scan elements and lev-el-sensitive-scan-design (LSSD) ele-ments. Each type of scan elementprovides its own benefits. Multiplexedflip-flop and clocked-scan techniques arebetter suited for designs that containedge-triggered flip-flops. LSSD tech-niques are better suited for latch-baseddesigns. The type of scan element youdecide to use depends on your designand your ASIC vendor. The examples inthis article use the multiplexed flip-floptechnique.

A multiplexed flip-flop scan elementcontains a single D-type flip-flop withmultiplexed inputs that allows selectionof either normal functional data or scan-input data. Figure 6a shows a multi-plexed flip-flop scan element. In normalmode (scan enable50), the system data,or functional input, goes through to the




flip-flop, which registers the data. In scanmode (scan enable51), scan data goesthrough to the flip-flop so that the flip-flop registers the scan data.

Clocked-scan elements aresimilar to multiplexed flip-flop elementsbut use a dedicated test clock to registerscan data into the flip-flop (Figure 6b).During normal operation, the systemclock registers the system data at thefunctional input into the flip-flop. Dur-ing scan mode, the scan clock registersthe scan data into the flip-flop.

LSSD uses three independent clocks tocapture data into the two latches withinthe scan cell (Figure 6c). During normalmode, the master latch uses the systemclock to latch system data at the func-tional input and to output this data to thenormal functional-data output path.During scan mode, the two scan clockscontrol the latching of data through themaster and slave latches to generate thedata at the scan output.

LOCKUP LATCHES

Scan chains are vulnerable to clock-skew problems for two main reasons. Thefirst reason has to do with layout andpropagation delay. The same clock maydrive hundreds or thousands of scan-storage cells with no circuitry betweenthem. Logically adjacent storage cells inthe scan chain may be physically sepa-rated in the layout. Clock skew between

Three types of scan-storage elements exist: multiplexed flip-flop elements (a), clocked-scan ele-ments (b), and level-sensitive-scan-design (LSSD) elements (c).

ORIGINAL D FLIP-FLOP

MULTIPLEXED FLIP-FLOP SCAN ELEMENT

0

1

FUNCTIONAL INPUT

SCAN INPUT

SCAN ENABLE

CLOCK

ORIGINAL D FLIP-FLOPCLOCKED-SCAN ELEMENT

FUNCTIONAL INPUT

SCAN INPUT

SYSTEM CLOCK

SCAN CLOCK

ORIGINAL LATCH

FUNCTIONAL INPUT

SCAN INPUT

SYSTEM CLOCK

SCAN CLOCK

D

EN

Q

D

EN

Q

1

MASTER LATCHSCAN

OUTPUT

FUNCTIONALOUTPUT

SLAVE LATCH

LEVEL-SENSITIVE SCAN-DESIGN ELEMENT

SCAN CLOCK 2

(a)

(b)

(c)

F igure 6

GLOSSARYAAuuttoommaattiicc tteesstt--ppaatttteerrnnggeenneerraattiioonn. (ATPG)—the processof generating scan-based produc-tion-test patterns automaticallyvia a CAD tool.CCaappttuurree ccyyccllee—the clock cycleduring scan mode in which thesystem switches the scan flip-flopmultiplexed inputs to select thenormal functional inputs ratherthan the scan inputs. At thispoint, the scan flip-flops “cap-ture” functional data after a scanpattern has shifted into the de-vice under test.CCoommbbiinnaattiioonnaall vveerrssuuss sseeqquueennttiiaallAATTPPGG—applies to how the ATPGtool handles scan data duringcapture cycles. This concept isimportant if you have multiple

clock domains and the logic be-tween domains interacts duringcapture cycles. When these con-ditions exist, you normally stag-ger your clocks for pattern gener-ation. For example, if you havetwo clock domains, clk1 and clk2,you assert clk1 at time 200 anddeassert it at time 250 while as-serting clk2 at time 300 and de-asserting it at time 350. This stag-gering of clocks helps to avoidany hold-time violations betweenclock domains.

Combinational scan tools can-not handle this situation. They as-sume that capture data from oneclock domain does not affect thecapture data of another chain. Ifyour ATPG tool does not support

sequential scan and your designhas interaction between the clockdomains, then you must tell thetool to generate only one scanclock at a time during capture cy-cles. This constraint makes thetool’s job more difficult becauseit has to generate more patternsto get the same level of fault cov-erage as if the tool had been ableto assert multiple clocks duringcapture cycles.

Sequential scan tools can han-dle this situation. The tool knowsthat data from clk1 changes dur-ing the capture cycle and that, inturn, changes the capture data ofsome flip-flops in the clk2 scanchain.FFaauulltt ggrraaddiinngg—the process of de-

termining the percentage ofmanufacturing faults a set of testpatterns can detect within a chip.Production testing—the processof verifying the correct manufac-ture of a chip. To accomplish thistesting, you usually create a set oftest vectors to run on a tester thattests packaged parts.SSeeqquueennttiiaall AATTPPGG—See combina-tional versus sequential ATPG.SShhiifftt mmooddee—the clock cycles dur-ing scan mode in which the scanflip-flop’s multiplexed inputsswitch to select the scan inputsrather than the normal functionalinputs. This mode allows you toshift in the current test patternprior to performing a capture cycle.


successive scan-storage cells must be lessthan the propagation delay be-tween the scan output of the firststorage cell and the scan input of the nextstorage cell. Otherwise, data slippage mayoccur. Thus, data that latches into thefirst scan cell also latches into the secondscan cell. This situation results in an er-ror because the second scan cell shouldlatch the first scan cell’s “old” data ratherthan its “new” data. Figure 7 demon-strates that the path delay for the data isless than that of the clock. Thus, the“new” data at Da passes all the waythrough to Dd in one clock period. Thesecond flip-flop should have latched the“old” value at Dc (a logic high) ratherthan the “new” value.

The second reason for clock skew isthat clock domains separate the scanchains. For example, all the flip-flopsfrom the clk1 clock domain in Figure 4are linked in the same scan chain. Like-wise all the flip-flops from the clk2 clockdomain form a second scan chain. If youwant to link these two scan chains toform a single scan chain, timing prob-lems could result. Two clock trees gener-ate the two clocks, which intro-duces some amount of skewbetween the two clocks. You cannot linkthe two scan chains unless you handlethis clock-skew problem. The timing forthis scenario would be very much thesame as that in Figure 7 except therewould be two separate clocks rather thana single clock.

Lockup latches are nothing more thantransparent latches.You use them to con-nect two scan-storage elements in a scanchain in which excessive clock skew ex-ists. Figure 8 illustrates the use of lock-up latches. The circuit contains two flip-flops. Flip-flop 1 represents the end of thescan chain that contains only elementsthat are in the clk1 clock domain. Flip-flop 2 represents the beginning of thescan chain that contains only elementsthat are in the clk2 clock domain. Al-though the figure doesn’t show it, theseflip-flops have multiplexed inputs. Theinputs of these flip-flops represent thescan inputs of the multiplexers. The latchhas an active-high enable, which be-comes transparent only when clk1 goeslow and effectively adds a half clock ofhold time to the output of flip-flop 1. Inthis figure, you assume that the systemsynchronously asserts clk1 and clk2,

Clock skew can cause data slippage. In this case, because the “new” data at Da passes all the waythrough to Dd in one clock period, the second flip-flop incorrectly latches this “new “ value insteadof the correct “old” value at Dc.

DaDb Dc Dd

CLKa

CLKa

DaDb

Dc

CLKb

Dd

CLKb

PATH DELAY OF THE DATA ISLESS THAN THE PATH DELAY OF THE CLOCK. THUS, DATA ATDa CAN PASS TO Dd ON A SINGLE CLOCK EDGE.

F igure 7

To reduce clock-skew problems, you can use lockup latches to connect two scan-storage elementsin a scan chain. In this case, the latch effectively adds a half-clock of hold time to the output of flip-flop 1.

Da Db DdDc De

CLK1

CLK2

CLK1

CLK2

Da

Db

Dc

EN

Dd

De

EN

LOCKUPLATCH

1 2F igure 8




which would be the normal case duringscan-mode operation. Although theclocks synchronously assert, someamount of clock skew between them stillexists because they come from differentclock trees.

Figure 8 shows the use of lockup latch-es to connect scan chains from differentclock domains. However, you can just aseasily use these latches to connect scanchains from various blocks within a chipthat, although on the same scan chain, arephysically remote from each other on thedie. You want to make the latch trans-parent during the inactive part of theclock. For example, both flip-flops in Fig-ure 8 trigger on the rising edge of theclock. Therefore, you want to make thelockup latch transparent during the lowperiod of the clock. If the flip-flops trig-ger on the falling edge of the clock, youwant the latch to be transparent when theclock is high.k

References1. Scan Synthesis User Guide, Synop-

sys, www.synopsys.com.2. ASIC/IC Design-for-Test Process

Guide, Mentor Graphics, www.mentorgraphics.com.

Authors’ BiographiesKen Jaramillo is a principal engineer atPhilips Semiconductors, where he hasworked for four years. He has worked as designer and architect of ASICs, FPGAs,and boards for products including avion-ics, high-speed serial buses, high-perform-ance gaming platforms, PCI-bus-relatedproducts, high-performance PC audio, andhigh-speed networking products. He has aBSEE from the University of Missouri(Kansas City) and a BSCE from the Uni-versity of Missouri (Columbia).

Subbu Meiyappan is a senior design engi-neer at VLSI Technology, a subsidiary ofPhilips Semiconductors. He has worked forthe company for three years, designing, de-veloping, synthesizing, simulating, and val-idating high-performance intellectual-property blocks for PCI, ARM-ASB-baseddevices, and high-performance ASICs. Hehas a BE from Annamalai University (An-namalai Nagar, India) and an MS fromTennessee Technological University(Cookeville, TN).

scan chain and lock up latch

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