scan testing - yonsei

SCAN Testing

Sungho Kang

Yonsei University

2Computer Systems Lab. YONSEI UNIVERSITY

IntroductionOutline

l Introductionl Scan Registersl Scan Celll Scan Methodologyl Scan Lengthl Partial Scanl Design Rulesl Conclusion


IntroductionScan

l Scan is a test methodology that allows one to control and observe all internal nodes in a synchronous design

l Application for finite state machinesl Combinational and sequential elements tested separatelyl Logic Testl Two mode operation§ Normal mode§ Test mode


IntroductionScan Design

Combinational

Q D

C

Q D

C

Q D

C

POPI

Clk

MUX0

MUX

MUX0

0

1

1

1

N/T_

Sin

Sout



l Huffman Model of Sequential Circuit

CombinationalCircuit

F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

Clock



l Normal Mode


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCAN INSCAN OUTMODE

MUX

7C o m p u t e r S y s t e m s L a b . YONSEI UNIVERSITY


l Test Mode : Flush Test (shift test of scan path)


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCAN INSCAN OUT

MODE

MUX



l Test Mode : Scan in of a test vector


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCAN INSCAN OUT

M O D E

M U X



l Test Mode : Apply the test vector to Pi and observe a response at PO


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCANINSCANOUT

M O D E

M U X



l Test Mode : Capture response by a clock tick


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCANINSCANOUT

MODE

MUX



l Test Mode : Scan Out of a response


F/F

F/F

F/F

PrimaryOutputs

Primary Inputs

SCAN INSCAN OUT

MODE

MUX


IntroductionScan Cell

l A specialized FF or latch activated only when the design is in scan mode§ Allows data to be scanned in for control§ Allows data to be scanned out for observation


IntroductionTest for Sequential Circuits

l Flush Test§ Used in two-clock circuits

§ Simultaneously activates both master clock and the scan clock inthe scan mode

§ Inputs of 0 and 1 are successively applied at the scan register input

§ Initialize FFs to 0 and shift 1 through FFs

l Shift Test§ Used in both two-clock and single-clock circuits

§ This test shift pattern of 0 and 1 through the shift register in the scan mode

§ 00110011... sequence is shifted through FFs


IntroductionScan Design Flow

l Complete HDL Design using scan design rulesl Synthesize logic using the selected ASIC libraryl Convert regular FFs to scan FFs§ Use test synthesis program

l Connects the scan data in a serial chain and clocks§ Use test synthesis program

l Generate test patterns automatically


IntroductionScan Test Operation Loop

l Put the chip into scan model Shift data into scan chain through Scan in§ While scanning in the next pattern through Scan in, scanning out

the results through Scan out of the previous patternl Apply the functional clock to latch responses into scan

FFsl Perform above 2 steps for each test pattern


IntroductionScan vs Conventional Test Methods

l Scan Conventional l Test Generation Automatic Manual l Vector Type Structural Functional l Test Coverage Extremely High Low to Mediuml Vector Set Minimal Large l Test Time Short Long l Tester Memory Minimal Large


IntroductionAdvantages of Scan Design

l Structured design is possiblel Can use combinational ATPGl Significant reduction of test generation timel High fault coverage, typically 99.5 l Ease of fault diagnosis


IntroductionDisadvantages of Scan Design

l Additional circuitry is added to FF§ SCAN flip-flop is more expensive§ Additional chip area

l Additional circuit pinsl Performance penalty§ Increased propagation time

l Test time increase§ Due to shift in and shift out

l Some designs are not easily realizable as scan designsl Need to store Patterns§ Motivation for BIST

l Inability to test circuits at full speed§ Motivation for Delay Fault Testing


Scan RegistersScan Registers

l Simultaneous controllability and observability

l Non-simultaneous controllability and observability



l Non-simultaneous controllability and observability§ Load the scan register with test data by setting T2=1 and clocking

CK2§ Drive the circuit to a predefined state with T1=0§ Load Q2 into latch Q1§ Inject signals into the circuit by setting T1=1§ Observe OPs by setting T2=0 and clock CK2 once§ Scan out data by setting T2=1 and clocking CK2



l Observability only

l Combining many observation points



l Controllability only


Scan RegistersScan Design

l Adding controllability and observability to a circuit§ To inject 0, an AND is used and to inject 1, an OR is used§ To inject 0 or 1, a MUX is used


Scan RegistersScan Design

l Controllability/Observability with scan chain § The normal path from A to B is broken when B1=1§ The top row of MUXs is used to inject data into a circuit from scan

register§ The lower row of MUXs is used for monitoring data within the

circuit


Scan RegistersFull Serial Scan


Scan RegistersIsolated Serial Scan

l Scan register is not in the normal data pathl Somewhat ad hoc since CPs and OPs is left up to the

designer


Scan RegistersFull Isolated Scan

l High overheadl Support real time testing§ A single test can be applied at the operational clock rate of the

systeml Support on-line testing § Circuit can be tested while in normal operation


Scan CellMultiplexed Data Flip-flop

l Setting TE = 1l Shifting the test patterns from SI into the flip-flopsl Setting TE = 0 and after a sufficient time for

combinational logic to settle, checking the output valuesl Applying a clock signal CLKl Setting TE = 1 and shifting out the flip-flop contents via Q


Scan CellTwo-port Dual-clock Flip-flop

l Sometimes it is useful to separate the normal clock from scan clock


Scan CellMultiplexed Data Shift Register Latch

l It is often desirable to insure race-free operation by employing a two-phase non-overlapping clock


Scan CellTwo-port Shift Register Latch

l Avoid the delay introduced by the MUXl LSSD


Scan CellRaceless Two-port D Flip-flop

l CLK : Control normal operationl SK : Select scan data and control scan process


Scan CellPolarity-hold Addressable Latch

l Random access scanl Since no shift operation occurs, a single latch per cell is

sufficientl Latches that are not addressed produce a scan-out value

of So = 1l The So output of all latches can be wired-ANDed together

to form the scan-out signal Sout


Scan CellFASCAN

l No delay in data pathl Additional MUX in clock path


Scan MethodsScan/Set

l Use generic isolated scan architecturel Add to the circuit a shift register whose sole purpose is

the shifting in and out of test data§ FFs(test purpose); Ls(system latches converted to 2-port latches)§ More overhead§ Possible to gate the latch contents into the test shift register

during normal system operation§ Possible to scan circuit nodes other than latch outputs into the

test shift register


Scan MethodsRandom Access Scan

l Non-serial Scan


Scan MethodsRandom Access Scan

l Treat each one of the latch elements as a bit in memoryl Each bit in the memory has its own unique address, and it

has a port which can load data into the latches so that the contents of the latch can be observed

l There is only one scan-in and one scan-outl Addressing scheme which allows each latch to be

uniquely selected, so that it can be either controlled or observed.

l Normal operation§ Scan clock is off

l Only one latch receives the scan clock and that value is loaded into the latch.


Scan MethodsLSSD

l Level Sensitive Scan Designl Level sensitive§ If the steady state responses to any of the allowed input changes

is independent of the transistor and wire delays in the networkl Polarity-hold hazard-free level-sensitive latch§ When a clock is enabled, the state of latch is sensitive to the level

of the corresponding data input§ To obtain race-free operation, clocks are non-overlapping

l Rules for LSSD § hazard-free D latches should be used for all system bistables§ A two-phase latch FSM structure should be used§ The L1 and L2 latches should be interconnected in a scan path

structure


Scan MethodsLSSD

Latch a

L1

Latch c

L1

Latch b

L2

L1

L2

A

A

AO

A

AO

Scan In

BA

DC

I

BA

C’A’CD

AI

B’

B

l D: normal data, I: scan data, C: system clock, A: scan clock, B: slave clock


Scan MethodsLSSD Double Latch Design

l Both L1 and L2 participate in system function

L1

L2

L1

L2

L1

L2

L1

L2

L1

L2

O/Ps

I/Ps

Scanout

CK1

CK3

CK2

SI

Com

bina

tiona

llo

gic

Com

bina

tiona

llo

gic



l Test Sequence

§ Scan mode: apply AB clock pairs to load SRLs

§ Apply Primary Input stimuli

§ Measure Primary Output response (clocks off)

§ Capture state responses into SRL (eg: pulse C)

§ Scan mode: pulse B clock to copy L1 to L2.

§ Apply AB clock pairs to unload SRLs



l Static Testing

CaptureEnd Scan inB

AB

X

Y

C1

YX

C1

L1 L2 L1 L2


Scan MethodsLSSD Single Latch Design

l Only L1 is used in normal operationl Very Expensivel Eliminate races

L1

L2

L1

L2

L1

L2

L1

L2

L1

L2

O/Ps

I/Ps

Scanout

CK4CK1

CK3

CK2

SI

Com

bina

tiona

llo

gic

Com

bina

tiona

llo

gic


Scan MethodsSRL with L2* Latch

l Additional clock and clocked data portl Significant reduction on silicon cost

DCK1

SICK3

L1

L2CK2


Scan MethodsSRL with L2* Latch

D = D1C = CK1

Q

Sin = D2A = CK2

D1CK1

D2CK2

Q

D1CK1

D2CK2

Q

DC

SinA

BD*C*

L1

L2


Scan MethodsSingle Latch Design with L2* Latch

L1

L2

L1

L2

Data inputSystem clock CK 1

Scan inputShiftclock CK 3

System/shiftclock CK2


Scan MethodsAdvantages of LSSD

l The correct operation of the logic network is independent of AC characteristics such as clock edge rise time and fall time

l Network is combinational in nature as far as test generation and testing is concerned

l The elimination of all hazards and races greatly simplifies both test generation and fault simulation


Scan LengthMultiple Test Session

l Test session§ Configuring scan paths and other logics§ Testing logic using scan test methodology

l Together Mode§ The entire circuit can be tested by 100 test patterns with length of

12§ 100 X 12 = 1200 clock cycles



l Separate Mode§ While C1 is being tested, C2, R3 and R4 are ignored § To test C1, 8 X 100 cycles are required § To test C2, 8 X 20 cycles are required § Total 960 clock cycles



l Overlapping Mode§ Initially, C1 and C2 can be combined and tested using 20 patterns

with length 12§ 12 X 20 cycles§ C2 is completely tested and C1 can be tested with remaining 80

patterns with length 8§ 8 X 80 cycles§ Total 880 clock cycles


Partial ScanScan Shift Reduction

l Target faults for each test vector§ If a test vector detects only a few faults, then a few FFs will be

required to be controlled or observed for the test vectorl Arrangement of FFs in the scan chain§ If FFs which are frequently required to be controlled (observed)

are located close to the scan input (output) line, a few scan shift operations are required

l Order of test vectors l Maximize the overlap between successive scan in

patterns


Partial ScanPartial Scan

l Full scan is not always feasiblel Retains many advantages of full scan and reduces the

costl Exclude certain flip-flops§ Fault coverage is a function of the number of scan FFs

l Main researches§ Flip-flop selection§ Test length reduction§ Retiming

l What do we lose in partial scan?§ Loss of fault coverage§ Difficult to automate in synthesis environments



l How to choose scan FFs and non-scan FFs?§ Testability Analysis§ Structural Analysis§ ATPG Based Analysis

l Used in conjunction with other schemes


Partial ScanATPG Based Analysis

l Begin with a fully scanned circuit and perform empirical evaluation for the removal of scan from each individual FF

l Select one or more FFs with lowest scan desirability and delete them from the scan point set

l Repeat the previous step until the phase change conditions are met

l Run the ATPG system and, if the desired fault coverage is not achieved, select and add scan FFs using the pruned fault set until the desired coverage is achieved or the upperbound on the number of scanned FFs allowed is reached

l Best results is obtained only when all test patterns for each fault are available


Partial ScanTestability Analysis

l Perform testability measure l Based on the results, select FFsl Continue the previous steps until upperbound on the

number of scanned FFs is selectedl Simple but low coverage



l SCOAP

§ CC0(Combinational 0 Controllability)

§ CC1(Combinational 1 Controllability)

§ CO(Combinational Observability)

§ SC0(Sequential 0 Controllability)

§ SC1(Sequential 1 Controllability)

§ SO(Sequential Observability)



l SCOAP

dab D Q

DFF

e

D QDFF

gfc G

AB

C

g

Node

abcdef

2

CC0

111222

5

CC1

111335

0

CO

444220

1

SC0

000010

2

SC1

000011

0

SO

222211


Partial ScanStructural Analysis

l Circuit

l Circuit Graph

l Partially Scanned Circuit

1 2

3

4 5 6

61

2

3

4 5

1 2

3

4 5 6

SCANIN SCANOUT

MODE



l Partial Scan Using I -Pathsl I-mode§ A module S with input port X and output port Y has an identity

mode (I-mode), denoted by IM( ) if S has a mode of operation in which the data on X is transferred to Y

§ Latches, registers, MUXs, busses, ALUs, etc.

l I-path§ An identity transfer path (I-path) exists from output port X of

module S1 to input port Y of module S2, denoted as IP( ), if data can be transferred unaltered, but possible delayed

§ Consists of a chain of modules, each of which has an I- mode



l I-mode example§ MUXÄIM(MUX: ) ; x = 0 ; t = 10ns ÄIM(MUX: ) ; x = 1 ; t = 10ns

§ ALUÄIM(ALU: ) ; x1x2 = 00 ; t = 20ns ÄIM(ALU: ) ; x1x2 = 01 ; B=0; Cin=0

§ RegisterÄIM(ALU: ) ; t = 1 clock cycle


Partial ScanTesting Using I-Paths

l Example § I-path exists from the output of the block C to input ports of R1,

R2 and R3§ I-path exists from output ports of R1, R2, R3 and R4 to input port

of C§ Assume that only one register can drive the bus at any one time

and a tristate driver is disabled when its control line is highl Test process of C § Time Controls Operation § t1-t32 Scan into R1 § t33 Contents of R1 are loaded onto the bus § Data on bus are loaded into R2 § t34 Test pattern is applied to C § Response from C is loaded into R3 § is loaded onto the bus § passes from bus through MUX § and is loaded into R1


Partial ScanTesting Using I-Paths

l Example


Partial ScanPartial Scan Using I-Paths

l Design Problems§ Identifying a subset of registers to be included in the scan path§ Scheduling the testing of logic blocks§ Determining efficient ways to activate the control lines when

testing a block of logic§ Determining ways of organizing the scan paths to minimize the

time required to test the logic



l I-mode§ Parallel-to-parallel § Parallel-to-serial§ Serial-to-parallel § Serial-to-serial

l Transfer-mode (T-mode)§ If an onto mapping exists between input port and output port of a

module§ T-path consists of a chain of modules having zero or more§ I-modes and at least one T-mode§ I-paths and T-paths are used for transmitting data from a scan

register to the input port of a block of logic to be tested§ ExampleÄArray of inverters that maps the input vector X into NOT(X)



l Sensitized-mode (S-mode)§ If a module has a mode of operation such that an error in the data

at input port produces an error in the data at output port§ S-path consists of a chain of modules having zero or more I-

modes and at least one S-mode§ I-paths and S-paths are used for transmitting response to a scan

register or primary outputs § ExampleÄSUM = A+BÄIf B is held at any constant value, an error in A produces an

error in SUM



l BALLAST


Partial ScanBALLAST

l Structured Partial Scan Designl A subset of storage cells is selected and made part of the

scan path so that the resulting circuit has a special balanced property

l Although the resulting circuit is sequential, only combinational ATPG is required and complete coverage if all detectable faults can be achieved

l Once a test pattern is shifted into the scan path, more than one normal system clock may be achieved before the test result is loaded into the scan path and subsequently shifted out


Partial ScanBALLAST

l Circuit Model§ Cloud : Maximal region of connected combinational logic§ A group of wires forms vacuous cloud if it connects the outputs of

one register directly to the inputs of anotherÄit represents primary inputs feeding the inputs of a registerÄit represents the outputs of a register that are primary outputs

§ Storage cells are clustered into registers as long as all storage cells share the same clock and controlÄC1, C2, C3 : Nonvacuous cloudsÄA1, A2, A3 : Vacuous clouds


Partial ScanBALLAST

l Balanced (B-structure)§ For any two clouds v1 and v2, all signal paths between v1 and v2

go through the same number of registers

l Nonbalanced Example§ Unequal paths between C1 and C3

§ Self loop (unequal paths between C and itself)


Partial ScanBALLAST

l Test procedure§ Given a B-structure SB, its combinational equivalent CB is the

combinational circuit formed from SB by replacing each storage cell in SB by a wire

§ Depth d of SB is the largest number of registers on any path between any two clouds

§ Let T = {t1, … tn} be a complete test set for all detectable stuck at faults in CB

l Each test pattern ti = {tia, tib } consists of two parts where tia is applied to PIs and tib is applied to PPIs


Partial ScanBALLAST

l Test procedure of SB§ Scan in the test pattern tib§ Apply tia to the primary inputs to S§ While holding tib at the PIs and tib in the scan path, clock the

registers in S, d times§ Place the scan path in its normal mode and clock it once

§ Observe the value on the POs

§ Simultaneously, scan out the results in the scan paths and scan in t(I+1)b


Partial ScanBALLAST

l To test SB § A pattern is shifted into the scan path R3 and R6 and held two

clock periods while a test pattern is also applied to the primary inputs A and B

§ After one clock period test results are captured in R1 and R2§ After the second clock period test results are captured in R4 and

R5§ Finally test results are captured in the scan path R3 and R6


Partial ScanBALLAST


Partial ScanBALLAST

l Any single stuck fault that is detectable in thecombinational logic in S is detectable by a test vector

l Some additional test may be required to detect shorts between the I/O of storage cells

l To select a minimal number of storage cells to be made part of scan path so that the resulting circuit is a balanced, is NP complete


Partial ScanBALLAST Example

l


Partial ScanBALLAST

l Nonbalanced circuits may require sequential ATPGl Example§ Consider the fault b s-a-1§ Fault b s-a-1 is redundant in combinational equivalent of the

circuit


Partial ScanScan Chain Correlation

l Unscanned flipflops are corrupted while test vectors are scanned in and while test outputs are scanned out


MUX

MODE

SCAN IN

SCAN OUT

PO’sPI’s n m

pp

qq



l Solution : Separate clock


MUX

MODE

SCAN IN

SCAN OUT

PO’sPI’s n m

pp

qq

C2C1



l Solution : Additional logic


MUX

MODE

SCAN IN

SCAN OUT

PO’sPI’s n m

pp

qq


Partial ScanCost Free Scan

l Use controllability of PIs to establish scan paths throughcombinational logic

l Analyzing the circuit to determine all the cost-free scanFFs

l Selecting the best input vector to establish the maximum number of cost-free scan FFs on the scan chain

l Example§ Free scan path is established when X1=0 and X2=1


Design RulesGeneral Scan Design Rules

l Disable asynchronous clears and presets during scan (Required)

l Most scan types require all asynchronous clears and presets for scan registers to be inactive in the scan mode, so that bits in the scan chain are not cleared as the scan chain is loaded

l Eliminate internal tristate contention during scan (Required)

l If internal busses do exist in the design, during scan mode the circuit can be put into a random state that may cause internal bus contention

l Prevent multiple driversl Disable all drivers with the scan enable signal l Add decoding logic to ensure that only one tristate enable

is turned on at any time



l Disable write signals for RAMs during scan (Required)l Important to preserve the content of the RAMs, as well as

FIFOs and register filesl Disable W EN to the RAM with the SCAN ENl Disable bidirectional output buffer during scan (Strongly

Recommended)l During the scan mode, registers along the scan chain will

be toggled frequently, thus turning on and off thebidirectional buffers, causing undesirable current spikes

l Avoid cross coupled NANDs or NORs (Strongly Recommended)

l Timing simulation(Strongly Recommended)l The shifting of data through the scan chain should be

thoroughly simulated to verify that there are no timing violations or internal bus contentions due to the scan operation



l No combinational Feedback Loops (Strongly Recommended)

l Use multiple scan chains (Recommended)§ Test time is related to the length of scan chain§ The scan enable pin can be shared§ Multiple chains of different lengths are allowed

l Scan chain loading using (Recommended)l When fanout problem in Ql Use lock-up latches (Recommended)§ Lock-up latches may be necessary between the scan out and scan

in of major blocks or when scan chains switches to a separate clock driver to avoid side effects of clock skew

l Make RAMs reasonably controllable (Recommended)l Fully synchronous Design (Recommended)l No gated or internally generated clocks


Design RulesFull Scan Design Rules

l One clock rule (Required)§ All flip-flops must have the same clock, or effectively the same

clock§ When some clocks are not directly controllable from the PIs, the

full scan circuit will have to be treated as a sequential circuit


Design RulesPartial Scan Design Rules

l Minimize destructive FFs (Strongly Recommended)§ Destructive : Flip-flops in scan chain can be reset or clocked

during scanl Example§ The mux-scan design uses the same clock for the scan flip-flops

as well as the non-scan flip-flops§ FF3 and FF4 become destructive



l Minimize destructive FFs (Strongly Recommended)§ Use load signal



l Minimize destructive FFs (Strongly Recommended)§ Gating clock



l Minimize destructive FFs (Strongly Recommended)§ Add a scan clock



l Partial scan can be selected by submodules or branches of a clock tree (Strongly Recommended)§ Put an entire branch of the clock tree in the scan chain and

multiplex that clock with a scan clock§ And leave flip-flops driven by another clock tree branch non-scan§ A higher degree of partial scan is required to achieve desired

testability


Design RulesMUX Scan Design Rules

l MUX scan chain

l Directly controllable clock for scan flip-flops (Required)l Internal clocks are not allowed to drive a scan flip-flop

unless it is multiplexed with a test clock during scan mode

l Avoid destructive flip-flops (Highly Recommended)


Design RulesDual-Phase Scan Clock Design

l Two-phased scan clock scan chain


Design RulesDual-Phase Scan Clock Design Rule

l Disable system clock for scan registers during scan mode (Required)§ Incorrect clock-disabling circuitry

l Keep internal clocks reasonably controllable (Highly Recommended)


Design RulesDual Port Scan Design

l Dual port scan chain


Design RulesDual Port Scan Design Rules

l Disable system clock for scan registers during scan mode (Required)§ Illegal scan chain connectionÄThe Q output of a scan flip-flop can trigger another scan flip-

flop, destroying the scan value at that flip-flopÄMake sure that the signals driving the normal clocks CK of the

scan flip-flops cannot toggle during the scan mode

l Keep internal clocks reasonably controllable (Highly Recommended)

scan testing - yonsei

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