scientific seminar on structure and architecture and

Technische Universität MünchenLehrstuhl für Schaltungsentwurf

Scientific Seminar on Structure and Architecture and

Application of Sensor Circuits

Topics for winterterm 2021/2022

LSE – Scientific Seminar on Structure, Architecture and Application of Sensor Circuits - Prof. Dr.-Ing. Ralf Brederlow 1


Registration and Grading

2LSE – Scientific Seminar on Structure, Architecture and Application of Sensor Circuits - Prof. Dr.-Ing. Ralf Brederlow

If you are interested in participating in the scientific seminar, please contact [email protected] the topics’ supervisors in advance via mail for the topics you are interested in. The topics are assigned by the respective supervisors only!

In case there is no topic available anymore you can still attend the kick-off meeting in case of people not showing up. Moreover, you can contact [email protected] to ask for additional topics in your research area of interest.

Grading:

✓Regular discussions (online/in presence) with the assigned supervisor about the progress of the work and the procedure

✓ Presentation of the results (15 min.) with subsequent discussion (5 min.) (50%)

✓Written elaboration of the results as a term paper in the form of a scientific paper in IEEE style (4 pages) (50%)

mailto:[email protected]



Timing and Deadlines (tbu)


When? What?

Kick-off 18.10.2021 (Monday)

16.45-18:15

Introduction & How to do a

literature research

Compulsory participation

Lecture 21.12.2021 (Tuesday)

15:00-16:30

How to prepare a scientific

presentation & article

Paper submission deadline 24.01.2022 (Monday)

until 23:00 PM

In Moodle and via email to

your supervisor

Presentations 25.01.2022 (Tuesday) &

26.01.2022 (Wednesday)

15:00-16:30


Topics Overview


Topic Supervisor Available

Packaging Technologies for Flexible Electrochemical Biosensors [email protected]

Large Data Handling of Sensor Arrays [email protected]

Non-Traditional Spike Encoding Techniques [email protected]

Physical Unclonable Functions (PUF) [email protected]

Hardware-Constrained Neural Network Architecture for Mixed-Signal

Accelerators

[email protected]

Metastability in Clock-Domain Crossings (CDCs) [email protected]

Parameter Variations and Nonidealities of Hall Sensors [email protected]

Highly Integrated MEMS Microphone for Hearing Aid Applications [email protected]

Low Power Matrix Multiplication Accelerators [email protected]











PACKAGING TECHNOLOGIES FOR FLEXIBLE

ELECTROCHEMICAL BIOSENSORS


Supervisor:

[email protected]

Focus:

• Flexible electronics/sensors

• Comparison of available packaging methods

for biosensors

• Outlook: Ideas for easy and cheap packaging

Background:• Biosensors detect and quantify biomarkers e.g.

in sweat, water or soil

• Challenge: Electronic part of the sensor read-

out must not be in contact with the fluid

• Easy, cheap and flexible packaging is needed

Figure 1. A packaged biosensor dipped in

test-liquid. Only the sensor part is in

contact with the fluid. [1]

Figure 2. Wearable sensors need to be

protected from sweat and other fluids. [2][1] Simple and Powerful encapsulation through Hybrid Packaging for Electrochemical Transducers, 2021, IEEE Xplore, DOI: 10.1109/SSI52265.2021.9466968

[2] Wearable flexible sensors – A brief overview, 2021, https://roboticsbiz.com/wearable-flexible-sensors-a-brief-overview/


https://roboticsbiz.com/wearable-flexible-sensors-a-brief-overview/


Large data handling of sensor arrays


Supervisor:

[email protected]

Tasks:

• Analyzing different data handling algorithms eg: polling, event-driven,

send on delta etc.

- Advantages/Disadvantages?

- Which is suitable for which applications?

• Finding better data transmission protocols in terms of power, bandwidth,

routability etc.

Background:

Artificial e-skin is made up of a large number of sensors. The data from

these sensors is transmitted to a central processing system for analysis in

order for the system to respond efficiently. The amount of data increases

with the number of sensors, which requires higher bandwidth and more

computation power.

In case of tactile sensing, the sensors are often stimulated only in certain

areas and for a short amount of time. Thus, it is better to extract and

transmit the meaningful information only, and filter the redundant data at

the sensor level itself.

Figure 2. Event-driven tactile skin. Sensory signals are only

forwarded when a tactile event is generated.*

Figure 1. Polling based data sampling.

*Cheng, Gordon, et al. "A comprehensive realization of robot skin: Sensors, sensing, control, and applications." Proceedings of the IEEE 107.10 (2019): 2034-2051.



Non-Traditional Spike-Encoding Techniques


Supervisor:

[email protected]

Tasks/Focus:

• Literature Research on different spike-encoding

techniques

• (Dis-)avantages of Rate-Codes vs. Temporal

Codes

• Comparison regarding information efficiency per

spike and therefore energy efficiency

Problem/Background:Spiking Neural Networks (SNN) are next generation

of neural networks and try to solve problems like

image recognition by emulating the human brain. The

brain transmits signals in so called spikes which are

binary events over time. Similar to well-known

Artificial Neural Networks (ANN) the spikes are often

encoded in their rates over time (spikes/second). This

is not very effective (slow) and also not biologically

plausible since the human brain encodes the

information also in the precise timing of the spikes.

Figure 2. Rate Codes vs. Temporal Codes [1] Radhakrishnan, Shiva Subbulakshmi, et al. "A biomimetic neural encoder for spiking neural network." Nature communications 12.1 (2021): 1-10.

[2] https://www.youtube.com/watch?v=zldal7b7sJ4

Figure 1. Information Processing in the human brain



Physical unclonable function (PUF)


Supervisor:

[email protected]

Tasks/Focus:

• What approaches are used to create PUFs

in standard CMOS processes?

• What are their advantadges/disadvantadges?

• Figure of merits to compare different concepts

Problem: Mobile and embedded devices

require to securely authenticate and be

authenticated by another party. (e.g. financial

transactions on a smartphone). Typically,

secret authentication keys are stored in

EEPROMs or SRAM cells. PUFs, however,

exploit physical IC characteristics to generate

a secret and reliable authentication key.

Figure 2. https://www.semanticscholar.org/paper/Design-of-

SRAM-PUF-with-improved-uniformity-and-Garg-

Kim/6851c6d0cec12f083d6002b06c337b1ac11cf02c/figure/1

Figure 1. https://www.kaspersky.de/blog/fingerprints-sensors-security/6785/

Figure 3. https://www.researchgate.net/figure/Physical-

Unclonable-Functions-Secure-Authentication-

Mechanism_fig1_319004864



Hardware-Constrained Neural Network

Architecture for Mixed-Signal Accelerators


Supervisor:

[email protected]

Tasks:1. Understand the hardware constraints and impact of

neural network architecture on them (e.g., required

memory space)

2. Investigate how the architecture of neural network

can enhance the accelerator design in circuit and

system level.

3. Create technical roadmap for existing solutions

Background:Mixed-signal neural network accelerator shows its excellent

computation/power efficiency that makes implementing small- to

middle-scale neural network on edge devices possible for inference

computation with only a tiny power consumption. Whether the

accelerator can work with best efficiency and achieve a best trade-

off between various hardware constraints (e.g., memory load, power

consumption, latency, accuracy…) is strongly affected by the

structure of the implemented neural network. Optimizing the neural

network architecture for certain hardware constraints can

significantly improve the efficiency of accelerators in fact.

Source Figure 2: Mixed Precision DNNs: All you need is a good parametrization, Stefan Uhlich et al , ICLR 2020

Figure 1. Training Neural Network for less latency

Figure 2. Loss Function to train memory-constraint mixed-precision model



Metastability in Clock-Domain

Crossings (CDCs)


Supervisor:

[email protected]

Focus:

• What is the reason for metastability in CDCs?

• What approaches exist to design CDC interfaces with a minimized or

non-existing possibility of metastability?

• Can metastability be avoided by clever circuit design of interfaces and

storage elements?

• Comparison of different approaches with respect to speed, area and

energy consumption.

Background:Modern System-on-Chips (SoCs) are often desigend as globally

asynchronous locally synchronous systems (GALS). Energy consumption is

reduced by avoiding global clocks driving large loads and throughput can

be increased by operating different components with different clock speeds.

The most critical component of GALS are the interfaces at CDCs, where

sampling data generated asynchronously or in other clock-domains can

cause metastability or increased delays in storage elements like Flip-Flops

or Muller C-Elements.

Figure 1. Metastability and multi-flop [1]

[1] Plassan. 2016: “Conclusively Verifying Clock-Domain Crossings in Very Large Hardware Designs

[2] Polzer, 2013: “Muller C-Element metastability Containment”

Figure 2. Muller C-Element [2]



Parameter Variations and Nonidealities

of Hall Sensors


Supervisor:

[email protected]

Tasks/Focus:• Investigating and characterization of Hall Sensors for extracting offsets in their performance and thus generating PUFs.

• Exploring various hall sensor design methodologies and techniques for offset mitigation and cancellation.

• Exploring use of Hall Sensors for PUF generation, if any.

• Exploring PUF generation circuit designs and techniques for other sensors and seeking possibilities to integrate them for Hall sensor PUFs.

Problem/Background:Although IC manufacturers and designer aim for consistent performance and behavior of their devices across all the operating conditions but dissimilarities

emerging from fabrication process causes the similar products to behave slightly different. Such anomalies in the behavior of the Hall sensors can be used to

extract unique digital fingerprint that may serve as unique identifier for each sensor. This can be regarded as physical unclonable function i.e. PUF.

Hall Plate with SPDT MOS switches

connected to the amplifier

Block diagram of signal conditioning circuit

with two Sample and Hold(S/H) circuits and a summing amplifierSwitched hall plate with two states,

CLK is used to switch between the states

Hall Sensor model

Exploring offset and PUF patterns

via Hall Senor characterization

Circuit design techniques for PUF generation in linear Hall Sensors Fabrication of Hall sensors for

PUF extractionSource figure: https://ieeexplore.ieee.org/document/585275


https://ieeexplore.ieee.org/document/585275


Low power Matrix Multiplication

accelerators


Sreenivas Jambunathan

[email protected]

Tasks/Focus:

• Understanding basic matrix multiplication

accelerator

• Power and Area analysis of different accelerator

configurations and approaches

• Influence of memory on power and bandwidth

Problem/Background:As Moore’s law slows down, and IoT applications

gain popularity, the need for low power specialized

hardware is rising. Matrix Multiplication is used in

many IoT end point applications, to accelerate

machine learning algorithms. It is computationally

intensive and requires special hardware and

approaches to achieve optimum performance and

power.

Figure 1. Matrix Multiplication accelerator with 16 Processing Elements (PEs)


Highly integrated MEMS Microphone for

Hearing Aid Application


Supervisor:

[email protected]

Focus:

• Piezo vs Cap MEMS Microphone

• Comparison of different MEMS microphones

and their AFE Amplifier

• Outlook: Advantages and Disadvantages of

different designs

Background:• MEMS Microphones can be used for hearing

aid application, is the interface between real

world and the Human

• Challenge is to have a high SNR

• Low power is needed due to battery

Figure 1. MEMS Microphone with AFE

Amplifier. [1]

Figure 2. Weared hearing aid.[1] https://www.electronicdesign.com/technologies/analog/article/21808368/vesper-introduces-digital-mems-microphone-with-integrated-adc


scientific seminar on structure and architecture and

Documents