scott christopher smith - ndsuscotsmit/smith_cv.pdf · reactivated ieee-hkn, ece’s honor society,...
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Scott Christopher Smith
CONTACT INFORMATION:
North Dakota State University
Department of Electrical and Computer Engineering room 101D
PO Box 6050
Fargo, ND 58108-6050
Phone: (701) 231-7394
Email: [email protected]
Webpage: http://www.ndsu.edu/pubweb/~scotsmit
WORK EXPERIENCE:
Professor of Electrical and Computer Engineering with Tenure (August 2013 – Present)
North Dakota State University, Department of Electrical and Computer Engineering
Taught Digital Design (ECE 275) – FS17
Taught Advanced Digital Design (ECE 475 / 773) – Sp18, Sp17, Sp16, Sp15
Taught Field Experience (ECE 496) – Sp18, FS17, Sp17, FS16, Sp16, FS15, Sp15, FS14, Sp14, FS13
Co-Taught Introduction to Electrical & Computer Engineering (ECE 111), as lead instructor – Sp15
Department Chair of Electrical and Computer Engineering (Summer 2013 – Spring 2017)
North Dakota State University, Department of Electrical and Computer Engineering
Managed 18 faculty, 5 staff, yearly department budget of $2.5M+, equipment inventory of $1.5M+, and 4 degree programs
Hired 7 new ECE faculty, 1 new full-time IT System Administrator, and 1 Visiting Assistant Professor, all of whom are doing well
Associate Professor of Electrical Engineering with Tenure (August 2007 – August 2013)
Adjunct Associate Professor of Computer Science & Computer Engineering (September 2008 – August 2013)
University of Arkansas, Department of Electrical Engineering and Department of Computer Science & Computer Engineering
Taught Advanced Digital Design (ELEG 4914 / ELEG 5914 / CSCE 4914) – Sp13, Sp12, Sp11, Sp10
Taught Digital Design (ELEG 2904 / CSCE 2114) – FS12, FS11, FS10, FS09
Taught Digital Design I (ELEG 2903 / CENG 2113) – FS08, FS07
Taught Digital Design II (ELEG 2913 / CENG 2123) – Sp09, Sp08
Interim Associate Department Head (September 2009 – August 2011)
University of Arkansas, Department of Electrical Engineering
In charge of the undergraduate curriculum, including ABET certification
Substantially revised undergraduate curriculum to provide students with more elective options
Changed how academic advisors were assigned to students to provide students with substantially better advising
Devised scheme to reduce faculty teaching load from 4 to 3 courses per year for research active faculty
Associate Professor of Computer Engineering with Tenure (promoted March 2007, to be effective September 2007)
Assistant Professor of Computer Engineering (August 2001 – August 2007)
University of Missouri – Rolla (Missouri University of Science & Technology), Department of Electrical & Computer Engineering
Taught Digital Logic (CpE 412) – FS06, FS05, FS04, FS03, FS02
Taught Digital System Modeling (CpE 318) – WS07, WS06, WS05, WS04, WS03, WS02
Taught Introduction to Computer Engineering (CpE 111) – FS06, FS05, FS01
Supervised Computer Engineering Lab I (CpE 112) – WS07, FS06
Graduate Research Assistant (August 1999 – May 2001)
University of Central Florida: NULL Convention Logic (NCL) Project, sponsored by Theseus Logic, Inc.
Developed formal methodologies for designing optimal NCL circuits and throughput optimal NCL systems
Adjunct Faculty for Computer Engineering (August 1999 – December 1999)
University of Central Florida, Department of Electrical & Computer Engineering
Taught High Performance Computer Architecture (EEL 5708) – FS99
Instructed over 50 students, including 16 students at 5 off campus locations through taped lectures (FEEDS)
Graduate Research Assistant (May 1999 – August 1999)
University of Central Florida: VMGOES Project, sponsored by U.S. Department of Defense
Tested neural network vehicle models using MODSAF
Performed statistical analysis of generated vehicle model data
Graduate Teaching Assistant (August 1998 – May 1999)
University of Central Florida, Department of Electrical & Computer Engineering
Taught Digital Circuits and Systems Lab (EEL 3342) – WS99, FS98
Taught Computer Systems Design Lab (EEL 4767) – WS99, FS98
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Graduate Teaching Assistant (January 1997 – December 1997)
University of Missouri – Columbia, Department of Electrical & Computer Engineering
Taught Experimental Electrical Engineering Lab (ECE 255) – FS97, WS97
Supervised Senior Capstone Design Lab (ECE 398/399) – FS97, WS97
Electrical / Computer Engineering Co-op (July 1996 – December 1996)
Motorola, Inc., Boynton Beach, Florida: Paging Products Group
Developed and coded InfoFLEX, which is used to broadcast and update information service messages to a large number of
subscribed pagers (i.e. information service messages are messages that are received by a large number of pagers, such as sport
scores, news, stock prices, etc.)
Electrical Engineering Intern (Summer 1996 and Summer 1995)
St. Louis City Water Division, St. Louis, Missouri
Worked on PLC design to convert the Chain of Rocks water treatment facility to a SCADA-controlled system
Assisted with the initial setup of a SCADA system to monitor water filters
Mapped and created an AutoCad drawing of the Chain of Rocks computer network
Engineering Intern (Summer 1994 and Summer 1993)
Horner & Shifrin, Inc., St. Louis, Missouri
Created a database for the Horner & Shifrin library
Surveyed properties and obtained lot information from City Hall
Downloaded survey data into AutoCad and created AutoCad drawings
MAJOR ACCOMPLISHMENTS AS ECE DEPARTMENT CHAIR AT NDSU: Increased Yearly New Research Funding by over 7X (> $1.5M (2015 and 2016) vs. $222K (2010 – 2013 average))
Increased Yearly ECE PhD Graduates by 10X (10 per year (2015 and 2016) vs. previous 10-year average of 1 per year)
Moved ECE from below expectations in teaching, research, and service in 2013 to the only CoE department above expectations in
all categories by 2015, and did so with a faculty approval rating above 4.0/5.0
Doubled ECE’s Female Faculty and Initiated Spousal Hires to Retain ECE’s 2 New Female Faculty
ECE Faculty Won NSF CAREER Award (2016; first in more than 10 years)
ECE Faculty Appointed as NSF Program Director (2016; first in over 20 years)
First Ever ECE Faculty Appointed as IEEE Distinguished Lecturer (2016) & ACM Distinguished Speaker (2015)
ECE Grad Students Received CoE TA of the Year Award (2016 and 2017) and RA of the Year Award (2016 and 2017)
ECE Faculty Received CoE Teacher of the Year Award (2015)
ECE Staff Received ND Governor’s Award for Excellence in Public Service (2016; only 6 awards for entire state)
ECE Student Selected as Graduation Commencement Speaker (May 2016)
Wrote First Dept. Newsletter in 6 Years, resulting in a $143,750 Gift to Support ECE Research (largest single ECE gift at that time)
Setup a $250K Department Endowment from a portion of an Unrestricted Gift (largest single ECE gift to date)
Significantly Revised BS EE and BS CpE Curricula (2014)
Worked with Physics Department to add a BS EE/Physics Double Major (2017; first NDSU double major to span colleges)
Transitioned ECE PhD Program from Coursework-Focused to Research-Focused (2014)
Completely Overhauled Course Schedule to Efficiently Utilize Lab Space & Provide Faculty with More Research Time (2014)
Reorganized and Repurposed ECE Labs for Increased Efficiency (2014 and 2016)
Advocated for and Received 1 New Teaching Lab and 3 Renovated Research Labs for the Department
Reactivated IEEE-HKN, ECE’s Honor Society, after 20+ Years of Inactivity (1st new group inducted December 2016, and received
Key Chapter Recognition and Outstanding Chapter Award for AY 16/17 from IEEE-HKN International Board of Governors)
Elected as Secretary/Treasurer (2014), Vice-President (2015), and President (2016) of the Central States ECE Department Heads
Association (AR, MO, KS, OK, IA, SD, ND, NB)
Enabled Secure Remote Access of ECE Computers for Students and Faculty (2016)
Received 6 Grants as PI or Co-PI, including 3 from NSF, for a Total of $1.15M
ACADEMIC EXPERIENCE:
Ph.D. Computer Engineering, August 1998 – May 2001 (4.0 GPA)
University of Central Florida
Area of emphasis: Computer Architecture and Digital Systems
Advisor: Ronald F. DeMara
Dissertation: Gate and Throughput Optimizations for NULL Convention Self-Timed Digital Circuits - consisted of developing:
1) a formal methodology for designing optimal NULL Convention Logic (NCL) asynchronous delay-insensitive digital circuits,
which allows for speed/area/power tradeoffs
2) a formal methodology for designing throughput optimal NCL systems
3) a technique for reducing the NULL cycle, thus increasing throughput
4) an NCL 72+3232 MAC, which outperformed other delay-insensitive/self-timed MACs in the literature
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M.S. Electrical Engineering, January 1997 – May 1998 (4.0 GPA)
University of Missouri – Columbia
Area of emphasis: Computers and Digital Systems
Advisor: Michael J. Devaney
Master’s Project: Fourier Based Three Phase Power Metering System - consisted of designing and building an FFT implementation
of a 3-phase power metering system, using a DSP integrated with a 68000 core processor and a communications co-processor
B.S. Electrical Engineering, B.S. Computer Engineering, and Minor in Mathematics, August 1992 – May 1996
University of Missouri – Columbia
Graduated Magna Cum Laude with a GPA of 3.732
Advisor: Robert McLaren
Senior Project: PLC Controlled Model Railroad
CERTIFICATION:
Passed the EIT (now called FE) Examination (1996)
AREAS OF EXPERTISE:
Computer Architecture, Embedded Systems, Digital Logic, FPGAs, Asynchronous Logic, NULL Convention Logic,
CAD Tools for Digital Design, Computer Arithmetic, VHDL, VLSI, Secure/Trustable Hardware, Wireless Sensor Networks,
Robotics, Cyber Physical Systems
GRANTS: Total: $4,420,474; Total as PI: $1,796,556 (41%); Total Share: $1,832,725 (41%) 1) S. Srinivasan (50%) and S. C. Smith (50%), “SHF: Small: GOALI: Formal Equivalence Checking for Quasi-Delay-Insensitive
Circuits,” NSF, CCF-1717420, $449,999, August 2017 – August 2020.
2) J. Wang (30%), N. Gong (30%), S. C. Smith (20%), and R. Kavasseri (20%), “Female Graduate Recruiting Enhancement in
Electrical and Computer Engineering,” NDSU Graduate Student Recruitment Award, $3,500, June 2016 – December 2016.
3) E. Christianson (50%) and S. C. Smith (50%), “Remote Student Access to ECE Software,” NDSU Technology Fee Award,
$20,243.50, March 2016 – December 2016.
4) D. Dawn (35%), S. C. Smith (25%), N. Gong (20%), and J. Wang (20%), “II-NEW: Probe Station to Characterize Body Area
Network Sensor ICs for Cyber Physical Systems Applications,” NSF, CNS-1628961, $362,865, August 2016 – July 2019.
5) S. C. Smith (60%), N. Gong (20%), and J. Glower (20%), “GARDE: Design Projects to Enable Veteran Reintegration in an
Educational System,” NSF, CBET-1401507, $85,005, June 2016 – July 2019.
6) S. U. Khan (40%), S. C. Smith (20%), N. Gong (20%), and J. Glower (20%), “GARDE: Design Projects to Enable Veteran
Reintegration in an Educational System,” NSF, CBET-1401507, $39,291, July 2014 – June 2016.
7) S. C. Smith, “New Faculty Start-Up,” ND EPSCoR, $187,000, August 2014 – August 2016.
8) M. Thornton (34% from SMU), B. Reese (33% from MSU), and S. C. Smith (33%), “SHF: Small: A Register Transfer Level
Toolset for Low Power Asynchronous Design Using Null Convention Logic,” NSF, CCF-1116405, $350,000, July 2011 – June
2014.
9) J. Di (50%) and S. C. Smith (50%), “Development of an Ultra-Low Power IC Design and Packaging to Provide a Variety of
Critical Anti-Tamper Safeguards,” Air Force SBIR Phase I subcontract through Space Photonics, Inc., $33,303, January 2011 –
September 2011.
10) J. Di (50%) and S. C. Smith (50%), “Low-Power Radiation-Hardened Delay-Insensitive Asynchronous Microcontroller
Technology Capable of Operating in Extreme Temperature Environments,” NASA SBIR Phase I subcontract through APEI, Inc.,
$33,303, January 2011 – June 2011.
11) J. Di (50%), S. C. Smith (40%), and H. A. Mantooth (10%), “Ultra-Low Power Delay-Insensitive Asynchronous Circuits,” SRC,
$294,000, March 2011 – February 2014.
12) S. C. Smith (50%) and J. Wu (50%), “REU Site: Summer Research Experiences in Wireless Sensor Networks - Design and
Applications,” NSF, EEC-1005106, $367,734, May 2010 – April 2014.
13) S. C. Smith, “Lunar Regolith Excavator Team Proposal,” NASA, $4,000, October 2010 – June 2011.
14) S. C. Smith (20%), Po-Hao Huang (20%), Uche Wejinya (20%), H. Alan Mantooth (20%), and Larry Roe (20%), “Lunar
Regolith Excavator Team Proposal,” NASA, $5,000, October 2009 – May 2010.
15) S. C. Smith (25%), J. Di (25%), J. Wu (25%), and H. A. Mantooth (25%), “GAANN: Asynchronous and Mixed-Signal IC
Design and CAD for Next Generation Ultra-Low Power Computing and Communication Systems for Medical, Mobile, and
Sensor Network Applications,” U.S. Department of Education, P200A090279, $514,512 ($102,903 UA matching), August 2009 –
August 2013.
16) J. Di (34%), S. C. Smith (33%), and H. Zhou (33%), “TC: Medium: Collaborative Research: Side-Channel-Proof Embedded
Processors with Integrated Multi-Layer Protection,” NSF, CNS-0904943 and CNS-0905223, $200,000, September 2009 – August
2011.
17) J. Wu (50%) and S. C. Smith (50%), “Development of Ultra-Low Power Smart Biomedical Sensors: an Integrated Software-
Hardware Approach,” Arkansas Biosciences Institute, $42,900, July 2009 – June 2010.
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18) J. Di (50%), S. C. Smith (40%), and J. P. Parkerson (10%), “SEU/SEL Resistant Ultra-Low Power Asynchronous Processor
Design for Low-Temperature Applications,” NASA SBIR Phase I through Space Photonics, Inc., CD75P-09UA, $33,317,
February 2009 – July 2009. 19) J. Di (50%), S. C. Smith (35%), and H. A. Mantooth (15%), “DIMLOG: Ultra-Low Power Delay-Insensitive Asynchronous
Circuits,” DARPA, W15P7T-08-C-V404, $306,982, October 2008 – March 2010.
20) S. C. Smith (25%) and B. Driskill (75%), “Automated Bit-Wise Completion for Asynchronous NULL Convention Digital
Circuits,” University of Arkansas Student Undergraduate Research Fellowship (SURF) grant, $3,900, January 2008 – October
2008.
21) S. C. Smith (50%), J. Di (25%), and W. K. Al-Assadi (25%), “Collaborative Research: Integrating Asynchronous Digital Design
into the Undergraduate Computer Engineering Curriculum throughout the Nation,” NSF CCLI Phase II, DUE-0717572 and DUE-
0717767, $499,999, August 2007 – July 2011.
22) G. K. Venayagamoorthy (65%), S. C. Smith (20%), and K. A. Corzine (15%), “GAANN: Advanced Computational Techniques
and Real-Time Simulation Studies for the Next Generation Energy Systems,” Department of Education, P200A070504, $360,000,
June 2007 – May 2010.
23) S. C. Smith (67%) and W. K. Al-Assadi (33%), “Integrating Asynchronous Digital Design and Testing into the Undergraduate
Computer Engineering Curriculum,” NSF CCLI Phase I, DUE-0536343, $94,789, February 2006 – July 2007.
24) K. Krishnamurthy (50%) and S. C. Smith (50%), “REU: Summer Research Experiences for Undergraduates in Micro
Mechatronic Systems,” NSF, EEC-0139117, $94,214, March 2006 – August 2007. 25) S. C. Smith, “Group Selection in a Senior/Graduate Level Digital Circuit Design Course,” University of Missouri New Faculty
Teaching Scholars, $686, April 2005 – September 2005.
26) S. C. Smith, “DSP Filtering for Wayside MUX,” Quackenbush Engineering Solutions & Technologies (QuEST), LLC, $6,800,
July 2004 – October 2004.
27) S. C. Smith, “Evaluation of a Dissolution Rate Monitor on Base-soluble Polymers,” Brewer Science, Inc., $3,731, September
2003 – December 2003.
28) S. C. Smith, “Development and Speedup of Self-Timed Digital Circuits,” University of Missouri Research Board, $23,400,
January 2002 – May 2003.
SCHOLARLY WORK:
Book / Book Chapters
1) S. C. Smith and J. Di, “The Future of Asynchronous Logic,” in VLSI: Circuits for Emerging Applications, CRC Press,
October 2014.
2) F. Parsan and S. C. Smith, “CMOS Implementation of Static Threshold Gates with Hysteresis,” in VLSI-SoC: From Algorithms to
Circuits and System-on-Chip Design, pp. 196 – 216, Springer Berlin Heidelberg, 2013.
3) J. Di and S. C. Smith, “Asynchronous Digital Circuits,” in Extreme Environment Electronics, pp. 663 – 673, CRC Press,
November 2012.
4) S. C. Smith and J. Di, “Designing Asynchronous Circuits using NULL Convention Logic (NCL),” Synthesis Lectures on Digital
Circuits and Systems, Morgan & Claypool Publishers, Vol. 4/1, July 2009 (7 chapters).
Refereed Journal Publications
1) S. M. Ali, M. Jawad, M. U. S. Khan, K. Bilal, J. Glower, S. C. Smith, S. U. Khan, K. Li, and A. Y. Zomaya, “An Ancillary
Services Model for Data Centers and Power Systems,” IEEE Transactions on Cloud Computing, accepted April 2017.
2) V. Wijayasekara, A. Rollie, R. Hodges, S. Srinivasan, and S. C. Smith, “Abstraction Techniques to Improve Scalability of
Equivalence Verification for NULL Convention Logic (NCL) Circuits,” IET Electronics Letters, Vol. 52/19, pp. 1594-1596,
September 2016.
3) F. Parsan, S. C. Smith, and W. K. Al-Assadi, “Design for Testability of Sleep Convention Logic,” IEEE Transactions on VLSI
Systems, Vol. 24/2, pp. 743-753, February 2016.
4) L. Zhou, S. C. Smith, and J. Di, “Radiation Hardened NULL Convention Logic Asynchronous Circuit Design,” Journal of Low
Power Electronics and Applications, Vol. 5/4, pp. 216-233, October 2015.
5) R. S. P. Nair, S. C. Smith, and J. Di, “Delay Insensitive Ternary CMOS Logic for Secure Hardware,” Journal of Low Power
Electronics and Applications, Vol. 5/3, pp. 183-215, September 2015.
6) L. Zhou, R. Parameswaran, F. Parsan, S. C. Smith, and J. Di, “Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-
Low Power Asynchronous Circuit Design Methodology,” Journal of Low Power Electronics and Applications, Vol. 5/2, pp. 81-
100, May 2015.
7) M. Linder, J. Di, and S. C. Smith, “Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead
Secure IC Design Methodology,” Journal of Low Power Electronics and Applications, Vol. 3/4, pp. 300-336, October 2013.
8) M. Hinds, B. Sparkman, J. Di, and S. C. Smith, “An Asynchronous Advanced Encryption Standard Core Design for Energy
Efficiency,” Journal of Low Power Electronics, Vol. 9/2, pp. 175-188, August 2013.
9) W. Cilio, M. Linder, C. Porter, J. Di, D. R. Thompson, and S. C. Smith, “Mitigating Power- and Timing-based Side-Channel
Attacks Using Dual-Spacer Dual-Rail Delay-Insensitive Asynchronous Logic,” Elsevier’s Microelectronics Journal, Vol. 4/3, pp.
258 – 269, March 2013.
10) F. Parsan, W. K. Al-Assadi, and S. C. Smith, “Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits,”
IEEE Transactions on VLSI, Vol. 22/1, pp. 99 – 112, December 2013.
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11) S. C. Smith, W. K. Al-Assadi, and J. Di, “Integrating Asynchronous Digital Design into the Computer Engineering Curriculum,”
IEEE Transactions on Education, Vol. 53/3, pp. 349 – 357, August 2010.
12) A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. C. Smith, “Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power,”
Journal of Low Power Electronics, Vol. 4/3, pp. 337-348, December 2008.
13) V. Satagopan, B. Bhaskaran, A. Singh, and S. C. Smith, “Energy Calculation and Estimation for Delay-Insensitive Digital
Circuits,” Elsevier’s Microelectronics Journal, Vol. 38/10-11, pp. 1095-1107, October/November 2007.
14) V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, “DFT Techniques and Automation for Asynchronous
NULL Conventional Logic Circuits,” IEEE Transactions on VLSI Systems: Special Issue on System on Chip Integration. Vol.
15/10, pp. 1155-1159, October 2007.
15) S. C. Smith, “Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits,” IEEE
Transactions on VLSI Systems, Vol. 15/6, pp. 672-683, June 2007.
16) G. K. Venayagamoorthy, S. C. Smith, and G. Singhal, “Particle Swarm-Based Optimal Partitioning Algorithm for Combinational
CMOS Circuits,” Elsevier’s Engineering Applications of Artificial Intelligence, Vol. 20/2, pp. 177-184, March 2007.
17) S. K. Bandapati and S. C. Smith, “Design and Characterization of NULL Convention Arithmetic Logic Units,” Elsevier’s
Microelectronic Engineering: Special Issue on VLSI Design and Test, Vol. 84/2, pp. 280-287, February 2007.
18) S. C. Smith, “Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction,” Elsevier’s Journal of Systems
Architecture, Vol. 52/7, pp. 411-422, July 2006.
19) S. C. Smith, “Development of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit,” Elsevier’s
Integration, the VLSI Journal, Vol. 39/1, pp. 12-28, September 2005.
20) S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, “Optimization of NULL Convention
Self-Timed Circuits,” Elsevier’s Integration, the VLSI Journal, Vol. 37/3, pp. 135-165, August 2004.
21) S. K. Bandapati, S. C. Smith, and M. Choi, “Design and Characterization of NULL Convention Self-Timed Multipliers,” IEEE
Design and Test of Computers: Special Issue on Clockless VLSI Design, Vol. 30/6, pp. 26-36, November-December 2003.
22) S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “NULL Convention Multiply and Accumulate Unit with
Conditional Rounding, Scaling, and Saturation,” Elsevier’s Journal of Systems Architecture, Vol. 47/12, pp. 977-998, June 2002.
23) S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Delay-Insensitive Gate-Level Pipelining,” Elsevier’s
Integration, the VLSI Journal, Vol. 30/2, pp. 103-131, October 2001.
Patents
1) Jia Di and Scott Christopher Smith, Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L) Circuit Design,
provisional U.S. patent received, currently under review by USPTO for full patent.
2) Scott Christopher Smith, Jia Di, Jerry Frenkil, Aaron Arthurs, and Ron Foster, Single Component Sleep-Convention Logic
(SCL) Modules, U.S. Patent: 9,094,013 B2, July 28, 2015.
3) Scott Christopher Smith and Jia Di, Multi-Threshold Sleep Convention Logic without nsleep, U.S. Patent: 9,083,337 B2,
July 14, 2015.
4) Jia Di and Scott Christopher Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, U.S. Patent: 8,664,977
B2, March 4, 2014.
5) Jia Di and Scott Christopher Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, U.S. Patent: 8,207,758
B2, June 26, 2012.
6) Jia Di and Scott Christopher Smith, Ultra-Low Power Multi-Threshold Asynchronous Circuit Design, U.S. Patent: 7,977,972
B2, July 12, 2011.
7) Robert Nathan Nelms and Scott Christopher Smith, Selective Call Message Formatting, U.S. Patent: 6,148,178 November 14,
2000; International Patent: WO9838609 September 3, 1998.
8) Frederick Loring Kampe, Scott Christopher Smith, Jheroen Pieter Dorenbosch, and Robert Nathan Nelms, Reliably Updating an
Information Service Message, U.S. Patent: 6,016,107 January 18, 2000; International Patent: WO9839930 September 11, 1998.
9) Robert Nathan Nelms, Marcus A. Gade, Michael J. DeLuca, Frederick Loring Kampe, and Scott Christopher Smith, Selective
Call Device and Method for Battery Saving During Information Services, U.S. Patent: 5,929,773 July 27, 1999; International
Patent: WO9838809 September 3, 1998.
10) Scott Christopher Smith, Frederick Loring Kampe, and Jheroen Pieter Dorenbosch, Insert/Delete Modification of Information
Service Message, International Patent: WO9913658 March 18, 1999.
11) Robert Nathan Nelms, Tom Klein, Scott Christopher Smith, and Frederick Loring Kampe, Performing Updates to Multiple
Information Service Topics Using a Single Command, International Patent: WO9839929 September 11, 1998.
Refereed Technical Conference Publications
1) P. Rogers, R. Kavasseri, and S. C. Smith, “An FPGA-in the Loop Approach for HDL Motor Controller Verification,” IEEE
International Conference on Reconfigurable Computing and FPGAs, pp. 1-6, December 2017.
2) A. A. Sakib, S. C. Smith, and S. K. Srinivasan, “Formal Modeling and Verification for Pre-Charge Half Buffer Gates and
Circuits,” IEEE International Midwest Symposium on Circuits and Systems, pp. 519-522, August 2017.
3) N. S. Balaneji and S. C. Smith, “Analysis and Design of CMOS Resettable C-Elements,” IEEE International Midwest
Symposium on Circuits and Systems, pp. 104-107, August 2017.
4) P. Rogers, R. Kavasseri, and S. C. Smith, “An FPGA-based Design for Joint Control and Monitoring of Permanent Magnet
Synchronous Motors,” IEEE International Conference on Reconfigurable Computing and FPGAs, pp. 1-6, November 2016.
5) V. Wijayasekara, S. K. Srinivasan, and S. C. Smith, “Equivalence Verification for NULL Convention Logic (NCL) Circuits,”
32nd IEEE International Conference on Computer Design (ICCD), pp. 195-201, October 2014.
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6) A. Bell, P. Rogers, C. Farnell, B. Sparkman, and S. C. Smith, “Wireless Patient Monitoring System,” IEEE Healthcare
Innovation and Point-of-Care Technologies Conference, pp. 149-152, October 2014.
7) F. Parsan, J. Zhao, and S. C. Smith, “SCL Design of a Pipelined 8051 ALU,” IEEE International Midwest Symposium on
Circuits and Systems, pp. 885-888, August 2014.
8) B. Sparkman, M. Hinds, J. Di, and S. C. Smith, “An Asynchronous AES Core Design for Energy Efficiency,” SRC TECHCON,
September 2013.
9) P. Palangpour and S. C. Smith, “Sleep Convention Logic Using Partially Slept Function Blocks,” IEEE International Midwest
Symposium on Circuits and Systems, pp. 17-20, August 2013.
10) P. Varadharajan, W. K. Al-Assadi, S. F. Alam, and S. C. Smith, “Quantum-dot Cellular Automaton of Asynchronous Null
Convention Logic Multiplier Design,” IEEE International Midwest Symposium on Circuits and Systems, pp. 813-816, August
2013.
11) J. Foulkes, P. Tucker, M. Caronan, R. Curtis, L. G. Parker, C. Farnell, B. Sparkman, G. Zhou, J. Wu, and S. C. Smith, “Livestock
Management System,” International Conference on Embedded Systems and Applications, pp. 3-9, July 2013.
12) B. A. Bell, A. L. Suchanek, D. Cartman, J. D. Stuckey, C. Farnell, B. Sparkman, G. Zhou, J. Wu, and S. C. Smith, “Unexploded
Ordnance Detection with Cooperative Mobile Robots,” International Conference on Embedded Systems and Applications, pp. 67-
73, July 2013.
13) R. Liederbach, A. Little, F. Xiao, C. Zlibut, G. Zhou, C. Farnell, B. Sparkman, J. Wu, and S. C. Smith, “Developing an Ultra-
Low Power Remote Infrastructure Monitoring System,” International Conference on Embedded Systems and Applications, pp.
48-54, July 2013.
14) Z. Song and S. C. Smith, “Implementation of a Fast Fourier Transform Processor in NULL Convention Logic,” International
Conference on Computer Design, pp. 10-16, July 2013.
15) P. Shepherd, S. C. Smith, J. Holmes, A. M. Francis, N. Chiolino, and H. A. Mantooth, “Robust, Wide-Temperature Data
Transmission System for Space Environments,” IEEE Aerospace Conference, pp. 1-13, March 2013.
16) F. Parsan and S. C. Smith, “CMOS Implementation of Static Threshold Gates with Hysteresis: A New Approach,” IFIP/IEEE
International Conference on VLSI-SoC, pp. 41-45, October 2012.
17) F. Parsan and S. C. Smith, “CMOS Implementation Comparison of NCL Gates,” IEEE International Midwest Symposium on
Circuits and Systems, pp. 394-397, August 2012.
18) L. Zhou and S. C. Smith, “Accurate Throughput Derivation of Pipelined NULL Convention Logic Asynchronous Circuits,”
International Conference on Computer Design, pp. 51-54, July 2012.
19) B. Sparkman and S. C. Smith, “Reducing Energy Usage of NULL Convention Logic Circuits using NULL Cycle Reduction
Combined with Supply Voltage Scaling,” International Conference on Computer Design, pp. 3-8, July 2012.
20) R. B. Reese, S. C. Smith, and M. A. Thornton, “Uncle – An RTL Approach to Asynchronous Design,” IEEE International
Symposium on Asynchronous Circuits and Systems, pp. 65-72, May 2012.
21) M. Linder, J. Di, and S. C. Smith “MTD3L – A Secure IC Design Methodology with Reduced Overhead,” International
Conference on Microelectronics, Nanoelectronics, Optoelectronics, April 2012.
22) L. Zhou, M. Huang, and S. C. Smith, “High-Performance and Area-Efficient Hardware Design for Radix-2k Montgomery
Multipliers,” International Conference on Computer Design, pp. 65-71, July 2011.
23) W. Collins, D. Sanchez, Z. Sharp, S. C. Smith, and J. Wu, “Developing a Remote Digital Wildlife Camera Triggered by Spatially
Deployed Infrared Sensors,” International Conference on Embedded Systems and Applications, pp. 21-28, July 2011.
24) P. Killeen, J. Monkus, E. Klessig, D. Hearn, J. Wu, and S. C. Smith, “Developing a Smart Home System,” International
Conference on Embedded Systems and Applications, pp. 148-152, July 2011.
25) L. Zhou and S. C. Smith, “Standby Power Reduction Techniques for Asynchronous Circuits with Indeterminate Standby States,”
International Conference on Computer Design, pp. 10-16, July 2011.
26) B. Hollosi, J. Di, S. C. Smith, and H. A. Mantooth, “Delay-Insensitive Asynchronous Circuits for Operating under Extreme
Temperatures,” Government Microcircuit Applications & Critical Technology Conference, pp. 407-410, March 2011.
27) L. Zhou and S. C. Smith, “Static Implementation of Quasi-Delay-Insensitive Pre-Charge Half-Buffers,” IEEE International
Midwest Symposium on Circuits and Systems, pp. 636-639, August 2010. (nominated for best student paper)
28) L. Zhou, S. C. Smith, and J. Di, “Bit-Wise MTNCL: An Ultra-Low Power Bit-Wise Pipelined Asynchronous Circuit Design
Methodology,” IEEE International Midwest Symposium on Circuits and Systems, pp. 217-220, August 2010.
29) S. Yancey and S. C. Smith, “A Differential Design for C-Elements and NCL Gates,” IEEE International Midwest Symposium on
Circuits and Systems, pp. 632-635, August 2010. (nominated for best student paper)
30) S. C. Smith, D. Roclin, and J. Di, “Delay-Insensitive Cell Matrix,” International Conference on Computer Design, pp. 67-73,
July 2010.
31) C. M. Smith and S. C. Smith, “Comparison of NULL Convention Booth2 Multipliers,” International Conference on Computer
Design, pp. 3-9, July 2010.
32) W. A. Cilio, M. J. Linder, C. Porter, J. Di, and S. C. Smith, “Side-Channel Attack Mitigation Using Dual-Spacer Dual-Rail
Delay-Insensitive Logic (D3L),” IEEE SoutheastCon, pp. 471-474, March 2010.
33) B. Hollosi, T. Zhang, R. S. P. Nair, Y. Xie, J. Di, and S. C. Smith, “Investigation and Comparison of Thermal Distribution in
Synchronous and Asynchronous 3D ICs,” IEEE International Conference on 3D System Integration, September 2009.
34) J. Wu and S. C. Smith, “Integrated Software-Hardware Design for Ultra-Low Power Infrastructure Monitoring,” International
IEEE Intelligent Transportation Systems Conference, pp. 375-382, October 2009.
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35) L. Zhou and S. C. Smith, “Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit,” IEEE
International Midwest Symposium on Circuits and Systems, pp. 499-502, August 2009.
36) R. S. P. Nair, S. C. Smith, and J. Di, “Delay-Insensitive Ternary Logic,” International Conference on Computer Design, pp. 3-9,
July 2009.
37) P. Palangpour, G. K. Venayagamoorthy, and S. C. Smith, “Particle Swarm Optimization: A Hardware Implementation,”
International Conference on Computer Design, pp. 134-139, July 2009.
38) A. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, “Ultra-Low Power Delay-Insensitive Circuit Design,” IEEE International
Midwest Symposium on Circuits and Systems, pp. 503-506, August 2008.
39) B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S. C. Smith, H. A. Mantooth, and M. Schupbach, “Delay-Insensitive Asynchronous
ALU for Cryogenic Temperature Environments,” IEEE International Midwest Symposium on Circuits and Systems, August 2008.
40) I. P. Dugganapally, W. K. Al-Assadi, V. Pillai, and S. C. Smith, “Design and Implementation of FPGA Configuration Logic
Block Using Asynchronous Semi-Static NCL Circuits,” IEEE Region 5 Technical Conference, April 2008.
41) I. P. Dugganapally, W. K. Al-Assadi, T. Tammina, and S. C. Smith, “Design and Implementation of FPGA Configuration Logic
Block Using Asynchronous Static NCL,” IEEE Region 5 Technical Conference, April 2008.
42) M. V. Joshi, S. Gosavi, V. Jagadeesan, A. Basu, S. Jaiswal, W. K. Al-Assadi, and S. C. Smith, “NCL Implementation of Dual-
Rail 2s Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives,” IEEE Region 5 Technical Conference, April
2007.
43) S. R. Mallepalli, S. Kakarla, S. Burugapalli, S. Beerla, S. Kotla, P. K. Sunkara, W. K. Al-Assadi, and S. C Smith,
“Implementation of Static and Semi-Static Versions of a Quad-Rail NCL 24+8×8 Multiply and Accumulate Unit,” IEEE Region 5
Technical Conference, April 2007.
44) R. S. P. Nair, F. Kacani, R. Bonam, S. M. Gandla, S. K. Chitneni, V. Kadiyala, W. K. Al-Assadi, and S. C. Smith,
“Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2s Complement Multiplier,” IEEE
Region 5 Technical Conference, April 2007.
45) S. C. Smith and J. Di, “Detecting Malicious Logic Through Structural Checking,” IEEE Region 5 Technical Conference, April
2007.
46) J. Di and S. C. Smith, “A Hardware Threat Modeling Concept for Trustable Integrated Circuits,” IEEE Region 5 Technical
Conference, April 2007.
47) S. C. Smith, “Design of a Logic Element for Implementing an Asynchronous FPGA,” 15th ACM/SIGDA International Symposium
on Field-Programmable Gate Arrays, pp. 13-22, February 2007.
48) V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, “Design for Test Techniques for Asynchronous
NULL Conventional Logic (NCL) Circuits,” International Joint Conference on Computer, Information, and Systems Sciences,
and Engineering, December, 2006.
49) V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, and S. C. Smith, “Automation in Design for Test for Asynchronous Null
Conventional Logic (NCL) Circuits,” 12th NASA Symposium on VLSI Design, paper 3.1, October, 2005.
50) B. Bhaskaran, V. Satagopan, and S. C. Smith, “High-Speed Energy Estimation for Delay-Insensitive Circuits,” International
Conference on Computer Design, pp. 35-41, June 2005.
51) A. Singh and S. C. Smith, “Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation,” International
Conference on Computer Design, pp. 115-121, June 2005.
52) B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, “Implementation of Design For Test for Asynchronous NCL
Designs,” International Conference on Computer Design, pp. 78-84, June 2005.
53) G. Singhal, G. K. Venayagamoorthy, and S. C. Smith, “An Optimal Partitioning Algorithm for Combinational CMOS Circuits
Using Particle Swarm Optimization,” 14th IEEE North Atlantic Test Workshop, pp. 87-92, May 2005.
54) S. C. Smith, “Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum
Throughput,” International Conference on VLSI, pp. 407-412, June 2004.
55) S. C. Smith, “Design of a NULL Convention Self-Timed Divider,” International Conference on VLSI, pp. 447-453, June 2004.
56) S. C. Smith, “Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy,”
International Conference on VLSI, pp. 143-149, June 2003.
57) S. K. Bandapati and S. C. Smith, “Design and Characterization of NULL Convention Arithmetic Logic Units,” International
Conference on VLSI, pp. 178-184, June 2003.
58) S. C. Smith, “Speedup of Self-Timed Digital Systems Using Early Completion,” IEEE Computer Society Annual Symposium on
VLSI, pp. 107-113, April 2002.
59) S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Speedup of Delay-Insensitive Digital Systems Using
NULL Cycle Reduction,” 10th International Workshop on Logic and Synthesis, pp. 185-189, June 2001.
60) S. C. Smith and M. J. Devaney, “Fourier Based Three Phase Power Metering System,” 17th IEEE Instrumentation and
Measurement Technology Conference, Vol. 1, pp. 30-35, May 2000.
Refereed Educational Conference Publications
1) C. P. Farnell, B. Sparkman, and S. C. Smith, “Design of a Motor Control Board for the NASA Lunabotics Mining Competition,”
ASEE Midwest Section Conference, September 2012.
2) J. T. Roark and S. C. Smith, “Demonstration of the Benefit of Asynchronous vs. Synchronous Circuits,” ASEE Midwest Section
Conference, September 2012.
3) S. C. Smith and J. Di, “Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum
Throughout the Nation,” NSF CCLI/ TUES PI Conference, January 2011.
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4) S. C. Smith, W. K. Al-Assadi, and J. Di, “Integrating Asynchronous Digital Design into the Undergraduate Computer
Engineering Curriculum Throughout the Nation,” NSF CCLI PI Conference, August 2008.
5) S. C. Smith and W. K. Al-Assadi, “Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer
Engineering Curriculum,” 6th ASEE Global Colloquium on Engineering Education, October 2007.
6) S. C. Smith and W. K. Al-Assadi, “Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer
Engineering Curriculum,” ASEE Annual Conference & Exposition, June 2007.
7) S. C. Smith and W. K. Al-Assadi, “Teaching Asynchronous Digital Design in the Undergraduate Computer Engineering
Curriculum,” IEEE Region 5 Technical Conference, April 2007.
8) S. C. Smith, “Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum,” ASEE
Midwest Section Annual Conference, September 2006.
9) S. C. Smith, “Group Selection in a Senior/Graduate Level Digital Circuit Design Course,” ASEE Midwest Section Annual
Conference, September 2005.
Industry Seminars
1) J. Di and S. C. Smith, “DIMLOG: Delay-Insensitive, Multi-Threshold Logic for Ultra-Low Power Processing,” Microchip
Technology, Inc., AZ, September 15, 2009, via telecon.
2) J. Di and S. C. Smith, “DIMLOG: Delay-Insensitive, Multi-Threshold Logic for Ultra-Low Power Processing,” Texas
Instruments, Dallas, TX, July 10, 2009.
3) S. C. Smith, “Asynchronous Circuits to the Rescue,” Altera Corporation, San Jose, CA, June 14, 2006.
Workshops/Tutorials
1) S. C. Smith and J. Di, “Asynchronous Circuits and NULL Convention Logic (NCL),” University of Arkansas, June 22-24, 2012,
for NSF CCLI Phase II grant, 7 participants from 4 universities.
2) S. C. Smith and J. Di, “Asynchronous Circuits and NULL Convention Logic (NCL),” University of Arkansas, July 8-10, 2011,
for NSF CCLI Phase II grant, 8 participants from 8 universities.
3) S. C. Smith, “Ultra-Low Power Asynchronous Digital Circuits,” Hawaii University International Conferences on Mathematics and
Engineering, June 2011.
4) S. C. Smith and R. Guha, “Developing Modular Curricula,” NSF CCLI/ TUES PI Conference, January 2011.
5) S. C. Smith and J. Di, “Introduction to Asynchronous Circuits and NULL Convention Logic (NCL),” IEEE Midwest Symposium
on Circuits and Systems, July 2010.
6) S. C. Smith, J. Di, and W. K. Al-Assadi “Asynchronous Circuits and NULL Convention Logic (NCL),” University of Arkansas,
August 14-16, 2009, for NSF CCLI Phase II grant, 10 participants from 8 universities.
7) S. C. Smith and J. Di, “Introduction to Asynchronous Circuits and NULL Convention Logic (NCL),” International Conference
on Microelectronic Systems Education, July 2009.
8) S. C. Smith, J. Di, and W. K. Al-Assadi “Asynchronous Circuits and NULL Convention Logic (NCL),” University of Arkansas,
August 1-3, 2008, for NSF CCLI Phase II grant, 9 participants from 8 universities.
9) S. C. Smith, W. K. Al-Assadi, and J. Di, “Introduction to Asynchronous Circuits and NULL Convention Logic (NCL),” World
Congress in Computer Science, Computer Engineering, and Applied Computing, July 2008.
10) S. C. Smith, W. K. Al-Assadi, and J. Di, “Introduction to Asynchronous Circuits and NULL Convention Logic,” IEEE Region 5
Technical Conference, April 2007.
Invited Speaker
1) S. C. Smith, “The Future of Asynchronous Logic,” CMOS Emerging Technologies Research Conference, May 2015.
2) S. C. Smith, “The Future of Asynchronous Logic,” Florida International University, March 2015.
3) S. C. Smith, “Advanced Technologies for Tomorrow’s Smart Cities,” Keynote Address for IEEE International Frontiers of
Information Technology Conference, December 2014.
4) S. C. Smith, “Ultra-Low Power Asynchronous Digital Circuits,” National University of Science & Technology, December 2014.
5) S. C. Smith, “Panel on Smart Cities,” IEEE International Frontiers of Information Technology Conference, December 2014.
6) S. C. Smith, “Ultra-Low Power Asynchronous Digital Circuits,” Texas A&M University, October 2011.
TEACHING:
Graduate-Level Courses
1) Digital Logic at University of Missouri – Rolla (FS06, FS05, FS04, FS03, FS02)
Computer Arithmetic Hardware, Design Tradeoffs, Algorithmic State Machines, Asynchronous Logic Design
2) High Performance Computer Architecture at University of Central Florida (FS99)
Main, Virtual, and Cache Memory, Pipelining, RISC, CISC, and Networking Architectures
Graduate-Level / Senior-Level Courses 1) Advanced Digital Design at NDSU (Sp18, Sp17, Sp16, Sp15) and at University of Arkansas (Sp13, Sp12, Sp11, Sp10)
Mealy and Moore and Algorithmic State Machine Design and Optimization, VHDL Implementation of FSMs,
Functions/Procedures, and Generic Structures, Advanced Computer Arithmetic, Asynchronous Logic Design
2) Digital System Modeling at University of Missouri – Rolla (WS07, WS06, WS05, WS04, WS03, WS02)
Digital System Design, Simulation, and Synthesis with VHDL using Mentor Graphics design tool suite
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Undergraduate-Level Courses 1) Field Experience at North Dakota State University (Sp18, FS17, Sp17, FS16, Sp16, FS15, Sp15, FS14, Sp14, FS13)
Paper and Presentation detailing student’s 6+ month ECE internship/co-op experience
2) Digital Design at NDSU (FS17) and at University of Arkansas (FS12, FS11, FS10, FS09)
Computer Arithmetic, Boolean Algebra, Combinational Logic Design, Digital Components, Mealy and Moore Machine
Design, and Introduction to VHDL
3) Co-Taught Introduction to Electrical & Computer Engineering as lead instructor (Sp15)
Introduces each of the main areas of ECE using hands-on robotics projects with the Parallax ActivityBot
4) Digital Design II at University of Arkansas (Sp09, Sp08)
Mealy and Moore Machine and Algorithmic State Machine Design, Optimization, and VHDL Implementation, Advanced
Computer Arithmetic, Introduction to Microcontroller Architecture, Asynchronous Logic Design
5) Digital Design I at University of Arkansas (FS08, FS07)
Computer Arithmetic, Boolean Algebra, Combinational Logic Design, Digital Components
6) Introduction to Computer Engineering at University of Missouri – Rolla (FS06, FS05, FS01)
Computer Arithmetic, Boolean Algebra, Combinational and Sequential Logic Design, Digital Components
7) Supervised Computer Engineering Lab I at University of Missouri – Rolla (WS07, FS06)
Digital Circuit Design using Mentor Graphics Schematic Capture Tool (DA), Hardware Implementation with SSI, MSI, and
FPGA Components, Digital Oscilloscope Usage
8) Digital Circuits and Systems Lab at University of Central Florida (WS99, FS98)
Digital Circuit Design using Electronics Workbench, Hardware Implementation with SSI and MSI Components
9) Computer Systems Design Lab at University of Central Florida (WS99, FS98)
Digital System Design using Motorola 68HC11 Microprocessor, including both Hardware and Software
10) Experimental Electrical Engineering Lab at University of Missouri – Columbia (FS97, WS97)
Oscilloscope, DMM, and Signal Generator Usage, Analog Circuit Analysis, Filter Design
11) Supervised Senior Capstone Design Lab at University of Missouri – Columbia (FS97, WS97)
Helped students solve both hardware and software problems with their Senior Design Projects
Ph.D. Dissertations Advised
1) Venkat Satagopan, “Automated Pipelining Optimization, Energy Estimation, and DFT Techniques for Asynchronous NULL
Convention Circuits using Industry-Standard CAD Tools,” University of Missouri – Rolla, May 2007.
2) Bonita Bhaskaran, “Automated Synthesis and NCR Optimization for Asynchronous NULL Convention Circuits using Industry-
Standard CAD Tools,” University of Missouri – Rolla, May 2007.
3) Liang Zhou, “Ultra-Low Power and Radiation Hardened Asynchronous Circuit Design,” University of Arkansas, May 2012.
4) Ravi Sankar Parameswaran Nair, “Delay-Insensitive Ternary Logic Utilizing CMOS and CNTFET,” University of Arkansas,
August 2012.
5) Parviz Palangpour, “CAD Tools for Synthesis of Sleep Convention Logic,” University of Arkansas, May 2013.
6) Farhad Parsan, “Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based
Architectures,” University of Arkansas, December 2014.
Current Ph.D. Students
1) Nauman Jalil – at North Dakota State University (co-advised with Dr. Roger Green)
2) Brett Sparkman – at University of Arkansas (co-advised with Dr. Jia Di)
3) Syed Ahmad – at North Dakota State University
4) Ashiq Sakib – at North Dakota State University (co-advised with Dr. Sudarshan Srinivasan)
Master’s Theses Advised 1) Satish Bandapati, “Design and Characterization of Asynchronous Delay-Insensitive Arithmetic Components Using NULL
Convention Logic,” University of Missouri – Rolla, May 2003.
2) Sareen Devireddy, “Schematic Capture Design & Power Calculation for NULL Convention Delay-Insensitive Digital Circuits
using Mentor Graphics Design Tool Suite,” University of Missouri – Rolla, June 2003.
3) Sasikanth Duggini, “Design Tools for NULL Convention Logic Circuits,” University of Missouri – Rolla, May 2004.
4) Hiten Dharavat, “Radiation Testing of COTS CMOS Chips Against Continuous Gamma Radiations,” University of Missouri –
Rolla, May 2004 (co-advised with Dr. Akira Tokuhiro in Nuclear Engineering).
5) Anshul Singh, “Using a VHDL Testbench for Transistor-Level Simulation and Power Calculation of NULL Convention
Asynchronous Digital Circuits,” University of Missouri – Rolla, December 2004.
6) Arun Balasubramanian, “An Asynchronous FPGA for NULL Convention Logic Circuits,” University of Missouri – Rolla,
January 2005.
7) Ibrahim Kubilay, “3D Modeling of String Motion,” University of Missouri – Rolla, May 2006.
8) Ravi Sankar Parameswaran Nair, “Delay-Insensitive Ternary Logic (DITL),” University of Missouri – Rolla, August 2007.
9) Samarsen Mallepalli, “Generic Algorithms and NULL Convention Logic Hardware Implementation for Unsigned and Signed
Quad-Rail Multiplication,” University of Missouri – Rolla, August 2007.
10) Zhen Song, “Implementation of Fast Fourier Transform Processor in NULL Convention Logic,” University of Arkansas,
May 2011.
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11) Jingyi Zhao, “Comparison of Various Pipelined and Non-Pipelined SCL 8051 ALUs,” University of Arkansas, August 2012.
12) Vijay Pillai, “CAD Tool Design for NCL and MTNCL Asynchronous Circuits,” University of Arkansas, May 2013.
13) Paul Rogers, “Dynamic Partial Reconfiguration as an Approach to Motor Control Design,” North Dakota State University,
May 2018 (successfully defended February 2018; co-advised with Dr. Rajesh Kavasseri)
Undergraduate Projects Advised 1) Sarah Rosenbaum, Jim Ballmann, Nick Hamilton, and Alexis Sietins, “Stealth Cam Communications,” Senior Design Project,
University of Missouri – Rolla, December 2005.
2) Robert Pangrazio, Eric Peters, and Brad Roberts, “Human Interface Device - MOKI,” Senior Design Project, University of
Missouri – Rolla, December 2005.
3) Jonathan Baldwin, Etenia Ponder, and Lindsay Waters, “Autonomous Stair-Climbing Wheelchair,” REU Project, University of
Missouri – Rolla, Summer 2006.
4) José Martí, Raj Mishra, and Katrina Stevens, “Developing a Fishing System for Tetraplegics,” REU Project, University of
Missouri – Rolla, Summer 2006.
5) Warren Brooks, Steven Ortiz, Adam Kuentzler, and Nicholas Grither, “Fishing System for Tetraplegics,” Senior Design Project,
University of Missouri – Rolla, December 2007.
6) Jessica Rutledge, “Biomagnetic Imaging with the Selective Minimum Norm Method,” REU Project, University of Arkansas,
Summer 2008 (co-advised with Dr. Magda El-Shenawee).
7) Chris Bridges and Faheem Ibrahim, “Dynamic Power Control and Optimization of Autonomous Stair-Climbing Wheelchair,”
Senior Design Project, University of Arkansas, December 2008.
8) Chris Farnell and Michael Helms, “Multistage Gauss Gun with Dual Axis Tracking,” Senior Design Project, University of
Arkansas, May 2010.
9) Brian Stalling, Jacob Williams, Justin Robertson, and Shannen Adcock, “Lunar Regolith Excavator Communications System,”
Senior Design Project, University of Arkansas, May 2010.
10) Son Ha, Nadia Smith, and Adeline Kamaha, “Lunar Regolith Excavator Control System,” Senior Design Project, University of
Arkansas, May 2010.
11) Zihao Gong, “Design Project to Showcase Advantages of Asynchronous vs. Synchronous Circuits,” Senior Honors Project,
August 2010.
12) William Collins, Daniel Sanchez, and Zachary Sharp, “Developing a Remote Digital Wildlife Camera Triggered by Spatially
Deployed Infrared Sensors,” REU Project, University of Arkansas, Summer 2010 (co-advised with Dr. Jingxian Wu).
13) Peter Killeen, John Monkus, Biz Klessig, and D. Hearn, “Smart Home Monitoring System,” REU Project, University of Arkansas,
Summer 2010 (co-advised with Dr. Jingxian Wu).
14) Matthew Bell and Tavis Clemmer, “Autonomous Stair-Climbing Wheelchair Improvements,” Senior Design Project, University of
Arkansas, December 2010.
15) Matthew Huffmaster, Brett Sparkman, Christina Smith, David Fryauf, Alex Arguelles, and Nicholas Chiolino, “NASA Lunabotics
Competition,” Senior Design Project (May 2011)
16) Biz Klessig, Hanna Jones, and Kurt Waldrup, “IEEE Robotics Competition,” Senior Design Project, May 2011.
17) Brett Sparkman, “Utilizing NULL Cycle Reduction for Decreasing Energy Usage,” Honors Research Project, May 2011.
18) Justin Roark, “Demonstrating the Advantages of Asynchronous Circuits using an 8051 Microcontroller,” Honors Research
Project, May 2011.
19) Matthew Huffmaster, “Porting the NCL NULL Cycle Reduction Tool from Mentor to Synopsys,” Independent Study Project,
May 2011.
20) Hanna Jones, “Porting the NCL Threshold Combinational Reduction Tool from Mentor to Synopsys,” Independent Study Project,
May 2011.
21) Alex Arguelles, “Porting the NCL Gate Level Pipelining Tool from Mentor to Synopsys,” Independent Study Project, May 2011.
22) John Amos, Arturo Chavez, Justen Dawson, and Trent Chudej, “Unexploded Ordnances (UXO) Detection with Cooperative and
Mobile Robots,” REU Project, University of Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).
23) Mario McGregor, Chris Briley, Theresa Akede, and Ashley Jackson, “Developing an Ultra-Low Power Remote Infrastructure
Monitoring System,” REU Project, University of Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).
24) Joe Post, Alyssa Baccus, and Dylan Underwood, “Developing a Remote Fish Monitoring System,” REU Project, University of
Arkansas, Summer 2011 (co-advised with Dr. Jingxian Wu).
25) John Monkus, Erik Baumgartner, and Ryan May, “NASA Lunabotics Competition,” Senior Design Project, May 2012.
26) Brent A. Bell, Andrew L. Suchanek, Dalesha Cartman, and James D. Stuckey, “Unexploded Ordnance Detection with
Cooperative and Mobile Robots,” REU Project, University of Arkansas, Summer 2012 (co-advised with Dr. Jingxian Wu).
27) Ross Liederbach, Ashley Little, Flora Xiao, and Cornel Zlibut, “Developing an Ultra-Low Power Remote Infrastructure
Monitoring System,” REU Project, University of Arkansas, Summer 2012 (co-advised with Dr. Jingxian Wu).
28) James Foulkes, Peter Tucker, Mariflor Caronan, Rebecca Curtis, and Leslie G. Parker, “Livestock Management System,” REU
Project, University of Arkansas, Summer 2012 (co-advised with Dr. Jingxian Wu).
29) Alexsis Bell and Paul Rogers, “Wireless Patient Monitoring System,” REU Project, University of Arkansas, Summer 2013.
30) Jawaan Davis, Mehari Ghebreyohanne, and Ahmed Suleiman, “Personal Audio Amplifier,” Senior Design Project, NDSU,
December 2014.
31) Jeremy Reller, Yili Zou, Peng Gao, and Tyler Keller, “IR Environmental Control Device,” Senior Design Project, NDSU,
December 2014.
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32) Paul Viland, Jerika Cleveland, and Jacob Lewis, “Full-Featured Head Movement Controlled Mouse,” Senior Design Project,
NDSU, May 2017.
Course Development 1) Introduction to Electrical and Computer Engineering (ECE 111) – at NDSU
Substantially revised to be a team taught course that introduces each of the main areas of ECE using hands-on robotics projects
with the Parallax ActivityBot, along with guest speakers from industry (2014)
2) Advanced Digital Design (ECE 475 / 773) – at NDSU
Revised laboratory portion of course developed at UA to utilize new Altera DE2-115 FPGA boards (2015)
3) Advanced Digital Design (ELEG 4914 / ELEG 5914 / CSCE 4914) – at UA
Developed course from scratch, which includes a lab with 6 new experiments, most of which consist of designing a complex
digital system, implementing it with VHDL, simulating it with ModelSim, and then synthesizing it to an FPGA to test in
hardware (2010)
4) Digital Design I Lab (ELEG 2903L / CENG 2113L) – at UA
Added two new experiments: Combinational Logic Implementation using MUXes and RCA Design (2007)
Revised entire lab to emphasize circuit design and utilize Altera DE2 FPGA Boards (2008)
Revised course content and lab to include Mealy/Moore machine design and optimization, which was previously taught in
Digital II (2009)
5) Digital Design II Lab (ELEG 2913L / CENG 2123L) – at UA
Revised entire lab to emphasize complex system design and utilize Altera DE2 FPGA Boards (2008)
6) Digital Design II (ELEG 2913 / CENG2123) – at UA
Integrated material on asynchronous circuit design, as part of an NSF Phase II CCLI grant (2008)
7) Computer Engineering Lab I (CpE 112) – at UMR
Added three new experiments requiring digital circuit implementation using SSI and MSI components; whereas before all
circuits were implemented using an FPGA (2002)
Developed a method for implementing digital circuits designed using Mentor Graphics schematic capture tool (DA) on Altera’s
DE2 FPGA board; and revised all laboratory experiments to be compatible with the new design flow and hardware (2006)
8) Digital System Modeling (CpE 318) – at UMR
Revised course to emphasize VHDL design for synthesis, which is necessary for circuit implementation as an ASIC or on an
FPGA (2002)
Integrated material on asynchronous circuit design and optimization, as part of an NSF CCLI grant (2006)
9) Digital Logic (CpE 412) – at UMR
Significantly expanded course material to include various implementations of computer arithmetic circuits and their design
tradeoffs, Algorithmic State Machines (ASMs) for designing complex digital systems, and approximately one month of
asynchronous circuit design and optimization topics; whereas before the majority of the material was a review of fundamental
digital logic topics (i.e. those from CpE111). These topics were condensed into approximately two weeks of review, so that
more interesting graduate-level topics could be studied (2002)
10) Introduction to VLSI (Cp E311) – at UMR
Integrated material on asynchronous circuit design, as part of an NSF CCLI grant, with assistance from Dr. Waleed Al-Assadi
(2006)
EQUIPMENT DONATIONS SOLICITED:
1) Helped broker donation of 6390LV/LGS Scanning Electron Microscope (SEM) from NDSCS, and got state electrical board to give
NDSU a waiver to connect the SEM to the power grid, since it doesn’t have a UL listing (2016)
2) 20 Altera DE2-115 FPGA boards for use in multiple ECE courses (for NDSU, 2014)
3) 40 Altera DE2 FPGA boards for use in multiple EE and CSCE courses (for UA, 2007)
ENTREPRENEURIAL ACTIVITIES:
1) Co-founder of Ozark Integrated Circuits, Inc., a fabless IC design company located in Fayetteville, AR, specializing in extreme
environment electronics (2011)
2) Co-founder of NanoWatt Design, Inc., a fabless IC design company located in Fayetteville, AR, specializing in ultra-low power
digital IC design (2011)
3) Co-founder of VisuaLogistic Technologies, Inc., located in Fayetteville, AR, specializing in embedded system design for traffic
safety applications (2013)
UNIVERSITY SERVICE:
ECE Department Activities (at North Dakota State University)
1) Member of ECE PTE Committee (Fall 2017 – present)
2) Solicited NDSU ECE alumni for increased support, and brokered a $143,750 gift to support the research efforts of 6 ECE
Assistant Professors (9/30/16)
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3) Initiated CpE curriculum revision to follow the IEEE/ACM suggested curriculum topics, such that it now contains more software
and less EE
4) Initiated EE curriculum revision to provide students with much more flexibility selecting electives, which allows for more
interdisciplinary studies
5) Initiated revision of the ECE PhD program to change the degree from coursework-focused to research-focused
6) Initiated revision of ECE 111, Introduction to Electrical and Computer Engineering, to introduce each of the main areas of ECE
using hands-on robotics projects with the Parallax ActivityBot, along with guest speakers from industry
7) In conjunction with the faculty, changed the way raises are calculated in the department to a purely productivity-based formula
that rewards faculty based on their percent contribution to each category, which provides our most productive faculty with much
larger raises, in order to better incentivize increased production and help retain our most productive faculty
8) Hired 4 new tenure-track faculty in 2014, 2 new tenure-track and 1 non-tenure-track faculty in 2016, and 1 new tenure-track
faculty in 2017, which included 2 spousal hires to help retain our only 2 female faculty
9) Led the effort to get approval for and hire a much needed full-time IT staff dedicated to ECE who reports directly to me
10) Reorganized and repurposed ECE labs in order to provide much needed research space to newer faculty and group graduate
students and faculty by research area
11) Redistributed teaching load so that faculty teach 3 – 7 courses per year determined by research productivity
12) Reviewed and co-wrote many proposals with a multitude of ECE faculty to help them be more successful
13) Nominated a number of faculty, staff, and students for teaching, research, and service awards, with good success
14) Worked with Physics on a new double major program for Fall 2017, BSEE with a Second Major in Physics, which is the only
double major at NDSU to span colleges
15) Performed annual reviews for 15 – 18 faculty and 5 staff
16) Initiated major change to our ABET Assessment Approach to require less faculty time and provide more meaningful data
17) Wrote yearly Program Assessment Report
18) Led the vast majority of the multitude of new and transfer student orientation advising sessions
19) Conducted exit interviews with ECE graduating seniors every semester
20) Participated in Commencement Ceremony every semester
College of Engineering Activities (at North Dakota State University)
1) ECE Representative on College of Engineering Promotion Tenure and Evaluation Committee (Fall 2017 – present)
2) Chair of Interdisciplinary Cluster Hire Biomedical Engineering Faculty Search Committee (Fall 2017 – present)
3) Chair of Industrial & Manufacturing Engineering Department Chair Search Committee (2015 – 2016)
4) Worked with architects on CoE Master Plan and Ehly/Architecture renovation (2014 – 2015)
5) Worked with architects on STEM building planning, focusing on Electronic Instrumentation Lab (2013 – 2015)
6) Assisted Liberty Middle School students with robotics projects for Computer Science Week’s “Hour of Code” (12/8/15)
North Dakota State University Activities 1) Worked with NDSU RCA and John Deere on a Master Research Agreement, which was signed in 2015
2) Travelled to Pakistan to broker an MOA with the National University of Science & Technology (NUST), where they send fully
funded MS faculty to NDSU to pursue their PhD degree, after which they must teach at NUST for the following 6 years (2014)
3) Internal reviewer to select which MRI proposals go forward to NSF (2014)
4) Worked with the Library to get them to purchase the entire IEEE Digital Library, which is absolutely necessary to write
competitive proposals and perform cutting-edge research in ECE and CS (2014)
EE Department Activities (at University of Arkansas)
1) Organized and supervised tour of H.E. Williams facility (2013)
2) Member of Communications Faculty Search Committee (2011 – 2012)
3) Assisted with EE FEP recruiting demos and presentation (2011, 2012)
4) Interim Associate Department Head (Fall 2009 – Fall 2011)
5) Chair of Graduate Recruiting Committee (2009)
6) Chair of EE Seminar Series Committee (2009, Summer 2011 – Summer 2013)
7) Chair of Undergraduate Program Committee (2009 – 2011)
8) Chair of Communications/DSP Faculty Search Committee (2007 – 2008)
9) Member of General Faculty Search Committee (2007 – 2008)
10) Member of Undergraduate Recruiting Committee (2007 – 2013)
11) Member of Graduate Program Committee (2008 – 2013)
12) Member of Undergraduate Program Committee (2008 – 2009)
13) Member of EE Seminar Series Committee (2008 – 2009)
14) Junior Faculty Mentor for Jingxian Wu (2008 – present)
15) Demonstrated Stair-Climbing Wheelchair for 2 Freshman Engineering Program EE Recruiting Sessions (2008)
16) Demonstrated Stair-Climbing Wheelchair for high school students on University Day (2008)
17) Demonstrated Digital Circuits for University Day and 2 EE FEP Recruiting Sessions (2009, 2010)
18) Discussed EE undergrad research with ECAP students and participated in mock interview panel (Fall 2009)
19) Presented EE demos at Tyson Middle School (Fall 2009, 2010)
20) Presented EE demos at Holt Middle School (Spring and Fall 2010, Spring 2011, Spring 2012)
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21) Assisted with EE Summer Engineering Program (2010)
22) Supervised UA team participating in annual Lunabotics Mining Competition at Kennedy Space Center (2010-2012)
College of Engineering Activities (at University of Arkansas)
1) Member of Technology Committee (2008 – 2012)
2) Member of Academic Program Committee (2009 – 2012)
3) Assisted middle school teachers develop hands-on experiments teaching energy transformations, focusing on
electrical ↔ mechanical, during University of Arkansas’s Middle School Teachers Workshop (7/22–7/23, 2009)
Freshman Engineering Activities (at University of Arkansas)
1) Advised 6 FEP Honors Students’ Research (2012/2013)
2) Interviewed by FEP Students for Freshman Engineering Honors Colloquium course (2009, 2011)
3) Participated on Freshman Engineering Honors Colloquium Panel (2009)
4) Judge for Freshman Engineering Honors Research Symposium (2009)
5) Prepared Year End EE Freshman Engineering Project (2009)
6) Judge for Freshman of the Year Competition (2010, 2011)
University of Arkansas Activities 1) Member of Computing Activities Council (2012 – 2013)
2) Interviewed Prospective Freshman for Honors College Fellowships (2010, 2011)
3) Judge for University of Arkansas Graduate Student Research Symposium Poster Contest (2009)
ECE Department Activities (at University of Missouri – Rolla)
1) Mentor Graphics Liaison (2002 – 2007)
Supervised installation of updated digital design tool suite every 2-3 years (work closely with UMR IT)
Supervised Mentor Graphics TA to help solve tool problems
Prepared yearly Mentor Graphics license renewal report
2) Library Liaison (2003 – 2007)
3) Integrated Circuit and Logic Design (ICLD) Area Coordinator for the ECE Ph.D. Qualifying Exam (2005 – 2007)
4) CpE Ph.D. Qualifying Exam Revision Committee (2004)
5) CpE ABET Accreditation Committee (2001 – 2002)
6) CpE Undergraduate Studies Committee (2001 – 2007)
7) MTI (Missouri Transportation Institute) Liaison (2005 – 2007)
8) TA Evaluator (2004 – 2007)
Evaluated 11 potential ECE TAs as part of UMR’s GTA Workshop
9) Recruitment
Gave numerous departmental tours to prospective ECE students and parents (2002 – 2007)
Organized students for and participated in photo shoot for CpE brochure (2004)
Represented CpE at the Rolla High School Career Fair (2004)
Gave ECE department tour for UMR’s President’s Day open house (2003)
Gave ECE department tour for UMR’s Miner Days open house (2003)
Presented for CpE at the “Careers in Engineering and Technology” program in Springfield (2002)
Supervised ECE department exhibit for Engineers’ Week at the St. Louis Science Center (2002)
10) CpE Transfer Student Advisor (2004 – 2007)
11) Faculty Associate for UMR’s LEAD program for CpE111 (2005 – 2006)
12) Proctored FE Examination (2002)
Freshman Engineering Activities (at University of Missouri – Rolla)
1) Freshman Engineering Advisor (2001 – 2003)
2) Preview, Registration, and Orientation (PRO) Program Advisor (2002 – 2007)
Advised and registered approximately 200 new Freshman Engineering students
3) Mentored 2 groups of new freshman each year as part of UMR’s Opening Week program (2004, 2005, 2006)
4) Participated in making a video on “Classroom Respect” for UMR’s Opening Week program (2006)
University of Missouri System Activities
1) Reviewer for University of Missouri Research Board Proposals (2003, 2004, 2005, 2007)
2) Reviewer for University of Missouri New Faculty Teaching Scholars Proposals (2006)
PROFESSIONAL SERVICE:
Professional Organization Activities
1) President for the Central States ECE Department Heads Association (March 2016 – March 2017)
2) Vice President for the Central States ECE Department Heads Association (March 2015 – March 2016)
3) Secretary and Treasurer for the Central States ECE Department Heads Association (March 2014 – March 2015)
4) Co-Faculty Advisor for NDSU IEEE-HKN Chapter (2016 – present)
5) Faculty Advisor for the University of Arkansas Student Section of the IEEE (2008 – 2013)
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6) Secretary of the St. Louis Section of the IEEE (2007)
7) Secretary of the St. Louis Chapter of the IEEE Computational Intelligence Society (2005 – 2007)
8) President of the Rolla Subsection of the St. Louis Section of the IEEE (2004)
9) Vice-President of the Rolla Subsection of the St. Louis Section of the IEEE (2003)
10) Secretary and Treasurer of the Rolla Subsection of the St. Louis Section of the IEEE (2002)
Reviewing Activities
1) Reviewer for IEEE International Midwest Symposium on Circuits and Systems (2009, 2013, 2017, 2018)
2) Reviewer for ASEE/DoD SMART Scholarships (2016, 2017, 2018)
3) Reviewer for International Journal of Electronics and Communications (2018)
4) P&T Reviewer for University of Minnesota Duluth (2017)
5) Reviewer for IET Circuits, Devices & Systems (2017)
6) Reviewer for Journal of Low Power Electronics and Applications (2014, 2016, 2017)
7) Reviewer for IEEE Transactions on Circuits and Systems I (2016, 2017)
8) External Reviewer for PhD Dissertation: “Test and Testability of Asynchronous Circuits,” UNSW Canberra, Australia (2017)
9) Reviewer for IEEE Transactions on Device and Materials Reliability (2016)
10) Reviewer for Jordanian Journal of Computers and Information Technology (2016)
11) Reviewer for IEEE Transactions on Circuits and Systems II (2015)
12) Reviewer for IEEE International Symposium on Circuits and Systems (2015)
13) Reviewer for International Conference on Computing and Network Communications (2015)
14) Reviewer for Symposium on Emerging Topics in Computing and Communications (2015)
15) P&T Reviewer for South Dakota School of Mines & Technology (2014)
16) Reviewer for IEEE CloudNet (2014)
17) Reviewer for Architectural Science Review (2014)
18) P&T Reviewer for Indiana University – Purdue University Fort Wayne (2014)
19) Reviewer for IEEE Transactions on Computers (2013)
20) Reviewer for IEEE Transactions on Information Forensics & Security (2013)
21) Reviewer for IEEE Transactions on Education (2007, 2011, 2012, 2013)
22) Reviewer for Arabian Journal for Science and Engineering (2013)
23) Reviewer for International Conference on Advances in Electrical Engineering (2013)
24) Reviewer for ASEE North Midwest Section Annual Conference (2013)
25) Reviewer for NSF MRI proposal (2012)
26) Reviewer for Morgan Kaufmann book proposal “Digital Circuits with VHDL” (2012)
27) Reviewer for Portuguese Foundation for Science and Technology proposal (2012)
28) Reviewer for Current Engineering and Technological Research journal (2012)
29) Reviewer for Springer’s Journal of Supercomputing (2012)
30) Reviewer for NSF CCLI Phase 1 proposals (2010)
31) Reviewer for IEEE Instrumentation & Measurement Magazine (2010)
32) Reviewer for Israeli Science Foundation proposal (2010)
33) P&T Reviewer for University of South Alabama (2010)
34) Reviewer for Proceedings of the IEEE (2009)
35) P&T Reviewer for Southern Illinois University Carbondale (2009)
36) P&T Reviewer for University of Texas at San Antonio (2009)
37) Reviewer for IEEE International Intelligent Transportation Systems Conference (2009)
38) Reviewer for European Conference on Circuit Theory and Design (2009)
39) Reviewer for International Conference on Information Systems & Software Engineering (2009)
40) Reviewer for Journal of Electronic Testing: Theory and Applications (2008)
41) Reviewer for IEEE Transactions on Instrumentation & Measurement (2007, 2008)
42) Reviewer for IEEE International Computer Software and Applications Conference (2007, 2008)
43) Reviewer for IEEE Transactions on VLSI Systems (2005, 2006, 2007)
44) Reviewer for International Conference on Microelectronic Systems Education (2005, 2007, 2009)
45) Reviewer for NSF CCLI Phase 2 proposals (2006)
46) Reviewer for IEE Proceeding on Computers & Digital Techniques (2006, 2007)
47) Reviewer for Journal of Low Power Electronics (2006)
48) Reviewer for IEEE Industrial Applications Society Meeting (2005, 2006)
49) Reviewer for IEEE Region 5 Technical Conference (2006, 2007)
50) Judge for IEEE Region 5 Student Papers Contest (2006, 2007, 2008, 2009, 2011)
51) Reviewer for Elsevier’s Integration, the VLSI Journal (2004, 2006)
52) Reviewer for ASEE Midwest Section Annual Conference (2005)
53) Reviewer for 2nd International Workshop on Frontiers for Information Technology (2004)
54) Reviewer for IEEE Design & Test special issue on Clockless VLSI Design (2003)
55) Reviewer for International Joint Conference on Neural Networks (2003)
56) Reviewer for “Fundamentals of Digital Logic with VHDL Design,” by Brown and Vranesic (2001)
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57) Reviewer for ASEE Conference (2000)
Conference/Journal Organization Activities
1) Guest Editor for Journal of Low Power Electronics and Applications Special Issue on Low-Power Asynchronous Circuits (2015)
2) Program Committee Member for 2016 ECEDHA Annual Conference (2015-2016)
3) Member of Technical Program Committee for IEEE CloudNet (2014, 2015, 2016)
4) Publicity Co-Chair for IEEE International Frontiers of Information Technology Conference (2015)
5) Publicity Co-Chair for 2016 IEEE International Electro-Information Technology Conference (2015-2016)
6) Session Co-Chair for IEEE International Frontiers of Information Technology Conference (2014)
7) Organized Special Session on “Intelligent Structural Health and Safety Monitoring,” along with J. Wu and S. Sedigh, for IEEE
International Intelligent Transportation Systems Conference (2009)
8) Member of Program Committee for IEEE International Intelligent Transportation Systems Conference (2009)
9) Member of Technical Program Committee for International Conference on Information Systems & Software Engineering (2009)
10) Session Chair for IEEE International Midwest Symposium on Circuits and Systems (2013)
11) Session Chair for International Conference on Computer Design (2009, 2010, 2011, 2012)
12) Member of Program Committee for International Conference on Microelectronic Systems Education (2005, 2007)
13) Session Chair for IEEE Region 5 Technical Conference (2007)
14) Session Moderator for ASEE Midwest Section Annual Conference (2005)
15) Session Chair for International Conference on VLSI (2003, 2004)
16) Session Chair for International Conference on Embedded Systems and Applications (2003, 2011, 2013)
17) Session Chair for IEEE Computer Society Symposium on VLSI (2002)
PROFESSIONAL SOCIETY MEMBERSHIP:
Central States Electrical & Computer Engineering Department Heads Association (CSECEDHA)
President (March 2016 – March 2017)
Vice President (March 2015 – March 2016)
Secretary and Treasurer (March 2014 – March 2015)
Institute of Electrical and Electronics Engineers (IEEE)
Elected Senior Member (2006)
Faculty Advisor for the University of Arkansas Student Section of the IEEE (2008 – 2013)
Secretary of the St. Louis Section of the IEEE (2007)
President of the Rolla Subsection of the St. Louis Section of the IEEE (2004)
Vice-President of the Rolla Subsection of the St. Louis Section of the IEEE (2003)
Secretary and Treasurer of the Rolla Subsection of the St. Louis Section of the IEEE (2002)
IEEE – Eta Kappa Nu (IEEE-HKN): Electrical and Computer Engineering Honor Society
Co-Faculty Advisor for NDSU Section (2016 – present)
IEEE Computer Society
IEEE Computational Intelligence Society
Secretary of the St. Louis Chapter of the IEEE Computational Intelligence Society (2005 – 2007)
American Society for Engineering Education (ASEE)
National Academy of Inventors
Sigma Xi: Scientific and Engineering Research Honor Society
Tau Beta Pi: Engineering Honor Society
Golden Key National Honor Society
PROFESSIONAL DEVELOPMENT:
1) Participated in CASE Development for Deans and Academic Leaders Training (2016)
2) Participated in NDSU Leadership Seminars (2015)
3) Participated in NDSU Leadership Workshop (March 2014)
4) Attended NDSU’s Pedagogical Luncheons (August 2013 – present)
5) Attended University of Arkansas’s Teaching Camp (August 2011)
6) Participated in University of Arkansas’s Not-So-New Faculty Luncheon & Discussion Program (2009 – present)
7) Participated in University of Arkansas’s RSO Advisor Development Series (2010 – present)
8) Participated in University of Arkansas’s Baum Teaching Workshop (8/21/08)
9) Participated in University of Arkansas’s New Faculty Luncheon & Discussion Program (2007 – 2009)
10) Attended seminar on “Conducting Research on Teaching and Learning in Engineering and the Sciences” (3/11/05)
11) Successfully completed the University of Missouri – Rolla Grant Writing Workshop (2004)
12) Successfully completed the University of Missouri New Faculty Teaching Scholars Program (2003)
Included three workshops on course design, effective teaching, and academic portfolio development
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13) Successfully completed the NSF-sponsored Engineering Education Scholars Workshop (July 27-30, 2002)
Covered effective teaching techniques and grant writing
Participants were first year faculty and final year Ph.D. students
I was 1 of 32 selected to participate out of over 70 applicants
14) Participated in UMR’s New Faculty Forum Program (2001 – 2002)
HONORS & AWARDS:
1) Inducted into the National Academy of Inventors (2013)
2) University of Arkansas Outstanding Mentor Award (2012)
3) Nominated for IEEE Region 5 Outstanding Engineering Educator Award (2011)
4) Nominated for UA Outstanding Faculty Advisor Award (2011)
5) William D. and Margaret A. Brown Outstanding Electrical Engineering Faculty Award, $3,500 cash prize (2010)
6) Nominated for the Dr. John and Mrs. Lois Imhoff Award for Outstanding Teaching and Student Mentorship (2010)
7) Elected IEEE Senior Member (2006)
8) Appeared in Marquis Who’s Who in Science and Engineering, 8th Edition (2005/2006)
9) Received Recognition of Teaching Excellence from UMR Committee for Effective Teaching and Faculty Awards (AY 2002/2003)