sct: an approach for testing and configuring nanoscale devices

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Page 1: SCT: An Approach For Testing and Configuring Nanoscale Devices

SCT: An Approach For Testing and Configuring Nanoscale DevicesReza M.P. Rad and Mohammad Tehranipoor

Department of CSEE

University of Maryland Baltimore County

reza2,tehrani @umbc.edu

ABSTRACT

Molecular electronics-based devices are assumed to includeat least 1010 gate-equivalents/cm2 and defect densities as highas 10%; novel test strategies are necessary to efficiently testand diagnose these nanoscale devices. Configuration time, testtime and defect map size are among the major challenges forthese new devices. In this paper, we propose a new approachthat simultaneously configures and tests nano devices. A newbuilt-in self-test (BIST) scheme for testing and defect toleranceof nanoscale devices is proposed. The proposed procedure isbased on testing reconfigurable nanoblocks at the time of imple-menting a function of a desired application on that block. Thissimultaneous configuration and test (SCT) procedure consider-ably reduces the test and configuration time. It also eliminatesthe need for storing the location of the defects in the defect mapon/off-chip. The presented probabilistic analyses results showthe effectiveness of this process in terms of test and configura-tion time for architectures with rich interconnect resources.

I. INTRODUCTION

Emerging technologies in developing nanoscale devicesshow horizons of a new era in digital circuit design. Thesetechnologies are becoming mature enough to implement de-vices with switching or transistor properties in few nanometerdimensions. Different molecules with switching and rectify-ing properties can provide diode-logic circuits [1]. Many ofthese molecular switches are programmable and can save theirstate of connection or disconnection, hence it is possible to cre-ate configurable circuits using these switches. Carbon nano-tubes (NTs) are synthesized with few nanometers in diameterand micrometers in length [2]. Also nanowires (NWs) with di-ameters as small as 3 nanometer and lengths of few hundredmicrometers are reported in [3] and [4]. Several experimentsto arrange nanowires in array structures are reported in [5] and[6]. Directed self-assembly and self-alignment techniques aremainly used to create these structures. Nano-Imprint lithog-raphy [7] is progressing to enable us with more precise de-signs and more flexibility in designing non-regular structuresin nanoscale regime.

Different architectures are suggested in literature based onavailable nanoscale device and assembly technologies. Gold-stein et. al. in [8] suggested an array architecture for nanoscalecircuits. This design is an island-style architecture in whichclusters are interconnected in an array structure. The islandstyle architecture provides rich interconnect between clustersthat improves flexibility of the fabric. DeHon and Wilson in [9]presented a detailed PLA-based FPGA architecture and used

a technique, called modulated doping of nanowires, to cre-ate an interface for accessing nanowires through CMOS wires.Strukov and Likharev in [10] suggested a new cell-based archi-tecture and an interface scheme using special metal pins im-plemented on surface of substrate to provide the contacts withnanowires laying on the substrate.

Testability, defect tolerance, efficient access mechanismfrom CMOS support circuits to easily provide configurationand input/output signals, and also rich interconnect are the mainchallenges in design and test of nanoscale devices. Because ofthe high defect densities (up to 10%) in assembly and devicetechnology, approximately all fabricated circuits using thesetechnologies will have a handful of defects. Therefore, it is nec-essary that these circuits must be highly testable and an efficientdefect tolerance scheme must be designed within them. The re-configurability which is usually inherited to these circuits fromtheir basic components, i.e. reconfigurable molecular switches,can provide a static fault tolerance for these devices. It has beenshown in Teramac custom computer that reconfigurable archi-tectures can tolerate high defect densities [11].

As commonly proposed in literature, a defect detection pro-cess must be performed and location of all defects in the devicemust be detected and stored as a defect map and in configura-tion phase, defective components should be avoided [12][13].Several techniques have been proposed to extract the locationof faulty blocks in nanoscale architectures [14][15][22].

There are several difficulties with these approaches in dealingwith the high defect densities of nanoscale devices. Locating alldefects in a reconfigurable architecture with high defect densityis a very challenging and time consuming task, especially indevices with high densities like nanoscale circuits. Even if ef-fective methods could be found to determine the exact locationof all defects in such architectures, storing all these informa-tion will need very large memories. Note that we cannot usethe on-chip nanoscale resources as memory to store the defectmap since they are unreliable. On the other hand, using on-chipCMOS scale memory for defect map will result in considerablearea overhead. Therefore, it will not be practical to store thislarge defect map on-chip. It will not also be practical to shipthe defect map of each chip along with it to the customer.

One possible solution is that customer’s programming toolbe able to perform both configuration and test. That meansthe tool should first apply the tests and extract the defect map,then configure the device for a specific application. Implement-ing an on-chip BIST circuit or using an on-chip microproces-sor will significantly speed up this process but it will still bea very time consuming process to find the location of all de-fects in a chip with extremely large number of blocks. This

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Page 2: SCT: An Approach For Testing and Configuring Nanoscale Devices

process should probably be repeated every time a chip is recon-figured because of the existence of aging defects in nanoscaledevices and also due to very high memory requirements forstoring the defect map for all chips (different chips will havedifferent defect maps). As above discussion shows, manufac-turing test of nanoscale devices will face challenges in terms ofcreating, shipping and storing the defect map.

Application-dependent testing of nanodevices can be consid-ered as another possible solution. However, there are funda-mental differences between using these techniques for FPGAs[16] and for nano devices because the defect rate of nano de-vices is significantly higher than that of CMOS FPGAs. Inapplication-dependent testing of FPGAs, an application is firstcompletely configured on the FPGA and then it is tested. How-ever, due to high defect densities in nanoscale devices, it is notpossible to implement the application completely and then ap-ply the test, because the probability of having a fault-free con-figured application in this case will be very low.

One of the approaches suggested for FPGA BIST [18] is toconfigure a number of blocks of a FPGA as test pattern genera-tors (TPGs) and some other blocks as response analyzers (RAs).The remaining configurable blocks can be selected as block un-der test (BUT) to receive the test patterns from TPGs and sendthe outputs to RAs. The BUT should be configured with a setof appropriate circuits and each time TPGs should provide testsfor that specific function implemented on BUT and test it [18].

A. Contribution and Paper Organization

In this paper we propose a technique that simultaneouslyconfigures and tests a nano device. The application is first di-vided into smaller functions fi, where fi f1 f2 fT , im-plementable on nanoblocks. Then the function fi is configuredin a nanoblock and is tested using a BIST procedure. If con-figured fi is fault-free, then the technique configures anotherblock with function f j. If it is faulty, fi will be configured intoanother block and tested. The proposed approach is very effi-cient in terms of the overall time to configure and test the circuitand also tolerating defects. Also the requirement of storing thedefect map on/off-chip is eliminated because there will be noneed to find the exact location of defects. In this technique, ablock may be defective while the function fi configured into itwill operate without fault. This method is architecture indepen-dent and can be applied to all nanoscale architectures with highdefect rate conditions having rich interconnect resources.

Section II presents our proposed SCT technique. In Sec-tion III, interconnect requirements of the proposed method arebriefly discussed. Section IV presents a probabilistic analysis tocalculate average amount of time required to configure and testa circuit on a nanoscale architecture using the proposed method.The results of time analysis are compared with the approxima-tions made for a previously proposed test method [22]. Thepaper ends with conclusions in Section V.

II. SIMULTANEOUS CONFIGURATION AND TEST (SCT)METHOD

As mentioned above, locating all defects inside a nano de-vice with very high density (1010 gate-equivalents/cm2) andhigh defect density (up to 10%) will become a challenging and

time consuming task. In this paper a method is proposed fortesting and configuring circuits that can be used to avoid thetime consuming process of locating all defects. We assumethat the architecture have rich interconnect resources and isable to provide efficient access to its logic blocks through itsinput/output interfaces. Such architectures are presented in lit-erature [9][13][17].

The proposed method, in this paper, is conceptually similarto those proposed for FPGAs [18], but we consider TPG andRA to be components of BIST circuit and to be implementedin CMOS scale to provide tests and analyze the responses. De-tailed architecture of the proposed BIST circuit for testing con-figured blocks is described in this section and interconnect test-ing issues will be discussed in next section. The main differencebetween our method and the FPGA BIST method suggested in[18] is that in our method the goal of testing is not to confirmthe correct functionality of a BUT for all functions. Here, thegoal is to make sure that each function ( fi) of an applicationconfigured into a block is working correctly. So, the test pat-terns should be applied for testing that function only.

In SCT method instead of testing all resources of a recon-figurable architecture to locate all the defects in it, each blockof the architecture can be tested for the specific function of acircuit, i.e. fi, after fi is configured into a block of the device.The applied test here just checks the correct functionality of theconfigured function ( fi), rather than diagnosing all defects ofthe block. So, there might be defects in molecular switches ornanowires of the block but as long as those defects do not causeany malfunctioning the function fi is identified as fault-free. Inother words, creating the function fi on a block b j requires justa subset of all nanowires and switches of that block. So, if thedefective components of the block are not used during config-uring fi into that block, then the function can operate withoutfault. Therefore, the defects of the block are tolerated.

In SCT procedure, the application is divided into m-inputfunctions and each time one of these functions ( fi) should beconfigured into a block of the device and the input and outputlines from the BIST circuit to fi must be configured. Also, thesame function fi should be configured into the LUT of the BISTcircuit (see Figure 1). Next, the BIST circuit can simply applyexhaustive set of test patterns (2m) to the function and test itsfunctionality. If the implemented function passes the test, thenit can be reliably used in the circuit. The process of selecting afunction, mapping it to a block of the device and creating con-nections between that function and the BIST circuit and testingthe function will be repeated for all functions of the applica-tion. If a function fails the test then we should configure anotherblock with that function and the test process should be repeated.

Note that methods and tools for configuring nanoscale recon-figurable architectures will be similar to those used for FPGAs[19] but some modifications may be required due to architec-tural differences.

Figure 1 shows the proposed BIST scheme. The BIST circuitis composed of an m-bit counter, an m-input LUT and a com-parator, resulting in low BIST area overhead. BIST circuit isassumed to be implemented in reliable CMOS scale.

Figure 2 shows the SCT procedure. In this procedure, a func-tion fi of the desired application is selected (line #10) from the

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Page 3: SCT: An Approach For Testing and Configuring Nanoscale Devices

Function under test:

Nanoscale architecture with rich interconnect resources

m-input LUTimplementsan ideal copy of the function under test

m-bitcounter

m-bit

1-bit

1-bit comparator

CMOS scale BIST

Pass/Fail

circuit

fi

fi Block b j

Clk

BIST_LUT

fi( )

Fig. 1. The proposed CMOS BIST circuit used to test nano devices.

01: Define:02: Set of available blocks: B= b1 , b2, .., bM ;03: Set of functions of the application: F= f1 , f2 , .., fT ;04: Set of (defective block, # of defects) :05: DB= b1 n1 , b2 n2 , .., bx nx ;06: Set of discarded blocks: DiB ;07: # iterations a block should be detected as08: defective before it is discarded: Discard Threshold ;

09: while (F )10: Choose ( fi from F) ; F = F - fi ;

Config (BIST LUT with fi);11: if (B )12: while (B )13: Choose (b j from B); B = B - b j ;14: Config (b j with fi) ; ConfigRoutes (b j to BIST);15: if (BIST ( fi,b j) = fail )16: DB = DB + (b j ,1) ;17: else Break ;18:19: else if (B )20: while (DB )21: Choose ((bk,nk) from DB) ;22: Config (bk with fi) ; ConfigRoutes (bk to BIST);23: if ( BIST ( fi,bk)=fail )24: increment (nk) ;25: if (nk Discard Threshold)26: DB = DB - (bk,nk) ; DiB = DiB + bk ;27:28: else Break ;29:30: if (B and DB )31: Application is not implementable on the device.32:

Fig. 2. The SCT procedure.

list of functions (F) and configured on the LUT of the BIST cir-cuit (BIST LUT, line #10). If there are available blocks in theblock list (B), one of them, e.g. b j, will be selected and removedfrom the list of available blocks (line #13). Then function fi willbe mapped into this block (b j) and the wires between this blockand BIST circuit are configured (line #14). If the test fails (line#15), the block will be sent to the set of defective blocks, i.e.DB (line #16). This will be repeated until either all functionsare configured into the blocks of the device (F ) and theprocedure is successfully finished or there are still some func-tions of the application left unmapped and the set of availableblocks (B) becomes empty. In this case all the blocks of thedevice have been tried once, either they have been successfullyused to implement one of the functions or they have shown de-fective behavior and were sent to the set of defective blocks

Functions under test

CMOS-scale BIST circuits

BIST 1

BIST 2

BIST N/2

BIST N/2 +1

BIST N/2 +2

BIST N

Fig. 3. Parallel use of multiple BIST circuits for testing nano devices.

(DB). If a block shows faulty behavior for one function, it doesnot mean that it will necessarily be faulty for every function be-cause different functions will use different subsets of switchesand nanowires of a block. Therefore, if there are some func-tions of the application left, defective blocks of the device canbe tried (line #21). However, if a block is tried for a numberof different functions and for all of them showed a faulty be-havior, i.e. nk Discard T hreshold (where nk is the numberof times block bk was used to implement a function and the re-sult was faulty), then the block should be discarded and sent todiscarded block list, i.e. DiB (line #26). After trying all the de-fective blocks of the device if still there are some functions ofthe application left, then the application is identified to be notimplementable on the device.

As seen in the figure, two selections should be made duringthese steps. First, one of the functions of the circuit should beselected from the set of all functions, i.e. F (line #10). Then, anappropriate block of the device should be selected and config-ured with the selected function (line #13 or #21). Block selec-tion is a decision that programming device should make basedon the available blocks in the architecture, communications be-tween the function being implemented ( fi) and other functionsof the application and timing requirements of the circuit.

Low area overhead of this BIST structure provides the op-portunity of parallel implementation of these testers on the chipso that at any time more than one function can be implementedand tested on the device as shown in Figure 3. When multi-ple BIST circuits are implemented, test time will be reduced.In this case, more than one function and more than one blockof the device should be selected at any time. Proper methodsbased on heuristics can be used for these selections.

The interconnections between functions of the circuit alsoneed to be configured and tested. This will be further discussedin the next section.

III. INTERCONNECTS AND THEIR TEST PROCESS

A. CMOS Scale Interconnects

To complete the configuration of the application, intercon-nections between the functions should be configured and tested.The SCT procedure explained earlier does not consider testingthe interconnections between the functions. It uses interconnect

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Page 4: SCT: An Approach For Testing and Configuring Nanoscale Devices

resources of the device to provide an access for BIST to sendtest patterns and receive test responses to and from a function.

If the interconnects of the nano architecture are fabricated inCMOS scale, the problem of testing them can be removed (dueto their reliability) or a CMOS test strategy such as those pro-posed in [20] can be used to ensure the fault-free status of theinterconnects. In case of detecting a fault on CMOS wires, wecan discard the chip and this will not be very costly because ofthe low defect density of CMOS technology. Since the inter-connects are assumed to be in CMOS scale and defect-free, theconnections between functions of the circuit can be made afterthe SCT procedure to complete the configuration of the circuit.

CMOS interconnections in nanoscale architectures are usedin the architectures proposed in [10], [17] and [21]. The relia-bility and low defect density of CMOS wires provides consid-erable simplicity in test and configuration process of nanoscalearchitectures. Such nanoscale architectures will not be as areaefficient as those architectures with nanowires used as inter-connects. As discussed in [10], [17] and [21], the accessibil-ity, testability and configurability provided by reliable CMOSscale interconnects are necessary for nanoscale architectures tobe practical.

The SCT procedure proposed in previous section and alsotime analyses presented in the next section are based on theassumption of a nanoscale architecture with CMOS intercon-nections between the blocks.

B. Nanoscale Interconnects

If the interconnect system used in the nanoscale architectureis based on nanowires, then it has high defect rates. One possi-ble solution to make the results of the SCT procedure efficientin this situation is to perform a pre-processing step to test theinterconnects. In this pre-processing step, interconnects of thearchitecture must be tested and fault-free connections shouldbe determined. Since the structure of nanoscale architecturesis predicted to be very regular, testing the interconnects can beaccomplished in a reasonable amount of time and the resultscan be passed to the programming device to be used during theconfiguration and test process described earlier.

Another suggestion is that, when an implemented functionon a block of a device fails during the test process, there isa possibility of fault both in the function and in the intercon-nects used for communication between the function and theBIST circuit. The programming tool should decide whether tochange the block which was used for implementing the functionor just change the interconnects used between the function andthe BIST circuit and test the same block again (using the newinterconnects). This decision should be made based on the con-figuration time requirements and defect probability of blocksand interconnects. Based on these, appropriate heuristic meth-ods can be developed to find a fault-free implementation of thefunction in an optimum amount of time. Also, methods needto be proposed to test nanoscale interconnects created betweenthe functions. When compared to using CMOS scale intercon-nects, the SCT procedure will require more time in case of usingnanoscale interconnects.

min0 min1 min2 min2-1m

X1

X2

LUT

X1

Xm

X2

Out

Xm

...

...

Fig. 4. Implementation of an m-input function on a 2m 1 2m crossbarconfigured as a lookup table. Function F x1 x2 xm ∑ Minterms 0 2 4is implemented as an example.

IV. ANALYSIS OF THE SCT METHOD

Since no nanodevice is available to perform any real imple-mentation, in this section, a probabilistic analysis is presentedto show the timing requirements of the proposed process. Wefirst calculate the probability of occurring a fault in a function ficonfigured into a block of the device. Based on this probabilitywe calculate the average number of blocks that must be config-ured to finally find a fault-free implementation for the function.Hence, we can calculate the required number of clock cyclesfor configuring and testing function fi. Finally, for an appli-cation with T functions ( f1, f2, ..., fT the average number ofclock cycles required to configure and test all functions can becalculated. The results are compared with the number of cyclesrequired to apply the BIST method presented in [22].

To keep the analysis simple, CMOS scale interconnects areassumed for the architecture. We target an application that canbe partitioned into T small functions each with m inputs, i.e.functions f1, f2, , fT . As Figure 4 shows, an m-inputfunction can be implemented on a 2m 1 2m crossbar ofnanowires configured as an m-input lookup table (LUT). Notethat since diode logic cannot provide signal inversion, comple-ment of the m input signals should either be applied to the blockor created inside the block. As seen in the figure, switcheson the junctions of the vertical nanowires with first 2m hori-zontal nanowires are configured to provide the minterms. Theswitches on the junctions of vertical nanowires with last hori-zontal nanowire (Out) are configured to provide the sum of theminterms specified by the function. So, the first 2m horizontalwires create the AND terms (minterms) and the last horizontalwire create the OR term.

First, we calculate the average probability of having a faultin a function configured in a LUT. Let’s assume that Po is theprobability of an open fault in a molecular switch, Pc showsthe probability of a closed fault in a molecular switch and Pwdenotes the probability of a fault caused by a defect in one ofthe nanowires. The probability of an implemented minterm tobe faulty is given by:

P f aulty minterm 1 P f ault f ree minterm

1 1 pcm 1 po

m 1 1 pw2m 2

The probability of an m-input function with x minterms to befaulty is obtained from:

P f aulty f unction 1 P f ault f ree f unction

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Page 5: SCT: An Approach For Testing and Configuring Nanoscale Devices

1 1 pcm 1 po

m 1 1 pwx 1 pw

2m 1

The average probability of having a fault in a function (Pf f )and the probability of successful implementation (Psi) of a func-tion on this structure after a number of repeated configurations(Nr) will be:

Pf f∑2m

x 1 P f aulty f unction

2m

Psi 1 Pf f P Nr 1f f Nr 1

log Psi1 Pf f

logPf f

Nr can also be defined as the average number of blocks thatshould be configured to finally find a fault-free implementationof a function fi on the device with a probability higher thanPsi. The average number of switches to be configured for afunction can be calculated as the average number of mintermsin a function multiplied by the number of switches for eachminterm. As seen in the Figure 4, there are m 1 switchesfor each minterm to be configured, so the average number ofswitches to be configured for a function (Ns f ) is:

Ns fm 1

2m

2m

∑x 1

xm 1 2m 1

2

We assume that access and configuration structure of the ar-chitecture is capable of configuring Ncs switches in each cycle.It should also be noted that 2m tests should be applied to each ofthe configured functions to test it exhaustively. Therefore, theaverage number of cycles required to configure and test an m-input function with a success probability higher than Psi wouldbe:

# Con f ig & Test Cycles prob Psi Nr 2m Nr Ns f

Ncs

First term in the above equation is the number of cycles re-quired for testing the configured functions (each time a functionis configured, 2m test patterns should be applied to it). Secondterm is the number of cycles required for configuring the func-tion. For a circuit with T m-input functions, the time of per-forming SCT procedure assuming N parallel BIST circuits, asshown in Figure 3, can be calculated as:

# Cycles SCT NrTN

2m Ns f N

Ncs1

In this equation, first term of the sum is the cycles required toapply 2m test patterns through N parallel BIST circuits to Nconfigured functions and the second term of the sum is the cy-cles required to configure the functions into the blocks throughconfiguration circuitry (Ncs switches in each cycle).

To compare this with the number of cycles required to testa nanoscale architecture using previously proposed test meth-ods, we calculate the estimated cycles for testing a circuit withthe same specifications mentioned earlier (T m-input functions)based on the BIST method proposed in [22]. The numberof configurations required for testing a K K nanoblock of ananofabric is calculated to be 4K 6 and the number of config-urations required for testing a K K switchblock of a nanofab-ric is estimated to be 4K2 [22].

To make a fair comparison, here we use the same assump-tions and parameters used in the analysis of our SCT method.We assumed using CMOS scale interconnects for the architec-ture hence, the required number of cycles for test and configu-ration of the interconnects were omitted from the calculations.Therefore, to keep the same conditions for [22], we assume theswitchblocks of the architecture to be fault-free. So, we omitthe 4K2 configurations required for testing each switchblock inthe architecture. Based on our analysis, the number of cyclesrequired for BIST method proposed in [22] based on these as-sumptions can be calculated as:

# Cycles BIST 22

T

1 pw 2K 1 pc K2 1 po K2

4K 6Ncs

2

where K 2m 1 2m.Once defect map is created and stored, it can be used to con-

figure the functions of the design on the device. Therefore, ad-ditional cycles will be required to implement the functions ofthe circuit based on the calculated defect map. Also, as dis-cussed in [22], applying the test patterns in that BIST process(and almost all other proposed methods) will not result in find-ing the exact location of the faulty block. Hence, there will besome fault-free blocks that are determined as faulty during thesetest methods. That means recovery, i.e. the ratio of detectedfault-free blocks to all fault-free blocks, in these test methods islower than 100%. To achieve high recovery it is suggested thata recovery procedure should be applied to exactly locate thefaulty blocks. This diagnostic procedure will require consider-able number of reconfigurations that will significantly increasethe test time. In analysis presented above we assumed that thetest process can exactly locate the faulty blocks (in other wordswe assumed 100% recovery). This assumption causes the BISTformula to show test cycles lower than the actual number ofcycles required by the BIST method presented in [22].

The number of cycles for SCT procedure and for BIST pro-cess proposed in [22] are compared for different defect proba-bilities and design parameters and the results are presented inFigures 5 and 6. In each of these figures, constant values areassigned to m, T , Ncs and Psi. Different values are assigned toN, i.e. the number of parallel working BIST circuits, and tothe fault probabilities of the molecular switches and nanowires.As the results demonstrate, in most cases the required cyclesfor our SCT procedure is considerably less than cycles of BISTmethod of [22].

As Figure 7 shows, increasing N, i.e. the number of con-current BIST circuits, will result in decreasing the overall timeof the SCT procedure and increasing the BIST area overhead.However, increasing N will not decrease overall SCT proceduretime linearly. If the configuration circuitry is capable of config-uring a constant number of switches in each cycle (Ncs), then asN increases configuration time will become the dominant partof the SCT procedure and this part cannot be reduced throughadding the number of parallel BIST circuits (N). Adding moreparallel configuration circuitry, i.e. increasing Ncs from 5 to 20as shown in the figure, will reduce the configuration time andthis in turn reduces the SCT time. Area overhead resulted by

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Page 6: SCT: An Approach For Testing and Configuring Nanoscale Devices

0

5e+06

1e+07

1.5e+07

2e+07

2.5e+07

3e+07

3.5e+07

4e+07

4.5e+07

5e+07

0 0.004 0.008 0.012 0.016 0.02 0.024 0.028 0.032 0.036 0.04

Required cycles for test

Fault Probablity in nanowires and switches (Pw=Po=Pc)

SCT (N=1)SCT (N=5)SCT (N=10)SCT (N=20)BIST [22]

Fig. 5. Number of cycles required for testing a nano device using SCTmethod and BIST method proposed in [22] when m 3 T 1000000 Psi0 999 Ncs 5.

0

5e+06

1e+07

1.5e+07

2e+07

2.5e+07

3e+07

3.5e+07

4e+07

4.5e+07

5e+07

0 0.004 0.008 0.012 0.016 0.02 0.024 0.028 0.032 0.036 0.04

Required cycles for test

Fault Probablity in nanowires and switches (Pw=Po=Pc)

SCT (N=1)SCT (N=5)SCT (N=10)SCT (N=20)BIST [22]

Fig. 6. Number of cycles required for testing a nano device using SCT methodand BIST method proposed in [22] when m 4 T 500000 Psi 0 999 Ncs5.

adding the parallel BIST circuits will be still small comparingto the area required to store the defect map as previously pro-posed by BIST methods such as [14][15][22].

V. CONCLUSION

A new approach to testing nanoscale devices was proposedin this paper. This approach, called simultaneous configurationand test (SCT), is an architecture independent method. Themethod is based on exhaustive testing of the functions of anapplication while they are being configured into the nanoscaledevice. This method removes the requirement of storing thelocation of all defects in a large defect map. Probabilistic anal-yses on the number of cycles required to accomplish the SCTprocedure in comparison to another BIST process, demonstratethe time effectiveness of the proposed method. The results con-firm the efficiency of SCT for high density and high defect ratenanoscale devices compared to previously proposed test meth-ods whose purpose is to locate all the defects and create a defectmap.

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0

3e+06

6e+06

9e+06

1.2e+07

1.5e+07

0 5 10 15 20 25 30 35

Required cycles for SCT procedure

Area overhead in terms of parallel BIST circuits (N)

p=.001, Ncs=5p=.005, Ncs=5p=.01, Ncs=5p=.001, Ncs=20p=.005, Ncs=20p=.01, Ncs=20

Fig. 7. SCT procedure time versus N, i.e. the number of parallel BIST circuits,which is a measure of BIST area overhead (m 3 T 1000000 Psi 0 999).

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