sd card fianal project documentation
TRANSCRIPT
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CHAPTER-1
INTRODUCTION
A memory card (also called a flash memory card) is
solid-state electronic data storage device. First invented by Toshiba in the 1980s,
memory cards save the stored data even after the memory device is
disconnected from its power source. This ability to retain data is the key for flash
memory card applications, for example, in digital cameras, where the saved
pictures are not lost after the memory card is removed from the camera.
Memory cards are used in consumer electronics like Digital cameras, Mobile
phones MP3 players and also in industrial application like embedded computers,
Communication devices, Security systems.
1.CLASSIFICATION OF MEMORY CARDS:
There are many different types of memory cards available in the market. Some ofthe most commonly known memory cards are
Smart media (SM) card
Multimedia card (MMC)
Compact flash (CF) card
Memory stick (MS) card
Secure digital (SD) card
1.1 Smart Media Card:
The SM card was first developed in 1995 by Toshiba and was also called
the Solid State Floppy Disc Card. The SM card consists of a single NAND flash
chip embedded in a thin
Plastic card and it is the thinnest card of all. Figure 3.1 shows a Typical SM card.
The Dimensions of the card are 45.037.00.76mm, and it weighs Only 1.8 g.
The card consists of a flat electrode terminal with 22 pins.The capacities of these
cards ranged from 0.5 to 128 MB, and the data transfer rate was approximately 2
MB/s. SM cards were designed to operate at either 3.3 or 5 V.
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Figure: Smart Media Card
1.2 Mult im edia Card:
MMCs were first developed in the
late 1970s by Intgenix and SanDisk.
These cards were
Initially used in mobile phone and
pager devices. The card dimensions
are 24.0 x32.0 x1.4 mm and it has 8
pins. The MMC operating voltage is
3.3 V, and the data transfer rate is
approximately 2.5 MB/s. MMCs are
available with capacities up to 4 GB
Fig: Mult i m edia Card
1.3 Compact Flash Card:
CF cards were first developed in
1994 by SanDisk. These are the
cards offering the highest capacities
from 2 MB to 100 GB. The card
operating voltage is 3.3 or 5 V.CF
cards are available at very high
storage capacities. CF cards operate
at high speeds
Fig:Compact Flash Card
1.4Memory Stic k Card:
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The Memory Stick cards were first
developed by Sony in 1998.Although
the original Memory Stick was
only128 MB, the largest capacity
currently available is 16 GB.Figure
3.4 shows a typical MS card. MS has
now been replaced with Memory
Stick PRO, Memory Stick Duo and
Memory Stick PRO-HG operating
data transfer speed of this card is 60
MB/s.
Figure: Memory Stick Card
1.5 Secure Dig ital Card:
The SD card stands for secure digital was originally developed by Matsushita,
SanDisk, and Toshiba in 2000. SD cards nowadays a used in many portable
devices, such as Digital cameras, mobile Phones, PDAs, handheld computers,
video recorders, GPSReceiver and many other Applications. Standard SD cards
are available with capacities from 4 MB to 4 GB.In August of 1999 Panasonic,
SanDisk and Toshiba Collaborated to Form SD Association (SDA) to develop SDcards further and which makes standards for all other companies. SD card
further divided into three types of families base on the Extension of memory size
and the file system used to access the card as follows.
1.6 SD FORMAT FAMILIES INCLUDE:
1. SECURE DIGITAL STANDARD CAPACITY (SDSC)
2. SECURE DIGITAL HIGH CAPACITY (SDHC)
3. SECURE DIGITAL EXTENDED CAPACITY (SDXC)
The secure digital standard capacity
(SDSC) has been developed with
capacities ranging from 2GB to 4GB
and these memory cards can
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support only FAT16 file system
because of maximum address
access up to 4GB only.
Another version is secure digitalHigh capacity (SDHC) has been
developed with Capacities ranging
from 4GB to 32GB and the file
Systems used in these memory
cards Is FAT-32 because of the
increase in the memory Size we
require more number of Address line
are needed so FAT -32 is required to
access More than 4GB and
Finally last type is secure digital
extended Capacity (SDXC) has been
developed with Capacities ranging
from 32GB to 2TB and file Used in
these memory cards are ex FAT
(Extended file system) which can
support more than 32 GB memory
.The data transfer Speed is
approximately 1520 MB/s.
Normal SD Cards operate at 2.73.6
V and have 9 Pins. Mini SD cards
were first released in 2003.They has
the dimensions20.0 21.5 1.4 mm
and micro SD cards were released in
2008, and they have the
dimensions11.0 15.0 1.0 mm and
a weight of 0.5 grams.
SD cards are available in three
different sizes: normal SD, mini SD,
and micro SD. Figure 3.7 shows the
three types of SD cards.Normal SD
cards have the dimensions 24.0
32.0 2.1 mm and a weight of
2gram
Figure: SD Cards
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CHAPTER -2
INTRODUCTIONTO SPI PROTOCOL
2.1 SECURE DIGITAL MUSIC INITIATIVE:
The Secure Digital Music Initiative (SDMI) is developing a
comprehensive system to Prevent music piracy. Which follows the technique
called water marking in which an inaudible message is hidden in music to provide
copyright information to devices like MP3 players and recorders and most of the
time these memory cards are used in MP3Players for storing music files and
these cards are interfaced using SDMI protocol. Later on this protocol was
replaced by SDIO (SECURE DIGITAL I/O) in order to over- Come some of the
drawbacks in SDMI protocol and some of them are interfacing Problem and
platform dependent will arise while connecting with new devices so, in Order to
overcome these problems there is a need of common standard for interfacing
Memory card with other devices like cameras and GPS devices. This type
common Interfacing is provided by the SDIO Protocol.
2.2 SECURE DIGITAL I/O (SDIO):
The SDIO (Secure Digital I/O) card is based on andcompatible with the SD Memory card. This compatibility includes mechanical,
electrical, power, signaling and Software. The intent of the SDIO card is to
provide high-speed data I/O with low power Consumption for mobile electronic
devices. A primary goal is that an SDIO card inserted into a non-SDIO aware
host will cause no physical damage or disruption of that device or its software. In
this case, the SDIO card should simply be ignored. Once inserted into an SDIO
aware host, the detection of the card will be via the normal means described in
the SD specification with some extensions. In this state, the SDIO card will be
idle and draw A small amount of power (15 mA averaged over 1 second).During
the normal
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Initialization and interrogation of the card by the host, the card will identify itself
as an SDIO device. The host software will then obtain the card information in a
triple (linked List) format and determine if that cards I/O function(s) are
acceptable to activate. This Decision will be based on such parameters as power
requirements or the availability of appropriate software drivers. If the card is
acceptable, it will be allowed to power up fully and start the I/O function(s) built
into it.
2.3 SDIO CARD MODES:
There are 3 signaling modes defined for SD physical specification version 1.01
memory
Cards that also apply to SDIO Card. There are
1. SPI MODE
2. Full Speed Card
3. Low Speed Card
2.3.1 SPI (Card mandatory support):
This is one of the mode used to access the memory cards in which the read/write
Operation are done in serial fashion i.e. data will send in packet format serially to
Destination and the pin configuration of micro SD card will be changed according
to the mode initiated before accessing the memory card and the pin configuration
Will be given tabulated format in below.
2.3.2 1-bit SD data transf er mod e (Card mand atory s uppor t);
This mode is identical to the 1 data bit (narrow) mode defined for SD Memory
Card. In this mode, data is transferred on the DAT [0] pin only. In this mode pin 8,
which is undefined for memory, is used as the interrupt pin all other pins and
signaling protocols are identical to the SD Memory specification.
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2.3.3 4-bit SD data transfer m ode
(Mandatory for High-Speed cards, op t ional for Low -Speed);
This mode is identical to the 4 data bit mode (wide)
defined for SD Memory Cardin this Mode, data is transferred on all 4 data pins
(DAT [3:0]). In this mode the interrupt pin is not available for exclusive use as it is
utilized as a data transfer line. Thus, if the interrupt Function is required a special
timing is required to provide interrupts. The 4-bit SD mode Provides the highest
data transfer possible, up to 100 Mb/sec.This table recommends the usage of 9
pins in micro SD card in the above different modes
2.4 SDIO PIN CONFIGURATION:
The most of the time 4-bit mode is used because in this mode four data
lines are use and It has more data rate compared to 1-bit mode. Where as in
embedded system the Resources are less so, we require an easy way to access
the memory card for that purpose SPI protocol will useful more compared to
other two modes. In SPI mode data Transferring Pin is multiplexed with
command so, this will provide a better reduction in Connection between the
microcontroller and the SD card pins and simple instructions are Required to
access the data from card in SPI protocol.
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2.5 PIN CONFIGURATION IN SPI PROTOCOL:
In this application the microcontroller will be configured
with micro SD card forRead and write operation so, there is a need of physical
connection between the two Elements. As micro SD card is very think in size it
results in more complicated will Soldering so, in order to avoid that problem we
used SD card adopter which bigger then Micro SD card and it is easy to have a
connection between two elements without any Damage .the adopter will show as
below There is difference in pin configuration depending upon the usage of
adopter or micro SD Card is given below
Fig: mini sd adaptors
2.5.1 Memory cards are designed on tw o techno logies:
NOR technology and NAND technology. NOR technology provides high-speed
random Access capabilities, where data as small as a single byte can be
retrieved. NOR Technology-based memory cards are often found in mobile
phones, personal digital Assistants and computers. NAND technology was
invented after the NOR technology, and it allows sequential access to the data in
single pages but cannot retrieve single bytes of data like NOR flash. NAND
technology- based memory cards are commonly found in Digital cameras, mobile
phones, audio and video devices, and other devices where the Data is written
and read sequentially.
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CHAPTER -3
INTERFACING OF MICRO SD CARD TO MICROCONTROLLER
3.1 GENERAL DESCRITION OF MEMORY CARD:
The Secure Digital (SD) Card is a flash-based
memory card consists of microcontroller which is inter connected with flash
memory and performs some of the crucial operation like data transferring and
power up initialing process and accepting basic communication commands
likeCMD0, CMD15, CMD55, ACMD41.
The data rate will depends on clock frequency which was supplied to
the memory card from host and most important factor is power supply this was
also provided by the host and power rating should strictly followed while
regulating the power given to the memory card usually voltage will be around 2.7
to 3.6 v
While initializing the memory card we should know the operating
voltage of that memory card by sending a specific command in response the
memory card will send code word which tells about the operating voltage
conditions and based on the code word
The power is supplied to the memory card by using the regulator circuit.
In order to access the memory card we should know the basic
information like operating voltage, data rate , file format and correction codes all
of these information was available in memory card registers and these registers
are in built and designed by the manufacturer.
Micro SD card consists of 9 pins which are connected to the
microcontroller. In general the electric characteristics are different for the two
elements so, there is in built interface drivers are present inside the memory cardwhich interface the signals coming from the microcontroller and it synchronize
the operations between the outside host microcontroller and inside
microcontroller of memory card
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Flash controller is interface between the microcontroller and the memory core
inside the memory card. Which deals with read and writes operation on data
present in the memory
Core .the microcontroller inside the memory card will schedule the flash
controller according to the command obtained by the host controller and control
the internal operations.
3.2 BLOCKDIAGRAM OF MEMORY CARD:
3.2.1 Memory A rray Parti t ioning :
The basic unit of data transfer
to/from the SanDisk SD Card is one
byte. All data transfer Operations
that require a block size always
define block lengths as integer
multiples of Bytes. Some special
functions need other partition
granularity. Figure 1-2 shows the
Memory Array Partitioning.For block-
oriented commands, the following
definition is used.
Block:
A unit related to block-oriented read
and write commands. Its size is the
numberof bytes that are transferred
when one block command is sent by
the host. The Size of a block is either
programmable or fixed; information
about allowed block sizes and the
programmability is stored in the CSD
Register. The granularity of the
erasable units is, in general, not the
same as for the block-oriented
Commands.
Sector:
A unit related to the erase
commands. Its size is the number of
blocks that are erased in one portion.The size of a sector is fixed for each
device. The information about the
sector size (in blocks) is stored in the
CSD Register.For devices that
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include write protection, the following
definition is used.
WP Group :
Minimal units that may haveindividual write protection. Its size is
the number of groups to be writes
protected by one bit. The size of a
WP group is fixed for each device.
The information about the size is
stored in the CSD Register.
3.3 SANDISK SD MEMORY CARD:
Figure: Memory A rray Part i t ioning
3.4 REGISTER INFORMATION:
In micro SD card there are five registers are available which possess information
like Packet size, security codes etc. Each register size is variable in length and
by using Specific commands is usedto get the information in the register.
Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR
and SCR. These can be accessed only by corresponding commands The OCR;
CID, CSD and SCR registers carry the card/content specific information, while
the RCA and DSR Registers are configuration registers storing actual
configuration parameter.
The registers are as follows
1. Operation condition register (OCR)
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2. Card identification register(CID)
3. Relative card address (RCA)
4. Card specific data(CSD)
5. SD configuration register(SCR)
3.4.1 OCR regis ter:
The 32-bit operation
conditions register stores the VDD
voltage profile of the card.
Additionally, this register includes
status information bits. One status bit
I Set if the card power up procedure
has been finished. This register
includes another status bit indicating
the card capacity status after set
power up status bit. The OCR
register shall be implemented by the
cards.The32-bit operation Conditions
register stores the VDD voltage
profile of the card. Bit 7 of OCR is
newly defined for Dual Voltage Card
and set to 0 in default. If a Dual
Voltage Card does not receive
CMD8; OCR bit 7 in the response
indicates 0, and the Dual VoltageCard which received CMD8, sets this
bit to 1.Additionally, this register
Includes 2 more status information
bits. Bit 31 - Card power up status
bit, this Status bit is set if the card
power up procedure has been
finished. Bit 30 Card Capacity
status bit, this status bit is set to 1 if
card is High Capacity SD Memory
Card. 0 indicates that the card is
Standard Capacity SD Memory
Card. The Card
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3.4.2 CID Regis ter:
The Card Identification (CID) register is 128 bits wide. It
contains the card identification Information used during the card identification
phase. Every individual flash card shall have a unique identification number.
3.4.3 RCA Regis ter:
The writable 16-bit relative card address register carries the
card address that is published by the card during the card identification. This
address is used for the addressed host-card Communication after the card
identification procedure. The default value of the RCA Register is 0x0000. The
value0x0000 is reserved to set all cards into the Stand-by State with CMD7.
3.4.4 CSD Regis ter:
The Card Specific Data (CSD) Register configuration information
is required to access The Cell Type column defines the CSD field as read-
only(R), one-time Programmable(R/W) or erasable (R/W/E). The values are
presented in real world units for each field and coded according to the CSD
structure.
3.4.5 SCR Regis ter:
In addition to the CSD register there is another configurationregister that named - SD CARD Configuration Register(SCR). SCR provides
information on SD Memory Card's special features that were configured into the
given card. The size of SCR register is 64 bit. This register shall be set in the
factory by the SD Memory Card manufacturer.
Here, we used a PIC18F452 to access an SD card. Generally SD card
is interfaced to PIC18F452 via SPI. We didn't use any file system here. It writes
the 8 bit digital data From RAM to the MMC using a multiple block write
command or A single block Consists of 512 bytes, also called as a sector.SD
card is interfaced to PIC via SPI (serial peripheral interfacing). Inbuilt SPI module
is Available in PIC18F452.The SPI mode allows 8 bits of data to be
synchronously transmitted and received simultaneously. Here, PIC18F452 is SPI
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master and SD card is SPI slave to accomplish communication typically three
pins are used
Serial Data out (SDO)RC5/SDO
Serial Data In(SDI)RC4/SDI/SDA Serial Clock (SCK) RC3/SCK/SCL
3.5 INTERFACE OF SD CARD TO PIC MICROCONTROLLER:
SD card works at 3.6 V (max) and PIC18F452 at 5V. So,
we need a voltage level Convertor for interfacing PIC to SD card. A simple
resistor based voltage divider is used to connect CS, CLK and SCK. Now, if a
4.3v (max o/p of PIC) appears across any of the above three pins, then the
voltage at corresponding SD card pins will be 2.48v (comes in Range of logic
high of SD card). 'Data out' of MMC is directly connected to SPI 'data in' Of PIC.
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CHAPTER -4
SD CARD COMMANDS AND RESPOCE
Here, we used a PIC18F452 to access an SD card. Generally
SD card is interfaced to PIC18F452 via SPI. We didn't use any file system here.
It writes the 8 bit digital data From RAM to the MMC using a multiple block write
command or A single block Consists of 512 bytes ,also called as a sector.
4.1 INITILIZING PROCESS:
To initiate an operation on SD card, we need to send
corresponding 6byte long SD card command (structure on below figure) which is
specific to each operation like single block read, multiple block read and single
block write as well as multiple block write, SD card initialization etc.
The SD Memory Card wakes up in the SD mode. It will enter SPI
mode if the CS signal is asserted (negative) during the reception of the reset
command (CMD0) and the card is inidle state. If the card recognizes that the SD
mode is required it will not respond to the Command and remain in the SD mode.
If SPI mode is required the card will switch to SPI and respond with the SPI
mode R1 response.
The only way to return to the SD mode is by entering the power cycle. In SPI
mode the SD Memory Card protocol state Machine is not observed. All the SD
Memory Card commands supported in SPI mode Are always available.
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The default command structure/protocol for SPI mode is the CRC checking is
disabled, Since the card powers up in SD bus mode .CMD0 must be followed by
a valid CRC byte(Even though the command is sent using SPI structure).Once in
SPI mode ,CRCs are Disabled by default
CMD0 is a static command and always generates the same 7-bit CRC of 4Ah
.Adding the 1.end bit (bit 0) to the CRC creates a CRC byte of 95h.The
following hexadecimal sequence can be used to send CMD0 in all situations for
SPI mode, since the CRC byte (although required) is ignored once in SPI mode
the entire CMD0 sequence appears as 40 00 00 00 00 95 (hexadecimal)
4.1.1 Bus Trans fer Protection :
Every SD Memory Card token transferred on the bus is
protected by CRC bits. In SPI Mode, the SD Memory Card offers a non-protected
mode which enables systems built with reliable data links to exclude the
hardware or firmware required for implementing The CRC generation and
verification functions in the non-protected mode the CRC bits of the command,
response and data tokens are still required in the tokens. However, they aredefined as dont care for the transmitter and ignored by the receiver. The SPI
interface is initialized in the non-protected mode. The host can turn this option on
and off using CRC_ON_OFF command (CMD5).
Command 0 (CMD0) is also called Command (0, 0, 0x95)
There are different types of command responses. Now, for getting a response
from SD Card, 0xff is send and the received data will be the response. For some
commands, we need to wait until the correct response is received, by
continuously checking for the response. There are commands for reading, writing
etc. Every data read or data write Operation is completed by reading or writing of
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a total of 512 bytes of data. A sector is 512 bytes. (Default blocks size). We
cannot terminate the read or write operation in the mid-way within a block.
4.2 SD CARD INITILIZATION:
When an SD card is powered ON, we need to initialize
the SD card and bring it to SPI mode. This requires a series of commands and
need to check the response whether it is correct or not for the particular
command.
Whenever the active low signal is given to chip select pin of SD card after few
clock Cycles the command (CMD0) is passed to CMD pin of SD card and wait for
response. Here we have three types of response format are available in that R1
response is Acknowledged by SD card by receiving the initializing command and
the response is Passed to the DATA OUT pin of SD card
Every command was send in the form of packet and even if
data also send to the SD card In the packet format given below as we are using
SPI protocol by default CRC is Disabled and data received by SD card will be
checked by the valid response given by Memory card as it is known as data
response .After sending the data we continuously Check at the DATA OUT pin of
SD card for the response. As if data is reached Successfully to SD card then it
returns the value zero so that we can send the next packet Of data else we have
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to retransmitted the data to SD card .the value one indicates the Error While
writing the data and at that condition we have to send the data again to SD Card
.To Check the data as it reached without any error CRC check is used as it is
little Bit Complicated to generate the polynomial and check sum because of
hardware Limitations we followed another approach which is level converter
which enhances the Voltage of Transmitting bit which is sending to destination
memory card .this solves the problem of loss of data while Transmitting
4.2.1 Single B lock Read:
The argument specifies the location to start to read in unit of byte
or block. The sector address specified by upper layer must be scaled properly.
When a CMD17 is accepted, a read operation is initiated and the read data blockwill be sent to the host. After a validdata token (FEh) is detected, the host
controller receives following data field and twobyte CRC. The CRC bytes must be
flushed even if it is not needed. If any error occurred during the read operation,
an error token will be returned instead of data packet.
Fig:Reading o perat ion t iming d iagram
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Mult iple Block Read:
The Multiple Block Read command reads multiple blocks in
sequence from the specified Address. When number of transfer blocks has not
been specified before this command,TheTransaction will be initiated as an open-
ended multiple blocksread, the read Operationwill continue until stopped with a
CMD12. The received byte immediately FollowingCMD12 is a stuff byte; it should
be discarded before receiving the response ofTheCMD12. Before every data
packet, a data token (FEh) is sent by the card. If the data Token is not received,
then it waits for the token.
Fig:Mul t ip le block read t imin g diagram
4.2.2 Single Blo ck Write:
When a write command is accepted, the host controller sends a
data packet to the card after a byte space. The packet format is same as Block
Read command. The CRC field can have any invalid value unless the CRC
function is enabled. When a data packet has been sent, the card responds a
Data Response immediately following the data packet the data response trails a
busy flag to process the write operation. Most cards cannot Change write block
size and it is fixed to 512 bytes. Before every data packets a data Token is
written so that the MMC/SD could confirm that the next 512 bytes received after
the write token (FEh) is the data block to be stored in the SD/MMC. In principle of
the SPI mode, the CS signal must be asserted during a transaction however
there is an exception to this rule. When the card is busy, the host controller can
be asserts CS to release SPI bus for any other SPI devices. The card will drive
do signal low again when reselect it during internal process is in progress.
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Therefore a preceding busy check (wait ready immediately before command and
data packet) instead of post wait can eliminate waste wait time. In addition the
internal process is initiated a byte after the data response, this means eight
clocks are required to initiate internal write Operation. The state of CS signal
during the eight clocks is negligible so that it can do by Bus release process
described below.
Fig:Single block wr i te t iming d iagram
4.2.3 Mult iple B lock Write:
The Multiple Block Read command writes multiple blocks in
sequence from the specified Address. When number of transfer blocks has not
been specified prior to this command the transaction will be initiated as an open-
ended multiple block write, the write Operation will continue until it is terminated
with a Stop Tran token(FDh). The busy flag will appear on the DO line a byte
after the Stop Tran token. As for SDC, the multiple block write transaction must
be terminated with a Stop Tran token independent of the Transfer type, pre-
defined or open-ended.
Fig:Mul t ip le block wr i te t iming d iagram
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4.3 COMMANDS FOR SD CARD:
The following commands are used in SPI mode while writing the
instructions
CMD0 : To Initialize the Card into SPI Mode
CMD9 : To read CSD
CMD10 : To read CID
CMD12 : Stops the multiple read/write Block
CMD13 : To read Status register
CMD17 : Read a Block
CMD18 : Multiple Block Read
CMD25 : Multiple Block Write
CMD58 : To read OCR
CMD24 : Single Block Write
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CHAPTER -5
THE FILE SYSTEM
5.1 FILE SYSTEM:
A file system (or file system) is an abstraction to store, retrieve and
update a set offiles. The term also identifies the data structures specified by
some of those abstractions, which are designed to organize multiple files as a
single stream of bytes, and the network protocols specified by some other of
those abstractions, which are designed to allow files on a remote machine to be
accessed
The file system manages access to the data and the metadata of the files, andmanages the available space of the device(s) which contain it. Ensuring reliability
is a major responsibility of a file system. A file system organizes data in an
efficient manner
5.2 SPACE MANAGEMENT:
File systems allocate space in a granular manner, usually
multiple physical units on the device. The file system is responsible for
organizing files and directories, and keeping track of which areas of the media
belong to which file and which are not being used
File system fragmentation occurs when unused space or single files are
not contiguous. As a file system is used, files are created, modified and deleted.
When a file is created the file system allocates space for the data. Some file
systems permit or require specifying an initial space allocation and subsequent
incremental allocations as the file grows. As files are deleted the space they were
allocated eventually is considered available for use by other files. This creates
alternating used and unused areas of various sizes. This is free space
fragmentation. When a file is created and there is not an area of contiguous
space available for its initial allocation the space must be assigned in fragments.
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When a file is modified such that it becomes larger it may exceed the space
initially allocated to it, another allocation must be assigned elsewhere and the file
becomes fragmented
5.2.1 Filenames:
A filename (or file name) is used to identify a storage location in the file
system. Most file systems have restrictions on the length of filenames. In some
file systems, filenames are case-insensitive (i.e., filenames such
as FOO and foo refer to the same file); in others, filenames are case-sensitive
(i.e., the names FOO and foo refer to two separate files).
Most modern file systems allow filenames to contain a wide range of characters
from the Unicode character set. Most file system interface utilities, however, haverestrictions on the use of certain special characters, disallowing them within
filenames (the file system may use these special characters to indicate a device,
device type, directory prefix, or file type). However, these special characters
might be allowed by, for example, enclosing the filename with double quotes (").
For simplicity, special characters are generally discouraged within filenames.
5.2.2 Directori es:
File systems typically have directories (also called folders) which allow theuser to group files into separate collections. This may be implemented by
associating the file name with an index in at able of contents or an in ode in
a Unix-like file system. Directory structures may be flat (i.e. linear), or allow
hierarchies where directories may contain subdirectories. The first file system to
support arbitrary hierarchies of directories was used in the Multicast operating
system
Windows makes use of the FAT, NTFS, ex FAT and Re FS file systems
5.3 FILE ALLOCATION TABLE (FAT):
Is the name of a computerfile system architecture
and a family of industry standard file systems utilizing it. The FAT file system is a
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legacy file system which is simple and robust. It offers good performance even in
light-weight implementations, but cannot deliver thesame performance, reliability
and scalability as some modern file systems. It is however supported for
compatibility reasons by virtually all existing operating systems forpersonal
computers, and thus is a well-suited format for data exchange between
computers and devices of almost any type and age from the early 1980s up to
the present.
The FAT file system is simple yet robust. It offers reasonable performance
even in very light-weight implementations and is therefore widely adopted and
supported by virtually all existing operating systems forpersonal computers as
well as some home computers and a multitude ofembedded systems. This
makes it a useful format forsolid-state memory cards and a convenient way to
share data between operating systems.
5.4 FILE SYSTEM TYPES:
Original 8-bit FAT,FAT12,FAT16, FAT32
5.4.1 FAT 32:
In order to overcome the volume size limit of FAT16, while at the same time
allowing DOS real mode code to handle the format, Microsoft designed a new
version of the file system, FAT32, which supported an increased number of
possible clusters
Cluster values are represented by 32-bit numbers, of which 28 bits are
used to hold the cluster number. The boot sector uses a 32-bit field for the sector
count, limiting the FAT32 volume size to 2 TB for a sector size of 512 bytes and
16 TB for a sector size of 4,096 bytes the maximum possible size for a file on an
FAT32 volume is 4 GB minus 1 byte or 4,294,967,295 (232
1) bytes.
A FAT file system is composed of
different sections:
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5.4.2 Bo ot Secto r:
On non-partitioned devices,
e.g.Floppy,the BootSector(VBR) is
the first sector (logical sector 0 with
physical CHS address 0/0/1 or LBA
address 0)). For partitioned devices
such as hard drives, the first sector
is the Master Boot Record defining
partitions, while the first sector of
partitions formatted with an FAT file
system is again the Boot Sector.
Typically MBR consists of
Jump Code
Size of the memory card Root Directory Address
FAT table Address
Files system type
Name of the memory car
5.4.3 File Allo cation Table:
A volume's data area is divided up into identically sized clusters,
small blocks of contiguous space. Cluster sizes vary depending on the type of
FAT file system being used and the size of the partition; typically cluster sizes lie
somewhere between 2 KB and 32 KB. Each file may occupy one or more of
these clusters depending on its size; thus, a file is represented by a chain of
these clusters (referred to as a singly linked list). However these clusters are not
necessarily stored adjacent to one another on the disk's surface but are often
instead fragmentedthroughout the Data Region.
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The File Allocation Table (FAT) is contiguous number of sectors immediately
following the area of reserved sectors. It represents a list of entries that map to
each cluster on the volume. Each entry records one of five things:
the cluster number of the next cluster in a chain
a special end of cluster-chain (EOC) entry that indicates the end of a chain
a special entry to mark a bad cluster
a zero to note that the cluster is unused
5.4.4 Root Directory :
A directory table is a special type of file that represents a directory
(also known as a folder). Each file or directory stored within it is represented by a
32-byte entry in the table. Each entry records the name, extension, attributes
(archive, directory, hidden, read-only, system and volume), the date and time of
last modification, the address of the first cluster of the file/directory's data and
finally the size of the file/directory. Aside from the Root Directory Table in FAT12
and FAT16 file systems, which occupies the special Root Directory
Region location, all Directory Tables are stored in the Data Region. The actual
number of entries in a directory stored in the Data Region can grow by addinganother cluster to the chain in the FAT.
5.4.5 Data Sector s:
The length of the data region varies depending on the size of the device.
Entire data region is divided into clusters 32*512 Bytes. So that minimum file size
in the FAT 32 is 4kb.
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5.5 DATA READING PROCESS IN FAT32:
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CHAPTER -6
MICROCONTROLLER AND INTERFACING MODULES
6.1 FEATURES OF MICROCONTROLLER:
(PIC18F452)
Internal SPI Module
Internal RAM 1536bytes
32k Program Memory
40Mhz Clock
Easily available in market
Cheap compared other companies and other PIC versions
6.2 PIN DIAGRAM:
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6.3 FUNCTIONAL BLOCK DIAGRAM OF PIC18F452:
This device comes in 28-pin and 40/44-pin packages.The 28-pin
devices do not have a Parallel Slave Port (PSP) implemented and the number of
Analog-to-Digital (A/D) converter input channels is reduced
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6.4 MEMORY ORGANISATION:
There are three memory blocks in Enhanced MCU devices. These memory
blocks are:
Program Memory
Data RAM
Data EEPROM
Data and program memory use separate busses, which allows for concurrent
access of these blocks.
6.4.1 (i)Prog ram Memory:
A 21-bit program counter is capable of addressing the 2-Mbyte program memory
space. Accessing a location between the physically implemented memory and
the 2-Mbyte address will cause a read of all 0s (a NOP instruction). The
PIC18F452 have 32 Kbytes of FLASH memory, while the PIC18F242 and
PIC18F442 have 16Kbytes of FLASH. This means the PIC18FX52 devices can
store up to 16K of single word instructions, and PIC18FX42 devices can store up
to 8K of single word instructions. The RESET vector address is at 0000h and the
interrupt vector addresses are at 0008h and 0018h. Figure shows the Program
Memory Map for PIC18F25452 device.The code space is generally implemented
as ROM, EPROM or flash ROM. In general, external code memory is not directly
addressable due to the lack of an external memory interface. The exceptions are
PIC17 and select high pincount . Some operations, such as bit setting and
testing, can be performed on any numbered register, but bi-operand arithmetic
operations always involve W (the accumulator), writing the result back to either W
or the other operand register. To load a constant, it is necessary to load it into W
before it can be moved into another register. On the older cores, all register
moves needed to pass through W, but this changed on the "high end" cores .
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6.4.2 Program Memory Map and Stack for PIC18F452:
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6.4.3 (i i ) Flash Program Memor y:
The FLASH Program Memory is readable, writable, and erasable during
normal operation over the entire VDD range. A read from program memory is
executed on one byte at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a
time. A bulk erase operation may not be issued from user code. Writing or
erasing program memory will cease instruction fetches until the operation is
complete. The program memory cannot be accessed during the write or erase,
therefore, code cannot execute. An internal programming timer terminates
program memory writes and erases. A value written to program memory does not
need to be a valid instruction. Executing a program memory location that forms
an invalid instruction results in a NOP.
6.4.4 (ii i) Data EEPROM Memory:
The Data EEPROM is readable and writable during normal operation
over the entire VDD range. The data memory is not directly mapped in the
register file space. Instead, it is indirectly addressed through the Special Function
Registers (SFR).There are four SFRs used to read and write the program and
data EEPROM memory. These registers are:
EECON1
EECON2
EEDATA
EEADR
The EEPROM data memory allows byte read and writes. When interfacing to the
data memory block, EEDATA holds the 8-bit data for read/write and EEADR
holds the address of the EEPROM location being accessed. These devices have
256 bytes of data EEPROM with an address range from 0h to FFh. The
EEPROM data memory is rated for high erase/ writes cycles. A byte write
automatically erases the location and writes the new data (erase-before-write).
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The write time is controlled by an on-chip timer. The write time will vary with
voltage and temperature, as well as from chip to chip.
6.5 OSCILLATOR CONFIGURATION:
The PIC18FXX2 can be operated in eight different Oscillator modes. The user
can program three configuration bits (FOSC2, FOSC1, and FOSC0) to select one
of these eight modes:
1. LP Low Power Crystal
2. XT Crystal/Resonator
3. HS High Speed Crystal/Resonator
4. HS + PLL High Speed Crystal/Resonator with PLL enabled
5. RC External Resistor/Capacitor
6. RCIO External Resistor/Capacitor with I/O pin enabled
7. EC External Clock
8. ECIO External Clock with I/O pin enabled
6.6 I/O PORTS:
Depending on the device selected, there are either five ports or three ports
available. Some pins of I/O Ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin. Each port has three
registers for its operation. These registers are:
TRIS register (data direction register)
PORT register (reads the levels on the pins of the Device)
LAT register (output latch)
The data latch (LAT register) is useful for read-modify-write operations on the
value that the I/O pins are driving.
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6.7 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE:
The Master Synchronous Serial Port (MSSP) module is a serial
interface useful for communicating with other peripheral or microcontroller
devices. These peripheral devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module can operate in one of two
modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in hardware:
Master mode
Multi-Master mode
Slave mode
6.7.1 Cont rol Regis ters:
The MSSP module has three associated registers. These include
a status register (SSPSTAT) and two control registers (SSPCON1 and
SSPCON2). The use of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP module is operated in SPI or
I2C mode. Many of the higher end flash based PICs can also self-program (write
to their own program memory). Demo boards are available with a small boot
loader factory programmed that can be used to load user programs over an
interface such asRS-232orUSB, thus obviating the need for a programmer
device. Alternatively there is bootloader firmware available that the user can load
onto the PIC using ICSP. The advantages of a bootloader over ICSP is the far
superior programming speeds, immediate program execution following
programming, and the ability to both debug and program using the same cable.
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6.8 MSSP BLOCK DIAGRAM (SPI MODE):
6.9 REGISTERS:
The MSSP module has four registers for SPI mode operation. These are:
MSSP Control Register1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible
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SSPCON1 and SSPSTAT are the control and statusregisters in SPI mode
operation. The SSPCON1 register is readable and writable. The lower 6 bits of
the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write.
Bit 7 SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end ofdata output time
0 = Input data sampled at middle of
data output time
SPI Slave mode
SMP must be cleared when SPI is
used in Slave m
Bit 6 CKE: SPI Clock Edge Select
When CKP = 0:
1 = Data transmitted on rising edge
of SCK
0 = Data transmitted on falling edge
of SCK
When CKP = 1:
1 = Data transmitted on falling edge
of SCK
0 = Data transmitted on rising edge
of SCK
Bit 5 D/A: Data/Address bit
Used in I2C mode only
Bit 4 P: STOP bitUsed in I
2C mode only. This bit is
cleared when cleared.
Bit 3 S: START bit
Used in I2C mode only
Bit 2 R/W: Read/Write bit information
Used in I2C mode only
Bit 1 UA: Update Address
Used in I2C mode only
Bit 0 BF: Buffer Full Status bit
(Receive mode only)
1 = Receive complete, SSPBUF is
full
0 = Receive not complete, SSPBUF
is empty
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Bit 7 WCOL: Write Collision Detect
bit (Transmit mode only)
1 = The SSPBUF register is written
while it is still transmitting the
previous word
(Must be cleared in software)
0 = No collision
Bit6 SSPOV: Receive Overflow
Indicator bit
SPI Slave mode:
1 = A new byte is received while the
SSPBUF register is still holding the
previous data. In case of overflow,
the data in SSPSR is lost. Overflowcan only occur in Slave mode. The
user
Must read the SSPBUF, even if only
transmitting data, to avoid setting
overflow
(Must be cleared in software).
0 = No overflow
Bit5 SSPEN: Synchronous Serial
Port Enable bit
1 = Enables serial port and
configures SCK, SDO, SDI, and SS
as serial port pins
0 = Disables serial port and
configures these pins as I/O port pins
Bit 4 CKP: Clock Polarity Select bit
1 = IDLE state for clock is a high
level
0 = IDLE state for clock is a low level
Bit (3-0) SSPM3:SSPM0:
Synchronous Serial Port Mode
Select bits
0101 = SPI Slave mode, clock =
SCK pin, SS pin control disabled, SScan be used as I/O pin
0100 = SPI Slave mode,
Clock = SCK pin,
SS pin control enabled
0011 = SPI Master Mode,
Clock = TMR2 output/2
0010 = SPI Master Mode,
Clock = FOSC/64
0001 = SPI Master Mode,
Clock = FOSC/16
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0000 = SPI Master Mode,
Clock = FOSC/4
6.9.1 Operation:
When initializing the SPI, several options need to be specified. This is done by
programming the appropriate control bits (SSPCON1) and SSPSTAT.
These control bits allow the following to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (IDLE state of SCK)
Data input sample phase (middle or end of data output time)
Clock edge (output data on rising/falling edge of SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer
register (SSPBUF). The SSPSR shifts the data in and out of the device, MSBfirst. The SSPBUF holds the data that was written to the SSPSR, until the
received data is ready. Once the 8 bits of data have been received, that byte is
moved to the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT), and the interrupt flag bit, SSPIF, are set. This double buffering
of the received data (SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON1), will be set. User software must
clear
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the WCOL bit so that it can be determined if the following write(s) to the SSPBUF
register completed successfully. When the application software is expecting to
receive valid data, the SSPBUF should be read before the next byte of data to
transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT), indicates
when SSPBUF has been loaded with the received data (transmission is
complete).
When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if
the SPI is only a transmitter. Generally, the MSSP Interrupt is used todetermine
when the transmission/reception has completed. The SSPBUF must be read
and/or written. If the interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does not occur. SSPBUF
(SSPSR) for data transmission. The SSPSR is not directly readable or writable,
and can only be accessed by addressing the SSPBUF register. Additionally, the
MSSP status register (SSPSTAT) indicates the various status conditions.
6.9.2 Enablin g SPI I/O:
To enable the serial port, SSP Enable bit, SSPEN (SSPCON1), must be set.
To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON
registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and
SS pins as serial port pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the TRIS register) appropriately
programmed. That is:
SDI is automatically controlled by the SPI module
SDO must have TRISC bit cleared
SCK (Master mode) must have TRISC bit cleared
SCK (Slave mode) must have TRISC bit set
SS must have TRISC bit set
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Any serial port function that is not desired may be overridden by programming
the corresponding data direction (TRIS) register to the opposite value.
6.10 SPI MASTER/SLAVE CONNECTION:
6.10.1 Typical Conn ection :
Figure shows a typical connection between two microcontrollers.
The master controller (Processor 1)initiates the data transfer by sending the SCK
signal.Data is shifted out of both shift registers on their programmed clock edge,
and latched on the opposite edge of the clock. Both processors should beprogrammed to the same ClockPolarity (CKP), and then both controllers would
send and receive data at the same time. Whether the data is meaningful (or
dummy data)depends on the application software. This leads to three scenarios
for data transmission:
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Master sends data Slave sends dummy data
Master sends data Slave sends data
Master sends dummy data Slave sends data
6.11 SPI MASTER MODE:
The master can initiate the data transfer at any time because it controls the SCK.
The master determines when the slave (Processor 2, Figure 15-2) is to broadcast
data by the software protocol. In Master mode, the data is transmitted/received
as soon as the SSPBUF register is written to. If the SPI is only going to receive,
the SDO output could be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the SDI pin at the
programmed clock rate. As each byte is received, it will be loaded into the
SSPBUF register as if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver applications as a Line Activity
Monitor mode. The clock polarity is selected by appropriately programming the
CKP bit (SSPCON1). This then, would give waveforms for SPI
communication as shown in
Figure where the MSB is transmitted first. In Master mode, the SPI clock rate (bitrate) is user programmable to be one of the following:
FOSC/4 (or TCY)
FOSC/16 (or 4 TCY)
FOSC/64 (or 16 TCY)
Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure shows the
waveforms for Master mode. When the CKE bit is set, the SDO data is valid
before there is a clock edge on SCK. The change of the input sample is shown
based on the state of the SMP bit. The time when the SSPBUF is loaded with the
received data is shown.
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6.12 SLAVE MODE:
In Slave mode, the data is transmitted and received as the external clock pulses
appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by the external clock source
on the SCK pin. This external clock must meet the minimum high and low times
as specified in the electrical specifications. While in SLEEP mode, the slave can
transmit/receive data. When a byte is received, the device will wake-up from
sleep.
6.12.1 Slave Select Syn chr on ization:
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode
with SS pin control enabled (SSPCON1 = 04h). The pin must not be driven
low for the SS pin to function as an input. The Data Latch must be high. When
the SS pin is low, transmission and reception are enabled and the SDO pin is
driven. When the SS pin goes high, the SDO pin is nolonger driven, even if in the
middle of a transmitted byte, and becomes a floating output. External pull-up/pull-
down-resistors.
When the SPI module resets, the bit counter is forced to 0. This can be
done by either forcing the SS pin to a high level or clearing the SSPEN bit. To
emulate two-wire communication, the SDO pin can be connected to the SDI pin.
When the SPI needs to operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO. The SDI can always be left
as an input (SDI function), since it cannot create a bus conflict.
6.13 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVE TRANSMIT
(USART):
The Universal Synchronous Asynchronous Receiver Transmitter
(USART) module is one of the two serial I/O modules. (USART is also known as
a Serial Communications Interface or SCI.) The USART can be con- figured as a
full duplex asynchronous system that can communicate with peripheral devices,
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such as CRT terminals and personal computers, or it can be configured as a half-
duplex synchronous system that can communicate with peripheral devices, such
as A/D or D/A integrated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes
Asynchronous (full-duplex)
Synchronous - Master (half-duplex)
Synchronous - Slave (half-duplex)
In order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal
Synchronous Asynchronous Receiver Transmitter
Bit SPEN (RCSTA) must be set (= 1),
Bit TRISC must be cleared (= 0), and
Bit TRISC must be set (=1).
6.13.1 USART Asyn chron ous Mode:
In this mode, the USART uses standard non-return-to- zero (NRZ) format (one
START bit, eight or nine data bits and one STOP bit). The most common data
format is 8-bits. An on-chip dedicated 8-bit baud rate genera- tor can be used to
derive standard baud rate frequencies from the oscillator. The USART transmits
and receives the LSB first. The USARTs transmitter and receiver are functionally
independent, but use the same data format and baud rate. The baud rate
generator produces a clock, either x16 or x64 of the bit shift rate, depending on
bit BRGH (TXSTA). Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data bit). Asynchronous mode
is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
The USART Asynchronous module consists of the following important elements:
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Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
Bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Dont care
Synchronous mode:
1 = Master mode (clock generated
internally from BRG)
0 = Slave mode (clock from external
source)
Bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
Bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN
in SYNC mode.
Bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Bit 3 Unimplemented: Read as '0'
Bit 2 BRGH: High Baud Rate Select
bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
Bit 1 TRMT: Transmit Shift Register
Status bit
1 = TSR empty
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0 = TSR full
Bit 0 TX9D: 9th bit of Transmit Data
Can be Address/Data bit or a parity
bit.
Bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures
RX/DT and TX/CK pins as serial port
pins)
0 = Serial port disabled
Bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
Bit 5 SREN: Single Receive Enable
bit
Asynchronous mode:
Dont care
Synchronous mode - Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is
complete.
Synchronous mode - Slave:
Dont care
Bit4 CREN: Continuous Receive
Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until
enable bit CREN is cleared (CREN
overrides SREN)
0 = Disables continuous receive
Bit 3 ADDEN: Address Detect
Enable
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection,
enable interrupt and load of the
receive buffer
When RSR is set
0 = Disables address detection, all
bytes are received, and ninth bit can
be used as parity bit
Bit 2 FERR: Framing Error bit
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1 = Framing error (can be updated
by reading RCREG register and
receive next valid byte)
0 = No framing error
Bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by
clearing bit CREN)
0 = No overrun error
Bit 0 RX9D: 9th bit of Received Data
This can be Address/Data bit or a
parity bit, and must be calculated by
user firmware.
6.13.2 USART A synch ronou s Transm it ter :
The USART transmitter block diagram is shown in Figure. The heart of the
transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREG. The TXREG register is
loaded with data in software.
The TSR register is not loaded until the STOP bit has been transmitted
from the previous load. As soon as the STOP bit is transmitted, the TSR is
loaded with new data from the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register (occurs in one TCY), the TXREG
register is empty andflag bit TXIF (PIR1) is set.
This interrupt can be enabled/disabled by setting/clearing enable bit TXIE(PIE1). Flag bit TXIF will be set, regardless of the state of enable bit TXIE
andcannot be cleared in software. It will reset only when new data is loaded into
the TXREG register.
While flag bit TXIF indicated the status of the TXREG register, another bit,
TRMT (TXSTA), shows the status of the TSR register. Status bit TRMT is a
read only bit, which is set when the TSR register is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to determine if the TSR
register is empty.
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6.13.3 To set up an asynch ronou s transmissio n:
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed
baud rate is desired, set bit BRGH
2. Enable the asynchronous serial port by clearing bit SYNC and setting bit
SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as
address/data bit.
5. Enable the transmission by setting bit TXEN, which will also set bit TXIF.
6. If 9-bit transmission is selected; the ninth bit should be loaded in bit TX9D.
7. Load data to the TXREG register (starts transmission).
USART TRANSMIT BLOCK:
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6.13.4 USART Asyn chro nous Receiver:
The receiver block diagram is shown in Figure The data is received on the
RC7/RX/DT pin and drives the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the baud rate; whereas the
main receive serial shifter operates at the bit rate or at FOSC. This mode would
typically be used in RS-232systems. To set up an Asynchronous Reception:
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed
baud rate is desired, set bit BRGH
2. Enable the asynchronous serial port by clearing bit SYNC and setting bit
SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is complete and an interrupt will be
generated if enable bit RCIE was set.7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any
error occurred during reception.
8. Read the 8-bit received data by reading the RCREG register.
9. If any error occurred, clear the error by clearing enable bit CREN.
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10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register
(INTCON) are set.
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6.14 LEVEL CONVERTER MAX 232:
Operates
1.0-F Charge-Pump
CapacitorsOperates up To 120 Kbit/s
Two Drivers and Two Receivers 30-
V Input Levels Low Supply Current
...8 mA Typical ESD Protection
Exceeds JESD 22 2000-V Human-
Body Model (A114-A) Upgrade with
Improved ESD (15-kV HBM) and 0.1-
F Charge-Pump Capacitors is
Available with the MAX202
Applications TIA/EIA-232-F,
Battery-Powered Systems,
Terminals, Modems, and Computers.
The MAX232 is a dual driver/receiver that includes a capacitive voltage
generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each
receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers
have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept
30-V inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F
levels
6.15 VOLTAGE REGULATOR (7805):
A voltage regulatoris designed to automatically maintain a
constant voltage level. A voltage regulator may be a simple "feed-forward" design
or may include negative feedback control loops. It may use anelectromechanical mechanism, or electronic components. Depending on the
design, it may be used to regulate one or more AC or DC voltages.
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3-Terminal Regulators
Output Current up to 1.5 A
Internal Thermal-Overload Protection High Power-Dissipation Capability
Internal Short-Circuit Current Limiting
Output Transistor Safe-Area Compensation
This series of fixed-voltage integrated-circuit voltage regulators is designed for a
wide range of applications. These applications include on-card regulation for
elimination of noise and distribution problems associated with single-point
regulation. Each of theseregulators can deliver up to 1.5 A of output current. The
internal current-limiting and thermal-shutdown features of these regulators
essentially make them immune to overload. In addition to use as fixed-voltage
regulators, these devices can be used with external components to obtain
adjustable output voltages and currents, and also can be used as the power-pass
element in precision regulators.Load regulation is the change in output voltage
for a given change in load current (for example: "typically 15 mV, maximum
100 mV for load currents between 5 mA and 1.4 A, at some specified
temperature and input voltage.
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6.16 REGULATOR FOR SD CARD (LM1117):
Available in 1.8V, 2.5V, 2.85V,
3.3V, 5V, and Adjustable
Versions
Space Saving SOT-223 and
LLP Packages
Current Limiting and Thermal
Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117: 0C to 125C
LM1117I: 40C to 125C
The LM1117 is a series of low
dropout voltage regulators with a
dropout of 1.2V at 800mA of load
current. It has the same pin-out as
National Semiconductor's industry
standard LM317. The LM1117 is
available in an adjustable version,
which can set the output voltage
from 1.25V to 13.8V with only two
external resistors. In addition, it is
also available in five fixed voltages,
1.8V, 2.5V, 2.85V, 3.3V, and 5V. The
LM1117 offers current limiting and
thermal shutdown. Its circuit includes
a zener trimmed band gap reference
to assure output voltage accuracy to
within 1%.
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6.17 BLOCK DIAGRAM:
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6.18 WORKING OF THE PROJECT:
This Project requires two PIC18F452 microcontrollers in order to
handle two SD cards. Because PIC18452 microcontroller having single SPI
module and each SPI module can handle only one SD card.
Here we represent microcontroller which is reading the data from SD card named
as TX PIC and microcontroller which writes the data to SD card named as RX
PIC.
The Source memory card is
connected to TX PIC. The
microcontroller first initializes the SD
card into SPI mode. After successful
initialization process the TX PIC
reads the data from starting sector of
the SD card and each sector having
512Bytes.
Even though SD card sends one
byte of data at an instant and at the
same time TX PIC stores the 8bits of
data sequentially in the internal
RAM. Up on receiving 512th Byte
from SD card. The microcontroller
stops reading operation. Then TX
PIC ready to transfer 512Bytes of
data to the RX PIC microcontroller.
Figure: Reading data from SD card
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After successful reading operation from source SD card the TX PIC is
ready to transfer the data to the RX PIC, in advance the USART in TX PIC is
configured as transmitter and USART in RX PIC is configured as receiver.
So that TX PIC transmits 512bytes of data in the form of 8bits at an instant
in a serial fashion which is stored in internal RAM. Then RX PIC receives
512Bytes sequentially as Byte by Byte and stores into its internal RAM shown in
above figure. Here level converter increases the voltage levels of every
transmitting binary bit by TX PIC.
So it is clear that there is no attenuation while transmitting data to RX PIC
this makes data transmission is done without having any errors. Any error
correction and detection codes are not required if level converters are used and it
is applicable for only short distance only.
Up on receiving 512Bytes the RX PIC ready to perform write operation on
first sector or according to the address mentioned in the program to the
destination SD card.
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The RX PIC transmit 512Bytes in internal RAM to SPI module Byte
by Byte and then SPI module sends 512Bytes of data to the same sector as in
the Source SD card to the Destination SD card. After successful writing operation
of 512bytes RX PIC sends Acknowledgement to the TX PIC. It informs that one
sector is completed so that another sector can start to read from the Source SD
card this Process is repeated until the final sector of the Source SD card. Finally
data in the Source SD card is completely transferred to destination memory card.
Figure: Wri t ing data into SD card
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