24.4 An Auto -Sellectable-Frequency Pulse-WidthModulator for Buck Converters with Improved Light-Load Efficiency

Tsz Yin Man, Philip K. T. Mok, Mansun ChanThe Hong Kong University of Science and Technology, Kowloon, Hong KongIn order to be useful for mobile systems, the switching frequenciesof modern buck converters (BCs) are in the MHz- or even GHz-range to enable the use of compact off-chip inductors andcapacitors [1], or even on-chip Ls and Cs [2]. However, such highswitching frequencies increase both the switching loss and thegate-drive loss, and degrade BC light-load efficiency since theselosses are independent of load current. Pulse-frequency modulation(PFM) is known to improve light-load efficiency by scaling theswitching frequency with the load current so that the switchingloss and the gate-drive loss are reduced with decreased loadcurrent. However, PFM makes the BC output spectrum changewith the load current. This unpredictable spectrum causes supply-integrity to be an issue in mobile systems where differentspectrum-sensitive circuits, such as communication ICs, are oftenused. Recently, the light-load efficiency of BCs operating at aconstant switching frequency in MHz range have been improved [3,4]. However, the methods used only reduce the gate-drive loss,which is the power required to switch the power PMOS and NMOStransistors (Mp and MN in Fig. 24.4.1), but not the switching loss,which is the power needed to switch the switching node (Vx in Fig.24.4.1). BC light-load efficiency can only be greatly improved whenthese two losses are simultaneously reduced.In this work, an auto-selectable-frequency pulse-width modulator(ASFPWM) is introduced to enable BCs to use compact off-chip Lsand Cs and to minimize both the switching loss and the gate-driveloss without causing a supply-integrity problem. ASFPWM auto-matically selects the BC switching frequency (fs) based on its loadcurrent (ILOAD) fs is chosen from a set of pre-defined frequencies,which are all binary-weighted multiples of a fundamentalfrequency fD (e.g., fs = 2'fD, where i = N...N, andN is a finite positiveinteger). As shown in Fig. 24.4.1, the spectral components of theoutput, VOUTTf) of a BC with ASFPWM are all located at multiplesoffD regardless of ILOAD Therefore, the spectrum of such a BC is aspredictable as one with pulse-width modulation (PWM) at f and,even though fs is scaled with ILOAD, supply-integrity is not aproblem in ASFPWM. Furthermore, the light-load efficiency isgreatly improved as the switching loss and gate-drive loss aresimultaneously reduced with decreasing ILOAD. Compact off-chip Lsand Cs can be used by designing the maximum fs ofASFPWM tobe in the MHz range (e.g. [fs]max = 2%fD)Figure 24.4.1 shows the block diagram of a BC with ASFPWM; itconsists of a frequency selection unit (FSU), a control unit (CU),and an adaptive dead-time unit (ADTU). The FSU automaticallydetermines fs by comparing ILOAD with different thresholds(ILOADTHi, where i = 0...N), each ILOADTH i corresponds to a particu-lar switching frequency (e.g., 2fD). The FSU produces the clocksignal (VcLK) based on the selected fs. The CU regulates the BCoutput (VOUT) and keeps it close to the reference voltage (VREF) bycontrolling the duty-cycle of the PWM signal (VPWM). The ADTUadaptively adjusts the dead-time between the gate signals drivingMp (VGp) and MN (VGN) so that cross conduction is prevented whilebody-diode conduction and charge sharing loss [5] are minimized.The ADTU enables a synchronous BC to operate in thediscontinuous-conduction mode (DCM) to further improve light-load efficiency.Figure 24.4.2 shows the schematic of the FSU. The load current ofthe BC is obtained by sensing the inductor current, IL, with an on-chip current sensor that produces a voltage, VSEN, by forcing acurrent, IsEN, which is proportional to IL, through the resistor RsEcN.The voltage VSEN is compared with two thresholds (VTHP and VTHM)using two comparators (CMPp and CMPm). By designing the BC toonly perform auto-frequency selection in DCM, one fixed threshold(e.g., VTHm) is enough to represent different ILOADTH i for different

s based on the following rrelationships

where L is the inductor, k is the scaling factor of the current sensor,VBAT is the input voltage andM is the voltage conversion ratio. TheFSU as implemented can compare ILOAD with different ILOADTH_without a sophisticated load-current sensor or multiplecomparators so that the design complexity and power consumptionare reduced. Moreover, VTHP can be used to set the maximumallowable inductor current so that output ripple of the BC in DCMcan be well managed. Based on the outputs of comparators storedin the RS-latches, f/ is changed by the finite-state machine (FSM)at the beginning of each cycle. For example, fs is increased, ordecreased, when VSEN is larger, or smaller, than VTHP, or VTHM,respectively. Once VSEN is in between VTHP and VTHM, the FSMmaintains the same fs. The RS-latches are reset on the falling-edgeof VCLK to prepare for sensing the remaining cycle.

Figure 24.4.3 shows the schematic of the ADTU. Adaptive dead-time is provided by the comparator (CMP), which is modified fromthe one in [5]. Transistors M21, M22, M31 and M32 provide the CMPwith push-pull driving and multiple feed-forward paths to improveits response time. MN is turned on when the CMP detects that Vxis just below ground in both DCM and continuous-conduction mode(CCM). An RS-latch with falling-edge reset is used to turn MN offfor the remaining cycle in DCM. Mp is turned on at the falling-edgeof VCLK in DCM. In CCM, MN is turned off by VCLK through thereset-dominated (RD) RS-latch and MP is turned on once MN isfully turned off. Regardless of whether DCM or CCM is used, Mp isturned off when Vpwm from the CU is a logic one.

The BC with ASFPWM was implemented in a 0.35cm CMOSprocess with 1.4mM2 chip area and is able to provide a regulatedoutput of 0.9V with 5OOmA maximum output current for an inputin the range from 1.8 to 3V. The fD of the ASFPWM is chosen to be250kHz to improve light-load efficiency. Four pre-definedfrequencies are used (fs = 250kHz, 500kHz, 1MHz, or 2MHz). A2.2f1 off-chip L and a 2.2uF off-chip C are used to reduce area.Figure 24.4.4 shows the measured efficiency of the BC withASFPWM and the corresponding fs as a function of ILOAD Theefficiency of the same BC operated with PWM and f, = 2MHz isincluded as a reference. It is seen that efficiency of the BC withASFPWM is improved once fs is hopped to a lower value with areduced ILOAD At ILOAD = 10mA, the efficiency is about 70%, whichis significant for battery-powered mobile systems since they areoften in the standby mode. Compared to a PWM BC, the efficiencyis improved by about 25% in the light-load regime (e.g. ILOAD = 5 tolOmA). Figure 24.4.5 shows the measured output spectra of the BCwith ASFPWM for different values of ILOAD Experimental resultsprove that ASFPWM can confine all the BC output spectralcomponents to multiples of fD which is 250kHz in this design,regardless of the value of ILOAD Figure 24.4.6 shows measuredVOUT, VX and inductor current (IL) for the BC with ASFPWM atdifferent values of ILOAD The peak-to-peak output ripple voltage iswell managed to below 30mV for different values of ILOADn An insetin Fig. 24.4.6 shows that ADTU minimizes the conduction time ofthe MN body diode to about 4ns when ILOAD = 5OOmnA. The chipmicrograph is shown in Fig. 24.4.7.Acknowledgment:This work was supported by the Research Grant Council of Hong Kong SARGovernment, China, under Project 617705. Moreover, the authors would like tothank Allen Ng and S. F. Luk for their technical support.

References:[11 P Hazucha, G. Schron, J. Hahn et al., "A 233-MHz 80%-87% EfficientFour-Phase DC-DC Converter Utilizing Air-Core Inductors on Package," IEEEJ. Solid-State Circuits, pp. 838-845, Apr. 2005.[21 M. Alimadadi, S. Sheikhaei, G. Lemieux et al., "A 3GHz Switching DC-DCConverter Using Clock-Tree Charge-Recycling in 90nrm CMOS with IntegratedOutput Filter," ISSCC Dig. Tech. Papers, pp. 532-533, 2007.[31 S. Musunuri and P Chapman, "Inprovement of Light-Load EfficiencyUsing Width-Switching Scheme for CMOS Transistors," IEEE PowerElectroniics Letters, pp. 105-110, Sept. 2005.[41 M. D. Mulligan, B. Broach and T. H. Lee, "A 3MHz Low-Voltage BuckConverter with Improved Light Load Efficiency," ISSCC Dig. Tech. Papers, pp.528-529, 2007.[51 T. Y Man, P K. T. Mok and M. Chan, "A CMOS-Control Rectifier forDiscontinuous-Conduction Mode Switching DC-DC Converters," ISSCC Dig.Tech. Papers, pp. 358-359, 2006.

'LOADTH i-'Lf(VTHmk R5sEN and f s =2fD (1)2VBlATM(M M1)

VTHP 4

VUUT()tLOAD = /4

_ AT + 'LOAD 1/3

_ /[ /F , /'LOAD= 12

_ t + 4 A A A A 'LOAD 1

fD 2fD 3fD 4fD 5fD 6fD 7ND 8fD Freq.

Figure 24.4.1: Block diagram of the BC with ASFPWM.

Comparator (CMP).....................................................................................................................

IB ! 22: :~~~~~~ ,fD

,2fD Time

n n -O

4fD Time

h n n n n -OT+8fD Time

Time

Figure 24.4.2: Schematic of the frequency selection unit.

1-1

C.,

a

.,

w

*VGP

Figure 24.4.3: Schematic of the adaptive dead-time unit.

Feak - 'LOAD = 2OmA, f = 500kHz LOAD = 500mA, f = 2MHz

dt dBt/

RWI WII 128

Figure 24.4.5- Measured output spectra of the BC with ASFPWM.

2.0

1.75- 1.5I 1.25-

1.0-

0.75-

0.5

0.25

10 100

'LOAD (mA)Figure 24.4.4. Measured efficiency and switching frequency of the BC withASFPWM.

'LOAD = 10mA 'LOAD = 4OmAVOUT t50mv VOUT 50mV

4K12V 1f t L2Lxi t j iA ]A JI 11 sL L a2Ls.1A

2.5ps

= ,05.1A

O.5yLs

/LOAD -= 20mA /LOAD -~500mA.,4 . , ErVOUT t50mV VOUT t20mV

$l2fJLXn2V vx2V

'L0. 2 A .2A

1 IL.1AA -

1pis 0.25[is

Figure 24.4.6: Measured time-domain responses of the BC with ASFPWM.

Continued on Page 626

85 -

ASFPWM

75 \65-

55

45

35 . . *PWM@2MHz VBAT=3V

VOUT = 0.9V

Figure 24.4.7: Chip micrograph of the BC with ASFPWM.