sembt4 arch cpu

8/13/2019 Sembt4 Arch Cpu

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Maths is not everything


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CPU

PC

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memory

address

IR

data

ADD r5,r1,r3200

ADD r5,r1,r3


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CPU

PC

data memory

program memory

address

data

address

data


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header LDR r1,[r4]

SUB r0,r0,r1 ;3 addresses instruction MOV sp,#INIT_SP ; set-up stack pointer ADR lr, start+1 ; Processor starts in ARM state,

BX lr ; so small ARM code header used; to call Thumb main program.

CODE16 ; Subsequent instructions are Thumb.

start

;**********************************************************************;* This an example of 16 bits code (Thumb mode);**********************************************************************

BL irq_init ; init. interruptsforever BL seg_rot ; check display of hex digits MOV r0,#0xf

BL leds_on ; sw on the ledschksw0 BL sw_rd ; read DIP_SW port, r0 carries word AND r0,r0 ; check if any DIP_SW has been mod. BEQ chksw0 ; if not, keep checking


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MOV.w #0x05,R5 ; move source to destination

; assign a hexadecimal value 0x05 to Register R5

MOV.w #0x03,R6 ; move source to destination

; assign a hexadecimal value 0x03 to Register R6

CMP.w R6, R5 ; compare source to destination

; R5-R6 = 5-3 = 2 greater than 0, so R5 > R6

JNEsomewhere ; jump if not equal

; The program will jump to somewhere because R5 "R6


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r0

r1

r2r3

r4

r5

r6

r7

r8

r9

r10r11

r12

r13r14

link reg. in BL

r15 (PC)

CPSR

31 0

N Z C V

Status Register

sp for procedure linkage


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byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3

bit 31 bit 0 bit 31 bit 0

little-endian big-endian


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Processor CoreThe engine that fetches instructions and execute themE.g.: ARM7TDMI, ARM9TDMI, ARM9E-S

CPU CoreConsists of the ARM processorcore and some tightly coupledfunction blocks

Cache and memorymanagement blocks

E.g.: ARM710T, ARM720T,ARM74T, ARM920T, ARM922T,ARM940T, ARM946E-S, andARM966E-S ARM710T


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AND, ORR, EOR

BIC : bit clear

LSL, LSR : logical shiftleft/right

ASL, ASR : arithmetic

shift left/right

ROR : rotate rightRRX : rotate right

extended with C


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Carry bitC

Zero bitZ

Negative bitN

General interrupt enableGIE

Turns off the CPU.CPUOFF

Oscillator offOSCOFF

Turns off the DCO dc generator.SCG0

Turns off the SMCLK.SCG1

Overflow bitV

R3 (CG2) Constant Generator

R4-R15 General Purpose registers


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1111

1110

1101

1100

1011

1010

10011000

0111

0110

0101

0100

0011

0010

0001

0000

4 to 16

Decoder

Op-code Op-code Instruction Format

0000 UndefinedSingle Operand

0001 RCC, SWPB, RRA, SXT, PUSH, CALL, RETI

0010 JNE, JEQ, JNC, JCJumps

0011 JN, JGE, JL, JMP

0100 MOV

Double Operand

0101 ADD

0110 ADDC

0111 SUBC1000 SUB

1001 CMP

1010 DADD

1011 BIT

1100 BIC

1101 BIS

1110 XOR

1111 ANDRMR2012


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Memory0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 mov.w r5,r4

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 rrc.w r5

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 jc main

0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 mov.w #0x0600,r1

0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

PC

Instruction Register15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0


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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code S-reg Ad b/w As D-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code b/w Ad D/S-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code Condition 10-bit, 2s complement PC offset


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Mnemonic Operation Description

Arithmetic instructionsADD(.B or .W) src,dst src+dstdst Add source to destinationADDC(.B or .W) src,dst src+dst+Cdst Add source and carry to destinationDADD(.B or .W) src,dst src+dst+Cdst (dec) Decimal add source and carry to destinationSUB(.B or .W) src,dst dst+.not.src+1

dst Subtract source from destinationSUBC(.B or .W) src,dst dst+.not.src+Cdst Subtract source and not carry from destinationLogical and register control instructions

AND(.B or .W) src,dst src.and.dstdst AND source with destinationBIC(.B or .W) src,dst .not.src.and.dstdst Clear bits in destinationBIS(.B or .W) src,dst src.or.dstdst Set bits in destinationBIT(.B or .W) src,dst

src.and.dst

Test bits in destination

XOR(.B or .W) src,dst src.xor.dstdst XOR source with destinationData instructionsCMP(.B or .W) src,dst dst-src Compare source to destination

MOV(.B or .W) src,dst srcdst Move source to destination


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Mnemonic Operation Description

Logical and register control instructions

RRA(.B or .W) dst MSBMSB!LSBC

Roll destination right

RRC(.B or .W) dst CMSB!LSBC Roll destination right through carrySWPB( or .W) dst Swap bytes Swap bytes in destination

SXT dst bit 7bit 8!bit 15 Sign extend destinationPUSH(.B or .W) src SP-2SP, src@SP Push source on stackProgram flow control instructions

CALL(.B or .W) dst SP-2SP,PC+2@SPdstPC

Subroutine call to destination

RETI @SP+SR, @SP+SP Return from interrupt


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Op-coderrc

b/w16-bits

AdRegister

D-regr5

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1


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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code Condition 10-bit, 2s complement PC offset


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Op-codeJC

ConditionCarry Set

10-Bit, 2s complement PC offset

-28

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0


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add.w r4,r10 ;r10 = r4 + r10

Registers

CPUMemory

ADDER

PCPC

R10

R4

IRDataBus(1cycle) 0x540a

0x540a

Addres

sBus

PC

ALU


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Memory

Registers

DataBus(+1cycle)

CPU

ADDER

PCPC

R10

R4


Addres

sBus

PC0x543a

Ad

dress

Bus

0002

ALU

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add.w @r4+,r10 ;r10 = M(r4+) + r10


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Memory

Registers

AddressBus

DataBus(+1cycle)

DataBus(+1cycle)

CPU

ADDER

0x000cPCPC

PC

PC

R10


Addres

sBus

0x501aPC

ALU

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add.w cte,r10 ;r10 = M(cte) + r10


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Memory

Registers

AddressBus

DataBus(+1cycle)

DataBus(+1cycle)

CPU

ADDER

0000

0xc018PCPCPC

R10


Addres

sBus

0x521aPC

ALU

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add.w &cte,r10 ;r10 = M(cte) + r10


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Memory

Registers

CPU

ADDER

PCPC

PC

R10

DataBus(+1cycle)


Addres

sBus

PC0x503a

0x0064

ALU

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add.w #100,r10 ;r10 = #100 + r10


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Registers

CPU

ADDER

PCPC

R10

0000

0001

0002

0004

0008

ffff


Addres

sBus

PC0x531a

ALU

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add.w #1,r10 ;r10 = #1 + r10


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Memory

Registers

AddressBus

Data Bus (+1 cycle)

DataBus(+1cycle)

CPU

ADDER

0x000c

PCPC

PC

Address Bus

Data Bus (+1 cycle)

DataBus(+1cycle)

PC Data Bus (+1 cycle)0x0218


Addres

sBus

0x501a PCPC

ALU

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add.w cte,var ;var = M(cte) + M(var)


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Example Src Dst Cycles Length

add R5,R8 Rn Rm 1 1

add @R5,R6 @Rn Rm 2 1

mov @R5+,R0 @Rn+ PC 3 1add R5,4(R6) Rn x(Rm) 4 2

add R8,EDE Rn EDE 4 2

add R5,&EDE Rn &EDE 4 2

add #100,TAB(R8) #n x(Rm) 5 3

add &TONI,&EDE &TONI &EDE 6 3

add #1,&EDE #1 &EDE 4 2RMR2012


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sembt4 arch cpu

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