semiconducttor memories(97 2003)

7/27/2019 Semiconducttor Memories(97 2003)

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A Seminar on

Semiconductor

memories


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OVERVIEW

1) Introduction2) Requirements3) Configuration of Memory Chip

4) Semiconductor memory classification5) Periphery

DecodersSense Amplifiers

Input/output BuffersControl Timing Circuitry

6) Reliability & Yield7) Conclusion


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introduction 1. Data storage essential for processing.2. Binary storage.3. Switches.

4. Random & Efficient access to all memory location.5. Data access is fast so less data access time.6. Data accessed by means of binary memory address

applied to chips address pins.

'0'

'1'Read

Write


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Requirements

1. Easy reading.2. Easy Writing.

3. High density.4. Speed, more speed and still more speed.5. Bulkier data processing.

6. Minimizing the amount of error.


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Memory Chip Configuration

R o w

D e c

Memory Cell Array

Row AddressN bits

Complete Address

N+M Bits

2M

Cells

Din

DoutI/O Controld

in

dout

Column Dec.

2N

CellsWL

DL

Cell

ControlSignals

I / O

I n

t e r f a c e

Column AddressM Bits


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Semiconductor Memory Classification

Read-Write Memory Non-VolatileRead-Write

Memory Read-Only Memory

EPROM E

2 PROM

FLASH

Random Access

Non-Random Access

SRAM

DRAM

Mask-Programmed Programmable (PROM)

FIFO

Shift Register CAM

LIFO


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RAM 1. Random write and read operation for any cell2. Volatile data3. Most of computer memory4. DRAM

Low Cost High DensityMedium Speed

5. SRAMHigh SpeedEase of useMedium Cost


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1-Transistor DRAM Cell

C S M 1

BL

WL

C BL

WL

X

BL

V DD V T

V DD /2

V DD

GND

Write "1" Read "1"

sensing V DD /2

V V BL V PR E V BI T V PR E C S

C S C BL+------------------------= =

Write: C S is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.


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6-transistor CMOS SRAM Cell

V DD

QQ

M 1 M 3

M 4 M 2

M 5

BL

WL

BL

M 6


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ROM 1. Non-volatile Data2. Method of Data Writing3. Mask ROM

Data written during chip fabrication4. PROM

Fuse ROM: Non-rewritableEPROM: Erase data by UV rays

EEPROM: Erase and write through electrical meanso Speed 2-3 times slower than RAMo Upper limit on write operationso Flash Memory High density, Low Cost


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Examples of ROM

Fuse ROM EEPROM

WL

DL

WL

DL

Floating Gate


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Characteristics of Different NVM


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Non-Volatile Memories The Floating-gate transistor

(FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n + n +_ p

t ox

t ox

Device cross-section Schematic symbol

G

S

D


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Floating-Gate Transistor Programming

0 V

- 5 V 0 V

D S

Removing programmingvoltage leaves charge trapped

5 V

- 2.5 V 5 V

D S

Programming results in higher V T .

20 V

10 V 5 V 20 V

D S

Avalanche injection


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Periphery

DecodersSense AmplifiersInput/output BuffersControl / Timing Circuitry


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Row Decoders

Collection of 2M

complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


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Hierarchical Decoders

A 2 A 2

A 2 A 3

WL 0

A 2 A 3 A 2 A 3 A 2 A 3

A 3 A 3 A 0 A 0

A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1

A 1 A 1

WL 1

Multi-stage implementation improves performance

NAND decoder using2-input pre-decoders


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Sense Amplifiers

t p C V

I av ---------------- =

make V as small as possible

small large

Idea: Use Sense Amplifer

output input

s.a. small transition


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Sense Amplifiers Operation

D V (1)

V (1)

V (0)

t

V PRE

V BL

Sense amp activated Word line activated


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Differential Sense Amplifier

Directly applicable toSRAMs

M 4

M 1

M 5

M 3

M 2

V DD

bit bit

SE

Out y


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Latch-Based Sense Amplifier

VDD

BL

SE

SE

BLEQ

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.


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Reliability and Yield


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CONCLUSION Use of microprocessor controlled items hasincreased with time, so the requirement of semi conductor memory has increased.It is the additional driver, that has made thesoftware associated with computers moresophisticated .


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REFERENCES 1) Sedra & Smith, Microelectronic Circuits, 4 th

Edition, Chapter 13 Section 13.9, 13.10, 13.11, 13.12

2) VLSI Memory Chip Design, Kiyoo Itoh


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semiconducttor memories(97 2003)

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