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Seminar on Architectures and Design Methods for Embedded Systems

Seminar Topic Architecture of the ARM Processor Family

Submitted By Sambhavi Parajuli

2nd Semester, INFOTECH University of Stuttgart

Under the Supervision of Dominik Lücke

Submitted Date 19th July 2006

Seminar Paper on Architectures and Design Methods for Embedded Systems

Table of Contents

Abstract Paper Structure

1. Introduction ---------------------------------------------------------------------1 2. The ARM Organisation-------------------------------------------------------2

2.1. The ARM Components ---------------------------------------------------2 2.2. The ARM Pipeline --------------------------------------------------------2 2.3. The ARM Processor Mode -----------------------------------------------3

3. The Components of the ARM Processor-----------------------------------4 3.1. The ARM Registers-------------------------------------------------------4 3.2. The Banked Registers ----------------------------------------------------4 3.3. Current Program Status Register ----------------------------------------5 3.3.1. Interrupt Mask-----------------------------------------------------5 3.3.2. Condition Flags ---------------------------------------------------5 3.3.3. Instruction Set Design--------------------------------------------5 3.3.4. Interrupt and Exceptions -----------------------------------------6

4. The ARM Processor Families ------------------------------------------------7 4.1. The ARM7 Family---------------------------------------------------------7 4.2. The ARM9 Family---------------------------------------------------------9 4.3. The ARM10 Family -------------------------------------------------------10 4.4. The ARM11 Family -------------------------------------------------------11 5. Types of Instruction Supported by the ARM Processors --------------12 5.1. Data Processing Instructions ---------------------------------------------12 5.1.1. Arithmetic Instructions--------------------------------------------12 5.1.2. Move Instructions -------------------------------------------------12 5.1.3. Bit-wise Logical Instructions ------------------------------------13 5.1.4. Comparison Instructions------------------------------------------13 5.1.5. Multiply Instructions ----------------------------------------------13 5.2. Branch Instructions --------------------------------------------------------14 5.3. Load/Store Instructions ---------------------------------------------------14 5.3.1. Single Register Transfer Instructions --------------------------14 5.3.2. Multiple Register Data Transfer Instructions -----------------15 5.3.3. Swap Instructions -------------------------------------------------16 5.4. Software Interrupt Instruction--------------------------------------------16 5.5. Program Status Register Instructions------------------------------------17 5.6. Coprocessor Instructions--------------------------------------------------17 6. Conclusion -----------------------------------------------------------------------18

References Abbreviations

Created by sambhavi Architecture of the ARM Processor Family i

Chapter 1: Introduction

Abstract

This article is about the architecture of ARM processors, which is a RISC design. It includes the history of development of ARM processors, the organisation of the ARM components, and different types of registers, modes, pipelines and instruction sets supported by the ARM processors. It also gives the outlines of the development of wide range of ARM processor families incorporating different types of technology, which provide benefits in the area of power consumption, system cost, development cost, time-to-market and performance. Thus the enhancement made in the development of the ARM processors has provided to create an innovative product design such as portable devices, automotive and industrial control devices and security critical applications.

Paper Structure

Chapter 1 starts with introduction of the ARM processor. It also includes features of the ARM processors. Chapter 2 describes the ARM components and the internal organization of the ARM processor. It also introduces the ARM pipeline and the ARM processor mode. Chapter 3 describes the components of the ARM processor that includes the ARM registers, banked registers and program status registers. It also describes condition flags, instruction set design and interrupt and exceptions available in the ARM processor. Chapter 4 introduces development of wide range of the ARM processor families based on various design techniques. Chapter 5 introduces the different types of instruction supported by the ARM processor. It describes six different types of the ARM instructions. Chapter 6 has conclusion of this paper. Finally, a list of references and abbreviations are included in this paper. 1. Introduction

The first Acorn RISC Machine (ARM) processor was developed at Acorn Computers Limited in 1985. In the late 80’s Apple Computer started working with Acorn on a new version of Arm core. In 1990 Acorn together with Apple Computer and VLSI Technology Inc. established a new company named Advanced RISC Machines (ARM) Limited. ARM Ltd adopted RISC technology to design the ARM processors, which have benefits such as high performance, low power consumption, low-cost, and low silicon area. ARM Ltd. developed ARM6 for the first time. The evolution of the architecture of ARM processor has continued since the first processor, with the significant architecture enhancements from the original architecture. The following Berkeley RISC design features are found in the ARM architecture.

• A large register file • A load and store architecture, where data processing is carried out solely in registers, the core

cannot directly manipulate data in memory. All data manipulation must be done by loading registers with information located in memory performing data operation and then storing the result back to memory.

• Uniform and fixed-length instruction fields • Simple addressing modes

Some of the RISC design features are rejected in the ARM architecture.

• Register windows • Delay branches • Single cycle execution of instructions

The ARM architecture includes some other features besides the features mentioned above.

• Arithmetic Logic Unit (ALU) and 32-bit barrel shifter • Auto increment and auto decrement addressing • Conditional execution of instruction reducing branch overhead i.e. reducing pipeline flushing

and increase execution speed

Created by sambhavi Architecture of the ARM Processor Family 1

Chapter 2: The ARM Organization

2. The ARM Organization The ARM Processor is either based on Von Neumaan architecture or Harvard architecture. In Von Neumann architecture data items and instructions share the same bus whereas in Harvard architecture data items and instructions use separate buses. ARM7 is based on Von Neumann architecture. However, the ARM processors after ARM9 onwards are based on Harvard architecture. 2.1 The ARM Components The ARM components are as follows:

• The register bank • The barrel shifter that can shift/rotate an operand by number of bits in a single operation. • The Arithmetic Logic Unit (ALU) for the arithmetic and logic operations • The address register and incrementer and the memory data registers • The instruction decoder which translates instructions before they are executed and control

logic

Figure 1: The internal organization of the ARM processor [17] Most of the ARM instructions typically have two source registers and a single result or destination register. However, move, comparison and branch instructions do not support such 3-address format. The source operands are read from register bank using the internal buses A and B respectively. The second operand, which is passed to the barrel shifter through the internal bus B, is shifted by wide number of bits in an operation. Then the ALU takes the registers values from the internal bus A and barrel shifter and computes the result. The data processing instructions write the result directly to the destination register of the register bank using the ALU bus. The load and store instructions use the ALU to generate an address, which is sent to the address register using the ALU bus. The PC value in the address register is incremented before the next register value from or to the next memory location is read or written. This process continues until the interrupt or exception occurs. 2.2 The ARM Pipeline The ARM processors utilize pipeline mechanism to increase execution speed. The pipeline design of each processor family is different. The ARM7 uses a simple three-stage pipeline. It consists of fetch, decode and execute stages. In the fetch stage the instruction is read from the memory and in the decode stage the instruction is decoded


Chapter 2: The ARM Organization

to build the control signal. The register bank is read, the operand is shifted and the ALU operation is performed. The result is finally written back to the register bank. As shown below in figure 2, the instruction is fetched from the memory in the first cycle t, then in the second cycle t+1, the first instruction is decoded and the next instruction is fetched. In the third cycle t+2, the first instruction is executed, the second instruction is decoded and the third instruction is fetched. The pipeline permits the processor to execute an instruction in each cycle. I i I=instruction i+1 i+2

Fetch Decode Execute



t t+1 t+2 t+3 t+4 cycle Figure 2: ARM7 Three-stage pipeline

The ARM9 core supports a five-stages pipeline. The five-stage pipeline has a separate memory and write back stages in addition to fetch, decode and execute stages. The memory stage is used to access memory for load and store instruction and write back stage is used to write result back to register file. As the pipeline length increases the amount of work done per clock is reduced which allows the higher clock frequency. Thus in turn increases the performance.

Decode Execute Memory Write Fetch

Figure 3: ARM9 Five-stage pipeline [1] The ARM10 core supports a six-stage pipeline by adding issue stage between fetch and decode stages. The ARM10 core allows the higher clock frequency than the ARM7.

Issue Decode Execute Memory Write Fetch

Figure 4: ARM10 six-stage pipeline [1] 2.3 The ARM Processor Mode The ARM architecture supports seven operating modes. There are one user mode and six privileged modes. The user mode is the normal program execution mode. A program that writes directly to the current program status register or when an exception occurs can change the processor mode. The privileged modes are used to handle exceptions and software interrupts which suspend the normal execution of sequential instruction and jump to a specific location. The six privileged modes are abort, fast interrupt request, interrupt request, supervisor, system and undefined. The exceptions and interrupts cause a mode change: reset, interrupt request, fast interrupt request, data abort, prefetch abort, and undefined instructions.

Table 1: Processor mode [1] Processor mode Abbreviation Mode[4:0] Abort Abt 10111 Fast interrupt request Fiq 10001 Interrupt request Irq 10010 Supervisor Svc 10011 System Sys 11111 Undefined Und 11011 User Usr 10000


Chapter 3: Components of the ARM Processor

3. Components of the ARM Processor 3.1 The ARM Registers The Arm processor has 37 registers in total. These include a program counter, six program status registers and 30 general-purpose registers. At any one time only 18 of these registers: 16 data registers and 2 processor status registers are visible depending upon the processor mode. All the registers are 32 bits in size. Each processor mode can use the r0-r12 general-purpose registers, r13: the stack pointer and r14: link register, r15: the program counter and program status register. The general-purpose registers r0-r8 are available no matter which mode is the processor. A few registers r8-r12 are common to all the processor modes except in the fast interrupt request mode. When the processor is in the fast interrupt mode, these registers r8-r12 are replaced with different set of registers r8_fiq-r12_fiq. There are two program status registers: current program status register (cpsr) and saved program status register (spsr). The spsr can only be modified and read in the privileged mode and the cpsr is common to all the modes. However, there is no spsr available in the user mode.

R0 R1 R2 R3 R4 R5 R6 R7 R8 R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq

R13 sp R13_fiq R13_irq R13_svc R13_undef R13_abt R14 lr

R14_fiq

R14_irq

R14_svc

R14_undef

R14_abt R15 pc

Cpsr - spsr_fiq spsr_irq spsr_svc spsr_undef spsr_abt

user and fast interrupt interrupt supervisor undefined abort system request request

Figure 5: Register Organization [1]

3.2 The Banked Registers Out of 37 registers 20 registers are only available when the processor is in a particular privileged mode and these registers are called the banked registers. In other words, the registers are “banked” in privileged mode. However, the system mode does not have banked registers. Each processor mode has banked registers: r13, r14 and spsr with a post fixed character to the mode mnemonic. For example, supervisor mode has banked registers r13_svc, r14_svc and spsr_svc. However, fast interrupt request mode has banked registers: spsr_fiq and r8_fiq -r14_fiq. This is mainly for handling fast interrupt processing without the need to save or restore these registers and therefore minimize the overhead of context switching. Another benefit is since fast interrupt request (FIQ) is the last entry in the vector table, the exception processing can be done without a branch instruction.



When the processor mode is changed, a banked register from the new mode will replace an existing register of the user mode. For example, when there is a mode change from the user mode to the supervisor mode then the user mode registers r13 and r14 are replaced by the banked register r13_svc and r14_svc of the supervisor mode. The banked register r14 contains the current program counter. The cpsr of the user mode is copied to the spsr_svc of supervisor mode. Then the interrupt vector is loaded into the program counter r15 to start exception processing. The original cpsr and program counter are restored back from the banked registers spsr and r14 respectively when the supervisor mode changes back to the user mode. 3.3 Current Program Status Register The current program status register (cpsr) contains the current status of the processor. It is used to monitor and control internal operations. It is 32-bit register. The cpsr has four different fields with 8 bits width each. They are flags, status, extension and control. The saved program status register (spsr) contains the copy of cpsr when a processor enters a new privileged mode. Flags Status Extension Control 31 30 29 28 27 24 7 6 5 4 0 Jazelle Processor DSP Interrupt mask mode condition flags Fast Interrupt mask Thumb state

N Z C V Q J I F T Mode

N=Negative, Z=Zero, C=Carry, V=Overflow

Figure 6: A program status register [1]

3.3.1 Interrupt Mask The ARM processor can control the masking of two interrupts request: interrupt request (IRQ) and fast interrupt request (FIQ). The cpsr has two interrupt disable bits and used for disabling the interrupt request. In figure 6, I and F are interrupt request and fast interrupt disable bits respectively. 3.3.2 Condition Flags The flag field contains the condition code flags namely negative result from ALU flag (N), zero result from ALU flag (Z), ALU operation carry flag (C), and ALU operation overflow flag (V). The flag changes whenever the result of arithmetic and logical operations changes. In some ARM processor there is J bit found in flag field. This is only available in Jazelle-enabled processor, which supports direct bytecode execution of Java. The condition flags are depicted in figure 6. Some processor cores, which support the DSP extension, have Q bit in the flag field. When Q bit is set, then an overflow or saturation has occurred in the DSP instruction. The enhanced DSP extensions include support for saturated arithmetic operations to accelerate signal-processing requirements. The saturated arithmetic operations are count leading zero (CLZ), signed saturated 32-bit or 64-bit add and subtract and signed multiply accumulate 32-bit or 64-bit. These operations are used to saturate the result i.e. set when overflow occurs. 3.3.3 Instruction Set Design The ARM core supports three instruction sets: ARM, Thumb and Jazelle. The ARM instruction set is a standard instruction set, which supports 32-bit instructions. This instruction set is used when the processor is in the ARM state. Most of the ARM instructions support Created by sambhavi Architecture of the ARM Processor Family 5


3-address format and can access all 16 32-bit registers. Most ARM instructions are conditionally executed. Conditional execution depends upon the condition flags of the cpsr and the condition field in the instruction. Before execution, the processor checks the condition field and condition flags in the cpsr. If they match, then the instruction is executed otherwise the instruction is ignored.

Table2: Condition Mnemonic [1]

Mnemonic Name Condition flags EQ Equal Z NE not equal Z CS/HS Carry set/ unsigned higher or same C CC/LO Carry clear/ unsigned lower C MI minus/negative N PL plus/positive or zero N VS Overflow V VC no overflow V HI unsigned higher ZC LS unsigned lower or same Z or c GE signed greater than or equal NV or nv LT signed less than Nv or nV GT signed greater than NzV or nzv LE signed less than or equal Z or Nv or nV AL Always Ignored

The Thumb instruction set supports 16-bit instructions. The ARM processor executes the Thumb instructions only when it is in the Thumb state. Most of the Thumb instructions are executed unconditionally. The instructions are a two-address format and can access only 8 32-bit registers. Some of the features are similar on both the instruction sets. They both support load/store architecture and support for 8-bit byte, 16-bit half word and 32-bit word data type and half words are aligned to 2-byte boundaries and words are aligned on 4-byte boundaries. [16] The Thumb instruction set has lower performance than the ARM (ARM 40%faster) in case of 32-bit memory. However, the Thumb code will be faster than the ARM code by about 45% in case of 16-bit wide memory. It has higher code density and saves around 30% space. [18] The Jazelle instruction set supports 8-bit instructions and allows executing Java bytecode and thus provides high performance. The Jazelle instruction set is not openly available. 3.3.4 Interrupt and Exceptions The ARM processor can be in the user mode or the privileged mode. When an exception occurs then the processor stops normal execution and enters in one of the exception modes. Before switching to a new exception mode, the current program counter is saved into a banked register r14 of the appropriate exception mode. The cpsr is also stored into the spsr of the same exception mode. The mode is changed to the appropriate exception mode. Then the processor loads the program counter at the specific address range, which is in the vector table, depending on the exception type. The vector table contains the branch instruction to handle a particular exception. Once the exception is handled, the program counter and the cpsr are restored from the banked registers r14 and the spsr respectively. Then the processor starts executing in the user mode. The ARM processor will be in the supervisor mode on reset. The ARM processors support seven different types of exceptions as shown in the table 3. Created by sambhavi Architecture of the ARM Processor Family 6

Chapter 4: The ARM Processor Families


Table 3: The interrupt vector table [1]

Exception/interrupt Abbreviation Address High address Reset RESET 0x00000000 0xffff0000 Undefined instruction UNDEF 0x00000004 0xffff0004 Software interrupt SWI 0x00000008 0xffff0008 Prefetch abort PABT 0x0000000c 0xffff000c Data abort DABT 0x00000010 0xffff0010 Reserved - 0x00000014 0xffff0014 Interrupt request IRQ 0x00000018 0xffff0018 Fast Interrupt request FIQ 0x0000001c 0xffff001c

For example: when SWI instruction is executed the software interrupt vector is called. Interrupt request vector is called when the interrupt request (IRQ) bit of the cpsr is not set. When an exception occurs while executing Thumb code, the processor will switch to the ARM mode to handle the exception. The BX instruction is used to change the T bit in the cpsr instead of directly writing to the cpsr. Thus, the processor switches back to the Thumb mode to continue running the Thumb code. reset BCX exceptions end of exceptions BX

ARM

THUMB

ARM

THUMB

ARM

Figure 7: Thumb exception processing [18]

4. The ARM Processor Families The development of ARM processor cores has been continued since 1985. There is a continuous evolution of the architecture of the ARM processors since its first processor by adopting various design techniques such as 16/32-bit RISC architecture, different types of pipelines, DSP and Jazelle technology and memory managements. 4.1 The ARM7 Family The ARM7 family is 32-bit RISC microprocessor. It uses Von Neumann architecture. It also supports 16-bit Thumb instruction set, which enables high code density and offers lower power consumption and high performance. It supports up to 130 MIPS (Dhrystone 2.1) performance on a typical 0.13µm process technology. [6] It has a three-stage pipeline that permits multiple instructions to process at the same time. Codes supported by ARM7 can be migrated to new process technologies hence they are forward compatible with ARM9 and ARM10 and Intel’s Xscale technology allowing reuse of application code. Most of the processors of this family do not support MMU or MPU and cache. The memory management unit (MMU) is used for handling memory accesses needed by the processor, and provides virtual to physical address mapping and controls access permissions. The memory protection unit (MPU) does not do the address translation but instead uses a few number of memory regions, which are controlled with coprocessors registers. [1] Each region has specific access permissions and is mainly used for systems that require limited memory protection. If the processors have memory


management unit then they support many operating systems and RTOS including windows CE, Palm OS and Linux. This family of ARM7 processors offers both synthesisable and hard macro processors. Some processors support core with DSP and Jazelle technology for Java acceleration. ARM7TDMI supports Embedded ICE debug technology and JTAG interface unit and coprocessor interface. ARM720T supports MMU for handling the Linux and Microsoft embedded platform operating systems. ARM7EJ-S supports Jazelle for Java acceleration. “S” means the core is synthesisable. ARM7 processors are widely used in many applications such as portable instruments in hand held data acquisition unit, portable computing in palmtop computer, imaging in JPEG controller and information system in smart card.

Table 4: Performance characteristic of the ARM7 Family [6]

Cache size(Inst/Data)

Tightly Coupled Memory

Memory Mgmt

Thumb DSP Jazelle

ARM720T 8k unified - MMU Yes No No ARM7EJ-S - - - Yes Yes Yes ARM7TDMI - - - Yes No No ARM7TDMI-S - - - Yes No No

ETM Interface

Coprocessor Interface

Control Logic and Bus Interface Unit

ARM v5TEJ

CPU core

Jazelle

ETM Interface Embedded ICE-RT Logic

ARM7TDMI

core

Coprocessor Interface Bus Interface Unit

ARM7TDMI ARM7EJ-S

Figure 8: ARM7TDMI and ARM7EJ-S processors [7] Figure 8 depicts two different types of the ARM7 family processor. The ARM7TDMI is a 32-bit RISC processor, which supports 32-bit ARM instruction set and 16-bit Thumb instruction set. It has unified bus interface and coprocessor interface. It supports extensive debug facilities. It has Embedded ICE- real time debug unit and ETM interface. The ARM7EJ-S is a synthesisable 32-bit RISC processor, which supports DSP operation and Jazelle technology. It also has coprocessor interface, ETM interface for extensive debug facilities and unified bus interface.



4.2 The ARM9 Family The ARM9 family is also a 32-bit RISC processor with ARM and Thumb instruction sets. However, the ARM9 family uses a Harvard Architecture that means it uses separate bus for data and instruction. It supports five-stage pipeline for multiple instructions and therefore the ARM9 processor can run athigher clock frequencies than the ARM7 family. It supports up to 300 MIPS (Dhrystone 2.1) in a typical 0.13µm process technology. [8] They are also portable to 0.18µm, 0.15µm and 0.13µm silicon processes. [8] It supports 4-16k caches, MMU or MPU. The ARM9 family has two subgroups: ARM9 Thumb family and ARM9E family. The ARM9 Thumb family comprises ARM920T and ARM922T having 16k/16k caches and 8k/8k caches respectively and supports operating systems such as Symbian OS, Windows CE, Linux and Palm OS. Both do not support DSP and Jazelle features but use a MMU. They are mainly used in handheld product as such in videophone, PDAs, digital consumer product like set-top boxes, game console, MP3 audio and MPEG4 video and imaging like desktop printer, digital video cameras.

Table 5: Performance characteristic of the ARM9 Thumb Family [8]



Memory Mgmt

Thumb DSP Jazelle

ARM920T 16k/16k - MMU Yes No No ARM922T 8k/8k MMU Yes No No

The ARM9E family processors are also 32-bit RISC processors which supports Thumb instruction set, which provides high code density. This provides saving of memory up to 35% over 32-bit code. [14] It also supports the DSP instruction set extensions, which increase the DSP processing capability thus offering low power consumption and higher performance. It also includes Embedded ICE-RT logic for debugging and tracing facilities for real time system. It has variable size instruction and data caches and instruction and data tightly coupled memory (TCM) interfaces to improve deterministic real time response. TCM is fast on-chip memory that bypasses the cache, has guaranteed low latency and gives the best memory access performance. The ARM926EJ-S processor also includes Jazelle technology, which enables the direct Java Byte code execution. It is designed to use in small portable Java-enabled devices such as mobile phones and PDAs. The ARM9E family processors are used in wide variety of applications in addition to the applications mentioned above for the ARM9 family. They are used in the area of automotive like ABS, powertrain, industrial control systems like motion control, power delivery, networking and storage.

Table 6: Performance characteristic of the ARM9E Family [10]



Memory Mgmt

Thumb DSP Jazelle

ARM926EJ-S Variable Yes MMU Yes Yes Yes ARM946E-S Variable Yes MPU Yes Yes No ARM966E-S - Yes - Yes Yes No ARM968E-S N/a Yes DMA Yes Yes No ARM996H-S MPU Yes Yes No



ETM Interface

ARM9TDMI Core

Coprocessor Interface AMBA ASB Interface

Core


ARM946E-S

Data TCM Interface

Instr. TCM Interface

Write buffer

MPU

Data cache

MPU

Instr, cache

AMBA ASB InterfaceCoprocessor Interface

ARM9E

ETM Interface

Write buffer

ARM920T

MMU

16K Data cache

MMU

16K Instr. cache


Figure 9: ARM920T processor [9] and ARM946E-S processor [11] Figure 9 depicts two different types of ARM9 family processor. The ARM920T is a hard Macrocell having 16k/16k instruction and data caches with MMU, which supports operating systems including Windows CE, Linux and Palm OS. It supports 16-bit Thumb instruction set but does not support DSP operations and Jazelle technology. It has a standard AMBA Bus interface and EMT interface for real time debugging capability and coprocessor interface. The ARM946E-S is a synthesisable 32-bit RISC processor. It has variable size instruction and data caches, instruction and data tightly coupled memory interface, coprocessor interface and a standard AMBA Bus interface. It supports 16-bit Thumb instruction set and DSP operations but does not support Jazelle technology. It uses MPU. 4.3 The ARM10 Family The ARM10 family is also 32-bit RISC processor with ARM, Thumb and DSP instruction sets. It supports six-stage pipelines, which provides the highest MIPS/MHz i.e. 1.35 MIPS/MHz [12] as compared to the ARM7 and ARM9 families. The ARM7 provides 0.97 MIPS/MHz and the ARM9 family provides 1.1MIPS/MHz. [12] It has a floating-point coprocessor, which is IEEE754 standard [1] with vector operations. It also uses Harvard Architecture. . It supports up to 450 MIPS (Dhrystone 2.1) in a typical 0.13µm process technology. [12] They have MMU supporting Windows CE, Symbian OS, Palm OS and Linux. The ARM10E family comprises the ARM1020E and ARM1022E processors with separate 32K/32K and 16k/16k data and instruction caches respectively and the ARM1026EJ-S processor is a fully synthesisable processor, which supports ARM Jazelle technology for Java acceleration. Like other families of ARM processors, the ARM10 family is also portable to 0.18µm, 0.15µm and 0.13µm silicon processes. [12] They are mainly used in handheld product as such in videophone, PDAs, digital consumer product like set-top boxes, game console, laser printer and VOIP telephone, digital video cameras, automotive and industrial control system such as signal processing and motion controls.

Table 7: Performance characteristic of the ARM10E Family [12]



Memory Mgmt

Thumb DSP Jazelle

ARM1020E 32k/32k - MMU Yes Yes No ARM1022E 16k/16k - MMU Yes Yes No ARM1026EJ-S Variable Yes MMU or

MPU Yes Yes Yes



Write buffer

ARM1020E

ETM Interface

MMU

32 Data Cache

MMU

32 Instr. Cache


DataInstr

AMBA Bus Interface Coprocessor Interface

ARM10 Core

Figure 10: ARM1020E processor [12] Figure 10 depicts the ARM1020E processor of ARM10 family. The ARM1020E is 32/16-bit RISC architecture with 32-bit ARM instruction set and 16-bit Thumb instruction set. It has MMU and 32k/32k instruction and data caches. It supports DSP operations but does not support Jazelle technology. It has ETM interface for debugging real time applications. It also has coprocessor interface and dual 64-bit AMBA bus interface. 4.4 The ARM11 Family The ARM11 family is also based on Harvard architecture. It comprises the ARM1136J (F)-S, ARM11 MPCore, ARM1156T2 (F)-S and the ARM1176JZ (F)-S processors, which are designed for high performance applications. It supports up to 740 Dhrystone 2.1 MIPS in 0.13µ process technology. [13] All except ARM1156T2 (F)-S which, uses nine-stage pipeline, use eight-stage pipeline with high frequency clock and have separate load store and instruction pipelines. They use ARMv6 instruction set architecture, which includes single instruction multiple data (SIMD) extension for media processing to accelerate video processing performance. All core except ARM1156T2 (F)-S include the ARM Jazelle extensions for Java bytecode execution but all cores have the DSP extensions. The ARM1156T2 (F)-S supports TrustZone technology for reliable implementation of security critical applications and services. [14] They support operating systems such as Windows CE, Symbian OS and Linux. They use separate cache and tightly coupled memory (TCM). All cores are synthesisable which helps for fast integration of core in system on chip design. The ARM1136JF-S, ARM1156T2F-S and ARM1176JZF-S support optional floating-point coprocessor functions for fast floating point operations.

Table 8: Performance characteristic of the ARM11 Family [13]

Cache

size(Inst/Data)


Memory Mgmt

Thumb DSP Jazelle

ARM11 MPCore Variable - MMU+ Cache

Yes Yes Yes

ARM1136J(F)-S Variable Yes MMU Yes Yes Yes ARM1156T2(F)-S Variable Yes MPU Yes Yes No ARM1176JZ(F)-S Variable Yes MMU+

TrustZone Yes Yes Yes


Chapter 5: Types of Instruction Supported by the ARM Processors

5. Types of Instruction Supported by the Arm Processors The ARM processors support three types of instruction set: the ARM instruction set, the Thumb instruction set and Jazelle instruction set. The Thumb code is typically 65% of the size of the ARM code. [14] The processor can be switched between ARM and Thumb states easily. The processor reads the instruction as 16-bit Thumb instructions if T bit of cpsr is set and if T bit of cpsr is reset, it reads as the ARM instructions. If J bit of cpsr is set then the processor reads the instruction as Jazelle instructions. The ARM instruction set can support six different types of instruction.

• Data processing instructions • Branch instructions • Load/Store instructions • Software interrupt instruction • Program status register instructions • Coprocessor instructions

5.1 Data Processing Instructions: The data processing instructions are used to manipulate data in general-purpose registers. They are five different types of data processing instruction namely arithmetic instructions, move instructions, logical instructions, comparison instructions, and multiply instructions. The data processing instructions employ a 3-address format; they are two source operands and the destination register. The first source operand is always a register and the second source operand is a register, a shifted register or an immediate value. [2] The shift instructions are not found in the ARM processor. However, it uses a barrel shifter to carry out shift operations together with arithmetic and logical operations. Most of the data processing instructions support the barrel shifter. These instructions do not affect the condition flags when suffix S is not used in the instructions. If suffix S is contained in the instructions, then it updates the condition flags. 5.1.1 Arithmetic Instructions: These instructions perform arithmetic operations on two source operands and the destination register contains the result.

Table 9: Arithmetic instructions supported by the ARM processors [3]

Instruction syntax Meaning Action ADD Rd, Rn, op2 Add Rd:=Rn +op2 ADC Rd, Rn , op2 Add with carry Rd:=Rn+op2+C SUB Rd, Rn, op2 Subtract Rd:=Rn-op2 SBC Rd, Rn, op2 Subtract with carry Rd:=Rn-op2+C-1 RSB Rd, Rn, op2 Reserve Subtract Rd:=op2-Rn RSC Rd, Rn, op2 Reserve subtract with carry Rd:=op2-Rn+C-1

Note: Op2 is either an immediate value or register value, or shifted register value. This is also applied to other types of instruction described below. Rn is the source register and Rd is the destination register. 5.1.2 Move Instructions: These instructions move the value of second operand to the destination register.

Table 10: Move instructions supported by the ARM processors [3]

Instruction syntax Meaning Action MOV Rd, op2 Move Rd:=op2 MVN Rd, op2 Move negated Rd:= NOT op2



5.1.3 Bit-wise Logical Instructions: These instructions perform bit-wise logical operations on the two source registers.

Table 11: Bit-wise logical instructions supported by the ARM processors [3]

Instruction Syntax Meaning Action AND Rd, Rn, op2 Logical bit-wise AND Rd:=Rn AND op2 EOR Rd, Rn, op2 Logical bit-wise XOR Rd:=Rn EOR op2 ORR Rd, Rn, op2 Logical bit-wise OR Rd:=Rn OR op2 BIC Rd, Rn, op2 Bit clear Rd:=Rn AND NOTop2

5.1.4 Comparison Instructions: These instructions are used to compare or test a register.

Table 12: Comparison instructions supported by the ARM processors [3]

Instruction Syntax Meaning Action TST Rn, op2 Test Flag set as a result of Rn AND op2 TEQ Rn, op2 Test equivalence Flag set as a result of Rn EOR op2 CMP Rn, op2 Compare Flag set as a result of Rn-op2 CMN Rn, op2 Compare negated Flag set as a result of Rn +op2

5.1.5 Multiply Instructions: These instructions perform integer multiplication on two 32-bit registers and the result is stored in destination register. The result here is also 32-bit.

Table 13: Multiply instructions supported by the ARM processors [3]

Instruction Syntax Meaning Action MUL Rd, Rm, Rs Multiply Rd:=Rm*Rs MLA Rd, Rm, Rs, Rn Multiply and accumulate Rd:=(Rm*Rs) +Rn

The ARM processors support signed and unsigned long integer multiplication (64-bit result) for that they have built-in Multiply accumulate unit (MAC).

Table 14: Signed and unsigned long integer multiplication supported by the ARM processors [3]

Instruction Syntax Meaning Action UMULL RdLi,RdHi, Rm, Rs Unsigned Multiply long RdHi,RdLi:=unsigned(Rm*Rs) UMLAL RdLi,RdHi, Rm, Rs Unsigned Multiply

accumulate long RdHi,RdLi:=unsigned(RdHi,RdLi+Rm*Rs)

SMULL RdLi,RdHi, Rm, Rs Signed Multiply long RdHi,RdLi:=signed(Rm*Rs) SMLAL RdLi,RdHi, Rm, Rs Signed Multiply-accumulate

long RdHi,RdLi:=signed(RdHi,RdLi+Rm*Rs)

Considering some examples of data processing instructions without using barrel shifter and with using barrel shifter. ADD operation without barrel shifter: Initially, r0 = 0x00000000, r1 = 0x00000001, r2 = 0x00000002

ADD r0, r1, r2 After ADD operation, r0 = 0x00000003 The value stored in register r1 is added with the value stored in register r2. The result is stored into register r0. ADD operation with barrel shifter: Initially, r0 = 0x00000000, r1 = 0x00000005 ADD r0, r1, r1, LSL #1 Created by sambhavi Architecture of the ARM Processor Family 13


After ADD operation r0 = 0x0000000f, r1 =0x00000005 Register r1 is first shifted one location to the left, which generates twice r1. The ADD instruction then adds the result of the barrel shifter operation to register r1. The final result, which is three times the value stored in register r1, is stored into register r0.

Table 15: Barrel shifter operations [1]

Mnemonic Description LSL Logical shift left LSR Logical shift right ASR Arithmetic right shift ROR Rotate right RRX Rotate right extended

5.2 Branch Instructions The branch instructions change the flow of sequential execution of instructions and force to modify the program counter pc. The branch and link instruction (BL) is only used in case of a subroutine call. The address of the next instruction after BL operation is moved into the link register r14. After returning from the subroutine, the program counter is restored back to the r15 from the linked register.

Table 16: Branch instructions supported by the ARM processors [3]

Instruction Syntax Meaning Action B label Branch R15= label BL label Branch with link R15= label

R14=address of next instruction after BL

The address label is stored in the instruction as a signed pc-relative offset and gives a range of +/-32 MB. [1] The “modern” ARM cores support branch exchange (BX) and branch and exchange link instructions, which are used to switch the processor to execute Thumb instructions. 5.3 Load/Store Instructions The load/store instructions transfer data between memory and registers. The data values are loaded into registers from memory, processing of data is carried out using data processing instructions and the result is written back to memory from the registers. There are three types of load/store instructions: single register data transfer, multiple register data transfer and single data swap. 5.3.1 Single Register Transfer Instructions: These instructions are used to move a single data item in and out of register. [1] The data types may be signed or unsigned bytes, 16-bit half words, and a 32-bit words.

Table 17: Single register transfer instructions supported by the ARM processors [3]

Mnemonic Meaning Action LDR Load word into a register Rd<-mem32[address] STR Save byte or word from a register Rd->mem32[address] LDRB Load byte into a register Rd<-mem8[address] STRB Save byte from a register Rd->mem8[address] LDRH Load halfword into a register Rd<-mem16[address] STRH Save halfword into a register Rd->mem16[address] LDRSB Load signed byte into a register Rd<-SignExtend

(mem32[address]) LDRSH Load signed halfword into a register Rd<-SignExtend

(mem32[address])



The instruction syntax based on different addressing mode is given in the table 18. There are different types of addressing mode supported by the ARM processors. The addressing modes are register indirect addressing, base-plus-offset addressing and stack addressing. In case of register indirect addressing, the value in one register (base register) is used as a memory address. Considering an example LDR r0, [r1]. This means r0 is loaded with contents of memory location pointed to by contents of r1. In base-plus-offset addressing mode, there are three different types of indexing methods: preindex with writeback, preindex and postindex. The preindex with writeback addressing method is used to calculate an address from a base address register plus address offset and then update the address of the base register before the address is used. The preindex addressing method is similar to preindex with writeback addressing mode except it does not update the address of the base register whereas the postindex addressing method updates the address of the base register only after the address is used.

Table 18: Index Methods [1]

Index Method Data Base address register Instruction syntax Preindex with writeback Mem[base + offset] base + offset LDR r0, [r1, #12]! Preindex Mem[base + offset] Not updated STR r0, [r1, #12] Postindex Mem[base] base + offset STR r0, [r1], #12

Note: ! means the calculated address is written back to the base register by instruction 5.3.2 Multiple Register Data Transfer Instructions: These instructions allow multiple registers to be loaded from or stored to memory in a single instruction. Using these instructions, the transferring of block of data around memory can be done more efficiently than compared to single register data transfer instructions. The address of base register is used to determine the memory location where the transfer should occur i.e. where the registers are loaded from or stored to memory. However, the load-store multiple instructions can increase interrupt latency. The ARM processor does not usually interrupt instructions while they are executing. If an interrupt occurs, then it has no effect until the load/store multiple instruction is complete. The STM and LDM instructions together with the addressing modes are used to determine whether the base pointer is incremented or decremented before or after the memory is accessed.

Table 19: Multiple register data transfer instructions supported by the ARM processors [3] Instruction Syntax Meaning Action

LDM Load multiple registers Rd*N <-mem32[start address +4*N] STM Save multiple registers Rd*N -> mem32[start address +4*N]

Here N is the number of registers. The addressing modes supported by the ARM processor are as follows:

Table 20: The addressing mode [1]

Addressing mode Description IA Increment after IB Increment before DA Decrement after DB Decrement before

The ARM architecture uses the load-store multiple instructions to carry out stack operations. The pop operation uses a load multiple instruction and the push operation uses a store multiple instruction. A stack is either ascending or descending. A stack can be used as a full stack i.e. the stack pointer points to the last item on the stack or an empty stack i.e. the stack pointer points after the last item on the stack [1] that is the next free space in the stack. There are a number of load-store multiple addressing mode supporting stack operations.




Table 21: The stack implementation [1] Addressing mode

Description Pop =LDM Push =STM

FA Full Ascending LDMFA LDMDA STMFA STMIB FD Full Descending LDMFD LDMIA STMFD STMDB EA Empty Ascending LDMEA LDMDB STMEA STMIA ED Empty Descending LDMED LDMIB STMED STMDA Considering an example of load multiple instruction. Pre condition mem32[0x80018] = 0x03, mem32[0x80014] = 0x02, mem32[0x80010] = 0x01 r0 = 0x00080010, r1 = 0x00000000, r2 = 0x00000000, r3 = 0x00000000 LDMIA r0!, {r1-r3} Post condition r0 = 0x0008001c, r1 = 0x00000001, r2 = 0x00000002, r3 = 0x00000003

Table 22: Pre condition for LDMIA instruction and Post condition for LDMIA instruction [1] Pre condition Post condition

Memory address

Data Memory address

data

0x80020 0x000000005 0x80020 0x000000005 0x8001c 0x000000004 0x8001c 0x000000004 0x80018 0x000000003 0x80018 0x000000003 0x80014 0x000000002 0x80014 0x000000002 0x80010 0x000000001 0x80010 0x000000001

Address pointer

r0=0x80010 0x8000c 0x000000000

r3=0x00000000r2=0x00000000r1=0x00000000

Address pointer

r0=0x80010

0x8000c 0x000000000

r3=0x00000003r2=0x00000002r1=0x00000001

In the pre condition the base register r0 points to memory address 0x80010. The memory addresses 0x80010, 0x80014 and 0x80018 contain value 1, 2 and 3 respectively. The registers r1, r2 and r3 contain zero value. After the load multiple instruction executes registers r1, r2 and r3 contain value 1, 2 and 3 respectively. The base register r0 now points to memory address 0x8001c. 5.3.3 Swap Instructions: This instruction is used to swap the content of memory with the content of a register. Any other instructions or bus access do not interrupt this operation. In other words, this instruction is an atomic operation. It prevents any other instructions from reading and writing to that memory location which is currently used for reading and writing by this instruction. This instruction allows atomic update of semaphores i.e. it performs an indivisible bus operation.

Table 23: Single data swap instructions supported by the ARM processors [3] Instruction Syntax Meaning Action SWP Rd, Rm, [Rn] Swap a word between memory and a register tmp = mem32 [Rn]

mem32 [Rn]= Rn Rd=tmp

SWPBRd, Rm, [Rn] Swap a byte between memory and a register tmp = mem8 [Rn] mem8 [Rn]= Rn Rd=tmp

5.4 Software Interrupt Instruction This instruction is used to call the operating system routine (SWI exception handler). The processor mode changes to the supervisor mode when the processor executes this instruction and sets the program counter to 0x08. Then the SWI exception handler is called. After handling the exception, the program counter is restored from the link register where the address of next instruction is stored prior to mode change and the processor starts executing in the user mode. Each SWI instruction has SWI number which represents a particular function call.


Table 24: Software interrupt instruction supported by the ARM processors [3]

Instruction Syntax Meaning Action SWI SWI_number Software interrupt Lr_svc=address of instruction following the SWI

Spsr_svc=cpsr, pc=vectors +0x08,cpsr mode=SVC Cpsr I= 1(mask IRQ interrupts)

5.5 Program Status Register Instructions These instructions are used to transfer the content of program status registers to/ from general- purpose register. There are mainly two different types of instructions: MRS and MSR instructions. The MRS and MSR instructions allow the contents of the program status registers to be transferred from/to a general purpose registers.

Table 25: Program status register instructions supported by the ARM processors [3]

Instruction Syntax Meaning Action

MRS Rd, cpsr Copy program status register to a general purpose register

Rd:=psr

MSR cpsr, Rm Move a general purpose register to a program status register

Psr[field]:=Rm

The program status register is split into four 8-bit fields that can be individual written as: Control field –bits 0-7: 5 processor mode bits, I and F interrupt disable bits and T bit for Thumb code Extension field- bit 8-15: Reserved for future use Status field –bit 16-23: Reserved for future use Flag field –bit 24-31: NZCV flags (28-31) and 4 bits reserved for future use. But for the core supporting Jazelle technology, bit 24 is Jazelle state and for the DSP extension, bit 27 is Q flag for the DSP instructions. Note: Figure 6 depicts the program status register 5.6 Coprocessor Instructions Coprocessors instructions are supported by the ARM architecture. These instructions are part of the ARM instruction set. They are for additional computation and to control on-chip functions including caches and memory management. There are three types of coprocessor instruction: coprocessor data processing, coprocessor register transfer and coprocessor memory transfers.

Table 26: Coprocessor instructions supported by the ARM processors [3]

Instruction Syntax Meaning

CDP cp, opcode1, Cd, Cn {, opcode2} Coprocessor data processing MRC | MCR cp, opcode1, Rd, Cn, Cm {, opcode2} Coprocessor register transfer LDC | STC cp, Cd, addressing mode Coprocessor memory transfer

Note: The cp field represents the coprocessor number between p0 and p15. The opcode fields describe the operation carried out on the coprocessor. The Cn, Cm and Cd fields describe the registers within the coprocessor. [1] The coprocessor data processing is used to perform an operation in a coprocessor, the coprocessor register transfer is used to move data between the ARM registers and coprocessor registers and the coprocessor memory transfer is used to load and store blocks of memory to/ from coprocessor registers. Coprocessor 15 controls the cache, TCMs and memory management.


Chapter 6: Conclusion

6. Conclusion The ARM limited has continued developing a wide variety of 16/32-bit microprocessors since 1985. There is a continuous evolution of the architecture of the ARM processor using various design techniques such as RISC architectures, pipelines and DSP and Jazelle technology. This allows numerous benefits such as high performance, lower power consumption and system cost, and fast time-to-market. The enhanced configurability of the ARM processors has provided benefits in the wide areas of technology design and development such as embedded real-time control applications, automotive control systems, wireless digital cellular and portable applications and secure applications for smart cards and SIM cards. References

[1]: Andrew Sloss, Dominic Symes and Chris Wright, ARM System Developer’s Guide, Chapter 2: ARM Procesor Fundamentals, Chapter 3: Introduction to the ARM Instruction Set, 2004

[2]: ARM Instruction Set –ARM University Program v1.0 by ARM Limited [3]: ARM Instruction Set-Quick reference card, source: www.arm.com [4]: Carol Atack and Alex Van Someren, ARM RISC Chip: A Programmers’s Guide, 1993

[5]: David Seal, ARM Architecture Reference Manual (2nd Edition), 2001 [6]: http://www.arm.com/products/CPUs/families/ARM7Family.html [7]: http://www.arm.com/pdfs/ARM7_thumb_flyer_35_4.pdf [8]: http://www.arm.com/products/CPUs/families/ARM9Family.html [9]: http://www.arm.com/pdfs/ARM9_family_flyer_34_5.pdf [10]: http://www.arm.com/products/CPUs/families/ARM9EFamily.html [11]: http://www.arm.com/pdfs/ARM9E_flyer_063_4.pdf [12]: http://www.arm.com/products/CPUs/families/ARM10EFamily.html [13]: http://www.arm.com/products/CPUs/families/ARM11Family.html [14]: http://www.arm.com [15]: http://www.go-ecs.com/arm/armtek1.htm [16]: Steve Furber, ARM System Architecture, 1996 [17]: Shuqiang Zhang, WinARM, Simulating Advanced RISC Machine Architecture [18]: Trevor Martin, An Introduction to ARM7 Architecture


http://www.arm.com/products/CPUs/families/ARM7Family.html

http://www.arm.com/pdfs/ARM7_thumb_flyer_35_4.pdf


http://www.arm.com/pdfs/ARM9_family_flyer_34_5.pdf

http://www.arm.com/products/CPUs/families/ARM9EFamily.html

http://www.arm.com/pdfs/ARM9E_flyer_063_4.pdf

http://www.arm.com/products/CPUs/families/ARM10EFamily.html


List of Abbreviations

Abbreviations ARM: Advanced RISC Machine RISC: Reduced Instruction Set Computer VLSI: Very Large Scale Integration Ltd: Limited ALU: Arithmetic and Logic Unit MAC: Multiply Accumulate Unit cpsr: current program status register spsr: saved program status register DSP: Digital Signal Processing SWI: Software Interrupt MMU: Memory Management Unit MPU: Memory Protection Unit CPU: Central Processing Unit JTAG: Joint Test Action Group ICE: In-Circuit Emulation OS: Operating System RTOS: Real Time Operating System PDA: Personal Digital Assistant MIPS: Microprocessor without Interlocked Pipes Stages/Millions Instructions Per Second TCM: Tightly coupled Memory ETM: Embedded Trace Macrocell RT: Real Time IEEE: Institute of Electrical and Electronics Engineers MPEG: Moving Picture Experts Group

Created by sambhavi Architecture of the ARM Processor Family

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