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Sensitivity Analysis of SOI based FINFETs andCircuit Tuning

Ankur Sharma and Mukul Gupta

I. INTRODUCTION

Inherent to any device operation is a tradeoff between devicedelay and device power consumption. As more and moredevices are being integrated on a single chip, inevitably thereis a necessity to reduce the overall chip power consumptionwhile avoiding the timing violations. In this work, we studythe sensitivity of delay and power consumption of Finfet basedlogic family to various device parameters like supply voltage,gate length, gate width, fin thickness and oxide thickness.Sensitivity study then has been utilized to perform tuningof two sample circuits where we explored the energy delaytrade-off. We verify the accuracy of our linear delay andpower model against HSPICE simulations by generating paretocurves.

The rest of the report has been organized as follows: Section2 introduces SOI based Finfet modeling followed by sensitivityanalysis in section 3. Optimization of a sample circuits asshown in fig.(6) and fig.(5) and related experimental resultshave been discussed in sections 4 and 5, respectively.Lastly,conclusions and future work have been discussed in section 6.

II. SOI BASED FINFET MODEL

Finfet structure is shown in fig.(2). tox represents gateoxide thickness,tsi fin thickness, 2h gate width and Lg gatelength. In this project, Finfet is modeled as a back-to-backSOI MOSFET as shown in fig.(3). Body thickness of each SOIdevice is essentially half of fin thickness.PTM device models[1] have been used for our project.

III. SENSITIVITY ANALYSIS

In this section we present the sensitivity analysis of powerconsumed by a device (dynamic, Pdyn and subthreshold leak-age, Pleak) and delay of a device, D, with respect to supplyvdd, length l, width w, fin thickness finT and oxide thicknesstox, based on HSPICE simulations carried out on inverter(s)circuits. The test circuits for delay and power analysis areshown in fig.(1). Note that for rest of the report, we refer toany parameter by variable xj where j can take values from 1to 5. Also, x′

j would be used to refer to the parameter valuesof the next stage device. This would be required in delay andpower modeling in next section.

Delay has been evaluated as the time difference betweeninput signal crossing 0.5Vdd and the output signal crossing0.5 ∗Vdd where Vdd is the supply voltage. Dynamic energy iscomputed as the average ‘short circuit’ energy supplied by thesource while the load is charging while excluding the energyconsumed by the load. It was observed that when the load

Fig. 1. Circuit for sensitivity analysis. Above for FO4 delay calculation andbelow for power calculation

was discharging, dynamic energy consumed is very small com-pared to the scenario when the load is getting charged. We haveanalyzed only sub-threshold leakage because, apparently, gateleakage has not been modeled properly in the PTM modelsthat are being used, as gate leakage is varying arbitrarily withcircuit parameters. When the steady state input value is high,gate leakage is very small and therefore, we can measure sub-threshold leakage with greater accuracy. Leakage power hasbeen estimated as the average power dissipated by the supplywhen the circuit is in steady state and the input is high. Thesensitivity table has been shown in fig.(4).Below we explainthe observations of the sensitivity analysis.

Delay shows positive sensitivity towards length, oxidethickness and fin thickness. Since drain current is inverselyproportional to length and oxide thickness, with increasingeither of them, the delay would also increase. By increasingfin thickness, probably, threshold voltage rises and as a result,we are observing an increase in delay. Delay shows negativesensitivty towards supply voltage and width of the device. Anincrease in width implies decrease in drain-source resistance,thereby an increase in the drain current and hence a decreasein the delay. Delay is most sensitive to change in width andleast sensitive to changes in fin thickness.

Dynamic power shows positive sensitivity towards length,

2

Fig. 2. Finfet Structure

Fig. 3. SOI based Finfet Model

width, supply and fin thickness. With an increase in length,two contradictory phenomena are observed - decrease in drivecurrent of the device and increase in the parasitic capacitance.Former happens to reduce the dynamic power whereas lattertends to increase the power. Observations revealed that, appar-ently, latter dominates the former. With an increase in width,drive current and parasitic capacitance change supplementeach other by increasing the power. With supply, its obviousthat power would increase. Dynamic power shows negativesensitivity for oxide thickness. This is so because, drive currentis inversely proportional to the oxide thickness. Dynamicpower is most sensitive to supply voltage and least sensitiveto fin thickness.

Leakage shows positive sensitivity for oxide thickness,supply voltage and width. With increasing oxide thickness,sub-threshold swing rises. With increasing width the resistivityof drain-source drops. Leakage shows negative sensitivitytowards length because subthreshold leakage current is directlyproportional to the negative exponential of the length. Leakageis most sensitive to length and least sensitive to fin thickness.

IV. CIRCUIT TUNING

We use the sensitivity values to develop a linear modelof delay, leakage power and dynamic power and formulatea delay constrained optimization problem that minimizes sub-threhsold leakage power subject to a delay budget. The aimof this experiment is to study the spread in delay-powertradeoff for a simple FINFet based circuit as shown in fig.

Fig. 4. Sensitivity table

and to verify our delay and power models by comparing theoptimization results with HSPICE simulation results. In thissection, we first describe the modeling and then formulate thedelay constrained optimization problem. where,

D =

D0 +

j=5∑

j=0

(

∂Di

∂xj

.∆xj

)

CL

CL = εox

(

(w0 + ∆w′)(l0 + ∆l′)

tox0 + ∆tox

)

where, D0 is the nominal value of delay per unit capacitance;w0 and l0 are nominal width, length and oxide thicknessvalues; w0 +∆w′ and l0 +∆l′ are the parameter values of thenext stage device. vdd, finT and tox have been assumed tobe same across all the devices. Ofcourse, nominal values of allparameters are same across all the devices. Finally, we expandequation given above and linearize it. Now we can define pathdelay, PDi, for path i as the sum of delay of all the devicesthat constitute the path,

PDi = sumd∈devices on pathD(d)

where, D(d) is the delay of device d lying on the path i.For leakage power we consider only subthreshold leakage

from drain to source. It has no dependence on next stagedevices and hence can be easily modeled as follows,

Pleak = Pleak0+

j=5∑

j=0

(

∂Pleak

∂xj

.∆xj

)

(1)

Having defined the model, we can now formulate the delayconstrained optimization problem to minimize the total powerconsumed by the circuit. Let, Ptot be the sum total of thepower consumed by all the devices in the circuit and PDmax

be the maximum path delay of the circuit.

Ptot =∑

d∈circuit

(Pleak(d)) (2)

PDmax = maxi∈circuit

PDi (3)

where, d is a device in the circuit and i is a path in the circuit.The optimization problem is then expressed as,

minimize Ptot (4)subject to (5)

PDmax ≤ δ (6)

3

Fig. 5. 2 nand circuit used for optimization

Fig. 6. single nand circuit used for optimization

where δ is the delay budget. We have implemetned thismodel in MATLAB. The code takes in any circuit as a treestructure. It automatically enumerates all the paths in the givencircuit and finds the delay sensitivity of each path and leakagesensitivity of the circuit. The model developed is then fed intoa cvx[2] optimizer which minimizes leakage power for a givendelay budget.

V. EXPERIMENTAL RESULTS

Experiments have been performed to verify the optimizationresults by comparing them with the simulations. First of all,by feeding the linear delay and power models and constraintsto the cvx optimization toolbox, we generate an energy-delayPareto curve. We refer to this Pareto curve as opt-paretocurve, ie, obtained from the optimization. Secondly, HSPICE

Fig. 7. Pareto curve for circuit with 2 nand gates

5.6 5.8 6 6.2 6.4 6.6 6.8 7 7.2x 10−10

2

2.5

3

3.5

4

4.5

5x 10−8

X: 6.823e−10Y: 1.613e−08

Delay (s)

Leak

age

(W)

Opt−ParetoScatterSim−Pareto

Fig. 8. Pareto curve for circuit with single nand gate

5.5 6 6.5 7x 10−10

1

1.5

2

2.5

3

3.5

4

4.5

5x 10−8

Delay (s)

Leak

age

(W)

ScatterSim−ParetoOpt−Pareto

simulations are performed using the optimum parameter valuesobtained from the previous step. Plotting the energy-delayvalues of the simulations we obtain another Pareto curve,referred to as sim-pareto curve. Independently, we simulate10000 samples of parameter values and obtain a scatter plotof energy-delay values. All this has been done for two cirucits- a single NAND gate, fig.(6), and two NAND gates connectedin series, fig.(5).

Here we show that the sim-pareto curves derived fromoptimum values yielded by the optimization toolbox usingthe models derived above, form a lower bound on the scatterplot, as shown in fig.(8) and fig.(7). This shows that ouroptimization methodology generates correct optimal parametervalues.

VI. FUTURE WORK AND CONCLUSIONS

In this work we have developed linear models of delayand power values based on sensitivity to fin thickness, oxidethickness, gate width, gate length and supply voltage.Leakagepower has been minimzed for a given delay budget within+/5% of the nominal values of parameters. However, wecan further extend our work for finding the optimal valuesover a larger range say +/20% by doing piece-wise linearoptimization by dynamically changing the nominal values ofparameters and sensitivities of delay and power. Also, we haveused SOI based finfet models for spice simulations which maynot be accurate. This experiment can be run on the latest BSIMmodels for accurate results.

REFERENCES

[1] ptm.asu.edu[2] http://cvxr.com/cvx/download/[3] A fully physical model for leakage distribution under process variations

in nanoscale double-gate CMOS,”IEEE”,September 2006