september 5, 2007 karem sakallah [email protected] qatar.cmu/~msakr/15447-f07

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Computer Architecture Fall 2007 © September 5, 2007 Karem Sakallah [email protected] www.qatar.cmu.edu/~msakr/15447-f07/ CS 447 – Computer Architecture Lecture 3 Computer Arithmetic (2)

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CS 447 – Computer Architecture Lecture 3 Computer Arithmetic (2). September 5, 2007 Karem Sakallah [email protected] www.qatar.cmu.edu/~msakr/15447-f07/. Last Time. Representation of finite-width unsigned and signed integers Addition and subtraction of integers - PowerPoint PPT Presentation

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Page 1: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

September 5, 2007

Karem [email protected]

www.qatar.cmu.edu/~msakr/15447-f07/

CS 447 – Computer Architecture

Lecture 3

Computer Arithmetic (2)

Page 2: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Last Time

°Representation of finite-width unsigned and signed integers

°Addition and subtraction of integers

°Multiplication of unsigned integers

Page 3: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Today°Review of multiplication of unsigned integers

°Multiplication of signed integers

°Division of unsigned integers

°Representation of real numbers

°Addition, subtraction, multiplication, and division of real numbers

Page 4: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Multiplication

°Complex

°Work out partial product for each digit

°Take care with place value (column)

°Add partial products

Page 5: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Multiplication Example

° 1011 Multiplicand (11 dec)

° x 1101 Multiplier (13 dec)

° 1011 Partial products

° 0000 Note: if multiplier bit is 1 copy

° 1011 multiplicand (place value)

° 1011 otherwise zero

° 10001111 Product (143 dec)

° Note: need double length result

Page 6: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Unsigned Binary Multiplication

Page 7: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Execution of Example

Page 8: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Flowchart for Unsigned Binary Multiplication

Page 9: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Multiplying Negative Numbers°This does not work!

°Solution 1•Convert to positive if required

•Multiply as above

• If signs were different, negate answer

°Solution 2•Booth’s algorithm

Page 10: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Observation°Which of these two multiplications is more difficult?

98,765 x 10,001

98,765 x 9,999

°Note:

98,765 x 10,001 = 98,765 x (10,000 + 1)

98,765 x 9,999 = 98,765 x (10,000 – 1)

Page 11: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

In BinaryLet Q = d d d 0 1 1 . . . 1 1 0 d d

QL = d d d 1 0 0 . . . 0 0 0 d d

QR = 0 0 0 0 0 0 . . . 0 1 0 0 0

Page 12: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

In BinaryLet Q = d d d 0 1 1 . . . 1 1 0 d d

QL = d d d 1 0 0 . . . 0 0 0 d d

QR = 0 0 0 0 0 0 . . . 0 1 0 0 0

Then Q = QL – QR

And M x Q = M x QL – M x QR

Page 13: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

A bit more explanation

P = M x Q

where M and Q are n-bit two’s complement integers

e.g., Q = -23 q3 + 22 q2 + 21 q1 + 20 q0

which can be re-written as follows:

Q = 20(q-1–q0)+21(q0-q1)+22(q1-q2)+23(q2-q3)

leading to

P = M x 20 x (q-1 - q0) + M x 21 x (q0 - q1) +

M x 22 x (q1 - q2) +M x 23 x (q2 - q3)

Page 14: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Finally!P = M x 20 x (q-1 - q0) +

M x 21 x (q0 - q1) +M x 22 x (q1 - q2) +M x 23 x (q2 - q3)

qi qi-1 qi-1 – qi Action

0 0 0 Noop

0 1 1 Add M

1 0 -1 Subtract M

1 1 0 Noop

Page 15: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Example of Booth’s Algorithm

Page 16: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Booth’s Algorithm

Page 17: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Division

°More complex than multiplication

°Negative numbers are really bad!

°Based on long division

Page 18: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Division of Unsigned Binary Integers

001111

1011

00001101

100100111011001110

1011

1011100

Quotient

Dividend

Remainder

PartialRemainders

Divisor

Page 19: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Flowchart for Unsigned Binary Division

Page 20: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Real Numbers

°Numbers with fractions

°Could be done in pure binary• 1001.1010 = 24 + 20 +2-1 + 2-3 =9.625

°Where is the binary point?

°Fixed?•Very limited

°Moving?•How do you show where it is?

Page 21: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Floating Point

°+/- .significand x 2exponent

°Misnomer

°Point is actually fixed between sign bit and body of mantissa

°Exponent indicates place value (point position)

Sig

n bi

t

BiasedExponent

Significand or Mantissa

Page 22: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Floating Point Examples

Page 23: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Signs for Floating Point

°Mantissa is stored in two’s complement

°Exponent is in excess or biased notation• e.g. Excess (bias) 128 means

• 8 bit exponent field

•Pure value range 0-255

•Subtract 128 to get correct value

•Range -128 to +127

Page 24: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Normalization

°FP numbers are usually normalized

° i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1

°Since it is always 1 there is no need to store it

° (c.f. Scientific notation where numbers are normalized to give a single digit before the decimal point

°e.g. 3.123 x 103)

Page 25: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

FP Ranges

°For a 32 bit number• 8 bit exponent

• +/- 2256 1.5 x 1077

°Accuracy• The effect of changing lsb of mantissa

• 23 bit mantissa 2-23 1.2 x 10-7

•About 6 decimal places

Page 26: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Expressible Numbers

Page 27: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Density of Floating Point Numbers

Page 28: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

IEEE 754 Formats

Page 29: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

FP Arithmetic +/-

°Check for zeros

°Align significands (adjusting exponents)

°Add or subtract significands

°Normalize result

Page 30: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

FP Addition & Subtraction Flowchart

Page 31: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

FP Arithmetic x/°Check for zero

°Add/subtract exponents

°Multiply/divide significands (watch sign)

°Normalize

°Round

°All intermediate results should be in double length storage

Page 32: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Floating Point Multiplication

Page 33: September 5, 2007 Karem Sakallah ksakalla@qatar.cmu qatar.cmu/~msakr/15447-f07

Computer Architecture Fall 2007 ©

Floating Point Division