n 12/24/13

n 1

Sequential Logic

•  Outputs of sequential logic depend on current inputs and prior input values §  Sequential logic might explicitly remember certain previous

inputs, or it might distill (encode) the prior inputs into a smaller amount of information called state

§  The state is a set of bits that contain all the information about the past necessary to determine the future behavior of the circuit

§  State elements •  Bistable circuit •  SR Latch •  D Latch •  D Flip-flop

n 1

SR Latch

•  One of the simplest sequential circuits is the SR (Set/Reset) latch §  It is composed of 2 cross-coupled NOR gates

•  It has 2 inputs (S, R) and 2 outputs (Q and Q)

§  When the set input (S) is 1 (and R = 0), Q is set to 1 •  Set makes the output (Q) to 1

§  When the reset input (R) is 1 (and S = 0), Q is reset to 0 •  Reset makes the output (Q) to 0

n 2

R

S

Q

Q

N1

N2 S

R Q

Q

SR LatchSymbol

n 12/24/13

n 2

SR Latch Analysis

•  Consider the four possible cases: a) S = 1, R = 0 b) S = 0, R = 1 c) S = 0, R = 0 d) S = 1, R = 1

n 3

SR Latch Analysis

n 4

a) S = 1, R = 0:

b) S = 0, R = 1:

R

S

Q

Q

N1

N2

0

1

1

00

0

0

0

1

1

then Q = 1 and Q = 0

R

S

Q

Q

N1

N2

1

0

0

10

1

0

0 1

1 then Q = 0 and Q = 1

n 12/24/13

n 3

SR Latch Analysis

n 5

c) S = 0, R = 0:

d) S = 1, R = 1:

R

S

Q

Q

N1

N2

1

1

0

00

0

We got Memory!

Invalid state: Q ≠ NOT Q

R

S

Q

Q

N1

N2

0

0

1

01

0

R

S

Q

Q

N1

N2

0

0

0

10

1

Qprev = 0 Qprev = 1

0

then Q = Qprev and Q = Qprev

0 1

1 1

1 0

0

0

0 0

0

then Q = 0 and Q = 0

SR Latch Recap

•  SR latch stores one bit of state §  Where is it stored?

•  SR latch can control the state with S and R inputs

•  SR latch generates the invalid state when S =1 and R = 1

n 6

n 12/24/13

n 4

D Latch

•  D latch solves the problem of the SR latch §  D latch blocks the invalid state when S =1 and R = 1 §  D latch separates when and what the state should be changed

•  D latch has 2 inputs (CLK, D) and 2 outputs (Q, Q) §  CLK controls when the output changes §  D (data input) controls what the output changes to §  Avoids invalid case (Q ≠ NOT Q when both S and R are 1)

n 7

D LatchSymbol

CLK

D Q

Q

D Latch Internal & Operation

n 8

S

R Q

Q

Q

QD

CLKD

R

S

CLK

D Q

Q

•  D latch operation §  When CLK = 1, D passes through to Q (D latch is transparent) §  When CLK = 0, Q holds its previous value (D latch is opaque)

S R Q0 0 Qprev0 1 01 0 1

Q

10

CLK D0 X1 01 1

DX10

Qprev0 0 1 1

0 1 0 1

1

0

0

0

0

0

Qprev

Qprev

Qprev

Qprev

1

0

1

0

1

0

0 1

1 0

n 12/24/13

n 5

D Latch Waveform

•  When evaluating latch, it would be confusing if you think previous and current value things

•  For good intuition, think with waveform §  When CLK = 1, D latch transfers input data (D) to output (Q) §  When CLK = 0, D latch maintains its previous value

n 9

D Flip-Flop

•  In digital logic design, it is very convenient if we can store input data at a certain moment (not during the whole time interval like D latch)

•  D flip-flop provides that functionality §  Q changes only on the rising edge of CLK

•  When CLK rises from 0 to 1, D passes through to Q

•  Otherwise, Q holds its previous value

•  Thus, a flip-flop is called an edge-triggered device because it is activated on the clock edge

n 10

D Flip-FlopSymbols

D Q

Q

n 12/24/13

n 6

D Flip-Flop Internal Circuit

•  Two back-to-back latches (L1 and L2) controlled by complementary clocks

•  When CLK = 0 §  L1 is transparent §  L2 is opaque §  D passes through to N1

•  When CLK = 1 §  L2 is transparent §  L1 is opaque §  N1 passes through to Q

•  Thus, on the edge of the clock (when CLK rises from 0 to 1) §  D effectively passes through to Q

n 11

CLK

D Q

Q

CLK

D Q

Q

Q

Q

D N1

CLK

L1 L2

D Flip-Flop

n 12

CLK

D Q

Q

CLK

D Q

Q

Q

Q

D N1

CLK

L1 L2

•  Note that input data should not be changed around the clock edge for D flip-flop to work correctly

n 12/24/13

n 7

D Flip-Flop

•  So, D flip-flop has the effect of sampling the current input data at the rising edge of the clock §  Note again that input data should not be changed around the clock edge for

D flip-flop to work correctly

n 13

Registers

n 14

CLK

D Q

D Q

D Q

D Q

D0

D1

D2

D3

Q0

Q1

Q2

Q3

D3:04 4

CLK

Q3:0

•  An N-bit register is a set of N flip-flops that share a common CLK input, so that all bits of the register are updated at the same time §  You can say N-bit flip-flops or N-bit register

•  Registers are the key building block of sequential circuits

n 12/24/13

n 8

Enabled Flip-Flops

•  Enabled flip-flips are useful when we wish to load a new value into a flip-flop only during some of the time, rather than on every clock edge §  Enabled flip-flop has one more input (EN) §  The enable input (EN) controls when new data (D) is stored §  When EN = 1, D passes through to Q on the clock edge §  When EN = 0, the flip-flop retains its previous state

n 15

InternalCircuit

D Q

CLKEN

DQ

0

1D Q

EN

Symbol

Resettable Flip-Flops

•  Resettable flip-flops are useful when we want to force a known state (i.e., 0) into some flip-flops in a system when we first turn it on §  Resettable flip-flop has “Reset” input §  When Reset is active, Q is reset to 0 §  When Reset is deactivated, the flip-flop

behaves like an ordinary D flip-flop

•  There are two types of resettable flip-flops §  Synchronous resettable FF resets at the

clock edge only §  Asynchronous resettable FF resets

immediately when Reset is active •  Asynchronously resettable flip-flop requires

changing the internal circuitry of the flip-flop

n 16

InternalCircuit

D Q

CLK

D QReset

Synchronously resettable flip-flop

Symbols

D QReset

r

Resettable flip-flop

n 12/24/13

n 9

Settable Flip-Flops

•  Settable flip-flops are also useful when we want to force a known state (i.e., 1) into some flip-flops in a system when we first turn it on §  Settable flip-flop has “Set” input §  When Set is active, Q is set to 1 §  When Set is deactivated, the flip-flop behaves like an ordinary D flip-flop

•  They comes in two flavors: Synchronous settable and Asynchronous settable

n 17

Symbols

D QSet

s

Registers

•  A register is a group of flip-flops. •  An n-bit register is made of n flip-flips and can store n

bits •  A register may have additional combinational gates to

perform certain operations

0 1 … n-1

n 12/24/13

n 10

4-Bit Register

•  A simple 4-bit register can be made with 4 D-FF •  Data is loaded in parallel

•  Common Clock •  At each positive-edge, 4 bits are loaded

in parallel •  Previous data is overwritten •  Entering data is called loading

•  Common Clear •  Asynchronous active-low clear •  When Clear = 0, all FFs are cleared; i.e.

0 is stored.

4-Bit Register (cont.)

•  Question: How to modify this register to enable/disable loading new data (overwriting previous) ?

n 12/24/13

n 11

4-Bit Register (cont.)

•  Question: How to modify this register to enable/disable loading new data (overwriting previous) ?

•  Answer: When Load=0, the clock input to the FFs will never take a transition (0 to 1, 1 to 0), no new data will be loaded. When Load=1, normal data loading takes place

•  This is called clock gating

4-Bit Register (cont.)

•  Clock Skew Problem: •  It results from clock gating.

n 12/24/13

n 12

4-Bit Register (cont.)

•  Better Solution: Register with Parallel Load

•  Use a 2x1 MUX as shown:

n Q: Why a D-FF output is feedback?

4-Bit Register (cont.)

n clock n load

•  A 4-bit Parallel Load Register

•  When Load = 0, the data is not changed (no loading)

•  When Load = 1, the data is loaded in parallel at the rising edge (+ve)

n 12/24/13

n 13

Shift Registers

•  A shift register is a register which shifts its content (right, left, or both)

•  Made of flip-flops with common clock •  Useful to load data serially

0 1 … n-1

4-bit Shift Register

•  A simple 4-bit shift register can be made with 4 D-FF •  Common Clock

•  At each positive-edge, 1 bit is shifted in •  Rightmost bit is discarded

•  Which direction this register is shifting?

n 12/24/13

n 14

Using Shift Register (Examples)

•  Serial Addition

Shift Register with Parallel Load

•  Two control inputs (shift, load) •  Each stage consists of

•  D-FF •  OR gate •  Three AND gates

•  AND to enable shift •  AND to enable load •  AND for “no change”

•  Idea: Use a MUX to implement more functions (see next slides)

Qià Qi D0D1D2D3

n Serial Input à Q0

n Qi-1 à Qi ; i=1,…,3

n 12/24/13

n 15

Universal Shift Register

Question: Design a Universal Shift Register with the following capabilities: •  A clear control to clear the register to 0 •  A clock to synchronize the operations •  A shift-right control (associated with serial

in/out) •  A shift-left control (associated with serial

in/out) •  A parallel-load control (to parallel load n

bits) •  n-parallel output lines •  A control signal to leave register

unchanged

Universal Shift Register (cont.)

n 12/24/13

n 16

Universal Shift Register (cont.)

•  How does it work? •  4 D-FF and 4 MUXs with selection S0,S1 •  S0S1=00, FF output is feedback to its input •  S0S1=01, FF input comes from left FF or

serial-in (shift-right) •  S0S1=10, FF input comes from right FF or

serial-in (shift-left) •  S0S1=11, parallel data transferred in •  Applications: •  Parallel ↔ Serial conversions •  Arithmetic multiplication/division •  Delaying input sequence

Counters

•  Counter: A register (sequential circuit) that goes through a pre-determined sequence of states upon the application of input (clock or other source) pulses

•  Binary Counter: The sequence of the states follows the binary number sequence (e.g. 000 à 001 à 010 à 011 à etc.)

•  n-bit binary counter requires n flip-flops – counts from 0 to 2n-1 •  Sequences can be binary, BCD, random, etc. •  Counting can be up, down •  A modulo-n counter goes through values 0,1,2, …, (n-1)

•  e.g. modulo-10 up counter counts: 0,1,…9 •  Two Types of Counters:

•  Ripple counter (asynchronous): •  Flip-flop output transition serves as source for triggering the other flip-flops

•  Synchronous counter: •  common clock for all flip-flops (same design procedure)

n 12/24/13

n 17

Ripple Counters

•  Instead of having a common clock signal to all Flip Flops, in a Ripple counter the output of one stage (Flip Flop) is connected to the clock input of the next stage

•  T or JK flip flops are used for this construction because of their capability to flip their stored bits (J=K=T=1)

•  Clock is connected to the least significant bit

•  Flip flops are negative edge-triggered (clock is bubbled) – are active when the clock signal is falling (high to low)

•  Flip flops invert their stored bits, when the input clock signal goes from high (1) to low (0)

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n clock pulses n Q0

n clear’

n Q1

n Q2

n Q3

n Logic 1

Ripple Counters (cont.)

n Q1: How to make it count down? n Q2: What if we use positive-edge FF? n Q3: What if we use Q’ instead of Q?

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n J

n C

n Q

n Q’ n K n R

n clock pulses n Q0

n clear’

n Q1

n Q2

n Q3

n Logic 1

Q3 Q2 Q1 Q0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1 n . n .

n . n .

n . n .

n . n .

n Q4: Is this counter asynchronous? Why?

n 12/24/13

n 18

Ripple Counters with T-FF/D-FF

•  Alternative implementation of a 4-bit ripple counter using T-FF and D-FF

•  For a D-FF, connecting Q’ to D makes it to toggle at each clock!

n Src: Mano’s Textbook

Ripple Counters

•  Advantages: •  Simple hardware

•  Disadvantages: •  Asynchronous – delay dependent

•  Good for low power circuits

n 12/24/13

n 19

Synchronous Counters

•  Common clock to all FFs •  Design following the same design procedure for

synchronous sequential circuits (see slides 4_3) •  Important: Study the examples in slides 4_3

•  Counters have a regular pattern •  Alternatively, counters can be designed without

following the procedure (algorithmically, hierarchically)

4-bit Synchronous Binary Counter

•  When EN = 0 à No change •  When EN = 1

•  Least significant bit (A0) toggles at every clock

•  Other FFs toggle when all lower FFs are equal to 1 (e.g. 0011 à 0100)

•  Question: What will happen if we use a negative edge triggered FF?

n CO

n A0

n A1

n A2

n A3

n CO

n En

n A0

n A1

n A2

n A3

n CO

n En

n Building Bigger Counter

n Clock

n 12/24/13

n 20

4-bit Synchronous Binary Counter with D-FF

n D3 n Q3

n D2 n Q2

n D1 n Q1

n D0 n Q0

n Incrementer

n A3

n A2

n A1

n A0

n Y3

n Y2

n Y1

n Y0

n +1

n symbol

•  When En = 0, feed back same value •  When En = 1, increment the saved

value at each clock

•  XORs act like an adder •  EN = 1 à Q3Q2Q1Q0 + 0001 •  EN = 0 à Q3Q2Q1Q0 + 0000

•  Tip: XOR + D-FF = T-FF

Arbitrary Count Sequence

• Problem: Design a counter that has a repeated sequence of 6 states, as listed in table. In this sequence, flip-flops B and C repeat the binary count 00, 01, 10, while flip-flop A alternates between 0 and 1 every three counts.

• Notes: • Only 6 states (Module-6)

• 011, 111 are missing • Follow the usual design procedure

Present State

Next State

A B C A B C

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0

n 

n 12/24/13

n 21

Arbitrary Count Sequence – State Table

Present State Next State Flip-flop Inputs

A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 1 0 0 1 X X 1 0 X

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 0 0 0 X 1 x 1 0 x

• Assuming JK flip-flops

Arbitrary Count Sequence – Input Equations

BC A

00 01 11 10

0 0 0 x 1

1 x x x x

BC A

00 01 11 10

0 x x x x

1 0 0 x 1

n JA = B

n KA = B

BC A

00 01 11 10

0 0 1 x x

1 0 1 x x

BC A

00 01 11 10

0 x x x 1

1 x x x 1

n JB = C

n KB = 1

BC A

00 01 11 10

0 1 x x 0

1 1 x x 0

BC A

00 01 11 10

0 x 1 x x

1 x 1 x x

n JC = B’

n KC = 1

n 12/24/13

n 22

n clock

n JA

n C n A

n A’ n KA

n JB

n C n B

n B’ n KB

n JC

n C n C

n C’ n KC n Logic 1

n 000

n 001

n 010

n 110

n 101

n 100 n 011

n 111

n 1) What if the counter “finds itself” in state 111 or state 011? Will the counter be able to proceed (count) normally afterward? How?

n 2) Is this circuit safe or reliable?

n Arbitrary Count Sequence – Unused States

n JA = B n JB = C n JC = B’

n KA = B n KB = 1 n KC = 1

Summary

•  Registers and Counters are versatile sequential circuits

•  Registers •  Parallel Load Registers •  Shift Registers •  Universal Shift Registers

•  Counters •  Ripple counters •  Synchronous counters

n 12/24/13

n 23

Finite State Machine (FSM)

•  Finite state machine (FSM) is composed of 2 components: registers and combinational logic §  Register represents one of the finite number of states

•  K-bit register can represent one of a finite number (2K) of unique states

•  An initial state (in register) is assigned based on reset input at the (rising or falling) edge of clock

•  The next state may change depending on the current state as the next input comes in

§  Based on the current state (and input), output is determined via combinational logic

n 45

FSM Quick Example

•  Vending machine §  You are asked to design a vending machine to sell

cokes. •  Suppose that a coke costs 3TL •  The machine takes only 1TL coins

§  How would you design a logic with inputs and output?

n 46

State 0

reset State 1

1TL

State 2

1TL

State 3 /

coke out

1TL

n 12/24/13

n 24

Finite State Machine (FSM)

•  FSM is composed of §  State register

•  Stores the current state •  Loads the next state at the clock edge

§  Combinational logic •  Computes the next state based on

current state and input •  Computes the outputs based on current

state (and input)

n 47

CL

Next StateLogic

NextState

Inputs

Current State

NextState

CurrentState

S’ S

CLK

CL

OutputLogic

Outputs

Current State Outputs

This slide is the Moore FSM example

Finite State Machines (FSMs)

•  Next state is determined by the current state and the inputs •  Two types of FSMs differ in the output logic

§  Moore FSM: outputs depend only on the current state §  Mealy FSM: outputs depend on the current state and inputs

n 48

CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

n 12/24/13

n 25

Moore and Mealy

•  Edward F. Moore, 1925 - 2003 §  Together with Mealy, developed automata theory, the

mathematical underpinnings of state machines, at Bell Labs. §  Not to be confused with Intel founder Gordon Moore §  Published a seminal article, Gedanken-experiments on

Sequential Machines in 1956

•  George H. Mealy §  Published “A Method of Synthesizing Sequential Circuits” in 1955 §  Wrote the first Bell Labs operating system for the IBM 704

computer

n 49

Finite State Machine Example

•  Let’s design a simplified traffic light controller §  Traffic sensors (sensing human traffic): TA, TB

•  Each sensor becomes TRUE if students are present •  Each sensor becomes FALSE if students are NOT present (i.e., the street is empty)

§  Lights: LA, LB •  Each light receives digital inputs specifying whether it should be green, yellow, or

red

n 50

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

BravadoBlvd.

Dorms

Fields

DiningHall

Labs

TA

TB

LA

LB

CLK

Reset

TrafficLight

Controller

Inputs: clk, Reset, TA, TB Outputs: LA, LB

n 12/24/13

n 26

FSM State Transition Diagram

•  Moore FSM §  Circles represent states §  Arcs represent transitions between states §  Outputs are labeled in each state

n 51

S0 LA: green LB: red

S1 LA: yellow

LB: red

S2 LA: red

LB: green

S3 LA: red

LB: yellow

TA Reset TA

TB TB

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

BravadoBlvd.

Dorms

Fields

DiningHall

Labs

FSM State Transition Table

n 52

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset Current State

Inputs Next State

S TA TB S'

S0 0 X S1

S0 1 X S0

S1 X X S2

S2

S2

S3

X

X

X

0

1

X

S3

S2

S0

n 12/24/13

n 27

FSM Encoded State Transition Table

n 53

Current State Inputs Next State

S1 S0 TA TB S'1 S'0

0 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

State Encoding

S0 00

S1 01

S2 10

S3 11

S'1 = S1 ⊕ S0 S'0 = S1S0TA + S1S0TB

FSM Output Table

n 54

Current State Outputs

S1 S0 LA1 LA0 LB1 LB0

Output Encoding

green 00 yellow 01

red 10

LA1 = S1

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

0

0

1

1

0

1

0

1

0 0 1 0

0 1 1 0

1 0 0 0

1 0 0 1

LA0 = S1S0

LB1 = S1 LB0 = S1S0

n 12/24/13

n 28

FSM Schematic: State Register

n 55

S1

S0

S'1

S'0

CLK

state register

Reset

r

FSM Schematic: Next State Logic

n 56

S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1 S0

r

S'1 = S1 ⊕ S0 S'0 = S1S0TA + S1S0TB

n 12/24/13

n 29

FSM Schematic: Output Logic

n 57

S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r

LA1 = S1 LA0 = S1S0 LB1 = S1 LB0 = S1S0

FSM Timing Diagram

n 58

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

CLK

Reset

TA

TB

S'1:0

S1:0

LA1:0

LB1:0

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S1 (01) S2 (10) S3 (11) S0 (00)

t (sec)

??

??

S0 (00)

S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??

??

0 5 10 15 20 25 30 35 40 45

Green (00)

Red (10)

S0 (00)

Yellow (01) Red (10) Green (00)

Green (00) Red (10)Yellow (01)

n current state

n next state

n 12/24/13

n 30

FSM State Encoding

•  In the previous example, the state and output encodings were selected arbitrarily §  Different choice would have resulted in a different circuit

•  Commonly used encoding methods §  Binary encoding

•  Each state is represented as a binary number §  For example, to represent four states, we need 2 bits (00, 01, 10, 11)

§  One-hot encoding •  A separate bit is used for each state •  Only one bit is HIGH at once (one-hot)

§  For example, to represent four states, we need 4 bits (0001, 0010, 0100, 1000)

§  So, it requires more flip-flops

•  But, it often results in simpler next state and output logic

n 59

Moore vs. Mealy FSM

•  Two types of FSMs differ in the output logic §  Moore FSM: outputs depend only on the current state §  Mealy FSM: outputs depend on the current state and the inputs

n 60

CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

n 12/24/13

n 31

Snail Example

•  There is a snail §  The snail crawls down a paper tape with 1’s and 0’s on it §  The snail smiles whenever the last four numbers it has

crawled over are 1101

•  Design Moore and Mealy FSMs of the snail’s brain

n 61

State Transition Diagrams

n 62

Mealy FSM: arcs indicate input/output

Moore FSM: arcs indicate input

S0 0

reset

S1 0

1

0 0

S2 0

1

1

S3 0

0

0

S4 1

1

1

0

S0

reset

S1

1/0

0/0 0/0 S2

1/0

1/0

S3

0/0

1/1

1 11 110 1101

(1101)

0/0

1 11 110

n 12/24/13

n 32

Moore FSM State Transition Table

n 63

Current State

Inputs Next State

S A S'

S0 0 S0

S0 1 S1

S1 0 S0

S1

S2

S2

1

0

1

S2

S3

S2

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S3 S3

S4

S4

0

1

0

1

S0

S4

S0

S2

Moore FSM State Transition Table

n 64

Current State Inputs Next State

S2 S1 S0 A S'2 S'1 S'0

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 0 0

0 0 1 1 0 1 0

0 1 0 0 0 1 1

0 1 0 1 0 1 0

0 1 1 0 0 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 0

1 0 0 1 0 1 0

State Encoding

S0 000

S1 001

S2 010

S3 011

S4 100

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S'2 = S1 S0 A S'1 = S1 S0 A + S1 S0 + S2A S'0 = S2 S1 S0 A + S1S0 A

n 12/24/13

n 33

Moore FSM Output Table

n 65

Current State Output

S2 S1 S0 Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

Y = S2

reset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

S0

S1

S2

S3

S4

0

0

0

0

1

Moore FSM Schematic

n 66

S2

S1

S0

S'2

S'1

S'0

Y

CLK

Reset

A

S2S1S0

S'2 = S1 S0 A S'1 = S1 S0 A + S1 S0 + S2A S'0 = S2 S1 S0 A + S1S0 A

Y = S2

n 12/24/13

n 34

Mealy FSM State Transition and Output Table

n 67

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSM

Current State

Inputs Next State Output

S A S' Y

S0 0 S0

S0 1 S1

S1 0 S0

S1

S2

S2

1

0

1

S2

S3

S2

S3 S3

0

1 S0

S1

0

0

0

0

1

0

0

0

Mealy FSM State Transition and Output Table

n 68

Current State Input Next State Output

S1 S0 A S'1 S'0 Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 0

0 1 1 1 0 0

1 0 0 1 1 0

1 0 1 1 0 0

1 1 0 0 0 0

1 1 1 0 1 1

State Encoding

S0 00

S1 01

S2 10

S3 11

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSM

S'1 = S1 S0 + S1 S0 A S'0 = S1 S0 A + S1S0 A + S1S0 A Y = S1 S0 A

n 12/24/13

n 35

Mealy FSM Schematic

n 69

S'1

S'0

CLK

Reset

S1

S0

A

Y

S0S1

S'1 = S1 S0 + S1 S0 A S'0 = S1 S0 A + S1S0 A + S1S0 A Y = S1 S0 A

Moore and Mealy Timing Diagram

n 70

Mealy Machine

Moore Machine

CLK

Reset

A

S

Y

S

Y

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S0 S3?? S1 S2 S4 S4S2 S3 S0

1 1 0 1 1 0 1 01

S2

S0 S3?? S1 S2 S1 S1S2 S3 S0S2

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSMreset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

n 12/24/13

n 36

Difference between Moore and Mealy

•  A Moore machine typically has more states than a Mealy machine for a given problem

•  A Mealy machine’s output rises a cycle sooner because it responds to the input rather than waiting for the state change

•  When choosing your FSM design style, consider when you want your outputs to respond

n 71

FSM Design Procedure •  Identify inputs and outputs

•  Sketch a state transition diagram

•  Write a state transition table

•  Select state encodings

•  For a Moore machine §  Rewrite the state transition table with the state encodings §  Write the output table

•  For a Mealy machine §  Rewrite the combined state transition table and output table with the state encodings

•  Write Boolean equations for the next state and output logic

•  Sketch the circuit schematic n 72