21 • 2011 IEEE International Solid-State Circuits Conference

ISSCC 2011 / SESSION 6 / SENSORS & ENERGY HARVESTING / 6.7

6.7 A 1.32pW/frame •pixel 1.2V CMOS Energy-Harvesting and Imaging (EHI) APS Imager

Suat U. Ay

University of Idaho, Moscow, ID

Recent advances in video sensor networks and implantable biomedical devices–e.g. retinal prostheses [1]– necessitate very low-voltage, low-leakage, andenergy-efficient image sensors that preferably produce their own power fromambient sources. A natural energy source for an image sensor that producesvideo images from impinging “sufficient” amount of light energy is the lightitself. This in mind, a CMOS image sensor that can both produce power fromlight and capture video images on same focal plane is developed. The CMOSenergy harvesting and imaging (EHI) active pixel sensor (APS) is incorporated ina 54×50 array along with low-power supporting electronics. It is designed in amature 0.5µm 2P3M CMOS process that has only high-Vt transistors.

A mixed-signal circuit design technique called supply boosting (SBT) [2,3] is uti-lized to overcome dynamic range and switch overdrive issues emanating fromthe low supply voltage of 1.2V and high-Vt. In SBT, the supply voltage is boost-ed locally once without compromising reliability margins of the process in use,while analog signal processing such as level shifting, amplification, or compari-son is performed. SBT is used in designing both a pixel source follower (PSF)and an improved version of a supply-boosted successive approximation registertype (SB-SAR) ADC from [3] for the EHI imager.

A circuit diagram of the EHI imager is shown in Fig. 6.7.1. The EHI pixel is com-posed of 2 photodiodes. One works as the integrating-type photodiode (D2) forimaging, and the other works as the micro solar cell (D1) for energy harvesting.The pixel contains 4 NMOS transistors. M1 is for resetting the FD node. M2 andM3 are the source follower and select transistors. M4 is the enable transistor forenergy harvesting. Anodes of D1s are connected to an energy-harvesting bus(EHB). Depending on the operation mode, EHB is either connected to ground(imaging mode, IM) or to an on-chip charge pump (CP) or directly to a load(energy harvesting mode-EHM). In IM, D1 and D2 work in parallel to dischargethe FD node. The FD node voltage is buffered to a column analog signal proces-sor (ASP) like a regular 3T APS pixel, and processed for imaging. During EHM,M4 is turned on shorting D2, and forcing D1 to work as a regular solar cell.

Timing diagrams for IM and EHM are shown in Fig. 6.7.2. A 1.2V supply makesbuffering FD node voltages impossible because of the high threshold voltage ofthe NMOS transistor (+0.8V), and its backgate bias. Thus, pixel reset and selectsignals are both boosted while SBT is utilized for PSF by boosting the pixel sup-ply voltage (VAAB) during row read. The pixel supply (VAAB) is driven by the sup-ply booster circuit (Fig. 6.7.1). When IN is asserted high (VAA), VAAB is boostedclose to 2VAA, and drops to VAA when IN is low. An on-chip 170pF booster capac-itor is used due to the very low PSF current consumption. Charge-based columnASPs, coupled to a single global charge amplifier [5], and a 10b SB-SAR ADCare used in the design to achieve low power. Reference currents are generatedon chip. 6b programmable current DACs are used to generate bias currents with60nA steps at 1.2V supply.

The EHI pixel layout is shown in Fig. 6.7.3. Die area for the imager is 2×2mm2

while the pixel size is 21µm2. An Nwell/P+/P-sub structure is used to form D1(P+/N-well) and D2 (N-well/P-sub) [4]. P+ is directly connected to EHB, while theN-well is connected to the drain of reset (M1) and gate of PSF (M2) transistors.A pixel fill factor of 32% was achieved due to the N-well design rules, the extratransistor (M4) area, and the extra routings of EHB and ground signals.

Two operation modes are available during EHM: direct drive (DD) and chargepump (CP). In both cases, all D1s are connected between EHB and groundthrough M4. During CP-EHM, all control signals except CP clock are stopped.The reference generator and iDACs are also turned off right after the CP com-parator bias is sampled. Thus, only the CP comparator consumes static power.

External capacitors CP1=1mF and CP2=10nF are used to measure CP efficiencyand rise time. The measured rise time is 270s achieving an efficiency levelbetween 70% and 89%, depending on the light level. Rise time depends on theCP1 value and can be reduced further by choosing it close to CP2. During CP-EHM, total power consumption of the chip is <1µW. CP control logic is designedsuch that the charge from CP2 is transferred to CP1 completely in 8 clock cycleswhile sequentially triggering clock phases as shown in Fig. 6.7.2.

Energy-harvesting efficiency and current-voltage/power-voltage (I-V/P-V) char-acteristics of the EHI pixels are measured for different light levels between1,000lux (overcast daylight) and 60,000lux (sunny daylight) at DD-EHM by usingan external load resistor (RL), as shown on Fig. 6.7.4a. At the maximum powerpoint (MPP), the 54×50 EHI pixel array produces 380mV and 8.75µA, resultingin 3.35µW of power for 60,000lux illumination. Power reduces to 2.1µW and1.0µW for 20,000lux and 1,000lux (normal and overcast daylight), respectively.Short-circuit voltages of the cells are between 400 and 450mV. Harvesting effi-ciency is also measured to be around 9% as shown on Fig. 6.7.4b at the MPP ofthe EHI pixels.

Imaging mode measurements are performed at various supply voltages (1.2 to1.6V), 7.4fps frame rate, ¼ pixel saturation, and optimum bias settings withwhich the EHI imager produces low FPN images, as shown on Fig. 6.7.5. Fullchip power at 1.5V is 27.4µW. Detailed block powers are measured at 1.2V. Pixelarray power consumption is directly measured to be 22nA resulting in 26.4nWpower consumption. This is achieved by using SBT while biasing each PSF to78nA, and fast row sampling resulting in 0.52% per frame PSF activity. The SB-SAR ADC consumes 3.13µW while running at 20kS/s, less than half of its max-imum speed. The global amplifier consumes 2.17µW, while iDAC and referencegenerator consume 3.21µW. 16 timing and control signals are generated offchip. Thus, the largest power is consumed on pads, which is about 5.64µW. Totalleakage current when the chip is powered down is 80nA. As a result, total powerconsumption is 14.25µW for 1.2V supply and 7.4fps.

An imager figure of merit (iFOM) is defined to quantify the total energy con-sumption per pixel for one code quantization of effective pixel signals and fordriving them off chip. Thus, total power consumption of the chip is used for cal-culating iFOM in J/pixel-code. Both FOM (from [6]) and iFOM are calculated andshown on Fig. 6.7.6. The EHI imager has 1.32pW/frame-pixel FOM and696fJ/pixel-code iFOM achieving lowest power consumption. These do notinclude the EHI imager’s ability to harvest energy from light and could be furtherreduced if a low-power MPP tracer and regulator is incorporated on-chip to drivechip power from a larger CP1.

Acknowledgments:This work was made possible by support from Micron Technology Foundation.

References:[1] L. Theogarajan, et al., “Minimally Invasive Retinal Prosthesis,” ISSCC Dig.Tech. Papers, pp.99-108, Feb. 2006[2] A. Mesgarani, et al., “Supply Boosting Technique for Designing Very Low-Voltage Mixed-Signal Circuits in Standard CMOS,” MWSCAS Dig. Tech. Papers,pp.893-896, Aug. 2010.[3] S. U. Ay, “A sub-1Volt 10-bit Supply Boosted SAR ADC Design in StandardCMOS,” Int. Journal on Analog Integrated Circuits and Signal Processing, Aug.2010.[4] M. Ferri, et al., “Integrated Micro-Solar Cell Structures for HarvestingSupplied Microsystems in 0.35-µm CMOS Technology,” IEEE SensorsConference, pp.542-545, Oct. 2009.[5] K.-B. Cho, et al., “A 1.5-V 550-µW 176x144 Autonomous CMOS Active PixelImage Sensor,” IEEE Tran. Elec. Dec., vol. 50/1, pp. 96-105, Jan 2003.[6] K. Kagawa, et al., “A 3.6pW/frame-pixel 1.35V PWM CMOS Imager withDynamic Pixel Readout and no Static Bias Current,” ISSCC Dig. of Tech. Papers.pp. 54-595, Feb. 2008.

©2011 IEEE

Session_06_Session_ 11/24/10 1:14 PM Page 21

22DIGEST OF TECHNICAL PAPERS •

ISSCC 2011 / February X, 2011 / X:XX XX

Figure 6.7.1: Circuit diagram of the EHI CMOS APS imager. Figure 6.7.2: Timing diagram of the EHI CMOS APS imager.

Figure 6.7.3: Energy harvesting and imaging (EHI) pixel layout.

Figure 6.7.5: Full chip power consumption and captured images at differentsupply voltages.

Figure 6.7.6: Performance comparison of the EHI imager and similar low-power imagers from [5] and [6].

Figure 6.7.4: Measured energy-harvesting characteristics of the EHI imager:(a) voltage-current/voltage-power (I-V/V-P) curves, (b) input-ouput powercharacteristics at maximum power point (MPP) for harvesting efficiency.

6

Session_06_Session_ 11/24/10 1:14 PM Page 22

23 • 2011 IEEE International Solid-State Circuits Conference ©2011 IEEE

ISSCC 2011 PAPER CONTINUATIONS

Figure 6.7.7: Micrograph of the EHI imager chip.

Session_06_Session_ 11/24/10 1:14 PM Page 23