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39
Session 1 BiTS Workshop 2007 Archive ARCHIVE 2007 DESIGNING FOR SOCKET ELECTRICAL INTEGRITY “Determining Inductance In Contactors” Ryan Satrom Everett Charles Technologies STG “Evaluation of a New Low Inductance Socket Technology - For High Speed Memory Device Testing” Joachim Moerbt Advantest (Europe) GmbH “Socket Life Cycle RF Testing” Gert Hohenwarter GateWave Northern, Inc. COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2007 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors. There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies. All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in & Test Socket Workshop’ are trademarks of BiTS Workshop LLC.

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Page 1: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

Session 1

BiTS Workshop 2007 Archive

ARCHIVE 2007

DESIGNING FOR SOCKET ELECTRICAL INTEGRITY

“Determining Inductance In Contactors” Ryan Satrom

Everett Charles Technologies STG

“Evaluation of a New Low Inductance Socket Technology - For High Speed Memory Device Testing”

Joachim Moerbt Advantest (Europe) GmbH

“Socket Life Cycle RF Testing” Gert Hohenwarter

GateWave Northern, Inc.

COPYRIGHT NOTICE

The papers in this publication comprise the proceedings of the 2007 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the

authors.

There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use

reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.

All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in & Test Socket Workshop’ are trademarks of BiTS Workshop LLC.

Page 2: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

1

Designing For Socket Electrical Integrity

Determining Inductance in Contactors

Ryan Satrom ECT - Semiconductor Test Group, MN2007 BiTS Workshop

TM

2

Introduction• Inductance

– Critical to contactor performance– Often interpreted incorrectly.

• Industry specs– Good for relative comparisons between probes– Not helpful when modeling and determining

inductance through contactor• Must increase our understanding to improve our

models and better predict performance

Page 3: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

2

Designing For Socket Electrical Integrity

3

The Problem• Two different definitions throughout industry• Defined different for signal integrity vs. power delivery• Often-used Definitions:

– Signal Integrity (Controlled Impedance): • Function of pitch, ground location(s) w.r.t. signal

– Power Delivery (Low Inductance): • Function of number of ground probes

regardless of location

4

The Problem• Loop inductance does not change depending on the

type of signal passing through the network• Therefore, these two inductance definitions cannot

both be completely accurate.• Must develop an understanding that doesn’t break

down, regardless of application• Must be consistent with electromagnetic theory

Page 4: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

3

Designing For Socket Electrical Integrity

5

Agenda

• Basic principles of inductance

• Comparison between an inductor and a probe

• An accurate understanding of inductance

• Examples using EM simulation

6

Principles of Inductance

• Inductance is the quantity of magnetic field lines per amp of current

• Magnetic field lines encircle all current-carrying conductors

• Current only flows in a loop. Likewise, inductance can only be measured in a loop

• Self-inductance and mutual-inductance are strictly mathematical concepts that cannot be explicitly measured.

Page 5: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

4

Designing For Socket Electrical Integrity

7

Principles of Inductance• Equation for loop inductance:

LLOOP = LSIG + LRTN – 2 x LMUTUAL

• LSIG, LRTN : Self-Inductance of signal path, return path

• LMUTUAL: Mutual Inductance between signal path and return path

• Loop inductance, LLOOP is the only value that can actually be measured

• Self-inductance or mutual-inductance alone provides little or no value

• Loop inductance is primary concern

8

Inductance in Contactors• Inductance in contactors is:

– Defined in a loop• Signal-Ground loop for Signals• Power-Ground loop for Power Delivery

– Power pins are the signal path for power delivery nets

– A function of pitch– A function of ground proximity and number of

adjacent ground pins• The quantity and positioning of ground probes

is best evaluated through 3D simulation• Loop inductance can be optimized for the

application and cost trade-offs

Page 6: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

5

Designing For Socket Electrical Integrity

9

Inductance in Contactors• Lower Inductance ≠ Higher Bandwidth

– Lower inductance does not necessarily yield higher bandwidth

– Increased bandwidth calls for controlled impedance• Not as concerned with inductance value• Concern is ratio of inductance to

capacitance• Power delivery focuses on minimizing inductance

10

Probe-Inductor Comparison• Reason for Comparison

– For Power Delivery, many engineers assume that a probe acts as an inductor

– Using this assumption, circuit theory is applied to derive the contactor inductance as being equal to the inductance spec divided by the number of ground probes

– Probes cannot be accurately modeled as inductors

– To determine inductance through contactor, must consider all source probes and ground probes

Page 7: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

6

Designing For Socket Electrical Integrity

11

Wire-Wound Inductors• Majority of magnetic fields are contained inside

windings• Inductance is a function of number of turns, size of

loop, and thickness of conductor• Inductance value is determined by loop inductance

from input lead (signal) to output lead (return)

SIGNAL RETURN

12

Inductance in Contactors• Current does not flow in helical direction• Size of loop is defined by both signal and return paths

– Individual probe does not create loop • Increasing number of parallel probes in path will

decrease inductance• However, must understand how currents travel to

understand which probes will impact inductance– All signals and currents will travel in the path of least

impedance

Page 8: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

7

Designing For Socket Electrical Integrity

13

DC Currents• At DC, impedance is dominated by resistance• Resistance of each probe approximately equal, so

current will travel equally through each probe

14

RF Currents• At RF, impedance is dominated by inductance• Same-direction currents will repel to decrease self-

inductance

Note: For a more thorough explanation, see “Signal Integrity - Simplified”, Eric Bogatin, 2004

Page 9: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

8

Designing For Socket Electrical Integrity

15

RF Currents• Opposite-direction (source and return) currents will

attract to each other to decrease mutual-inductance

16

RF Current - MLF/QFN• Return path will be dictated by path of least impedance• Ground probe(s) physical spacing with respect to source

will have a large effect on inductance• Excessive ground probes will provide little or no benefit

to lower loop inductance while adding cost– They may benefit for other reasons such as thermal

or contact resistance

Page 10: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

9

Designing For Socket Electrical Integrity

17

Modeling Inductance• Full device too large for 3D Solver• Must partition into manageable parts• Make sure to include all probes that will effect results • Simulate inductance of each part individually• Equivalent inductance of contactor is determined by

parallel combination of each power/ground loop inductance

Note: See also “Contactor Characterization of RF Test/Burn In”, Ling Li Ong and Tim Swettlen, BiTS 2006

18

Modeling Example• Simulate Partition of MLF/QFN device contactor• One power pin (signal path)• Probes in center array provide only ground reference

Page 11: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

10

Designing For Socket Electrical Integrity

19

Plotting the RF Currents• Same-direction currents repel

Opposite-direction currents attract

• Most of the current travels on probes closest to signal path

20

Modeling Results

• Inductance increases as pitch increases

• Probes closest to signal path have the greatest effect on inductance

1 Row Gnd Probes

2 Rows Gnd Probes

0.5mm 1.02 1.051mm 1.55 1.55

1.5mm 1.92 1.902mm 2.16 2.15

2.5mm 2.41 2.41

Inductance (nH)Ground Distance

Page 12: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #1

11

Designing For Socket Electrical Integrity

21

Conclusion• Inductance is a critical parameter that is often

interpreted incorrectly.• Loop inductance is best determined and optimized

through 3D simulation.– For Signal Integrity, path impedance can be

optimized for the application through modifying loop inductance to match impedance

• It is important to increase our understanding in order to improve our models and better predict performance

• Inductance must be defined in a way that is consistent for all applications

22

Thanks!Feedback is greatly appreciated

Feel free to contact me at [email protected]

Page 13: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

1

Designing For Socket Electrical Integrity

Evaluation of a new low inductance socket

technology– for high speed memory device testing

2007 Burn-in and Test Socket WorkshopMarch 11 - 14, 2007

Joachim Moerbt Advantest (Europe) GmbH

BiTS 2007New socket technology

2

Outline

• Target of the new socket• A new socket type• Evaluation phases of the new socket

• Electrical parameters• Mechanical reliability• Device under test• Yield evaluation• Handling method

• Conclusion

Page 14: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

2

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

3

TargetData Rate trends for memory devices• DDR-II/III• Graphic DRAM• Data rates > 2Gbit/sec

BiTS 2007New socket technology

4

Target• High speed memory devices• GDRAM, DDR-III, X-DRAM• 1GHz and beyond• Pin pitch 0.75mm

Page 15: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

3

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

5

New socket type

• New concept• No spring probe• Ultra low profile• Low inductance

Nu socket™

BiTS 2007New socket technology

6

Evaluation Phases

I. Electrical parameters• Self inductance• Bandwidth• Contact resistance, force - travel

II. Mechanical reliability• Contact resistance versus contact cycles• Scratch mark

III. Device under test on new socketIV. Yield evaluation under full productionV. Handling Method

Page 16: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

4

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

7

I. Electrical Parameters

• Self inductance

Rp

Rs

Ls

Low Inductance

Test Port

Test Port

Equivalent Circuit Model

• RF Impedance/Material Analyzer:HP4291A (1MHz ~ 1.8GHz)

• Test Fixture:HP16301

• Single probe measured

BiTS 2007New socket technology

8

I. Electrical Parameters

Nu-Socket® Inductance

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Frequency(GHz)

Indu

ctan

ce(n

H)

Target: 0.4nH

Page 17: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

5

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

9

I. Electrical Parameters

• Bandwidth • Vector Network Analyzer:Rohde & Schwarz ZVM(10MHz – 20GHz)

• Single probe measured

Test Port

Test Port

VS VINNu-Socket™

Terminal

4 terminal circuit

BiTS 2007New socket technology

10

I. Electrical Parameters

Nu-Socket® Bandwidth Measurement

-5

-4

-3

-2

-1

0

0 2 4 6 8 10 12 14 16 18 20Freqencey(GHz)

Inse

rtio

n L

oss(

dB)

Target:>8GHz @ -1dB>12GHz @ -2dB

Page 18: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

6

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

11

I. Electrical Parameters

• Force Analyzer:AIKOH

• DC Voltage Current Source/ Monitor: TR6143

• Single probe measured

DQ

DUT

Socket Board

Asource=100μA

TR6143 Press

• Contact resistance, force - travel

Nu-Socket™

ISVM Measurement

BiTS 2007New socket technology

12

Force Measurement & Contact-Resistance

0

5

10

15

20

25

30

35

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16

Stroke(mm)

Forc

e(gf

/pin

)

0

0.1

0.2

0.3

0.4

0.5

Con

tact

-Res

istan

ce(Ω

)

Meas Force Meas Contact-Resistance

I. Electrical Parameters

Target contact resistance: 0.2Ω

Page 19: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

7

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

13

II. Mechanical Reliability

• Mechanical reliability • Data Acquisition/Switch Unit: HP34970A

• Dynamic Test Handler: M6542AD

• Dummy Device : Au ball• Measured 60 probes

Vm

Itest

Hi forceLow force

Low sense Hi sense

Contact-Resistance

BiTS 2007New socket technology

14

II. Mechanical ReliabilityContact reliability

0.00

0.10

0.20

0.30

0.40

0.50

0 10000 20000 30000 40000 50000

Contact Cycle

Con

tact

Res

ista

nce(Ω)

Target contact resistance: 0.2Ω

Page 20: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

8

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

15

0.5mm

Lead-free solder alloy, single contact

II. Mechanical Reliability• Scratch Mark of the Nu-Socket™

BiTS 2007New socket technology

16

III. Device under test

• Device under test on new socket

• Test System: T5501• 4 Device GDDR3, 136 pins• Manual operation• Comparable measurement with

1.5nH spring probe socket

Page 21: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

9

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

17

III. Device under test

• Measurement result• 32 data signals, cycled over the DUT position• New socket: reduced setup and hold times

Data setup and hold timesnu-socket versus spring probe

0%

10%

20%

30%

40%

50%

60%

reduced equal increased

tdstdh

BiTS 2007New socket technology

18

IV. Yield evaluation

• Yield benefits under full production

• Test System: T5501• More than 3000 devices

productive GDDR3• Parallelism: 8 DUT• Handler operation: M6771

• Comparable measurement with 1.5nH spring probe socket

• Verification of speed sorting

Page 22: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

10

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

19

IV. Yield evaluation• Results of comparable measurement

• Higher speed class sorting increased• Max. frequency for test increased• Setup and hold times comparable• Scratch marks

acceptable• Contact reliability

to be improved

Speed class sorting

40%63%

2%

60%35%

0%

25%

50%

75%

100%

Spring probesocket

nu socket

Speed sort 1Speed sort 2Contact fail

BiTS 2007New socket technology

20

V. Handling method

• Changing the concept for handling

• Ultra low profile:Contact height reduced

• Reliable seating required for carrying:

New carrier shape• Compatibility for spring probe

socket required

Page 23: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

11

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

21

V. Handling method

• Contact of the Nu socket™ versus spring probe socket

DCC body(A)

Pusher base(A)

DCC body(A)

Pusher base(B)

adjusted by handler

BiTS 2007New socket technology

22

V. Handling method

• Force distribution Spring probe Nu-socket™

Contact Forcepusher pusher

F1 [spring probe] > F2 [Nu-socket™]

F1 F2

Page 24: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

Narch 11 - 14, 2007

Paper #2

12

Designing For Socket Electrical Integrity

BiTS 2007New socket technology

23

Conclusion• Very good electrical parameters• Long term reliability acceptable for

production – to be improved after field experiences

• Long term production evaluation ongoing• Contact reliability improved• Reliable handling solution available• Yield increase and improved speed

sorting can be expected

Page 25: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

1

Designing For Socket Electrical Integrity

Socket Life Cycle RF Testing

2007 Burn-in and Test Socket WorkshopMarch 12 - 15, 2006

Gert HohenwarterGateWave Northern, Inc.

www.gatewave.com

1/2007 BiTS 2007 Socket Life Cycling Test 2

A challenging test project was initiated by Analog Devices…..

• Determine variations in RF performance throughout a test regimen of 1 million cycles

• Test a significant number of sockets• Sockets provided by manufacturers• Data provided to manufacturers, then to AD

Page 26: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

2

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 3

Test Protocol

•• Perform initial characterizationPerform initial characterization•• Perform 4 successive measurementsPerform 4 successive measurements

(DUT probe engages/disengages)•• Run prescribed cycle numberRun prescribed cycle number

(exchange of surrogates as needed)•• Perform next set of 4 measurementsPerform next set of 4 measurements

•• Continue sequences until 1M cycles Continue sequences until 1M cycles is reachedis reached

1 02 03 04 05 81926 81927 81928 81929 65536

10 6553611 6553612 6553613 26214414 26214415 26214416 26214417 104857618 104857619 104857620 1048576

Test # Cycle #Test # Cycle #

1/2007 BiTS 2007 Socket Life Cycling Test 4

Device Actuation

Surrogate DUT is inserted into socketand actuated by the parallel moving top plate

Page 27: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

3

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 5

Parallel Plate Cyclers

The moving plate is inside the frame

1/2007 BiTS 2007 Socket Life Cycling Test 6

Test Setup Requirements

• Total number of RF tests expected >500• Different types of sockets• Robust• Fast • Repeatable• Low cost / applicable to more than 1 DUT

Page 28: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

4

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 7

Test Setup for RF Measurements

DUT plate with RF connections

Base plate

1/2007 BiTS 2007 Socket Life Cycling Test 8

Test Setup for RF Measurements

Page 29: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

5

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 9

Repeatability

Data for 20 successive setup engagements/disengagements with a very thin

conductive elastomer inserted

S21 deviations (f)

0.00

0.10

0.20

0.30

0.40

0.50

0 10 20 30 40

f [GHz]

VARAVEDEVSTDEVDEVSQ

GWN 1004

1/2007 BiTS 2007 Socket Life Cycling Test 10

• S-parametersS11, S21, S31/41

• Capacitance• Inductance• Transmission line parameters• Crosstalk

Evaluation

Page 30: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

6

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 11

Models

• Lumped element model:valid to ~f = 1/[7*√(L*C)]

• Transmission line model:no frequency limits

C2C1L2

R6

R4

T2

1/2007 BiTS 2007 Socket Life Cycling Test 12

Test Result Presentation

It was not known a priori what types of variations were to be expected.

Evaluation therefore was set up to include several different statistical functions and data presentations.

Color sequence

Page 31: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

7

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 13

Test ResultsDevice ‘X’

Time domain:

Reflections from a THRU into 50 Ohms

TDR thru

-0.25-0.15-0.050.050.150.25

-0.15 -0.05 0.05 0.15t [ns]

rho

GWN 1004

Impedance (peak) = f(dataset#)

46.0

48.0

50.0

52.0

54.0

56.0

1 4 7 10 13 16 19

Test #

Z [O

hms]

1/2007 BiTS 2007 Socket Life Cycling Test 14

Test ResultsDevice ‘X’

Time domain:

Transmission THRU into 50 Ohms

TDT

0.0

0.20.4

0.6

0.81.0

1.2

-0.05 0.00 0.05t [ns]

rho

GWN 1004

-27 -8 10 28 46 64

S1S17

0.00.20.40.60.81.0

rho

t [ps]

Test #

TDT as a function of time and test #

GWN 1104

Deviations as a function of time

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

-0.15 -0.05 0.05 0.15t [ns]

rho

VARPSTDEVAVEDEVDEVSQSKEWDEVMAXDEVMIN

GWN 1004

Page 32: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

8

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 15

Return Loss

Frequency domain: Reflections from a THRU into 50 Ohms

S11 (f) thru

-45-40-35-30-25-20-15-10-50

0 10 20 30 40

f [GHz]

dB

GWN 1004

S11 (f) thru

-180

-120

-60

0

60

120

180

0 10 20 30 40f [GHz]

S11

[deg

]

GWN 903

1/2007 BiTS 2007 Socket Life Cycling Test 16

S11 for a THRU into 50 Ohms

0 4 8 12 16 20 24 28 32 36 40

S1S6

S11S16

-50-45-40-35-30-25-20-15-10-50

S11 [dB]

f [GHz]Test #

S11 (f, test #) GWN 1004

Page 33: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

20072007Session 1

March 11 - 14, 2007

Paper #3

9

Designing For Socket Electrical Integrity

1/2007 BiTS 2007 Socket Life Cycling Test 17

Insertion Loss

Frequency domain:

Transmission THRU into 50 Ohms

S21 (f)

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

0 10 20 30 40f [GHz]

dB

GWN 1004

S21 deviations (f)

0.0

0.5

1.0

1.5

2.0

2.5

0 10 20 30 40

f [GHz]

VARAVEDEVSTDEVDEVSQ

GWN 1004

1/2007 BiTS 2007 Socket Life Cycling Test 18

S21 thru

0

5 10

1519

24 29 34 38

S1S6

S11S16

-5

-4

-3

-2

-1

0

S21 [dB]

f [GHz]

Test #

S21 (f, test #) GWN 1004

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Inductance and

Capacitance

Parameter Changes:

Capacitance/Inductance

C(f)

0.0

0.5

1.0

1.5

2.0

0 10 20 30 40

f [GHz]

pF

GWN 1004

L(f)

0.00.5

1.01.52.0

2.53.0

0 10 20f [GHz]

nHGWN 1004

1/2007 BiTS 2007 Socket Life Cycling Test 20

Insertion Loss Standard Deviation

Standard deviation for all test series participants

S21 Standard Deviation (f)

00.5

11.5

22.5

3

0 10 20 30 40f [GHz]

dB

GWN107

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Insertion Loss Standard Deviation (averages, sample ‘Device X’ plus all participants)

S21 deviations (f)

0.0

0.5

1.0

1.5

2.0

0 10 20 30 40f [GHz]

Best performersTotal averageDevice X

GWN107

1/2007 BiTS 2007 Socket Life Cycling Test 22

Return Loss Standard Deviation(averages, all participants)

0 4 8

12 16 20 24 28 32 36 40

0246

8

10

12

dB

f [GHz]

S11 Standard Deviation (f)

GWN107

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1/2007 BiTS 2007 Socket Life Cycling Test 23

• RF characteristics are affected by

– particle buildup– contactor wear– contact surface wear– distortion/damage

Example Causes for Performance Changes

1/2007 BiTS 2007 Socket Life Cycling Test 24

Particle Buildup

Abraded metal particles collect on surfaces and in gaps Effect: Change of resistance capacitance, inductance, leakage, shorts

Page 37: Session 1 - gatewave.com · Session 1 March 11 - 14, 2007 Paper #1 3 Designing For Socket Electrical Integrity 5 Agenda • Basic principles of inductance • Comparison between an

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Contactor Wear

Wear of outer and inner contact surfacesEffect: Change of resistance and inductance.

1/2007 BiTS 2007 Socket Life Cycling Test 26

Contact Surface Wear

Wear of contact surfaces (PCB)Effect: Change of resistance.

Depth profile

-30

-20

-10

0

10

20

30

0 500 1000 1500x (um)

z (u

m)

GWN 107

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Distortion

Effect: Change of resistance, capacitance and inductance.

1/2007 BiTS 2007 Socket Life Cycling Test 28

• A test environment for cycling tests was established• A significant number of test sockets was evaluated• Performance changes were highlighted via data

presentation• Changes unique to RF testing were identified• Tests are capable of pointing out weaknesses in the

socket and contactor design

Conclusion

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Thank you to all customers who made this possible

Richard LiggieroEricia Gertsch

Prof. J.B.Beyer

Acknowledgements