set de instrucciones hc12

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)

22 MC9S12C-Family / MC9S12GC-Family Freescale SemiconductorRev 01.20

1.1.3 Block Diagram

Figure 1-1. MC9S12C-Family / MC9S12GC-Family Block Diagram

16K, 32K, 64K, 96K, 128K Byte Flash

1K, 2K, 4K Byte RAM

SCI

VDDR

VDDAVSSA

VRHVRL

ATD AN2

AN6

AN0

AN7

AN1

AN3AN4AN5

PAD3PAD4PAD5PAD6PAD7

PAD0PAD1PAD2

IOC2

IOC6

IOC0

IOC7

IOC1

IOC3IOC4IOC5

PT3PT4PT5PT6PT7

PT0PT1PT2

RXDTXD

SCK

MISO

PS3

PS0PS1PS2

SSSPIPT

ADPT

T

DD

RT

PTS

DD

RS

Voltage Regulator

VDD1VSS1

PWM

Signals shown in Bold are not available on the 52 or 48 Pin Package

DD

RAD

VDDAVSSA

TimerModule

VDDXVSSX

VRHVRL

VSSR

RESET

EXTALXTAL

BKGD

R/W

MODB/IPIPE1

XIRQ

NOACC/XCLKS

SystemIntegration

Module(SIM)

HCS12

Periodic Interrupt

COP WatchdogClock Monitor

Background

PLLVSSPLL

XFCVDDPLL

Multiplexed Address/Data Bus

MultiplexedWide Bus

IRQ

LSTRB/TAGLOECLKMODA/IPIPE0

PA4

PA3

PA2

PA1

PA0

PA7

PA6

PA5

TEST/VPP

ADDR

12AD

DR11

ADDR

10AD

DR9

ADD

R8

ADDR

15AD

DR14

ADDR

13DA

TA12

DATA

11DA

TA10

DATA

9DA

TA8

DATA

15DA

TA14

DATA

13

PB4

PB3

PB2

PB1

PB0

PB7

PB6

PB5

ADD

R4

ADDR

3AD

DR2

ADDR

1AD

DR0

ADDR

7AD

DR6

ADDR

5DA

TA4

DATA

3DA

TA2

DATA

1DA

TA0

DATA

7DA

TA6

DATA

5

PE3PE4PE5PE6PE7

PE0PE1PE2

DDRA DDRB

PTA PTB

DD

RE

PTE

Debug12 Module

VDD2VSS2

Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package

CPU

PM3PM4PM5

PM0PM1PM2

PTM

DD

RM

PW2

PW0PW1

PW3PW4PW5

PP3PP4PP5PP6PP7

PP0PP1PP2

PTP

DD

RP

PJ6PJ7PT

J

DD

RJ

VDD1,2VSS1,2

VDDXVSSX

Internal Logic 2.5V

VDDPLLVSSPLL

PLL 2.5V

I/O Driver 5V

VDDAVSSA

A/D Converter 5V

VDDRVSSR

Voltage Regulator 5V & I/O

VRL is bonded internally to VSSAfor 52- and 48-Pin packages

MOSI

Module

MUX

Keyp

ad In

terru

ptKe

y In

t

MODC

MSCAN is not available on the9S12GC Family Members

Clock andReset

GenerationModule

MSCANTXCANRXCAN

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

jdiazs

Highlight

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)

Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family 27 Rev 01.20

Figure 1-5. MC9S12C32 and MC9S12GC32 User Configurable Memory Map

0x0000

0xFFFF

0xC000

0x8000

0x4000

0x0400

0xFF00

EXT

NORMALSINGLE CHIP

EXPANDED SPECIALSINGLE CHIP

VECTORSVECTORS

0xFF00

0xFFFF

BDM(If Active)

0xC000

0xFFFF

16K Fixed Flash EEPROM

0x8000

0xBFFF

16K Page Window2 * 16K Flash EEPROM Pages

0x3800

0x3FFF

0x0000

0x03FF

1K Register Space

Mappable to any 2K Boundary

Mappable to any 2K Boundary

2K Bytes RAM0x3800

The figure shows a useful map, which is not the map out of reset. After reset the map is:

0x0000–0x03FF: Register space0x0800–0x0FFF: 2K RAM

VECTORS

Flash erase sector size is 512 bytes

PAGE MAP

0x003E

0x003F

PPAGE

The flash page 0x003E is visible at 0x4000–0x7FFF in the memory map if ROMHM = 0.

In the figure ROMHM = 1 removing page 0x003E from 0x4000–0x7FFF.

© Motorola, Inc., 2001

CPU12RG/DRev. 2, 11/2001

CPU12 Reference Guide(for HCS12 and original M68HC12)

Reference Guide

Figure 1. Programming Model

7

15

15

15

15

15

D

X

Y

SP

PC

A B

NS X H I Z V C

0

0

0

0

0

0

70

CONDITION CODE REGISTER

8-BIT ACCUMULATORS A AND B

16-BIT DOUBLE ACCUMULATOR D

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

PROGRAM COUNTER

OR

STOP DISABLE (IGNORE STOP OPCODES)RESET DEFAULT IS 1

CARRY

OVERFLOW

ZERO

NEGATIVE

MASK (DISABLE) IRQ INTERRUPTS

HALF-CARRY (USED IN BCD ARITHMETIC)

MASK (DISABLE) XIRQ INTERRUPTSRESET OR XIRQ SET X,INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X

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Freescale Semiconductor, Inc.

For More Information On This Product, Go to: www.freescale.com

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CPU12RG/D

2 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA

Stack and Memory Layout

Interrupt Vector Locations

Notation Used in Instruction Set Summary

SP BEFOREINTERRUPT

SP AFTERINTERRUPT

HIGHER ADDRESSES

LOWER ADDRESSES

RTNLO

RTNHI

YLO

YHI

XLO

XHI

A

B

CCR

STACK UPON ENTRY TO SERVICE ROUTINEIF SP WAS ODD BEFORE INTERRUPT

STACK UPON ENTRY TO SERVICE ROUTINEIF SP WAS EVEN BEFORE INTERRUPT

SP +8 RTNLO SP +9 SP +9 SP +10

SP +6 YLO RTNHI SP +7 SP +7 RTNHI RTNLO SP +8

SP +4 XLO YHI SP +5 SP +5 YHI YLO SP +6

SP +2 A XHI SP +3 SP +4 XHI XLO SP +4

SP CCR B SP +1 SP +1 B A SP +2

SP –2 SP –1 SP –1 CCR SP

$FFFE, $FFFF$FFFC, $FFFD$FFFA, $FFFB$FFF8, $FFF9$FFF6, $FFF7$FFF4, $FFF5$FFF2, $FFF3$FFC0–$FFF1

Power-On (POR) or External ResetClock Monitor ResetComputer Operating Properly (COP Watchdog ResetUnimplemented Opcode TrapSoftware Interrupt Instruction (SWI)XIRQIRQDevice-Specific Interrupt Sources

CPU Register NotationAccumulator A — A or a Index Register Y — Y or yAccumulator B — B or b Stack Pointer — SP, sp, or sAccumulator D — D or d Program Counter — PC, pc, or pIndex Register X — X or x Condition Code Register — CCR or c

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CPU12RG/D

MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 3

Explanation of Italic Expressions in Source Form Columnabc — A or B or CCR

abcdxys — A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3.abd — A or B or D

abdxys — A or B or D or X or Y or SPdxys — D or X or Y or SP

msk8 — 8-bit mask, some assemblers require # symbol before valueopr8i — 8-bit immediate value

opr16i — 16-bit immediate valueopr8a — 8-bit address used with direct address mode

opr16a — 16-bit address valueoprx0_xysp — Indexed addressing postbyte code:

oprx3,–xys Predecrement X or Y or SP by 1 . . . 8oprx3,+xys Preincrement X or Y or SP by 1 . . . 8oprx3,xys– Postdecrement X or Y or SP by 1 . . . 8oprx3,xys+ Postincrement X or Y or SP by 1 . . . 8oprx5,xysp 5-bit constant offset from X or Y or SP or PCabd,xysp Accumulator A or B or D offset from X or Y or SP or PC

oprx3 — Any positive integer 1 . . . 8 for pre/post increment/decrementoprx5 — Any integer in the range –16 . . . +15oprx9 — Any integer in the range –256 . . . +255

oprx16 — Any integer in the range –32,768 . . . 65,535page — 8-bit value for PPAGE, some assemblers require # symbol before this value

rel8 — Label of branch destination within –256 to +255 locationsrel9 — Label of branch destination within –512 to +511 locations

rel16 — Any label within 64K memory spacetrapnum — Any 8-bit integer in the range $30-$39 or $40-$FF

xys — X or Y or SPxysp — X or Y or SP or PC

Operators

+ — Addition

±

— Subtraction

• — Logical AND

+ — Logical OR (inclusive)

⊕ — Logical exclusive OR

× — Multiplication

÷ — Division

M — Negation. One’s complement (invert each bit of M)

: — ConcatenateExample: A : B means the 16-bit value formed by concatenating 8-bit accumulator A with 8-bit accumulator B.A is in the high-order position.

Continued on next page

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CPU12RG/D


Operators (continued)

⇒ — TransferExample: (A) ⇒ M means the content of accumulator A is transferred to memory location M.

⇔ — ExchangeExample: D ⇔ X means exchange the contents of D with those of X.

Address Mode NotationINH — Inherent; no operands in object codeIMM — Immediate; operand in object codeDIR — Direct; operand is the lower byte of an address from $0000 to $00FFEXT — Operand is a 16-bit addressREL — Two’s complement relative offset; for branch instructionsIDX — Indexed (no extension bytes); includes:

5-bit constant offset from X, Y, SP, or PCPre/post increment/decrement by 1 . . . 8Accumulator A, B, or D offset

IDX1 — 9-bit signed offset from X, Y, SP, or PC; 1 extension byteIDX2 — 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes

[IDX2] — Indexed-indirect; 16-bit offset from X, Y, SP, or PC[D, IDX] — Indexed-indirect; accumulator D offset from X, Y, SP, or PC

Machine Codingdd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).ee — High-order byte of a 16-bit constant offset for indexed addressing.eb — Exchange/Transfer post-byte. See Table 3 on page 22.ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing,

or low-order byte of a 16-bit constant offset for indexed addressing.hh — High-order byte of a 16-bit extended address.ii — 8-bit immediate data value.jj — High-order byte of a 16-bit immediate data value.kk — Low-order byte of a 16-bit immediate data value.lb — Loop primitive (DBNE) post-byte. See Table 4 on page 23.ll — Low-order byte of a 16-bit extended address.mm — 8-bit immediate mask value for bit manipulation instructions.

Set bits indicate bits to be affected.pg — Program page (bank) number used in CALL instruction.qq — High-order byte of a 16-bit relative offset for long branches.tn — Trap number $30–$39 or $40–$FF.rr — Signed relative offset $80 (–128) to $7F (+127).

Offset relative to the byte following the relative offset byte, orlow-order byte of a 16-bit relative offset for long branches.

xb — Indexed addressing post-byte. See Table 1 on page 20 and Table 2 on page 21.

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CPU12RG/D


Access Detail

Each code letter except (,), and comma equals one CPU cycle. Uppercase = 16-bit operation and lowercase = 8-bit operation. For complex sequences see the CPU12 Reference Manual (CPU12RM/AD) for more detailed information.

Condition Codes Columns

f — Free cycle, CPU doesn’t use busg — Read PPAGE internallyI — Read indirect pointer (indexed indirect)i — Read indirect PPAGE value (CALL indirect only)n — Write PPAGE internallyO — Optional program word fetch (P) if instruction is misaligned and has

an odd number of bytes of object code — otherwise, appears as a free cycle (f); Page 2 prebyte treated as a separate 1-byte instruction

P — Program word fetch (always an aligned-word read)r — 8-bit data readR — 16-bit data reads — 8-bit stack writeS — 16-bit stack writew — 8-bit data writeW — 16-bit data writeu — 8-bit stack readU — 16-bit stack readV — 16-bit vector fetch (always an aligned-word read)t — 8-bit conditional read (or free cycle)T — 16-bit conditional read (or free cycle)x — 8-bit conditional write (or free cycle)

() — Indicate a microcode loop, — Indicates where an interrupt could be honored

Special Cases

PPP/P — Short branch, PPP if branch taken, P if notOPPP/OPO — Long branch, OPPP if branch taken, OPO if not

– — Status bit not affected by operation.0 — Status bit cleared by operation.1 — Status bit set by operation.∆ — Status bit affected by operation.? — Status bit may be cleared or remain set, but is not set by operation.⇑ — Status bit may be set or remain cleared, but is not cleared by operation.? — Status bit may be changed by operation but the final state is not defined.! — Status bit used for a special purpose.

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CPU12RG/D


Instruction Set Summary (Sheet 1 of 14)

Source Form Operation Addr.Mode

MachineCoding (hex)

Access DetailS X H I N Z V C

HCS12 HC12

ABA (A) + (B) ⇒ AAdd Accumulators A and B

INH 18 06 OO OO – – ∆ – ∆ ∆ ∆ ∆

ABX (B) + (X) ⇒ XTranslates to LEAX B,X

IDX 1A E5 Pf PP1 – – – – – – – –

ABY (B) + (Y) ⇒ YTranslates to LEAY B,Y

IDX 19 ED Pf PP1 – – – – – – – –

ADCA #opr8iADCA opr8aADCA opr16aADCA oprx0_xyspADCA oprx9,xyspADCA oprx16,xyspADCA [D,xysp]ADCA [oprx16,xysp]

(A) + (M) + C ⇒ AAdd with Carry to A

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

89 ii99 ddB9 hh llA9 xbA9 xb ffA9 xb ee ffA9 xbA9 xb ee ff

PrPfrPOrPfrPOfrPPfIfrPffIPrPf

PrfPrOPrfPrPOfrPP

flPrfPfIPrfP

– – ∆ – ∆ ∆ ∆ ∆

ADCB #opr8iADCB opr8aADCB opr16aADCB oprx0_xyspADCB oprx9,xyspADCB oprx16,xyspADCB [D,xysp]ADCB [oprx16,xysp]

(B) + (M) + C ⇒ BAdd with Carry to B

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

C9 iiD9 ddF9 hh llE9 xbE9 xb ffE9 xb ee ffE9 xbE9 xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – ∆ – ∆ ∆ ∆ ∆

ADDA #opr8iADDA opr8aADDA opr16aADDA oprx0_xyspADDA oprx9,xyspADDA oprx16,xyspADDA [D,xysp]ADDA [oprx16,xysp]

(A) + (M) ⇒ AAdd without Carry to A

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8B ii9B ddBB hh llAB xbAB xb ffAB xb ee ffAB xbAB xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – ∆ – ∆ ∆ ∆ ∆

ADDB #opr8iADDB opr8aADDB opr16aADDB oprx0_xyspADDB oprx9,xyspADDB oprx16,xyspADDB [D,xysp]ADDB [oprx16,xysp]

(B) + (M) ⇒ BAdd without Carry to B

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CB iiDB ddFB hh llEB xbEB xb ffEB xb ee ffEB xbEB xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – ∆ – ∆ ∆ ∆ ∆

ADDD #opr16iADDD opr8aADDD opr16aADDD oprx0_xyspADDD oprx9,xyspADDD oprx16,xyspADDD [D,xysp]ADDD [oprx16,xysp]

(A:B) + (M:M+1) ⇒ A:BAdd 16-Bit to D (A:B)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

C3 jj kkD3 ddF3 hh llE3 xbE3 xb ffE3 xb ee ffE3 xbE3 xb ee ff

PORPfRPORPfRPOfRPPfIfRPffIPRPf

OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

ANDA #opr8iANDA opr8aANDA opr16aANDA oprx0_xyspANDA oprx9,xyspANDA oprx16,xyspANDA [D,xysp]ANDA [oprx16,xysp]

(A) • (M) ⇒ ALogical AND A with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

ANDB #opr8iANDB opr8aANDB opr16aANDB oprx0_xyspANDB oprx9,xyspANDB oprx16,xyspANDB [D,xysp]ANDB [oprx16,xysp]

(B) • (M) ⇒ BLogical AND B with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

ANDCC #opr8i (CCR) • (M) ⇒ CCRLogical AND CCR with Memory

IMM 10 ii P P ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓

Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.

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CPU12RG/D


ASL opr16aASL oprx0_xyspASL oprx9,xyspASL oprx16,xyspASL [D,xysp]ASL [oprx16,xysp]ASLAASLB

Arithmetic Shift Left

Arithmetic Shift Left Accumulator AArithmetic Shift Left Accumulator B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH

78 hh ll68 xb68 xb ff68 xb ee ff68 xb68 xb ee ff4858

rPwOrPwrPwOfrPwPfIfrPwfIPrPwOO

rOPwrPwrPOwfrPPwfIfrPwfIPrPw

OO

– – – – ∆ ∆ ∆ ∆

ASLD

Arithmetic Shift Left Double

INH 59 O O – – – – ∆ ∆ ∆ ∆

ASR opr16aASR oprx0_xyspASR oprx9,xyspASR oprx16,xyspASR [D,xysp]ASR [oprx16,xysp]ASRAASRB

Arithmetic Shift Right

Arithmetic Shift Right Accumulator AArithmetic Shift Right Accumulator B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ ∆ ∆

BCC rel8 Branch if Carry Clear (if C = 0) REL 24 rr PPP/P1 PPP/P1 – – – – – – – –

BCLR opr8a, msk8BCLR opr16a, msk8BCLR oprx0_xysp, msk8BCLR oprx9,xysp, msk8BCLR oprx16,xysp, msk8

(M) • (mm) ⇒ MClear Bit(s) in Memory

DIREXTIDX

IDX1IDX2

4D dd mm1D hh ll mm0D xb mm0D xb ff mm0D xb ee ff mm

rPwOrPwPrPwOrPwPfrPwPO

rPOwrPPwrPOwrPwP

frPwOP

– – – – ∆ ∆ 0 –

BCS rel8 Branch if Carry Set (if C = 1) REL 25 rr PPP/P1 PPP/P1 – – – – – – – –

BEQ rel8 Branch if Equal (if Z = 1) REL 27 rr PPP/P1 PPP/P1 – – – – – – – –

BGE rel8 Branch if Greater Than or Equal(if N ⊕ V = 0) (signed)

REL 2C rr PPP/P1 PPP/P1 – – – – – – – –

BGND Place CPU in Background Modesee CPU12 Reference Manual

INH 00 VfPPP VfPPP – – – – – – – –

BGT rel8 Branch if Greater Than(if Z + (N ⊕ V) = 0) (signed)

REL 2E rr PPP/P1 PPP/P1 – – – – – – – –

BHI rel8 Branch if Higher(if C + Z = 0) (unsigned)

REL 22 rr PPP/P1 PPP/P1 – – – – – – – –

BHS rel8 Branch if Higher or Same (if C = 0) (unsigned) same function as BCC

REL 24 rr PPP/P1 PPP/P1 – – – – – – – –

BITA #opr8iBITA opr8aBITA opr16aBITA oprx0_xyspBITA oprx9,xyspBITA oprx16,xyspBITA [D,xysp]BITA [oprx16,xysp]

(A) • (M)Logical AND A with MemoryDoes not change Accumulator or Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

BITB #opr8iBITB opr8aBITB opr16aBITB oprx0_xyspBITB oprx9,xyspBITB oprx16,xyspBITB [D,xysp]BITB [oprx16,xysp]

(B) • (M)Logical AND B with MemoryDoes not change Accumulator or Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

BLE rel8 Branch if Less Than or Equal(if Z + (N ⊕ V) = 1) (signed)

REL 2F rr PPP/P1 PPP/P1 – – – – – – – –

BLO rel8 Branch if Lower(if C = 1) (unsigned)same function as BCS

REL 25 rr PPP/P1 PPP/P1 – – – – – – – –

Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.



MachineCoding (hex)


HCS12 HC12

C0

b7 b0

C0

b7 b0A Bb7b0

Cb7 b0

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CPU12RG/D


BLS rel8 Branch if Lower or Same(if C + Z = 1) (unsigned)

REL 23 rr PPP/P1 PPP/P1 – – – – – – – –

BLT rel8 Branch if Less Than(if N ⊕ V = 1) (signed)

REL 2D rr PPP/P1 PPP/P1 – – – – – – – –

BMI rel8 Branch if Minus (if N = 1) REL 2B rr PPP/P1 PPP/P1 – – – – – – – –

BNE rel8 Branch if Not Equal (if Z = 0) REL 26 rr PPP/P1 PPP/P1 – – – – – – – –

BPL rel8 Branch if Plus (if N = 0) REL 2A rr PPP/P1 PPP/P1 – – – – – – – –

BRA rel8 Branch Always (if 1 = 1) REL 20 rr PPP PPP – – – – – – – –

BRCLR opr8a, msk8, rel8BRCLR opr16a, msk8, rel8BRCLR oprx0_xysp, msk8, rel8BRCLR oprx9,xysp, msk8, rel8BRCLR oprx16,xysp, msk8, rel8

Branch if (M) • (mm) = 0(if All Selected Bit(s) Clear)

DIREXTIDX

IDX1IDX2

4F dd mm rr1F hh ll mm rr0F xb mm rr0F xb ff mm rr0F xb ee ff mm rr

rPPPrfPPPrPPPrfPPPPrfPPP

rPPPrfPPPrPPP

rffPPPfrPffPPP

– – – – – – – –

BRN rel8 Branch Never (if 1 = 0) REL 21 rr P P – – – – – – – –

BRSET opr8, msk8, rel8BRSET opr16a, msk8, rel8BRSET oprx0_xysp, msk8, rel8BRSET oprx9,xysp, msk8, rel8BRSET oprx16,xysp, msk8, rel8

Branch if (M) • (mm) = 0(if All Selected Bit(s) Set)

DIREXTIDX

IDX1IDX2

4E dd mm rr1E hh ll mm rr0E xb mm rr0E xb ff mm rr0E xb ee ff mm rr

rPPPrfPPPrPPPrfPPPPrfPPP

rPPPrfPPPrPPP

rffPPPfrPffPPP

– – – – – – – –

BSET opr8, msk8BSET opr16a, msk8BSET oprx0_xysp, msk8BSET oprx9,xysp, msk8BSET oprx16,xysp, msk8

(M) + (mm) ⇒ MSet Bit(s) in Memory

DIREXTIDX

IDX1IDX2

4C dd mm1C hh ll mm0C xb mm0C xb ff mm0C xb ee ff mm

rPwOrPwPrPwOrPwPfrPwPO

rPOwrPPwrPOwrPwP

frPwOP

– – – – ∆ ∆ 0 –

BSR rel8 (SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1)Subroutine address ⇒ PCBranch to Subroutine

REL 07 rr SPPP PPPS – – – – – – – –

BVC rel8 Branch if Overflow Bit Clear (if V = 0) REL 28 rr PPP/P1 PPP/P1 – – – – – – – –

BVS rel8 Branch if Overflow Bit Set (if V = 1) REL 29 rr PPP/P1 PPP/P1 – – – – – – – –

CALL opr16a, pageCALL oprx0_xysp, pageCALL oprx9,xysp, pageCALL oprx16,xysp, pageCALL [D,xysp]CALL [oprx16, xysp]

(SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1)(SP) – 1 ⇒ SP; (PPG) ⇒ M(SP); pg ⇒ PPAGE register; Program address ⇒ PC

Call subroutine in extended memory(Program may be located on anotherexpansion memory page.)

Indirect modes get program addressand new pg value based on pointer.

EXTIDX

IDX1IDX2

[D,IDX][IDX2]

4A hh ll pg4B xb pg4B xb ff pg4B xb ee ff pg4B xb4B xb ee ff

gnSsPPPgnSsPPPgnSsPPPfgnSsPPPfIignSsPPPfIignSsPPP

gnfSsPPPgnfSsPPPgnfSsPPPfgnfSsPPPfIignSsPPPfIignSsPPP

– – – – – – – –

CBA (A) – (B)Compare 8-Bit Accumulators

INH 18 17 OO OO – – – – ∆ ∆ ∆ ∆

CLC 0 ⇒ CTranslates to ANDCC #$FE

IMM 10 FE P P – – – – – – – 0

CLI 0 ⇒ ITranslates to ANDCC #$EF(enables I-bit interrupts)

IMM 10 EF P P – – – 0 – – – –

CLR opr16aCLR oprx0_xyspCLR oprx9,xyspCLR oprx16,xyspCLR [D,xysp]CLR [oprx16,xysp]CLRACLRB

0 ⇒ M Clear Memory Location

0 ⇒ A Clear Accumulator A0 ⇒ B Clear Accumulator B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH

79 hh ll69 xb69 xb ff69 xb ee ff69 xb69 xb ee ff87C7

PwOPwPwOPwPPIfwPIPwOO

wOPPwPwOPwP

PIfPwPIPPw

OO

– – – – 0 1 0 0

CLV 0 ⇒ VTranslates to ANDCC #$FD

IMM 10 FD P P – – – – – – 0 –

Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.



MachineCoding (hex)


HCS12 HC12

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nc

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CPU12RG/D


CMPA #opr8iCMPA opr8aCMPA opr16aCMPA oprx0_xyspCMPA oprx9,xyspCMPA oprx16,xyspCMPA [D,xysp]CMPA [oprx16,xysp]

(A) – (M)Compare Accumulator A with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

81 ii91 ddB1 hh llA1 xbA1 xb ffA1 xb ee ffA1 xb A1 xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆

CMPB #opr8iCMPB opr8aCMPB opr16aCMPB oprx0_xyspCMPB oprx9,xyspCMPB oprx16,xyspCMPB [D,xysp]CMPB [oprx16,xysp]

(B) – (M)Compare Accumulator B with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆

COM opr16aCOM oprx0_xyspCOM oprx9,xyspCOM oprx16,xyspCOM [D,xysp]COM [oprx16,xysp]COMACOMB

(M) ⇒ M equivalent to $FF – (M) ⇒ M1’s Complement Memory Location

(A) ⇒ A Complement Accumulator A

(B) ⇒ B Complement Accumulator B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ 0 1

CPD #opr16iCPD opr8aCPD opr16aCPD oprx0_xyspCPD oprx9,xyspCPD oprx16,xyspCPD [D,xysp]CPD [oprx16,xysp]

(A:B) – (M:M+1)Compare D to Memory (16-Bit)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8C jj kk9C ddBC hh llAC xbAC xb ffAC xb ee ffAC xbAC xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

CPS #opr16iCPS opr8aCPS opr16aCPS oprx0_xyspCPS oprx9,xyspCPS oprx16,xyspCPS [D,xysp]CPS [oprx16,xysp]

(SP) – (M:M+1)Compare SP to Memory (16-Bit)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8F jj kk9F ddBF hh llAF xbAF xb ffAF xb ee ffAF xbAF xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

CPX #opr16iCPX opr8aCPX opr16aCPX oprx0_xyspCPX oprx9,xyspCPX oprx16,xyspCPX [D,xysp]CPX [oprx16,xysp]

(X) – (M:M+1)Compare X to Memory (16-Bit)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8E jj kk9E ddBE hh llAE xbAE xb ffAE xb ee ffAE xbAE xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

CPY #opr16iCPY opr8aCPY opr16aCPY oprx0_xyspCPY oprx9,xyspCPY oprx16,xyspCPY [D,xysp]CPY [oprx16,xysp]

(Y) – (M:M+1)Compare Y to Memory (16-Bit)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8D jj kk9D ddBD hh llAD xbAD xb ffAD xb ee ffAD xbAD xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

DAA Adjust Sum to BCDDecimal Adjust Accumulator A

INH 18 07 OfO OfO – – – – ∆ ∆ ? ∆

DBEQ abdxys, rel9 (cntr) – 1⇒ cntrif (cntr) = 0, then Branchelse Continue to next instruction

Decrement Counter and Branch if = 0(cntr = A, B, D, X, Y, or SP)

REL(9-bit)

04 lb rr PPP (branch)PPO (no branch)

PPP – – – – – – – –



MachineCoding (hex)


HCS12 HC12

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CPU12RG/D


DBNE abdxys, rel9 (cntr) – 1 ⇒ cntrIf (cntr) not = 0, then Branch;else Continue to next instruction

Decrement Counter and Branch if ≠ 0(cntr = A, B, D, X, Y, or SP)

REL(9-bit)


PPP – – – – – – – –

DEC opr16aDEC oprx0_xyspDEC oprx9,xyspDEC oprx16,xyspDEC [D,xysp]DEC [oprx16,xysp]DECADECB

(M) – $01 ⇒ MDecrement Memory Location

(A) – $01 ⇒ A Decrement A(B) – $01 ⇒ B Decrement B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ ∆ –

DES (SP) – $0001 ⇒ SPTranslates to LEAS –1,SP

IDX 1B 9F Pf PP1 – – – – – – – –

DEX (X) – $0001 ⇒ XDecrement Index Register X

INH 09 O O – – – – – ∆ – –

DEY (Y) – $0001 ⇒ YDecrement Index Register Y

INH 03 O O – – – – – ∆ – –

EDIV (Y:D) ÷ (X) ⇒ Y Remainder ⇒ D32 by 16 Bit ⇒ 16 Bit Divide (unsigned)

INH 11 ffffffffffO ffffffffffO – – – – ∆ ∆ ∆ ∆

EDIVS (Y:D) ÷ (X) ⇒ Y Remainder ⇒ D32 by 16 Bit ⇒ 16 Bit Divide (signed)

INH 18 14 OffffffffffO OffffffffffO – – – – ∆ ∆ ∆ ∆

EMACS opr16a 2 (M(X):M(X+1)) × (M(Y):M(Y+1)) + (M~M+3) ⇒ M~M+3

16 by 16 Bit ⇒ 32 BitMultiply and Accumulate (signed)

Special 18 12 hh ll ORROfffRRfWWP ORROfffRRfWWP – – – – ∆ ∆ ∆ ∆

EMAXD oprx0_xyspEMAXD oprx9,xyspEMAXD oprx16,xyspEMAXD [D,xysp]EMAXD [oprx16,xysp]

MAX((D), (M:M+1)) ⇒ DMAX of 2 Unsigned 16-Bit Values

N, Z, V and C status bits reflect result ofinternal compare ((D) – (M:M+1))

IDXIDX1IDX2

[D,IDX][IDX2]

18 1A xb18 1A xb ff18 1A xb ee ff18 1A xb18 1A xb ee ff

ORPfORPOOfRPPOfIfRPfOfIPRPf

ORfPORPOOfRPP

OfIfRfPOfIPRfP

– – – – ∆ ∆ ∆ ∆

EMAXM oprx0_xyspEMAXM oprx9,xyspEMAXM oprx16,xyspEMAXM [D,xysp]EMAXM [oprx16,xysp]

MAX((D), (M:M+1)) ⇒ M:M+1MAX of 2 Unsigned 16-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 1E xb18 1E xb ff18 1E xb ee ff18 1E xb18 1E xb ee ff

ORPWORPWOOfRPWPOfIfRPWOfIPRPW


– – – – ∆ ∆ ∆ ∆

EMIND oprx0_xyspEMIND oprx9,xyspEMIND oprx16,xyspEMIND [D,xysp]EMIND [oprx16,xysp]

MIN((D), (M:M+1)) ⇒ DMIN of 2 Unsigned 16-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 1B xb18 1B xb ff18 1B xb ee ff18 1B xb18 1B xb ee ff

ORPfORPOOfRPPOfIfRPfOfIPRPf

ORfPORPOOfRPP

OfIfRfPOfIPRfP

– – – – ∆ ∆ ∆ ∆

EMINM oprx0_xyspEMINM oprx9,xyspEMINM oprx16,xyspEMINM [D,xysp]EMINM [oprx16,xysp]

MIN((D), (M:M+1)) ⇒ M:M+1MIN of 2 Unsigned 16-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 1F xb18 1F xb ff18 1F xb ee ff18 1F xb18 1F xb ee ff



– – – – ∆ ∆ ∆ ∆

EMUL (D) × (Y) ⇒ Y:D16 by 16 Bit Multiply (unsigned)

INH 13 ffO ffO – – – – ∆ ∆ – ∆

EMULS (D) × (Y) ⇒ Y:D16 by 16 Bit Multiply (signed)

INH 18 13 OfO OfO – – – – ∆ ∆ – ∆(if followed by page 2 instruction)

OffO OfO

EORA #opr8iEORA opr8aEORA opr16aEORA oprx0_xyspEORA oprx9,xyspEORA oprx16,xyspEORA [D,xysp]EORA [oprx16,xysp]

(A) ⊕ (M) ⇒ AExclusive-OR A with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

Notes:1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.2. opr16a is an extended address specification. Both X and Y point to source operands.



MachineCoding (hex)


HCS12 HC12

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CPU12RG/D


EORB #opr8iEORB opr8aEORB opr16aEORB oprx0_xyspEORB oprx9,xyspEORB oprx16,xyspEORB [D,xysp]EORB [oprx16,xysp]

(B) ⊕ (M) ⇒ BExclusive-OR B with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

ETBL oprx0_xysp (M:M+1)+ [(B)×((M+2:M+3) – (M:M+1))] ⇒ D16-Bit Table Lookup and Interpolate

Initialize B, and index before ETBL.<ea> points at first table entry (M:M+1)and B is fractional part of lookup value

(no indirect addr. modes or extensions allowed)

IDX 18 3F xb ORRffffffP ORRffffffP – – – – ∆ ∆ – ∆?

C Bit is undefined in HC12

EXG abcdxys,abcdxys (r1) ⇔ (r2) (if r1 and r2 same size) or$00:(r1) ⇒ r2 (if r1=8-bit; r2=16-bit) or(r1low) ⇔ (r2) (if r1=16-bit; r2=8-bit)

r1 and r2 may beA, B, CCR, D, X, Y, or SP

INH B7 eb P P – – – – – – – –

FDIV (D) ÷ (X) ⇒ X; Remainder ⇒ D16 by 16 Bit Fractional Divide

INH 18 11 OffffffffffO OffffffffffO – – – – – ∆ ∆ ∆

IBEQ abdxys, rel9 (cntr) + 1⇒ cntrIf (cntr) = 0, then Branchelse Continue to next instruction

Increment Counter and Branch if = 0(cntr = A, B, D, X, Y, or SP)

REL(9-bit)


PPP – – – – – – – –

IBNE abdxys, rel9 (cntr) + 1⇒ cntrif (cntr) not = 0, then Branch;else Continue to next instruction

Increment Counter and Branch if ≠ 0(cntr = A, B, D, X, Y, or SP)

REL(9-bit)


PPP – – – – – – – –

IDIV (D) ÷ (X) ⇒ X; Remainder ⇒ D16 by 16 Bit Integer Divide (unsigned)

INH 18 10 OffffffffffO OffffffffffO – – – – – ∆ 0 ∆

IDIVS (D) ÷ (X) ⇒ X; Remainder ⇒ D16 by 16 Bit Integer Divide (signed)

INH 18 15 OffffffffffO OffffffffffO – – – – ∆ ∆ ∆ ∆

INC opr16aINC oprx0_xyspINC oprx9,xyspINC oprx16,xyspINC [D,xysp]INC [oprx16,xysp]INCAINCB

(M) + $01 ⇒ MIncrement Memory Byte

(A) + $01 ⇒ A Increment Acc. A(B) + $01 ⇒ B Increment Acc. B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ ∆ –

INS (SP) + $0001 ⇒ SPTranslates to LEAS 1,SP

IDX 1B 81 Pf PP1 – – – – – – – –

INX (X) + $0001 ⇒ XIncrement Index Register X

INH 08 O O – – – – – ∆ – –

INY (Y) + $0001 ⇒ YIncrement Index Register Y

INH 02 O O – – – – – ∆ – –

JMP opr16aJMP oprx0_xyspJMP oprx9,xyspJMP oprx16,xyspJMP [D,xysp]JMP [oprx16,xysp]

Routine address ⇒ PC

Jump

EXTIDX

IDX1IDX2

[D,IDX][IDX2]

06 hh ll05 xb05 xb ff05 xb ee ff05 xb05 xb ee ff

PPPPPPPPPfPPPfIfPPPfIfPPP

PPPPPPPPPfPPP

fIfPPPfIfPPP

– – – – – – – –




MachineCoding (hex)


HCS12 HC12

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CPU12RG/D


JSR opr8aJSR opr16aJSR oprx0_xyspJSR oprx9,xyspJSR oprx16,xyspJSR [D,xysp]JSR [oprx16,xysp]

(SP) – 2 ⇒ SP;RTNH:RTNL ⇒ M(SP):M(SP+1);Subroutine address ⇒ PC

Jump to Subroutine

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

17 dd16 hh ll15 xb15 xb ff15 xb ee ff15 xb15 xb ee ff

SPPPSPPPPPPSPPPSfPPPSfIfPPPSfIfPPPS

PPPSPPPSPPPSPPPSfPPPS

fIfPPPSfIfPPPS

– – – – – – – –

LBCC rel16 Long Branch if Carry Clear (if C = 0) REL 18 24 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBCS rel16 Long Branch if Carry Set (if C = 1) REL 18 25 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBEQ rel16 Long Branch if Equal (if Z = 1) REL 18 27 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBGE rel16 Long Branch Greater Than or Equal(if N ⊕ V = 0) (signed)

REL 18 2C qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBGT rel16 Long Branch if Greater Than(if Z + (N ⊕ V) = 0) (signed)

REL 18 2E qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBHI rel16 Long Branch if Higher(if C + Z = 0) (unsigned)

REL 18 22 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBHS rel16 Long Branch if Higher or Same(if C = 0) (unsigned)same function as LBCC


LBLE rel16 Long Branch if Less Than or Equal(if Z + (N ⊕ V) = 1) (signed)

REL 18 2F qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBLO rel16 Long Branch if Lower(if C = 1) (unsigned)same function as LBCS


LBLS rel16 Long Branch if Lower or Same(if C + Z = 1) (unsigned)


LBLT rel16 Long Branch if Less Than(if N ⊕ V = 1) (signed)

REL 18 2D qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBMI rel16 Long Branch if Minus (if N = 1) REL 18 2B qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBNE rel16 Long Branch if Not Equal (if Z = 0) REL 18 26 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBPL rel16 Long Branch if Plus (if N = 0) REL 18 2A qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBRA rel16 Long Branch Always (if 1=1) REL 18 20 qq rr OPPP OPPP – – – – – – – –

LBRN rel16 Long Branch Never (if 1 = 0) REL 18 21 qq rr OPO OPO – – – – – – – –

LBVC rel16 Long Branch if Overflow Bit Clear (if V=0) REL 18 28 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LBVS rel16 Long Branch if Overflow Bit Set (if V = 1) REL 18 29 qq rr OPPP/OPO1 OPPP/OPO1 – – – – – – – –

LDAA #opr8iLDAA opr8aLDAA opr16aLDAA oprx0_xyspLDAA oprx9,xyspLDAA oprx16,xyspLDAA [D,xysp]LDAA [oprx16,xysp]

(M) ⇒ ALoad Accumulator A

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

LDAB #opr8iLDAB opr8aLDAB opr16aLDAB oprx0_xyspLDAB oprx9,xyspLDAB oprx16,xyspLDAB [D,xysp]LDAB [oprx16,xysp]

(M) ⇒ BLoad Accumulator B

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

LDD #opr16iLDD opr8aLDD opr16aLDD oprx0_xyspLDD oprx9,xyspLDD oprx16,xyspLDD [D,xysp]LDD [oprx16,xysp]

(M:M+1) ⇒ A:BLoad Double Accumulator D (A:B)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CC jj kkDC ddFC hh llEC xbEC xb ffEC xb ee ffEC xbEC xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ 0 –

Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.



MachineCoding (hex)


HCS12 HC12

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CPU12RG/D


LDS #opr16iLDS opr8aLDS opr16aLDS oprx0_xyspLDS oprx9,xyspLDS oprx16,xyspLDS [D,xysp]LDS [oprx16,xysp]

(M:M+1) ⇒ SPLoad Stack Pointer

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CF jj kkDF ddFF hh llEF xbEF xb ffEF xb ee ffEF xbEF xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ 0 –

LDX #opr16iLDX opr8aLDX opr16aLDX oprx0_xyspLDX oprx9,xyspLDX oprx16,xyspLDX [D,xysp]LDX [oprx16,xysp]

(M:M+1) ⇒ XLoad Index Register X

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CE jj kkDE ddFE hh llEE xbEE xb ffEE xb ee ffEE xbEE xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ 0 –

LDY #opr16iLDY opr8aLDY opr16aLDY oprx0_xyspLDY oprx9,xyspLDY oprx16,xyspLDY [D,xysp]LDY [oprx16,xysp]

(M:M+1) ⇒ YLoad Index Register Y

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CD jj kkDD ddFD hh llED xbED xb ffED xb ee ffED xbED xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ 0 –

LEAS oprx0_xyspLEAS oprx9,xyspLEAS oprx16,xysp

Effective Address ⇒ SPLoad Effective Address into SP

IDXIDX1IDX2

1B xb1B xb ff1B xb ee ff

PfPOPP

PP1

POPP

– – – – – – – –

LEAX oprx0_xyspLEAX oprx9,xyspLEAX oprx16,xysp

Effective Address ⇒ XLoad Effective Address into X

IDXIDX1IDX2

1A xb1A xb ff1A xb ee ff

PfPOPP

PP1

POPP

– – – – – – – –

LEAY oprx0_xyspLEAY oprx9,xyspLEAY oprx16,xysp

Effective Address ⇒ YLoad Effective Address into Y

IDXIDX1IDX2

19 xb19 xb ff19 xb ee ff

PfPOPP

PP1

POPP

– – – – – – – –

LSL opr16aLSL oprx0_xyspLSL oprx9,xyspLSL oprx16,xyspLSL [D,xysp]LSL [oprx16,xysp]LSLALSLB

Logical Shift Leftsame function as ASL

Logical Shift Accumulator A to LeftLogical Shift Accumulator B to Left

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH


rPwOrPwrPwOfrPPwfIfrPwfIPrPwOO


OO

– – – – ∆ ∆ ∆ ∆

LSLD

Logical Shift Left D Accumulatorsame function as ASLD

INH 59 O O – – – – ∆ ∆ ∆ ∆

LSR opr16aLSR oprx0_xyspLSR oprx9,xyspLSR oprx16,xyspLSR [D,xysp]LSR [oprx16,xysp]LSRALSRB

Logical Shift Right

Logical Shift Accumulator A to RightLogical Shift Accumulator B to Right

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – 0 ∆ ∆ ∆

LSRD

Logical Shift Right D Accumulator

INH 49 O O – – – – 0 ∆ ∆ ∆

MAXA oprx0_xyspMAXA oprx9,xyspMAXA oprx16,xyspMAXA [D,xysp]MAXA [oprx16,xysp]

MAX((A), (M)) ⇒ AMAX of 2 Unsigned 8-Bit Values

N, Z, V and C status bits reflect result ofinternal compare ((A) – (M)).

IDXIDX1IDX2

[D,IDX][IDX2]

18 18 xb18 18 xb ff18 18 xb ee ff18 18 xb18 18 xb ee ff

OrPfOrPOOfrPPOfIfrPfOfIPrPf

OrfPOrPOOfrPP

OfIfrfPOfIPrfP

– – – – ∆ ∆ ∆ ∆




MachineCoding (hex)


HCS12 HC12

C0

b7 b0

C0

b7 b0A Bb7b0

C0

b7 b0

C0

b7 b0A Bb7b0

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


MAXM oprx0_xyspMAXM oprx9,xyspMAXM oprx16,xyspMAXM [D,xysp]MAXM [oprx16,xysp]

MAX((A), (M)) ⇒ MMAX of 2 Unsigned 8-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 1C xb18 1C xb ff18 1C xb ee ff18 1C xb18 1C xb ee ff

OrPwOrPwOOfrPwPOfIfrPwOfIPrPw


– – – – ∆ ∆ ∆ ∆

MEM µ (grade) ⇒ M(Y);(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged

if (A) < P1 or (A) > P2 then µ = 0, elseµ = MIN[((A) – P1)×S1, (P2 – (A))×S2, $FF]where:A = current crisp input value;X points at 4-byte data structure that describes a trapezoidal membership function (P1, P2, S1, S2);Y points at fuzzy input (RAM location).See CPU12 Reference Manual for special cases.

Special 01 RRfOw RRfOw – – ? – ? ? ? ?

MINA oprx0_xyspMINA oprx9,xyspMINA oprx16,xyspMINA [D,xysp]MINA [oprx16,xysp]

MIN((A), (M)) ⇒ AMIN of 2 Unsigned 8-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 19 xb18 19 xb ff18 19 xb ee ff18 19 xb18 19 xb ee ff

OrPfOrPOOfrPPOfIfrPfOfIPrPf

OrfPOrPOOfrPP

OfIfrfPOfIPrfP

– – – – ∆ ∆ ∆ ∆

MINM oprx0_xyspMINM oprx9,xyspMINM oprx16,xyspMINM [D,xysp]MINM [oprx16,xysp]

MIN((A), (M)) ⇒ MMIN of 2 Unsigned 8-Bit Values


IDXIDX1IDX2

[D,IDX][IDX2]

18 1D xb18 1D xb ff18 1D xb ee ff18 1D xb18 1D xb ee ff



– – – – ∆ ∆ ∆ ∆

MOVB #opr8, opr16a1

MOVB #opr8i, oprx0_xysp1

MOVB opr16a, opr16a1

MOVB opr16a, oprx0_xysp1

MOVB oprx0_xysp, opr16a1

MOVB oprx0_xysp, oprx0_xysp1

(M1) ⇒ M2Memory to Memory Byte-Move (8-Bit)

IMM-EXTIMM-IDXEXT-EXTEXT-IDXIDX-EXTIDX-IDX

18 0B ii hh ll18 08 xb ii18 0C hh ll hh ll18 09 xb hh ll18 0D xb hh ll18 0A xb xb

OPwPOPwOOrPwPOOPrPwOrPwPOrPwO

OPwPOPwO

OrPwPOOPrPwOrPwPOrPwO

– – – – – – – –

MOVW #oprx16, opr16a1

MOVW #opr16i, oprx0_xysp1

MOVW opr16a, opr16a1

MOVW opr16a, oprx0_xysp1

MOVW oprx0_xysp, opr16a1

MOVW oprx0_xysp, oprx0_xysp1

(M:M+11) ⇒ M:M+12Memory to Memory Word-Move (16-Bit)

IMM-EXTIMM-IDXEXT-EXTEXT-IDXIDX-EXTIDX-IDX

18 03 jj kk hh ll18 00 xb jj kk18 04 hh ll hh ll18 01 xb hh ll18 05 xb hh ll18 02 xb xb

OPWPOOPPWORPWPOOPRPWORPWPORPWO

OPWPOOPPW

ORPWPOOPRPWORPWPORPWO

– – – – – – – –

MUL (A) × (B) ⇒ A:B8 by 8 Unsigned Multiply

INH 12 O ffO – – – – – – – ∆

NEG opr16aNEG oprx0_xyspNEG oprx9,xyspNEG oprx16,xyspNEG [D,xysp]NEG [oprx16,xysp]NEGA

NEGB

0 – (M) ⇒ M equivalent to (M) + 1 ⇒ MTwo’s Complement Negate

0 – (A) ⇒ A equivalent to (A) + 1 ⇒ ANegate Accumulator A0 – (B) ⇒ B equivalent to (B) + 1 ⇒ BNegate Accumulator B

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INH

INH


50

rPwOrPwrPwOfrPwPfIfrPwfIPrPwO

O


O

O

– – – – ∆ ∆ ∆ ∆

NOP No Operation INH A7 O O – – – – – – – –

ORAA #opr8iORAA opr8aORAA opr16aORAA oprx0_xyspORAA oprx9,xyspORAA oprx16,xyspORAA [D,xysp]ORAA [oprx16,xysp]

(A) + (M) ⇒ ALogical OR A with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

8A ii9A ddBA hh llAA xbAA xb ffAA xb ee ffAA xbAA xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

Note 1. The first operand in the source code statement specifies the source for the move.



MachineCoding (hex)


HCS12 HC12

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


ORAB #opr8iORAB opr8aORAB opr16aORAB oprx0_xyspORAB oprx9,xyspORAB oprx16,xyspORAB [D,xysp]ORAB [oprx16,xysp]

(B) + (M) ⇒ BLogical OR B with Memory

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

CA iiDA ddFA hh llEA xbEA xb ffEA xb ee ffEA xbEA xb ee ff


PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ 0 –

ORCC #opr8i (CCR) + M ⇒ CCRLogical OR CCR with Memory

IMM 14 ii P P ⇑ – ⇑ ⇑ ⇑ ⇑ ⇑ ⇑

PSHA (SP) – 1 ⇒ SP; (A) ⇒ M(SP)Push Accumulator A onto Stack

INH 36 Os Os – – – – – – – –

PSHB (SP) – 1 ⇒ SP; (B) ⇒ M(SP)Push Accumulator B onto Stack

INH 37 Os Os – – – – – – – –

PSHC (SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)Push CCR onto Stack

INH 39 Os Os – – – – – – – –

PSHD (SP) – 2 ⇒ SP; (A:B) ⇒ M(SP):M(SP+1)Push D Accumulator onto Stack

INH 3B OS OS – – – – – – – –

PSHX (SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1)Push Index Register X onto Stack

INH 34 OS OS – – – – – – – –

PSHY (SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1)Push Index Register Y onto Stack

INH 35 OS OS – – – – – – – –

PULA (M(SP)) ⇒ A; (SP) + 1 ⇒ SPPull Accumulator A from Stack

INH 32 ufO ufO – – – – – – – –

PULB (M(SP)) ⇒ B; (SP) + 1 ⇒ SPPull Accumulator B from Stack

INH 33 ufO ufO – – – – – – – –

PULC (M(SP)) ⇒ CCR; (SP) + 1 ⇒ SPPull CCR from Stack

INH 38 ufO ufO ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

PULD (M(SP):M(SP+1)) ⇒ A:B; (SP) + 2 ⇒ SPPull D from Stack

INH 3A UfO UfO – – – – – – – –

PULX (M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 2 ⇒ SPPull Index Register X from Stack

INH 30 UfO UfO – – – – – – – –

PULY (M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 2 ⇒ SPPull Index Register Y from Stack

INH 31 UfO UfO – – – – – – – –

REV MIN-MAX rule evaluationFind smallest rule input (MIN).Store to rule outputs unless fuzzy output is already larger (MAX).

For rule weights see REVW.

Each rule input is an 8-bit offset from the base address in Y. Each rule output is an 8-bit offset from the base address in Y. $FE separates rule inputs from rule outputs. $FF terminates the rule list.

REV may be interrupted.

Special 18 3A Orf(t,tx)O Orf(t,tx)O – – ? – ? ? ∆ ?(exit + re-entry replaces comma

above if interrupted)

ff + Orf(t, ff + Orf(t,

REVW MIN-MAX rule evaluationFind smallest rule input (MIN),Store to rule outputs unless fuzzy output is already larger (MAX).

Rule weights supported, optional.

Each rule input is the 16-bit address of a fuzzy input. Each rule output is the 16-bit address of a fuzzy output. The value $FFFE separates rule inputs from rule outputs. $FFFF terminates the rule list.

REVW may be interrupted.

Special 18 3B ORf(t,Tx)O ORf(t,Tx)O – – ? – ? ? ∆ !(loop to read weight if enabled)

(r,RfRf) (r,RfRf)

(exit + re-entry replaces comma above if interrupted)

ffff + ORf(t, fff + ORf(t,



MachineCoding (hex)


HCS12 HC12

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


ROL opr16aROL oprx0_xyspROL oprx9,xyspROL oprx16,xyspROL [D,xysp]ROL [oprx16,xysp]ROLAROLB

Rotate Memory Left through Carry

Rotate A Left through CarryRotate B Left through Carry

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ ∆ ∆

ROR opr16aROR oprx0_xyspROR oprx9,xyspROR oprx16,xyspROR [D,xysp]ROR [oprx16,xysp]RORARORB

Rotate Memory Right through Carry

Rotate A Right through CarryRotate B Right through Carry

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH




OO

– – – – ∆ ∆ ∆ ∆

RTC (M(SP)) ⇒ PPAGE; (SP) + 1 ⇒ SP;(M(SP):M(SP+1)) ⇒ PCH:PCL;(SP) + 2 ⇒ SPReturn from Call

INH 0A uUnfPPP uUnPPP – – – – – – – –

RTI (M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP (M(SP):M(SP+1)) ⇒ B:A; (SP) + 2 ⇒ SP (M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 4 ⇒ SP(M(SP):M(SP+1)) ⇒ PCH:PCL; (SP) – 2 ⇒ SP(M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 4 ⇒ SPReturn from Interrupt

INH 0B uUUUUPPP uUUUUPPP ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆(with interrupt pending)

uUUUUVfPPP uUUUUfVfPPP

RTS (M(SP):M(SP+1)) ⇒ PCH:PCL;(SP) + 2 ⇒ SPReturn from Subroutine

INH 3D UfPPP UfPPP – – – – – – – –

SBA (A) – (B) ⇒ ASubtract B from A

INH 18 16 OO OO – – – – ∆ ∆ ∆ ∆

SBCA #opr8iSBCA opr8aSBCA opr16aSBCA oprx0_xyspSBCA oprx9,xyspSBCA oprx16,xyspSBCA [D,xysp]SBCA [oprx16,xysp]

(A) – (M) – C ⇒ ASubtract with Borrow from A

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆

SBCB #opr8iSBCB opr8aSBCB opr16aSBCB oprx0_xyspSBCB oprx9,xyspSBCB oprx16,xyspSBCB [D,xysp]SBCB [oprx16,xysp]

(B) – (M) – C ⇒ BSubtract with Borrow from B

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆

SEC 1 ⇒ CTranslates to ORCC #$01

IMM 14 01 P P – – – – – – – 1

SEI 1 ⇒ I; (inhibit I interrupts)Translates to ORCC #$10

IMM 14 10 P P – – – 1 – – – –

SEV 1 ⇒ VTranslates to ORCC #$02

IMM 14 02 P P – – – – – – 1 –

SEX abc,dxys $00:(r1) ⇒ r2 if r1, bit 7 is 0 or$FF:(r1) ⇒ r2 if r1, bit 7 is 1

Sign Extend 8-bit r1 to 16-bit r2r1 may be A, B, or CCRr2 may be D, X, Y, or SP

Alternate mnemonic for TFR r1, r2

INH B7 eb P P – – – – – – – –



MachineCoding (hex)


HCS12 HC12

C b7 b0

Cb7 b0

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


STAA opr8aSTAA opr16aSTAA oprx0_xyspSTAA oprx9,xyspSTAA oprx16,xyspSTAA [D,xysp]STAA [oprx16,xysp]

(A) ⇒ MStore Accumulator A to Memory

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5A dd7A hh ll6A xb6A xb ff6A xb ee ff6A xb6A xb ee ff

PwPwOPwPwOPwPPIfwPIPw

PwwOPPwPwOPwP

PIfPwPIPPw

– – – – ∆ ∆ 0 –

STAB opr8aSTAB opr16aSTAB oprx0_xyspSTAB oprx9,xyspSTAB oprx16,xyspSTAB [D,xysp]STAB [oprx16,xysp]

(B) ⇒ MStore Accumulator B to Memory

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5B dd7B hh ll6B xb6B xb ff6B xb ee ff6B xb6B xb ee ff

PwPwOPwPwOPwPPIfwPIPw

PwwOPPwPwOPwP

PIfPwPIPPw

– – – – ∆ ∆ 0 –

STD opr8aSTD opr16aSTD oprx0_xyspSTD oprx9,xyspSTD oprx16,xyspSTD [D,xysp]STD [oprx16,xysp]

(A) ⇒ M, (B) ⇒ M+1Store Double Accumulator

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5C dd7C hh ll6C xb6C xb ff6C xb ee ff6C xb6C xb ee ff

PWPWOPWPWOPWPPIfWPIPW

PWWOPPWPWOPWP

PIfPWPIPPW

– – – – ∆ ∆ 0 –

STOP (SP) – 2 ⇒ SP;RTNH:RTNL ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);STOP All Clocks

Registers stacked to allow quicker recovery by interrupt.

If S control bit = 1, the STOP instruction is disabled and acts like a two-cycle NOP.

INH 18 3E (entering STOP) – – – – – – – –

OOSSSSsf OOSSSfSs

(exiting STOP)

fVfPPP fVfPPP

(continue)

ff fO

(if STOP disabled)

OO OO

STS opr8aSTS opr16aSTS oprx0_xyspSTS oprx9,xyspSTS oprx16,xyspSTS [D,xysp]STS [oprx16,xysp]

(SPH:SPL) ⇒ M:M+1Store Stack Pointer

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5F dd7F hh ll6F xb6F xb ff6F xb ee ff6F xb6F xb ee ff


PWWOPPWPWOPWP

PIfPWPIPPW

– – – – ∆ ∆ 0 –

STX opr8aSTX opr16aSTX oprx0_xyspSTX oprx9,xyspSTX oprx16,xyspSTX [D,xysp]STX [oprx16,xysp]

(XH:XL) ⇒ M:M+1Store Index Register X

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5E dd7E hh ll6E xb6E xb ff6E xb ee ff6E xb6E xb ee ff


PWWOPPWPWOPWP

PIfPWPIPPW

– – – – ∆ ∆ 0 –

STY opr8aSTY opr16aSTY oprx0_xyspSTY oprx9,xyspSTY oprx16,xyspSTY [D,xysp]STY [oprx16,xysp]

(YH:YL) ⇒ M:M+1Store Index Register Y

DIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

5D dd7D hh ll6D xb6D xb ff6D xb ee ff6D xb6D xb ee ff


PWWOPPWPWOPWP

PIfPWPIPPW

– – – – ∆ ∆ 0 –

SUBA #opr8iSUBA opr8aSUBA opr16aSUBA oprx0_xyspSUBA oprx9,xyspSUBA oprx16,xyspSUBA [D,xysp]SUBA [oprx16,xysp]

(A) – (M) ⇒ ASubtract Memory from Accumulator A

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆



MachineCoding (hex)


HCS12 HC12

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


SUBB #opr8iSUBB opr8aSUBB opr16aSUBB oprx0_xyspSUBB oprx9,xyspSUBB oprx16,xyspSUBB [D,xysp]SUBB [oprx16,xysp]

(B) – (M) ⇒ BSubtract Memory from Accumulator B

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]



PrfPrOPrfPrPOfrPP

fIfrfPfIPrfP

– – – – ∆ ∆ ∆ ∆

SUBD #opr16iSUBD opr8aSUBD opr16aSUBD oprx0_xyspSUBD oprx9,xyspSUBD oprx16,xyspSUBD [D,xysp]SUBD [oprx16,xysp]

(D) – (M:M+1) ⇒ DSubtract Memory from D (A:B)

IMMDIREXTIDX

IDX1IDX2

[D,IDX][IDX2]

83 jj kk93 ddB3 hh llA3 xbA3 xb ffA3 xb ee ffA3 xbA3 xb ee ff


OPRfPROPRfPRPOfRPP

fIfRfPfIPRfP

– – – – ∆ ∆ ∆ ∆

SWI (SP) – 2 ⇒ SP;RTNH:RTNL ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)1 ⇒ I; (SWI Vector) ⇒ PCSoftware Interrupt

INH 3F VSPSSPSsP* VSPSSPSsP* – – – 1 – – – –

(for Reset)

1 1 – 1 – – – –VfPPP VfPPP

*The CPU also uses the SWI microcode sequence for hardware interrupts and unimplemented opcode traps. Reset uses the VfPPP variation of this sequence.

TAB (A) ⇒ BTransfer A to B

INH 18 0E OO OO – – – – ∆ ∆ 0 –

TAP (A) ⇒ CCRTranslates to TFR A , CCR

INH B7 02 P P ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

TBA (B) ⇒ ATransfer B to A

INH 18 0F OO OO – – – – ∆ ∆ 0 –

TBEQ abdxys,rel9 If (cntr) = 0, then Branch;else Continue to next instruction

Test Counter and Branch if Zero(cntr = A, B, D, X,Y, or SP)

REL(9-bit)


PPP – – – – – – – –

TBL oprx0_xysp (M) + [(B) × ((M+1) – (M))] ⇒ A8-Bit Table Lookup and Interpolate

Initialize B, and index before TBL.<ea> points at first 8-bit table entry (M) and B is fractional part of lookup value.

(no indirect addressing modes or extensions allowed)

IDX 18 3D xb ORfffP OrrffffP – – – – ∆ ∆ – ∆?

C Bit is undefinedin HC12

TBNE abdxys,rel9 If (cntr) not = 0, then Branch;else Continue to next instruction

Test Counter and Branch if Not Zero(cntr = A, B, D, X,Y, or SP)

REL(9-bit)


PPP – – – – – – – –

TFR abcdxys,abcdxys (r1) ⇒ r2 or $00:(r1) ⇒ r2 or (r1[7:0]) ⇒ r2

Transfer Register to Registerr1 and r2 may be A, B, CCR, D, X, Y, or SP

INH B7 eb P P – – – – – – – –

or

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

TPA (CCR) ⇒ ATranslates to TFR CCR ,A

INH B7 20 P P – – – – – – – –



MachineCoding (hex)


HCS12 HC12

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

CPU12RG/D


TRAP trapnum (SP) – 2 ⇒ SP;RTNH:RTNL ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)1 ⇒ I; (TRAP Vector) ⇒ PC

Unimplemented opcode trap

INH 18 tntn = $30–$39or $40–$FF

OVSPSSPSsP OfVSPSSPSsP – – – 1 – – – –

TST opr16aTST oprx0_xyspTST oprx9,xyspTST oprx16,xyspTST [D,xysp]TST [oprx16,xysp]TSTATSTB

(M) – 0Test Memory for Zero or Minus

(A) – 0 Test A for Zero or Minus(B) – 0 Test B for Zero or Minus

EXTIDX

IDX1IDX2

[D,IDX][IDX2]INHINH

F7 hh llE7 xbE7 xb ffE7 xb ee ffE7 xbE7 xb ee ff97D7

rPOrPfrPOfrPPfIfrPffIPrPfOO

rOPrfPrPOfrPP

fIfrfPfIPrfP

OO

– – – – ∆ ∆ 0 0

TSX (SP) ⇒ XTranslates to TFR SP,X

INH B7 75 P P – – – – – – – –

TSY (SP) ⇒ YTranslates to TFR SP,Y

INH B7 76 P P – – – – – – – –

TXS (X) ⇒ SPTranslates to TFR X,SP

INH B7 57 P P – – – – – – – –

TYS (Y) ⇒ SPTranslates to TFR Y,SP

INH B7 67 P P – – – – – – – –

WAI (SP) – 2 ⇒ SP;RTNH:RTNL ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);WAIT for interrupt

INH 3E OSSSSsf OSSSfSsf – – – – – – – –

(after interrupt) or

fVfPPP VfPPP – – – 1 – – – –

or

– 1 – 1 – – – –

WAV

Calculate Sum of Products and Sum of Weights for Weighted Average Calculation

Initialize B, X, and Y before WAV. B specifies number of ele-ments. X points at first element in Si list. Y points at first ele-ment in Fi list.

All Si and Fi elements are 8-bits.

If interrupted, six extra bytes of stack used for intermediate values

Special 18 3C Of(frr,ffff)OOff(frr,fffff)O

– – ? – ? ∆ ? ?

(add if interrupt)

SSS + UUUrr, SSSf + UUUrr

wavr

pseudo-instruction

see WAV

Resume executing an interrupted WAV instruction (recover in-termediate results from stack rather than initializing them to zero)

Special 3C UUUrr,ffff(frr,ffff)O

UUUrrfffff(frr,fffff)O

– – ? – ? ∆ ? ?

(exit + re-entry replaces commaabove if interrupted)

SSS + UUUrr, SSSf + UUUrr

XGDX (D) ⇔ (X)Translates to EXG D, X

INH B7 C5 P P – – – – – – – –

XGDY (D) ⇔ (Y)Translates to EXG D, Y

INH B7 C6 P P – – – – – – – –



MachineCoding (hex)


HCS12 HC12

Fi

i 1=

B

∑ X⇒SiFi

i 1=

B

∑ Y:D⇒ and

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

set de instrucciones hc12

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