User's M

anual

SH7239 Group, SH7237 Group

User’s Manual: Hardware32

Rev.2.00 Jun 2013

Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

www.renesas.com

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

Page ii of xxx

Page iii of xxx

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights

of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

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of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by

you or third parties arising from the use of these circuits, software, or information.

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6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

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incurred by you resulting from errors in or omissions from the information included herein.

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"Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

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written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

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application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written

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expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to

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control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

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Electronics.

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owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

Page iv of xxx

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

Page v of xxx

How to Use This Manual

1. Objective and Target Users

This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.

This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes.

When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.

The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual.

The following documents have been prepared for the SH7239 and SH7237 Groups. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document.

Document Type Contents Document Title Document No.

Data Sheet Overview of hardware and electrical characteristics

⎯ ⎯

User′s Manual: Hardware

Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation

SH7239 Group, SH7237 Group User′s Manual: Hardware

This user′s manual

User′s Manual: Software

Detailed descriptions of the CPU and instruction set

SH-2A, SH2A-FPU Software Manual

REJ09B0086

Application Note Examples of applications and sample programs

Renesas Technical Update

Preliminary report on the specifications of a product, document, etc.

The latest versions are available from our web site.

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2. Description of Numbers and Symbols

Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below.

CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions.[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.

In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name".

(1) Overall notation

(2) Register notation

Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4)

(3)

(2)

Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.[Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234

(3) Number notation

An overbar on the name indicates that a signal or pin is active-low.[Example] WDTOVF

Note: The bit names and sentences in the above figure are examples and have nothing to dowith the contents of this manual.

(4) Notation for active-low

When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.

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3. Description of Registers

Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below.

Indicates the bit number or numbers.In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the caseof a 16-bit register, the bits are arranged in order from 15 to 0.

Indicates the name of the bit or bit field.When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]).A reserved bit is indicated by "−".Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank.

(1) Bit

(2) Bit name

Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.0: The initial value is 01: The initial value is 1−: The initial value is undefined

(3) Initial value

For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible.The notation is as follows:

R/W:R/(W):

R:

W:

The bit or field is readable and writable.The bit or field is readable and writable.However, writing is only performed to flag clearing.The bit or field is readable."R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields.The bit or field is writable.

Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of thismanual.

(4) R/W

Describes the function of the bit or field and specifies the values for writing.(5) Description

Bit

15

13 to 11

10

9

0

All 0

0

0

1

R

R/W

R

R

Address IdentifierThese bits enable or disable the pin function.

ReservedThis bit is always read as 0.

ReservedThis bit is always read as 1.

−

ASID2 to ASID0

−

−

−

Bit Name Initial Value R/W Description

[Bit Chart]

[Table of Bits]

14

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit:

Initial value:

R/W:

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W

⎯ ASID2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ACMP2Q IFE⎯ ASID1 ASID0 ACMP1 ACMP0

− 0 R

(1) (2) (3) (4) (5)

ReservedThese bits are always read as 0.

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4. Description of Abbreviations

The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description

BSC Bus controller

CPG Clock pulse generator

DTC Data transfer controller

INTC Interrupt controller

SCI Serial communication interface

WDT Watchdog timer

• Abbreviations other than those listed above Abbreviation Description

ACIA Asynchronous communications interface adapter

bps Bits per second

CRC Cyclic redundancy check

DMA Direct memory access

DMAC Direct memory access controller

GSM Global System for Mobile Communications

Hi-Z High impedance

IEBus Inter Equipment Bus

I/O Input/output

IrDA Infrared Data Association

LSB Least significant bit

MSB Most significant bit

NC No connection

PLL Phase-locked loop

PWM Pulse width modulation

SFR Special function register

SIM Subscriber Identity Module

UART Universal asynchronous receiver/transmitter

VCO Voltage-controlled oscillator

All trademarks and registered trademarks are the property of their respective owners.

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Contents

Section 1 Overview..................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 List of Products..................................................................................................................... 9 1.3 Block Diagram.................................................................................................................... 10 1.4 Pin Assignment ................................................................................................................... 11 1.5 Pin Functions ...................................................................................................................... 13

Section 2 CPU........................................................................................................21 2.1 Data Format ........................................................................................................................ 21 2.2 Register Descriptions.......................................................................................................... 21

2.2.1 General Registers ................................................................................................ 21 2.2.2 Control Registers ................................................................................................ 22 2.2.3 System Registers................................................................................................. 24 2.2.4 Floating-Point Registers (SH7239 Group Only)................................................. 25 2.2.5 Floating-Point System Registers (SH7239 Group Only) .................................... 26 2.2.6 Register Bank...................................................................................................... 29 2.2.7 Initial Values of Registers................................................................................... 29

2.3 Data Formats....................................................................................................................... 30 2.3.1 Data Format in Registers .................................................................................... 30 2.3.2 Data Formats in Memory .................................................................................... 30 2.3.3 Immediate Data Format ...................................................................................... 31

2.4 Instruction Features............................................................................................................. 32 2.4.1 RISC-Type Instruction Set.................................................................................. 32 2.4.2 Addressing Modes .............................................................................................. 36 2.4.3 Instruction Format............................................................................................... 41

2.5 Instruction Set ..................................................................................................................... 45 2.5.1 Instruction Set by Classification ......................................................................... 45 2.5.2 Data Transfer Instructions................................................................................... 52 2.5.3 Arithmetic Operation Instructions ...................................................................... 56 2.5.4 Logic Operation Instructions .............................................................................. 59 2.5.5 Shift Instructions................................................................................................. 60 2.5.6 Branch Instructions ............................................................................................. 61 2.5.7 System Control Instructions................................................................................ 63 2.5.8 Floating-Point Operation Instructions (SH7239 Group Only) ............................ 65 2.5.9 FPU-Related CPU Instructions (SH7239 Group Only) ...................................... 67 2.5.10 Bit Manipulation Instructions ............................................................................. 68

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2.6 Processing States ................................................................................................................ 69

Section 3 MCU Operating Modes .........................................................................71 3.1 Selection of Operating Modes ............................................................................................ 71 3.2 Input/Output Pins................................................................................................................ 72 3.3 Operating Modes ................................................................................................................ 72

3.3.1 Mode 2 (MCU Extension Mode 2) ..................................................................... 72 3.3.2 Mode 3 (Single Chip Mode) ............................................................................... 72

3.4 Address Map....................................................................................................................... 73 3.5 Initial State in This LSI....................................................................................................... 75 3.6 Note on Changing Operating Mode.................................................................................... 75

Section 4 Clock Pulse Generator (CPG) ...............................................................77 4.1 Features............................................................................................................................... 77 4.2 Input/Output Pins................................................................................................................ 81 4.3 Clock Operating Modes ...................................................................................................... 82 4.4 Register Descriptions.......................................................................................................... 86

4.4.1 Frequency Control Register (FRQCR) ............................................................... 86 4.4.2 MTU Clock Frequency Control Register (MCLKCR) ....................................... 89 4.4.3 AD Clock Frequency Control Register (ACLKCR) ........................................... 90 4.4.4 Oscillation Stop Detection Control Register (OSCCR) ...................................... 91

4.5 Changing the Frequency ..................................................................................................... 92 4.6 Oscillator ............................................................................................................................ 93

4.6.1 Connecting Crystal Resonator ............................................................................ 93 4.6.2 External Clock Input Method.............................................................................. 94

4.7 Oscillation Stop Detection .................................................................................................. 95 4.8 Notes on Board Design ....................................................................................................... 96

4.8.1 Note on Using an External Crystal Resonator .................................................... 96

Section 5 Exception Handling ...............................................................................99 5.1 Overview ............................................................................................................................ 99

5.1.1 Types of Exception Handling and Priority ......................................................... 99 5.1.2 Exception Handling Operations........................................................................ 101 5.1.3 Exception Handling Vector Table .................................................................... 103

5.2 Resets................................................................................................................................ 105 5.2.1 Types of Reset .................................................................................................. 105 5.2.2 Power-On Reset ................................................................................................ 106 5.2.3 Manual Reset .................................................................................................... 107

5.3 Address Errors .................................................................................................................. 109 5.3.1 Address Error Sources ...................................................................................... 109

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5.3.2 Address Error Exception Handling ................................................................... 110 5.4 Register Bank Errors......................................................................................................... 111

5.4.1 Register Bank Error Sources............................................................................. 111 5.4.2 Register Bank Error Exception Handling ......................................................... 111

5.5 Interrupts........................................................................................................................... 112 5.5.1 Interrupt Sources............................................................................................... 112 5.5.2 Interrupt Priority Level ..................................................................................... 113 5.5.3 Interrupt Exception Handling ........................................................................... 114

5.6 Exceptions Triggered by Instructions ............................................................................... 115 5.6.1 Types of Exceptions Triggered by Instructions ................................................ 115 5.6.2 Trap Instructions ............................................................................................... 116 5.6.3 Slot Illegal Instructions ..................................................................................... 116 5.6.4 General Illegal Instructions............................................................................... 117 5.6.5 Integer Division Instructions............................................................................. 117 5.6.6 Floating Point Operation Instruction (SH7239 Group Only)............................ 118

5.7 When Exception Sources Are Not Accepted .................................................................... 119 5.8 Stack Status after Exception Handling Ends..................................................................... 120 5.9 Usage Notes ...................................................................................................................... 122

5.9.1 Value of Stack Pointer (SP) .............................................................................. 122 5.9.2 Value of Vector Base Register (VBR) .............................................................. 122 5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 122 5.9.4 Note on Modifying Interrupt Mask Level (IMASK) through Status Register (SR) in CPU........................................................................................ 122

Section 6 Interrupt Controller (INTC) .................................................................123 6.1 Features............................................................................................................................. 123 6.2 Input/Output Pins.............................................................................................................. 125 6.3 Register Descriptions........................................................................................................ 126

6.3.1 Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18) 127 6.3.2 Interrupt Control Register 0 (ICR0).................................................................. 129 6.3.3 Interrupt Control Register 1 (ICR1).................................................................. 130 6.3.4 IRQ Interrupt Request Register (IRQRR)......................................................... 131 6.3.5 Bank Control Register (IBCR).......................................................................... 133 6.3.6 Bank Number Register (IBNR)......................................................................... 134

6.4 Interrupt Sources............................................................................................................... 136 6.4.1 NMI Interrupt.................................................................................................... 136 6.4.2 User Break Interrupt ......................................................................................... 136 6.4.3 H-UDI Interrupt ................................................................................................ 136 6.4.4 IRQ Interrupts ................................................................................................... 137 6.4.5 Memory Error Interrupt .................................................................................... 137

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6.4.6 On-Chip Peripheral Module Interrupts ............................................................. 138 6.5 Interrupt Exception Handling Vector Table and Priority.................................................. 139 6.6 Operation .......................................................................................................................... 147

6.6.1 Interrupt Operation Sequence ........................................................................... 147 6.6.2 Stack after Interrupt Exception Handling ......................................................... 150

6.7 Interrupt Response Time................................................................................................... 151 6.8 Register Banks .................................................................................................................. 157

6.8.1 Banked Register and Input/Output of Banks .................................................... 158 6.8.2 Bank Save and Restore Operations................................................................... 158 6.8.3 Save and Restore Operations after Saving to All Banks................................... 160 6.8.4 Register Bank Exception .................................................................................. 161 6.8.5 Register Bank Error Exception Handling ......................................................... 161

6.9 Interrupt Requests ............................................................................................................. 162 6.9.1 Handling Interrupt Request Signals as DTC Activating Sources and CPU Interrupt Sources but Not as DMAC Activating Sources ........................ 164 6.9.2 Handling Interrupt Request Signals as DMAC Activating Sources but Not as CPU Interrupt Sources........................................................................... 164 6.9.3 Handling Interrupt Request Signals as DTC Activating Sources but Not as CPU Interrupt Sources or DMAC Activating Sources .......................... 164 6.9.4 Handling Interrupt Request Signals as CPU Interrupt Sources but Not as DTC Activating Sources or DMAC Activating Sources ....................... 165

6.10 Usage Note ....................................................................................................................... 165 6.10.1 Timing to Clear an Interrupt Source ................................................................. 165 6.10.2 In Case the NMI Pin is not in Use .................................................................... 165 6.10.3 Negate Timing of IRQOUT.............................................................................. 165 6.10.4 Notes on Canceling Software Standby Mode with an IRQx Interrupt Request..................................................................................... 166

Section 7 User Break Controller (UBC)..............................................................167 7.1 Features............................................................................................................................. 167 7.2 Input/Output Pin ............................................................................................................... 169 7.3 Register Descriptions........................................................................................................ 170

7.3.1 Break Address Register_0 (BAR_0)................................................................. 171 7.3.2 Break Address Mask Register_0 (BAMR_0) ................................................... 172 7.3.3 Break Bus Cycle Register_0 (BBR_0).............................................................. 173 7.3.4 Break Address Register_1 (BAR_1)................................................................. 175 7.3.5 Break Address Mask Register_1 (BAMR_1) ................................................... 176 7.3.6 Break Bus Cycle Register_1 (BBR_1).............................................................. 177 7.3.7 Break Address Register_2 (BAR_2)................................................................. 179 7.3.8 Break Address Mask Register_2 (BAMR_2) ................................................... 180

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7.3.9 Break Bus Cycle Register_2 (BBR_2).............................................................. 181 7.3.10 Break Address Register_3 (BAR_3)................................................................. 183 7.3.11 Break Address Mask Register_3 (BAMR_3) ................................................... 184 7.3.12 Break Bus Cycle Register_3 (BBR_3).............................................................. 185 7.3.13 Break Control Register (BRCR) ....................................................................... 187

7.4 Operation .......................................................................................................................... 191 7.4.1 Flow of the User Break Operation .................................................................... 191 7.4.2 Break on Instruction Fetch Cycle...................................................................... 192 7.4.3 Break on Data Access Cycle............................................................................. 193 7.4.4 Value of Saved Program Counter ..................................................................... 194 7.4.5 Usage Examples................................................................................................ 195

7.5 Interrupt Source ................................................................................................................ 197 7.6 Usage Notes ...................................................................................................................... 198

Section 8 Data Transfer Controller (DTC) ..........................................................199 8.1 Features............................................................................................................................. 199 8.2 Register Descriptions........................................................................................................ 201

8.2.1 DTC Mode Register A (MRA) ......................................................................... 202 8.2.2 DTC Mode Register B (MRB).......................................................................... 203 8.2.3 DTC Source Address Register (SAR)............................................................... 204 8.2.4 DTC Destination Address Register (DAR)....................................................... 205 8.2.5 DTC Transfer Count Register A (CRA) ........................................................... 206 8.2.6 DTC Transfer Count Register B (CRB)............................................................ 207 8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ................................... 208 8.2.8 DTC Control Register (DTCCR) ...................................................................... 209 8.2.9 DTC Vector Base Register (DTCVBR)............................................................ 210 8.2.10 Bus Function Extending Register (BSCEHR) .................................................. 211

8.3 Activation Sources............................................................................................................ 211 8.4 Location of Transfer Information and DTC Vector Table ................................................ 211 8.5 Operation .......................................................................................................................... 216

8.5.1 Transfer Information Read Skip Function ........................................................ 221 8.5.2 Transfer Information Write-Back Skip Function .............................................. 222 8.5.3 Normal Transfer Mode ..................................................................................... 222 8.5.4 Repeat Transfer Mode....................................................................................... 223 8.5.5 Block Transfer Mode ........................................................................................ 225 8.5.6 Chain Transfer .................................................................................................. 226 8.5.7 Operation Timing.............................................................................................. 228 8.5.8 Number of DTC Execution Cycles ................................................................... 231 8.5.9 DTC Bus Release Timing ................................................................................. 234 8.5.10 DTC Activation Priority Order ......................................................................... 236

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8.6 DTC Activation by Interrupt............................................................................................. 238 8.7 Examples of Use of the DTC............................................................................................ 239

8.7.1 Normal Transfer Mode ..................................................................................... 239 8.7.2 Chain Transfer when Transfer Counter = 0 ...................................................... 240

8.8 Interrupt Sources............................................................................................................... 241 8.9 Usage Notes ...................................................................................................................... 241

8.9.1 Module Standby Mode Setting ......................................................................... 241 8.9.2 On-Chip RAM .................................................................................................. 242 8.9.3 DTCE Bit Setting.............................................................................................. 242 8.9.4 Chain Transfer .................................................................................................. 242 8.9.5 Transfer Information Start Address, Source Address, and Destination Address.......................................................................................... 242 8.9.6 Access to DTC Registers through DTC............................................................ 242 8.9.7 Notes on IRQ Interrupt as DTC Activation Source .......................................... 242 8.9.8 Note on SCI or SCIF as DTC Activation Sources ............................................ 243 8.9.9 Clearing Interrupt Source Flag.......................................................................... 243 8.9.10 Conflict between NMI Interrupt and DTC Activation...................................... 243 8.9.11 Operation when a DTC Activation Request has been Cancelled...................... 243 8.9.12 Note on Writing to DTCER .............................................................................. 243

Section 9 Bus State Controller (BSC) (SH7239A and SH7237A only).............245 9.1 Features............................................................................................................................. 245 9.2 Input/Output Pins.............................................................................................................. 247 9.3 Area Overview.................................................................................................................. 247

9.3.1 Address Map..................................................................................................... 247 9.3.2 Setting Operating Modes .................................................................................. 248

9.4 Register Descriptions........................................................................................................ 249 9.4.1 Common Control Register (CMNCR) .............................................................. 250 9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 1, 3 to 6) ......................... 253 9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 1, 3 to 6) ...................... 258 9.4.4 Bus Function Extending Register (BSCEHR) .................................................. 271

9.5 Operation .......................................................................................................................... 274 9.5.1 Endian/Access Size and Data Alignment.......................................................... 274 9.5.2 Normal Space Interface .................................................................................... 277 9.5.3 Access Wait Control ......................................................................................... 281 9.5.4 CSn Assert Period Expansion ........................................................................... 283 9.5.5 MPX-I/O Interface............................................................................................ 284 9.5.6 Wait between Access Cycles ............................................................................ 289 9.5.7 Bus Arbitration ................................................................................................. 297 9.5.8 Others................................................................................................................ 299

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9.6 Usage Note........................................................................................................................ 306

9.6.1 Note on Connection of External LSI Circuits such as SRAMs and ASICs ...... 306

Section 10 Direct Memory Access Controller (DMAC) .....................................307 10.1 Features............................................................................................................................. 307 10.2 Input/Output Pins.............................................................................................................. 309 10.3 Register Descriptions........................................................................................................ 310

10.3.1 DMA Source Address Registers (SAR)............................................................ 315 10.3.2 DMA Destination Address Registers (DAR).................................................... 316 10.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 317 10.3.4 DMA Channel Control Registers (CHCR) ....................................................... 318 10.3.5 DMA Reload Source Address Registers (RSAR)............................................. 326 10.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 327 10.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 328 10.3.8 DMA Operation Register (DMAOR) ............................................................... 329 10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).............. 333

10.4 Operation .......................................................................................................................... 335 10.4.1 Transfer Flow.................................................................................................... 335 10.4.2 DMA Transfer Requests ................................................................................... 337 10.4.3 Channel Priority................................................................................................ 341 10.4.4 DMA Transfer Types........................................................................................ 344 10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 353

10.5 Interrupt Sources............................................................................................................... 357 10.5.1 Interrupt Sources and Priority Order................................................................. 357

10.6 Usage Notes ...................................................................................................................... 359 10.6.1 Setting of the Half-End Flag and the Half-End Interrupt.................................. 359 10.6.2 Timing of DACK and TEND Outputs .............................................................. 359 10.6.3 CHCR Setting ................................................................................................... 359 10.6.4 Note on Activation of Multiple Channels ......................................................... 359 10.6.5 Note on Transfer Request Input ........................................................................ 359 10.6.6 Conflict between NMI Interrupt and DMAC Activation .................................. 360 10.6.7 Number of On-Chip RAM Access Cycles from DMAC .................................. 360

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) .....................................361 11.1 Features............................................................................................................................. 361 11.2 Input/Output Pins.............................................................................................................. 368 11.3 Register Descriptions........................................................................................................ 369

11.3.1 Timer Control Register (TCR).......................................................................... 373 11.3.2 Timer Mode Register (TMDR)......................................................................... 377

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11.3.3 Timer I/O Control Register (TIOR).................................................................. 380 11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR)................................ 399 11.3.5 Timer Interrupt Enable Register (TIER)........................................................... 400 11.3.6 Timer Status Register (TSR)............................................................................. 405 11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)............................... 412 11.3.8 Timer Input Capture Control Register (TICCR)............................................... 414 11.3.9 Timer Synchronous Clear Register S (TSYCRS) ............................................. 415 11.3.10 Timer A/D Converter Start Request Control Register (TADCR) ..................... 417 11.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4).................................................................. 420 11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ........................................................... 420 11.3.13 Timer Counter (TCNT)..................................................................................... 421 11.3.14 Timer General Register (TGR) ......................................................................... 421 11.3.15 Timer Start Register (TSTR) ............................................................................ 422 11.3.16 Timer Synchronous Register (TSYR)............................................................... 424 11.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ................................. 426 11.3.18 Timer Read/Write Enable Register (TRWER) ................................................. 429 11.3.19 Timer Output Master Enable Register (TOER) ................................................ 430 11.3.20 Timer Output Control Register 1 (TOCR1)...................................................... 431 11.3.21 Timer Output Control Register 2 (TOCR2)...................................................... 434 11.3.22 Timer Output Level Buffer Register (TOLBR) ................................................ 437 11.3.23 Timer Gate Control Register (TGCR) .............................................................. 438 11.3.24 Timer Subcounter (TCNTS) ............................................................................. 440 11.3.25 Timer Dead Time Data Register (TDDR)......................................................... 441 11.3.26 Timer Cycle Data Register (TCDR) ................................................................. 441 11.3.27 Timer Cycle Buffer Register (TCBR)............................................................... 442 11.3.28 Timer Interrupt Skipping Set Register (TITCR)............................................... 442 11.3.29 Timer Interrupt Skipping Counter (TITCNT)................................................... 444 11.3.30 Timer Buffer Transfer Set Register (TBTER) .................................................. 445 11.3.31 Timer Dead Time Enable Register (TDER) ..................................................... 447 11.3.32 Timer Waveform Control Register (TWCR) .................................................... 448 11.3.33 Bus Master Interface......................................................................................... 450

11.4 Operation .......................................................................................................................... 451 11.4.1 Basic Functions................................................................................................. 451 11.4.2 Synchronous Operation..................................................................................... 457 11.4.3 Buffer Operation............................................................................................... 459 11.4.4 Cascaded Operation .......................................................................................... 463 11.4.5 PWM Modes..................................................................................................... 468 11.4.6 Phase Counting Mode....................................................................................... 473

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11.4.7 Reset-Synchronized PWM Mode...................................................................... 480 11.4.8 Complementary PWM Mode............................................................................ 483 11.4.9 A/D Converter Start Request Delaying Function.............................................. 529 11.4.10 MTU2-MTU2S Synchronous Operation........................................................... 534 11.4.11 External Pulse Width Measurement.................................................................. 538 11.4.12 Dead Time Compensation................................................................................. 539 11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 542

11.5 Interrupt Sources............................................................................................................... 543 11.5.1 Interrupt Sources and Priorities......................................................................... 543 11.5.2 DMAC and DTC Activation............................................................................. 545 11.5.3 A/D Converter Activation................................................................................. 546

11.6 Operation Timing.............................................................................................................. 548 11.6.1 Input/Output Timing ......................................................................................... 548 11.6.2 Interrupt Signal Timing..................................................................................... 555

11.7 Usage Notes ...................................................................................................................... 561 11.7.1 Module Standby Mode Setting ......................................................................... 561 11.7.2 Input Clock Restrictions ................................................................................... 561 11.7.3 Caution on Period Setting ................................................................................. 562 11.7.4 Contention between TCNT Write and Clear Operations .................................. 562 11.7.5 Contention between TCNT Write and Increment Operations........................... 563 11.7.6 Contention between TGR Write and Compare Match ...................................... 564 11.7.7 Contention between Buffer Register Write and Compare Match ..................... 565 11.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 566 11.7.9 Contention between TGR Read and Input Capture........................................... 567 11.7.10 Contention between TGR Write and Input Capture.......................................... 568 11.7.11 Contention between Buffer Register Write and Input Capture ......................... 569 11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection .. 569 11.7.13 Counter Value during Complementary PWM Mode Stop ................................ 571 11.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 571 11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 572 11.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 573 11.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 574 11.7.18 Contention between TCNT Write and Overflow/Underflow............................ 575 11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode...................................................................... 575 11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode ...................................................................................................... 576 11.7.21 Interrupts in Module Standby Mode ................................................................. 576

11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 576

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11.7.23 Note on Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode............................................................................ 577

11.8 MTU2 Output Pin Initialization........................................................................................ 579 11.8.1 Operating Modes .............................................................................................. 579 11.8.2 Reset Start Operation ........................................................................................ 579 11.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 580 11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .............................................................................. 581

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) ................................611 12.1 Input/Output Pins.............................................................................................................. 614 12.2 Register Descriptions........................................................................................................ 615

Section 13 Port Output Enable 2 (POE2) ............................................................619 13.1 Features............................................................................................................................. 619 13.2 Input/Output Pins.............................................................................................................. 621 13.3 Register Descriptions........................................................................................................ 623

13.3.1 Input Level Control/Status Register 1 (ICSR1) ................................................ 624 13.3.2 Output Level Control/Status Register 1 (OCSR1) ............................................ 626 13.3.3 Input Level Control/Status Register 2 (ICSR2) ................................................ 627 13.3.4 Output Level Control/Status Register 2 (OCSR2) ............................................ 628 13.3.5 Input Level Control/Status Register 3 (ICSR3) ................................................ 630 13.3.6 Software Port Output Enable Register (SPOER) .............................................. 632 13.3.7 Port Output Enable Control Register 1 (POECR1)........................................... 633 13.3.8 Port Output Enable Control Register 2 (POECR2)........................................... 635 13.3.9 Port Output Enable Control Register 3 (POECR3)........................................... 640

13.4 Operation .......................................................................................................................... 642 13.4.1 Input Level Detection Operation ...................................................................... 645 13.4.2 Output-Level Compare Operation .................................................................... 646 13.4.3 Release from High-Impedance State ................................................................ 647

13.5 Interrupts........................................................................................................................... 648 13.6 Usage Notes ...................................................................................................................... 649

13.6.1 Pins States when the Watchdog Timer has Issued a Power-on Reset ............... 649 13.6.2 Input Pins.......................................................................................................... 649

Section 14 Compare Match Timer (CMT) ..........................................................651 14.1 Features............................................................................................................................. 651 14.2 Register Descriptions........................................................................................................ 652

14.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 653 14.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 654

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14.2.3 Compare Match Counter (CMCNT) ................................................................. 656 14.2.4 Compare Match Constant Register (CMCOR) ................................................. 656

14.3 Operation .......................................................................................................................... 657 14.3.1 Interval Count Operation .................................................................................. 657 14.3.2 CMCNT Count Timing..................................................................................... 657

14.4 Interrupts........................................................................................................................... 658 14.4.1 Interrupt Sources and DTC/DMAC Transfer Requests .................................... 658 14.4.2 Timing of Compare Match Flag Setting ........................................................... 659 14.4.3 Timing of Compare Match Flag Clearing......................................................... 659

14.5 Usage Notes ...................................................................................................................... 660 14.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 660 14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 661 14.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT................. 662 14.5.4 Compare Match between CMCNT and CMCOR ............................................. 662

Section 15 Watchdog Timer (WDT)....................................................................663 15.1 Features............................................................................................................................. 663 15.2 Input/Output Pin ............................................................................................................... 664 15.3 Register Descriptions........................................................................................................ 665

15.3.1 Watchdog Timer Counter (WTCNT)................................................................ 665 15.3.2 Watchdog Timer Control/Status Register (WTCSR)........................................ 666 15.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 668 15.3.4 Notes on Register Access.................................................................................. 669

15.4 WDT Usage ...................................................................................................................... 671 15.4.1 Canceling Software Standby Mode................................................................... 671 15.4.2 Using Watchdog Timer Mode........................................................................... 671 15.4.3 Using Interval Timer Mode .............................................................................. 673

15.5 Interrupt Source ................................................................................................................ 674 15.6 Usage Notes ...................................................................................................................... 674

15.6.1 Timer Variation................................................................................................. 674 15.6.2 Prohibition against Setting H'FF to WTCNT.................................................... 674 15.6.3 Interval Timer Overflow Flag........................................................................... 675 15.6.4 System Reset by WDTOVF Signal................................................................... 675 15.6.5 Manual Reset in Watchdog Timer Mode.......................................................... 675 15.6.6 Connection of the WDTOVF Pin...................................................................... 675

Section 16 Serial Communication Interface (SCI) ..............................................677 16.1 Features............................................................................................................................. 677 16.2 Input/Output Pins.............................................................................................................. 679 16.3 Register Descriptions........................................................................................................ 680

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16.3.1 Receive Shift Register (SCRSR) ...................................................................... 682 16.3.2 Receive Data Register (SCRDR) ...................................................................... 682 16.3.3 Transmit Shift Register (SCTSR) ..................................................................... 682 16.3.4 Transmit Data Register (SCTDR)..................................................................... 683 16.3.5 Serial Mode Register (SCSMR)........................................................................ 683 16.3.6 Serial Control Register (SCSCR)...................................................................... 687 16.3.7 Serial Status Register (SCSSR) ........................................................................ 690 16.3.8 Serial Port Register (SCSPTR) ......................................................................... 696 16.3.9 Serial Direction Control Register (SCSDCR)................................................... 698 16.3.10 Bit Rate Register (SCBRR) .............................................................................. 699 16.3.11 Sampling Mode Register (SPMR) .................................................................... 711

16.4 Operation .......................................................................................................................... 713 16.4.1 Overview .......................................................................................................... 713 16.4.2 Operation in Asynchronous Mode .................................................................... 715 16.4.3 Clock Synchronous Mode................................................................................. 726 16.4.4 Multiprocessor Communication Function ........................................................ 735 16.4.5 Multiprocessor Serial Data Transmission ......................................................... 737 16.4.6 Multiprocessor Serial Data Reception .............................................................. 738

16.5 SCI Interrupt Sources and DTC........................................................................................ 741 16.6 Serial Port Register (SCSPTR) and SCI Pins ................................................................... 742 16.7 Usage Notes ...................................................................................................................... 744

16.7.1 SCTDR Writing and TDRE Flag...................................................................... 744 16.7.2 Multiple Receive Error Occurrence .................................................................. 744 16.7.3 Break Detection and Processing ....................................................................... 745 16.7.4 Sending a Break Signal..................................................................................... 745 16.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 745 16.7.6 Note on Using DTC .......................................................................................... 747 16.7.7 Note on Using External Clock in Clock Synchronous Mode............................ 747 16.7.8 Module Standby Mode Setting ......................................................................... 747 16.7.9 Note for RXD Pin State on Setting RE Bit ....................................................... 747 16.7.10 Clearing Interrupt Flags .................................................................................... 748

Section 17 Serial Communication Interface with FIFO (SCIF)..........................749 17.1 Features............................................................................................................................. 749 17.2 Input/Output Pins.............................................................................................................. 751 17.3 Register Descriptions........................................................................................................ 751

17.3.1 Receive Shift Register (SCRSR) ...................................................................... 752 17.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 752 17.3.3 Transmit Shift Register (SCTSR) ..................................................................... 753 17.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 753

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17.3.5 Serial Mode Register (SCSMR)........................................................................ 754 17.3.6 Serial Control Register (SCSCR)...................................................................... 757 17.3.7 Serial Status Register (SCFSR) ........................................................................ 761 17.3.8 Bit Rate Register (SCBRR) .............................................................................. 769 17.3.9 FIFO Control Register (SCFCR) ...................................................................... 781 17.3.10 FIFO Data Count Register (SCFDR) ................................................................ 783 17.3.11 Serial Port Register (SCSPTR) ......................................................................... 784 17.3.12 Line Status Register (SCLSR) .......................................................................... 785 17.3.13 Serial Extended Mode Register (SCSEMR) ..................................................... 787

17.4 Operation .......................................................................................................................... 788 17.4.1 Overview........................................................................................................... 788 17.4.2 Operation in Asynchronous Mode .................................................................... 790 17.4.3 Operation in Clocked Synchronous Mode ........................................................ 800

17.5 SCIF Interrupts ................................................................................................................. 809 17.6 Usage Notes ...................................................................................................................... 810

17.6.1 SCFTDR Writing and TDFE Flag .................................................................... 810 17.6.2 SCFRDR Reading and RDF Flag ..................................................................... 810 17.6.3 Restriction on DMAC and DTC Usage ............................................................ 811 17.6.4 Break Detection and Processing ....................................................................... 811 17.6.5 Sending a Break Signal..................................................................................... 811 17.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 812 17.6.7 FER Flag and PER Flag of Serial Status Register (SCFSR)............................. 813

Section 18 Renesas Serial Peripheral Interface (RSPI) .......................................815 18.1 Features............................................................................................................................. 815 18.2 Input/Output Pins.............................................................................................................. 819 18.3 Register Descriptions........................................................................................................ 820

18.3.1 RSPI Control Register (SPCR) ......................................................................... 821 18.3.2 RSPI Slave Select Polarity Register (SSLP)..................................................... 824 18.3.3 RSPI Pin Control Register (SPPCR)................................................................. 825 18.3.4 RSPI Status Register (SPSR) ............................................................................ 826 18.3.5 RSPI Data Register (SPDR).............................................................................. 831 18.3.6 RSPI Sequence Control Register (SPSCR)....................................................... 832 18.3.7 RSPI Sequence Status Register (SPSSR).......................................................... 833 18.3.8 RSPI Bit Rate Register (SPBR) ........................................................................ 835 18.3.9 RSPI Data Control Register (SPDCR).............................................................. 836 18.3.10 RSPI Clock Delay Register (SPCKD) .............................................................. 841 18.3.11 SPI Slave Select Negation Delay Register (SSLND)........................................ 842 18.3.12 RSPI Next-Access Delay Register (SPND) ...................................................... 843 18.3.13 RSPI Command Register (SPCMD) ................................................................. 844

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18.4 Operation .......................................................................................................................... 849 18.4.1 Overview of RSPI Operations .......................................................................... 849 18.4.2 Controlling RSPI Pins....................................................................................... 851 18.4.3 RSPI System Configuration Example............................................................... 853 18.4.4 Transfer Format ................................................................................................ 862 18.4.5 Data Format ...................................................................................................... 865 18.4.6 Transmit Buffer Empty/Receive Buffer Full Flags........................................... 871 18.4.7 Error Detection ................................................................................................. 873 18.4.8 Initializing RSPI ............................................................................................... 878 18.4.9 SPI Operation.................................................................................................... 879 18.4.10 Clock Synchronous Operation .......................................................................... 891 18.4.11 Error Processing................................................................................................ 898 18.4.12 Loopback Mode ................................................................................................ 900 18.4.13 Interrupt Request .............................................................................................. 901

18.5 Usage Notes ...................................................................................................................... 902 18.5.1 DTC Block Transfer ......................................................................................... 902 18.5.2 DMAC Burst Transfer ...................................................................................... 902 18.5.3 Reading Receive Data....................................................................................... 902 18.5.4 DTC/DMAC and Mode Fault Error.................................................................. 902 18.5.5 Usage of the RSPI Output Pins as Open Drain Outputs ................................... 902 18.5.6 Unused Pins in Slave Mode .............................................................................. 903

Section 19 A/D Converter (ADC) .......................................................................905 19.1 Features............................................................................................................................. 905 19.2 Input/Output Pins.............................................................................................................. 908 19.3 Register Descriptions........................................................................................................ 909

19.3.1 A/D Control Registers 0 to 2 (ADCR_0 to ADCR_2)...................................... 911 19.3.2 A/D Status Registers 0 to 2 (ADSR_0 to ADSR_2) ......................................... 914 19.3.3 A/D Start Trigger Select Registers 0 to 2 (ADSTRGR_0 to ADSTRGR_2).... 915 19.3.4 A/D Analog Input Channel Select Registers 0 to 2 (ADANSR_0 to ADANSR_2).......................................................................... 917 19.3.5 A/D Bypass Control Registers 0 to 2 (ADBYPSCR_0 to ADBYPSCR_2) ..... 918 19.3.6 A/D Data Registers 0 to 15 (ADDR0 to ADDR7)............................................ 920 19.3.7 A/D Trigger Select Registers 0 to 2 (ADTSR_0 to ADTSR_2) ....................... 922 19.3.8 A/D Group-0 Data-0 Registers 0 to 2 (ADDR0GR0_0 to ADDR0GR0_2) ..... 927 19.3.9 A/D Group-1 Data-2 Registers 0 to 2 (ADDR2GR1_0 to ADDR2GR1_2) ..... 928

19.4 Operation .......................................................................................................................... 929 19.4.1 Single-Cycle Scan Mode .................................................................................. 930 19.4.2 Continuous Scan Mode..................................................................................... 933 19.4.3 2-Channel Scan Mode....................................................................................... 936

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19.4.4 Input Sampling and A/D Conversion Time ...................................................... 939 19.4.5 A/D Converter Activation by MTU2 and MTU2S ........................................... 941 19.4.6 External Trigger Input Timing.......................................................................... 942 19.4.7 Example of ADDR Auto-Clear Function.......................................................... 943 19.4.8 A/D Conversion Synchronization Function ...................................................... 945

19.5 Interrupt Sources and DMAC or DTC Transfer Requests ................................................ 955 19.6 Definitions of A/D Conversion Accuracy......................................................................... 956 19.7 Usage Notes ...................................................................................................................... 958

19.7.1 Analog Input Voltage Range ............................................................................ 958 19.7.2 Relationship between AVCC, AVSS and VCC, VSS....................................... 958 19.7.3 Range of AVREF Pin Settings.......................................................................... 958 19.7.4 Notes on Board Design ..................................................................................... 958 19.7.5 Notes on Noise Countermeasures ..................................................................... 959 19.7.6 Notes on Register Setting.................................................................................. 959 19.7.7 Permissible Signal Source Impedance .............................................................. 960 19.7.8 Influences on Absolute Precision...................................................................... 960 19.7.9 Notes when Two or More A/D Modules Run Simultaneously ......................... 960

Section 20 Controller Area Network (RCAN-ET) ..............................................965 20.1 Summary........................................................................................................................... 965

20.1.1 Overview........................................................................................................... 965 20.1.2 Scope................................................................................................................. 965 20.1.3 Audience ........................................................................................................... 965 20.1.4 References......................................................................................................... 966 20.1.5 Features............................................................................................................. 966

20.2 Architecture ...................................................................................................................... 967 20.3 Programming Model - Overview ...................................................................................... 969

20.3.1 Memory Map .................................................................................................... 969 20.3.2 Mailbox Structure ............................................................................................. 970 20.3.3 RCAN-ET Control Registers ............................................................................ 977 20.3.4 RCAN-ET Mailbox Registers........................................................................... 997

20.4 Application Note............................................................................................................. 1008 20.4.1 Test Mode Settings ......................................................................................... 1008 20.4.2 Configuration of RCAN-ET ........................................................................... 1009 20.4.3 Message Transmission Sequence.................................................................... 1015 20.4.4 Message Receive Sequence ............................................................................ 1018 20.4.5 Reconfiguration of Mailbox............................................................................ 1020

20.5 Interrupt Sources............................................................................................................. 1022 20.6 DTC Interface ................................................................................................................. 1023 20.7 DMAC Interface ............................................................................................................. 1024

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20.8 CAN Bus Interface ......................................................................................................... 1025

Section 21 Pin Function Controller (PFC) ........................................................1027 21.1 Register Descriptions...................................................................................................... 1038

21.1.1 Port A I/O Registers H and L (PAIORH and PAIORL) ................................. 1040 21.1.2 Port A Control Registers H1 and L1 to L4 (PACRH1 and PACRL1 to PACRL4) ............................................................ 1041 21.1.3 Port A Pull-Up MOS Control Registers H and L (PAPCRH and PAPCRL).. 1047 21.1.4 Port B I/O Register H, L (PBIORH, PBIORL)............................................... 1049 21.1.5 Port B Control Register H1, H2, L1, and L2 (PBCRH1, PBCRH2), PBCRL1, and PBCRL2) ....................................... 1050 21.1.6 Port B Pull-Up MOS Control Registers H and L (PBPCRH, PBPCRL) ........ 1058 21.1.7 Port C I/O Register L (PCIORL) .................................................................... 1060 21.1.8 Port C Control Registers L1 to L4 (PCCRL1 to PCCRL4) ............................ 1060 21.1.9 Port C Pull-Up MOS Control Register L (PCPCRL)...................................... 1069 21.1.10 Port D I/O Register L (PDIORL).................................................................... 1070 21.1.11 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4)............................ 1071 21.1.12 Port D Pull-Up MOS Control Register L (PDPCRL)).................................... 1079 21.1.13 Port E I/O Register L (PEIORL)..................................................................... 1080 21.1.14 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) ............................. 1081 21.1.15 Port E Pull-Up MOS Control Register L (PEPCRL) ...................................... 1089 21.1.16 Large Current Port Control Register (HCPCR) .............................................. 1090 21.1.17 DACK Output Timing Control Register (PDACKCR) .................................. 1091

21.2 Pull-Up MOS Control by Pin Function .......................................................................... 1096 21.3 Usage Notes .................................................................................................................... 1100

Section 22 I/O Ports...........................................................................................1101 22.1 Port A.............................................................................................................................. 1102

22.1.1 Register Descriptions...................................................................................... 1102 22.1.2 Port A Data Registers H and L (PADRH and PADRL).................................. 1103 22.1.3 Port A Port Registers H and L (PAPRH and PAPRL).................................... 1105

22.2 Port B.............................................................................................................................. 1107 22.2.1 Register Descriptions...................................................................................... 1107 22.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ................................. 1108 22.2.3 Port B Port