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Fidus Systems Inc.

35 Fitzgerald Road, Suite 400

Ottawa, Ontario K2H 1E6

Tel: (613) 828-0063

Fax: (613) 828-3113

Transforming Innovative Ideas into Great Products

Sidewinder Board User Guide by

Fidus Systems, Inc.

Version: 1.0

30-Jan-2018

Sidewinder Early Board Startup Guide Version: 1.14

Fidus Systems Inc. Confidential of 70

Revision History Revision Author Release Date Description of Change

0.1 TL 12-Jan-2018 First draft created from the previous document “Sidewinder

Early Board Bringup Guide.docx”

0.2 TL 23-Jan-18 -

1.0 TL 30-Jan-18 First Release

Sidewinder Early Board Startup Guide Version: 1.0, 16 January 2017

Fidus Systems Inc. Confidential Page i of iii

Table of Contents

1. OVERVIEW .................................................................................................................................................... 4

1.1 CARD VIEWS ................................................................................................................................................. 5

2. DETAILED VIEWS .......................................................................................................................................... 6

2.1 STATUS LED DEFINITIONS .............................................................................................................................. 6 2.2 USER DEFINED LEDS .................................................................................................................................... 7 2.3 JTAG CONNECTOR PINOUT (J104).................................................................................................................. 7 2.4 µSD CARD READER [J102] ............................................................................................................................ 9 2.5 3 PIN FAN CONNECTOR [J116] ....................................................................................................................... 9

3. VIVADO ES2 ENABLEMENT ........................................................................................................................ 10

4. OPERATION INFORMATION ........................................................................................................................ 11

4.1 MODE SELECT DIP SWITCH [SW8] ............................................................................................................... 11 4.2 POWER UP ................................................................................................................................................. 12 4.3 PCIE HOST ROOT PORT POWER .................................................................................................................... 13 4.4 M.2 BOOT DEVICE POWER ........................................................................................................................... 13 4.5 SECONDARY M.2 AND QSFP DEVICE POWER ................................................................................................. 14 4.6 PUSH-BUTTONS .......................................................................................................................................... 15 4.7 I2C BUS INTERFACES ................................................................................................................................... 16 4.8 SMBUS INTERFACES ................................................................................................................................... 18

5. LOOPBACK KIT .......................................................................................................................................... 19

5.1 PCIE (X16) ENDPOINT LOOPBACK BOARD ..................................................................................................... 19 5.2 PCIE (X16) HOST LOOPBACK CARD .............................................................................................................. 21 5.3 NVME M.2 LOOPBACK CARD ....................................................................................................................... 23 5.4 NVME U.2 LOOPBACK CABLE ...................................................................................................................... 23

6. SFF AND PCIE HOST EXCLUSIVITY ............................................................................................................. 24

7. RECOMMENDED DEFAULT MPSOC SIGNAL STATES ................................................................................. 26

8. CLOCK SYSTEM ......................................................................................................................................... 28

8.1 8-CH CLOCK GENERATOR [U115] ................................................................................................................ 29 8.2 PROGRAMABLE CLK GENERATOR [U133] ..................................................................................................... 30 8.3 PROGRAMABLE CLK GENERATOR [U116] ..................................................................................................... 31 8.4 8-CH CLOCK FANOUT [U114] ...................................................................................................................... 31 8.5 FEMTO CLOCK CONDITIONER [U117] ............................................................................................................. 32

9. REMAINING MPSOC SYSTEMS CONNECTIONS ......................................................................................... 33

9.1 POWER ...................................................................................................................................................... 34 9.2 NOR FLASH 1GBIT [U75, U76] ................................................................................................................. 36 9.3 DUAL NVME U.2 [J113] ............................................................................................................................ 37

9.3.1 NVME0 ................................................................................................................................................ 37 9.3.2 NVME1 ................................................................................................................................................ 39

9.4 DUAL NVME M.2 ....................................................................................................................................... 41 9.4.1 NVME2 [J110] .................................................................................................................................... 41 9.4.2 NVME3 [J111] .................................................................................................................................... 44

9.5 QSFP28 100G ETHERNET ......................................................................................................................... 47 9.5.1 QSFP0 [J8] .......................................................................................................................................... 47 9.5.2 QSFP1 [J9] .......................................................................................................................................... 48

9.6 SODIMM CARD SLOTS ................................................................................................................................ 50 9.6.1 PS Card Slot [J106] ............................................................................................................................ 50 9.6.2 PL Card Slot [J107] ............................................................................................................................ 53


Fidus Systems Inc. Confidential Page ii of iii

9.7 PCIE X16 ENDPOINT [J1] ............................................................................................................................ 58 9.8 PCIE X8 HOST (X16 CONNECTOR) [J100] .................................................................................................... 62 9.9 1G ETHERNET PHY [U2]-ETHERNET 1G [J120] ............................................................................................ 66 9.10 USB TO DUAL UART [U123]-USB MICRO [J33] ........................................................................................... 67

10. ERRATA OF KNOWN ISSUES ................................................................................................................. 68

10.1 TBD .......................................................................................................................................................... 68

Table of Figures

Figure 1 High Level Block Diagram ............................................................................................................ 4 Figure 2 Sidewinder-100 Physical Layout: Front, Top .............................................................................. 5 Figure 3 Sidewinder-100 Physical Layout: Back, Bottom ......................................................................... 5 Figure 4 Status LED's .................................................................................................................................. 6 Figure 5 PL-GPIO LED Location .................................................................................................................. 7 Figure 6 JTAG Connector (J104) ................................................................................................................ 8 Figure 7 DC Fan Breakout Header .............................................................................................................. 9 Figure 8 Vivado Menu Selection Options .............................................................................................. 10 Figure 9 Configuration Mode Select Dip Switch on Board (Shown in JTAG Mode) .............................. 11 Figure 10 Hot Swap Power Protection circuit diagram ........................................................................... 12 Figure 11 PCIe Host Root Power supply control logic ............................................................................ 13 Figure 12 Connector J110 - Optional Bootable M.2 NVME ................................................................... 13 Figure 13 Secondary M.2 and QSFP Power supply control logic .......................................................... 14 Figure 14 Push Button Switches Location ............................................................................................. 15 Figure 15 I2C Bus Block Diagram ........................................................................................................... 16 Figure 16 GLKGEN I2C Bus Breakout Header ........................................................................................ 16 Figure 17 Sidewinder Loopback kit accessories .................................................................................... 19 Figure 18 PCIE (X16) Endpoint Loopback Board assembly Drawing ..................................................... 19 Figure 19 PCIE (X16) Endpoint Loopback Board Functional Block Diagram ........................................ 20 Figure 20 PCIE (X16) Endpoint Loopback Board and Base Plate .......................................................... 20 Figure 21 Sidewinder Baseboard Test Setup.......................................................................................... 21 Figure 22 PCIE (X16) Host Loopback Card .............................................................................................. 21 Figure 23 PCIE (X16) Host Loopback Card Functional Block Diagram .................................................. 22 Figure 24 NVME M.2 Loopback Card ...................................................................................................... 23 Figure 25 NVME U.2 Loopback Cable...................................................................................................... 23 Figure 26 MPSoC Interface Names and Reference Designator ............................................................ 24 Figure 27 MPSoC Interface Bank Connections (Config 1) ..................................................................... 24 Figure 28 MPSoC Interface Bank Connections (Config 2) ..................................................................... 25 Figure 29 System Clocks Block Diagram................................................................................................. 28 Figure 30 Spread Spectrum Jumper ........................................................................................................ 30 Figure 31 System Assembly drawing ....................................................................................................... 33

Table of Tables

Table 1 MPSOC Status LEDs ...................................................................................................................... 6 Table 2 Power Status LEDs ........................................................................................................................ 6 Table 3 Additional Board Status LEDs ....................................................................................................... 6 Table 4 User Defined LED Signal Connections ......................................................................................... 7 Table 5 Xilinx Config/Debug [J104] Signal Connections ........................................................................... 8 Table 6 µSD Card Reader [J102] Signal Connections .............................................................................. 9


Fidus Systems Inc. Confidential Page iii of iii

Table 7 Fan Header [J116] Signal Connections ....................................................................................... 9 Table 8 Mode Select Configuration Table .............................................................................................. 11 Table 9 Mode Select DIP Switch Signal Connections ............................................................................. 12 Table 10 PCIe Host Power Enable Signal MPSoC Pin Assignment ....................................................... 13 Table 11 Secondary M.2 and QSFP Power Enable Signal MPSoC Pin Assignment ............................. 14 Table 12 On Board Push-button Signal Connections ............................................................................ 15 Table 13 I2C Bus Signal Connections .................................................................................................... 17 Table 14 SMBUS Signal Connections ...................................................................................................... 18 Table 15 PCIE (X16) Endpoint Loopback Board control signals ........................................................... 21 Table 16 PCIE (X16) Host Loopback Card Test Points and Control Signals ......................................... 22 Table 17 NVME M.2 Loopback Card Test Point ...................................................................................... 23 Table 18 8-CH CLK Generator [U115] Signal Connections .................................................................... 30 Table 19 Programable CLK Generator [U133] Signal Connections ...................................................... 30 Table 20 Programable CLK Generator [U116] Signal Connections ..................................................... 31 Table 21 8-CH Clock Fanout [U114] Signal Connections ....................................................................... 32 Table 22 Femto clock conditioner [U117] Signal Connections ............................................................. 32 Table 23 MPSoC Power Connection ........................................................................................................ 35 Table 24 NOR Flash 1GBIT [U75, U76] Signal Connections ................................................................. 36 Table 25 Dual NVME U.2 Clock Generator Control Signals ................................................................... 37 Table 26 NVME0 Signal Connections ..................................................................................................... 38 Table 27 NVME0 Signal Connections ...................................................................................................... 40 Table 28 NVMe M.2 [J110] Signal Connections ..................................................................................... 43 Table 29 NVMe M.2 [J111] Signal Connections .................................................................................... 46 Table 30 QSFP0 [J8] Signal Connections ............................................................................................... 48 Table 31 QSFP1 [J9] Signal Connections ............................................................................................... 49 Table 32 QSFP Power Enable Signal Connections ................................................................................ 49 Table 33 QSFP LED Signal Connections ................................................................................................. 49 Table 34 PS SoDIMM Card Slot [J106] Signal Connections ................................................................. 53 Table 35 PL SoDIMM Card Slot [J107] Signal Connections .................................................................. 57 Table 36 PCIe X16 Endpoint [J1] Signal Connections ........................................................................... 61 Table 37 PCIe X8 Host (X16 Connector) [J100] Signal Connections..................................................... 65 Table 38 Ethernet Signal Connections .................................................................................................... 66 Table 39 USB [J33] to Dual UART Signal Connections ........................................................................... 67


Fidus Systems Inc. Confidential Page 4 of vii

1. OVERVIEW

This guide provides instructions and information for the setup and operation of rev 3 Sidewinder

cards.

Jump to any section of the block diagram by using Ctrl + Click.

NVMe M.2[J111]

DDR4 SoDIMM16GB 64 bit ECC

2400 MT/s

SoDIMM Card Slot [J106]

1G Ethernet

PHY[U2]

PCIe X16 Endpoint[J1]

PCIe X8 Host (X16 Connector)[J100]

Xilinx Config/Debug[J104]

USB Micro[J33]

USB To Dual UART

[U123]

Ethernet 1G[J120]

NOR Flash 1GBIT(Lower)[U76]

NOR Flash 1GBIT(Upper)[U75]

NVMe M.2[J110]

QSFP28100G Ethernet

[J8]

QSFP28100G Ethernet

[J9]

GTY x4

GTY x4

UART x2

GTH x8GTH x16

ENET

DualNVME U.2

[J113]

GTH x8

DDR4 SoDIMM16GB 64 bit ECC

2400 MT/s

SoDIMM Card Slot [J107]

JTAG

GTY x4

GTY x4

QSPIQSPI

µSD Card Reader[J102]

XilinxMPSoC

Zynq Ultrascale+FFVC1760 pkg

[U1]PS

PL

Figure 1 High Level Block Diagram



1.1 Card Views

PCIe X8 Host

M.2 Card Slot (x2)PCIe Gen 4

PL-DDR4 Upper Bank

PS-DDR4 Lower Bank

U.2 Host (x2)

ATX Power

JTAG

QSFP28 (x2)

PCIe X16 Card Edge

Zu19 MPSOC

Ethernet

Dual USB to UART

Port

Front/Top (primary) side of Card

Figure 2 Sidewinder-100 Physical Layout: Front, Top

USER Push Buttons (x3)

USER Push Buttons (x3)

Mode select DIP Switch

µSD CardStatus LED (x13)

USER LED

(x10)

Back/Bottom (secondary) side of Card

Figure 3 Sidewinder-100 Physical Layout: Back, Bottom



2. DETAILED VIEWS

2.1 Status LED Definitions

Figure 4 Status LED's

Device Color Board Label Pin Name Pin Device

D1 GREEN/RED INIT B503_PS_INIT_N V27

U1 D37 GREEN DONE B503_PS_DONE Y28

D38 RED ERROR B503_PS_ERROR_OUT U27

D39 GREEN ERR STATS B503_PS_ERROR_STATUS V28

Table 1 MPSOC Status LEDs

Device Color Board Label Description

D44 GREEN 0V85 0V85 rail power good signal






D47 GREEN 12V ATX 12V available from J2 ATX connector

D48 GREEN 12V PCIe 12V available from J1 PCIE Host

D49 GREEN 3V3 PCIe 3V3 available from J1 PCIE Host

Table 2 Power Status LEDs

Device Color Board Label Pin Name Pin Device

D36 RED RESET RESET_N 12 U89

D42 GREEN N/A DAS/DSS_N/LED1_N 10 J110

D43 GREEN N/A DAS/DSS_N/LED1_N 10 J111

Table 3 Additional Board Status LEDs



2.2 User defined LEDS

An uncommitted group of ten (10) for use by the PL section. The table Below lists the LED pin

connections. All LEDs are active HIGH.

- High on output = LED is ON

- Low or Tri-state = LED is OFF

USER LEDs (x10)

Figure 5 PL-GPIO LED Location

Device Color Board

Label

MPSOC Description

Pin Name Pin

D53 GREEN LED0 B94_IO/L11_N/AD9_N B5 User defined LED

D54 GREEN LED1 B94_IO/L12_P/AD8_P A5 User defined LED

D55 GREEN LED2 B94_IO/L12_N/AD8_N A4 User defined LED

D61 GREEN LED3 B94_IO/L7_N/HDGC C5 User defined LED

D62 GREEN LED4 B94_IO/L7_P/HDGC C6 User defined LED

D63 GREEN LED5 B94_IO/L6_N/HDGC C1 User defined LED

D64 GREEN LED6 B94_IO/L6_P/HDGC D2 User defined LED

D65 GREEN LED7 B94_IO/L5_N/HDGC D3 User defined LED

D66 GREEN LED8 B94_IO/L5_P/HDGC D4 User defined LED

D67 GREEN LED9 B94_IO/L4_N/AD12_N D1 User defined LED

Table 4 User Defined LED Signal Connections

2.3 JTAG Connector Pinout (J104)



MPSoC JTAG [J104]

1

GND

VREF

TMS

TCK

TDO

HALT_N

NC

TDI

Figure 6 JTAG Connector (J104)

Device Pin Pin Name Schematic Net Name Pin Device

3V3_STG3 2

J104

U1

AD26 B503_PS_JTAG_TMS JTAG_TMS 4

AC26 B503_PS_JTAG_TCK CLK_JTAG_TCK_C 6

AD27 B503_PS_JTAG_TDO JTAG_TDO 8

AD25 B503_PS_JTAG_TDI JTAG_TDI 10

NO CONNECT 12

U89 11 OUT1 JTAG_SRST_N 14

GND

1

3

5

7

9

11

13

Table 5 Xilinx Config/Debug [J104] Signal Connections



2.4 µSD Card Reader [J102]

Schematic Net Name MPSOC

Device Pin Name Pin

SDIO_PROT B501_PS_MIO44 R29

U1

SDIO_DET B501_PS_MIO45 T29

SDIO_D0 B501_PS_MIO46 U28

SDIO_D1 B501_PS_MIO47 T28

SDIO_D2 B501_PS_MIO48 V30

SDIO_D3_CD B501_PS_MIO49 U29

SDIO_CMD B501_PS_MIO50 V29

CLK_SDIO B501_PS_MIO51 W30

Table 6 µSD Card Reader [J102] Signal Connections

2.5 3 Pin Fan connector [J116]

FAN Header [J116]

GND

12V_PCIE

ALERT

1

Figure 7 DC Fan Breakout Header

Schematic Net Name MPSOC

description Pin Name Pin

FAN_ALERT_OD B502_PS_MIO53 Y30 Input available for a fan/blower with built in “Alert”

feature. Function may vary between devices.

Table 7 Fan Header [J116] Signal Connections



3. VIVADO ES2 ENABLEMENT

NOTE: This section applies to early Sidewinder Boards that were shipped with Xilinx MPSoC devices

that were at Engineering Sample 2 (ES2) status.

In order to generate bitstreams for ES2 Xilinx MPSoC devices using Vivado, the proper licenses must

be acquired from Xilinx, and Vivado must be configured properly.

Step 1: Request Access to Early Access Lounge

Please use the following link to request access to access to Early Access Lounge:

http://www.xilinx.com/member/zynq_ultrascale_errata.html

Once access is granted, the Vivado Engineering Sample License should be populated at the following

link:

https://xilinx.entitlenow.com/AcrossUser

Step 2: Enable Vivado

In your Vivado installation scripts directory (e.g. C:\Xilinx\Vivado\2017.3\scripts), locate the init.tcl

scrip, and add the following line to the script: enable

enable_beta_device*

Step 3: (For Vivado 2017.x) Install Engineering Sample Devices in Vivado

a) At the Vivado HL selection menu, ensure the following selections are made:

Figure 8 Vivado Menu Selection Options

http://www.xilinx.com/member/zynq_ultrascale_errata.html

https://xilinx.entitlenow.com/AcrossUser


Fidus Systems Inc. Confidential Page 11 of iv

4. OPERATION INFORMATION

Given this card is designed to be compatible with PCIe, it is necessary for many of the interfaces to

default in a power OFF state in order to stay under the 25W PCIe power threshold at startup.

Therefore, it is necessary to enable power to the various interfaces as they are needed AFTER proper

PCIe enumeration and power negotiation with the system has taken place.

Thermal Consideration: It is important that this board operated in an

environment that provides at least 500LFM of airflow. The maximum Ambient

Air temperature cannot exceed 40 degrees.

4.1 Mode Select DIP Switch [SW8]

AN onboard DIP switch allows the user to easily select between the available mode configurations.

1

2

3

4

HIGH LOW

Mode Select DIP Switch [SW5]

Figure 9 Configuration Mode Select Dip Switch on Board (Shown in JTAG Mode)

MODE Switch

[4] [3] [2] [1]

JTAG LOW LOW LOW LOW

QSPI 24 LOW LOW LOW HIGH

QSPI 32 LOW LOW HIGH LOW

SD1 LOW HIGH LOW HIGH

Table 8 Mode Select Configuration Table

Switch MPSOC

Pin Name Pin

1 B503_PS_MODE0 AA27

2 B503_PS_MODE1 AC28

3 B503_PS_MODE2 AA28

4 B503_PS_MODE3 AB28



Table 9 Mode Select DIP Switch Signal Connections

4.2 Power Up

To power up, the card must be inserted into a PCIe slot, and the 12V ATX auxiliary power connector

(J2) MUST be connected. If the ATX power connector is not connected, the card will not come out of

reset.

All three supplies be active for the card to come out of reset.

6-Pin ATX Connector

[J2]

Hot Swap Controller with Current Limiting

(7.3A Limit)

12V0_ATX_IN12V0_ATX

PCIe X16 Connector

[J1]


(5.5A Limit)

12V0_PCIE_IN12V0_PCIE


(3A Limit)

3V3_PCIE_IN3V3_MAIN

Figure 10 Hot Swap Power Protection circuit diagram



4.3 PCIe Host Root Port Power

The Host Root Port (J100), is included to enable experimentation with the MPSoC as a PCIe Host.

When using this configuration, it is important to enable power to this connector by pulling the signal

PCIE_HOST_PWREN_N low.

Schematic Net Name MPSOC description

Pin Name Pin

PCIE_HOST_PWREN_ODN B501_PS_MIO35 N29 PCIe Host power enable (active-Low)

Table 10 PCIe Host Power Enable Signal MPSoC Pin Assignment


(3A Limit)

12V0_ATX 12V_PCIE_HOST

ONPCIE_HOST_PWREN_ODN

3V3_MAIN 3V3_PCIE_HOST

(3A)

Figure 11 PCIe Host Root Power supply control logic

4.4 M.2 Boot Device Power

One of the M.2 devices on the card, the device at J110, has the option of being the boot device for

the card. As such, this device will be powered up immediately when the board is inserted into a

system.

Bootable NVME Slot

NVME2 (J110)

Figure 12 Connector J110 - Optional Bootable M.2 NVME



4.5 Secondary M.2 and QSFP Device Power

The secondary M.2 device at J111, and two (2) QSFP connectors J8 and J9 defaults power state is

OFF.

To enable the power supply to that connector, the hardware signal QSFP_M2_PWREN_N must be

tied LOW.


Pin Name Pin

QSFP_M2_PWREN_N B501_PS_MIO34 P27 Sec M.2/QSFP power enable (active-Low)

Table 11 Secondary M.2 and QSFP Power Enable Signal MPSoC Pin Assignment

QSFP_M2_PWREN_N

3V3_STG2 3V3_QSFP_M2

(5A5)

Figure 13 Secondary M.2 and QSFP Power supply control logic


Fidus Systems Inc. Confidential Page 15 of i

4.6 PUSH-buttons

There are six (6) push-buttons on board. Three (3) are connected to dedicated control signals, the

remaining three (3) connected to uncommitted GPIO signals. All switches are normally high, pulled

low on button push

- No button push = HIGH

- Button pushed = LOW

Figure 14 Push Button Switches Location

Device Board Label MPSOC

Description Pin Name Pin

SW11 SW0 B94_IO/L11_P/AD9_P B6 User defined switch

SW12 SW1 B94_IO/L10_N/AD10_N A3 User defined switch

SW13 SW2 B94_IO/L10_P/AD10_P B3 User defined switch

SW8 CONFIG B503_PS_PROG_N Y27

SW9 PS SYS RESET B503_PS_SRST_N AB27

SW10 PS POWER ON RESET B503_PS_POR_N W27

Table 12 On Board Push-button Signal Connections



4.7 I2C Bus Interfaces

Sidewinder Uses multiple I2C buses to Communicate with several different devices. The block

diagram bellow outlines every I2C connection on board.

XilinxMPSoC


[U1]

8-CH Clock Fanout[U114]

8-CH Clock Generator

[U115]

Femto clock conditioner

[U117]

Prog CLK gen[U133]

Prog CLK gen[U116]

QSFP28100G Ethernet

[J8]

QSFP28100G Ethernet

[J9]

DDR4 SoDIMM

SoDIMM Card Slot [J107]SoDIMM Card Slot [J106]

I2C Header[J119]

DDR4 SoDIMM

0X6B 0X68 0X6C 0X6A 0X69

0X18, 0X30, 0X50 0X19, 0X31, 0X51

CLKGEN

DDR4

QSFP0

QSFP1

0X68 0X68

Figure 15 I2C Bus Block Diagram

The “CLKGEN” I2C bus is can be accessed via a 3-pin header (J119). This allows an external host to

communicate with or reconfigure the various clocking devices.

CLKGEN I2C Bus Header [J119]

SCL

SDA

GND

1

Figure 16 GLKGEN I2C Bus Breakout Header



Device Bus

Name Pin Pin Name Schematic Net Name Pin Name Pin Device

U1

CLKGEN

AD35 B500_PS_MIO15 CLKGEN_I2C_SDA_OD

SDATA_3V3 11 U114

SDATA_3V3 11 U115

SDATA 11 U117

SEL1/SDA 5 U133

SEL1/SDA 5 U116

AJ32 B500_PS_MIO14 CLK_CLKGEN_I2C_SCL_OD

SCLK_3V3 10 U114

SCLK_3V3 10 U115

SCLK 12 U117

SEL0/SCL 4 U133

SEL0/SCL 4 U116

DDR4

AJ30 B500_PS_MIO17 DDR4_I2C_SDA_OD 254 254 J106

254 254 J107

AJ31 B500_PS_MIO16 CLK_DDR4_I2C_SCL_OD 253 253 J106

253 253 J107

QSFP0 B11 B91_IO/L11_N/AD9_N QSFP0_I2C_SDA_OD SDA 12

J8 B12 B91_IO/L11_P/AD9_P CLK_QSFP0_I2C_SCL_OD SCL 11

QSFP1 H11 B91_IO/L2_P/AD14_P QSFP1_I2C_SDA_OD SDA 12

J9 G11 B91_IO/L2_N/AD14_N CLK_QSFP1_I2C_SCL_OD SCL 11

Table 13 I2C Bus Signal Connections



4.8 SMBUS Interfaces

Device Bus Name Pin Pin Name Schematic Net Name Pin Name Pin Device

U1

NVME0 SMBUS

C9 B93_IO/L12_N/AD0_N CLK_NVME0_SMBUS_CLK CLK_NVME0_SMBUS_CLK D2 J113B

D9 B93_IO/L12_P/AD0_P NVME0_SMBUS_DAT NVME0_SMBUS_DAT D1

NVME1 SMBUS

A8 B93_IO/L11_N/AD1_N CLK_NVME1_SMBUS_CLK CLK_NVME1_SMBUS_CLK D2 J113A

B8 B93_IO/L11_P/AD1_P NVME1_SMBUS_DAT NVME1_SMBUS_DAT D1

NVME2 SMBUS

A7 B93_IO/L10_N/AD2_N CLK_NVME2_MFG_CLK MFG_CLOCK 58 J110

B7 B93_IO/L10_P/AD2_P NVME2_MFG_DAT MFG_DATA 56

NVME3 SMBUS

D6 B93_IO/L9_N/AD3_N CLK_NVME3_MFG_CLK MFG_CLOCK 58 J111

E6 B93_IO/L9_P/AD3_P NVME3_MFG_DAT MFG_DATA 56

PCIE HOST SMBUS

L14 B90_IO/L8_P/HDGC/AD4_P CLK_PCIE_HOST_SMCLK_OD SMCLK B5 J100

K12 B90_IO/L7_N/HDGC/AD5_N PCIE_HOST_SMDAT_OD SMDAT B6

PCIE BP SMBUS

K14 B90_IO/L11_P/AD1_P CLK_PCIE_BP_SMCLK_OD SMCLK B5 J1

K10 B90_IO/L10_N/AD2_N PCIE_BP_SMDAT_OD SMDAT B6

Table 14 SMBUS Signal Connections


Fidus Systems Inc. Confidential Page 19 of 70

5. LOOPBACK KIT

Figure 17 Sidewinder Loopback kit accessories

The loopback kit contains several helpful items for use during initial development and testing.

Included are the following;

• PCIE (X16) Endpoint Loopback Board

• PCIE (X16) Host Loopback Card

• NVME M.2 Loopback Card (x2)

• NVME U.2 Loopback Cable

5.1 PCIE (X16) Endpoint Loopback Board

12V Out to SidewinderATX (J2)

PCIe X16 Loopback Endpoint

Barrel Jack

12V Input PCIE ResetWAKE/CLKREQLoopback Header

Figure 18 PCIE (X16) Endpoint Loopback Board assembly Drawing

The PCIE (X16) endpoint loopback board can be used in place of a host system during development.

When connected to an external 12V supply this device will provide Sidewinder with power, a PCIe

reference clock, and loopback connections on all PCIe data channels.



The diagram below illustrates all the major features of the PCIE (X16) endpoint loopback board.

PET[0] PER[0]

PET[15] PER[15]

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.

.

PICe x16Loopback Endpoint

CLKREQ_N

WAKE_N

PERST_N

100MHz

Ref CLKREFCLK

3V3

Integrated Buck Regulator(3A Limit)

12V

12V

3V3

PET[0] PER[0]

PET[15] PER[15]

.

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3V3_AUX

Figure 19 PCIE (X16) Endpoint Loopback Board Functional Block Diagram

The board comes attached to a heavy metal plate, used to create a stable test platform. A 6-Pin (5-

wire) ATX cable harness will be connected to the terminals on the right side of the board. This cable

attaches to J2 on Sidewinder board, and is necessary to provide more power than the PCIe ports

rated maximum.

Figure 20 PCIE (X16) Endpoint Loopback Board and Base Plate



Below is an example test setup.

Figure 21 Sidewinder Baseboard Test Setup

REF DES Connector


SW11 PERST_N A11 Indicates when the applied main power is within the specified

tolerance and stable.

Table 15 PCIE (X16) Endpoint Loopback Board control signals

5.2 PCIE (X16) Host Loopback Card

Figure 22 PCIE (X16) Host Loopback Card



PET[0] PER[0]

PET[15] PER[15]

.

.

.

.

.

.

.

.

.

.

.

.

.

.

PICe x16Host Loopback Board

CLKREQ_N

WAKE_N

PERST_N

REFCLK

3V3

12V

3V3

PET[0] PER[0]

PET[15] PER[15]

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

3V3_AUX

TP1

TP3TP2

TP5

TP4

100Ω

TDITDO

Figure 23 PCIE (X16) Host Loopback Card Functional Block Diagram

REF DES Connector


SW11 CLKREQ_N B12

Request that the PCI Express reference clock be

made available to allow the PCI Express interface

to send/receive data

TP1 12V A2, A3, B1, B2, B3 12V power rail

TP2 3V3AUX B10 3.3V auxiliary power rail

TP3 3V3 A9, A10, B8 3.3V power rail

TP4 PERST_N A11 Indicates when the applied main power is within

the specified tolerance and stable

TP5 WAKE_N B11 Reactivate the PCI Express Link hierarchy’s main

power rails and reference clocks

Table 16 PCIE (X16) Host Loopback Card Test Points and Control Signals



5.3 NVME M.2 Loopback Card

Figure 24 NVME M.2 Loopback Card

REF DES Connector


TP2 3V3 2, 4, 70, 72, 74, 12, 14, 16, 18 3.3V power rail

Table 17 NVME M.2 Loopback Card Test Point

5.4 NVME U.2 Loopback Cable

Figure 25 NVME U.2 Loopback Cable



6. SFF AND PCIE HOST EXCLUSIVITY

PCIe X8 Host (J100)

PL SO-DIMM (J107)

PS SO-DIMM (J106)

ATX Power (J2)

JTAG (J104)

PCIe X16 Card Edge (J1)

Zu19 MPSOC

USB to UART (J102)

QSFP1 (J9)

Ethernet (J120)

QSFP0 (J8)

NVME1 (J113-A)

NVME2 (J110)

NVME3 (J111)

NVME0 (J113-B)

Figure 26 MPSoC Interface Names and Reference Designator

Due to the fact that the number of PCIe interfaces on the card (6) exceeds the number of available

hard PCIe blocks in the MPSoC (5), the PCIe Host interface and one of the SFF (at J113) are mutually

exclusive.

i.e. a single bit stream can NOT support J100 and J113-NVME1 due to the limited number of PCIe

Hard IP Blocks.

Please refer to the figures below. Jump to any interface in the diagram by using Ctrl+Click.

Figure 27 MPSoC Interface Bank Connections (Config 1)



Figure 28 MPSoC Interface Bank Connections (Config 2)



7. RECOMMENDED DEFAULT MPSOC SIGNAL STATES

Schematic Net Name

MPSoC

Description Default Setting PIN Name

PIN Direction

QSFP_M2_PWREN_N P27 B501_PS_MIO34 Output Active LOW power enable signal for the QSFP and the M.2 interface on J111. HIGH: Power to Interface is OFF LOW: Power to Interface is ON

LOW

PCIE_HOST_PWREN_N N29 B501_PS_MIO35 Output Active LOW power enable signal for the HOST PCIE interface at J100. HIGH: Power to Interface is OFF LOW: Power to Interface is ON

LOW

NVME_CLK_GEN_PD_N AG35 B500_PS_MIO23 Output Active LOW power DOWN signal for NVME Clocks HIGH: Clocks are ON LOW: Clocks are OFF

HIGH

NVME*_CLK_EN_N (* is 0 to 4)

AH33 AG34 L27 L29

B500_PS_MIO24 B500_PS_MIO25 B501_PS_MIO26 B501_PS_MIO27

Output Active LOW clock Enable Signal Note: If latest ECO’s are applied to the hardware, these signals are NOT connected to the clock generator. It is safer to tie them LOW to ensure NVME clock presence. HIGH: NVME Clocks are OFF LOW: NVME Clocks are ON

LOW

PCIE_CLK_GEN_PD_N M27 B501_PS_MIO29 Output Active LOW power DOWN signal for PCIE Clocks HIGH: Clocks are ON LOW: Clocks are OFF

HIGH

PCIE_HOST_CLK_EN_N L30 B501_PS_MIO30 Output Active LOW clock Enable Signal Note: If latest ECO’s are applied to the hardware, these signals are NOT connected to the clock generator. It is safer to tie them LOW to ensure PCIE clock presence. HIGH: PCIE Clocks are OFF LOW: PCIE Clocks are ON

LOW



Schematic Net Name

MPSoC

Description Default Setting PIN Name

PIN Direction

PCIE_BP_CLK1_EN_N M28 B501_PS_MIO31 Output Active LOW clock Enable Signal Note: If latest ECO’s are applied to the hardware, these signals are NOT connected to the clock generator. It is safer to tie them LOW to ensure PCIE clock presence. HIGH: PCIE Clocks are OFF LOW: PCIE Clocks are ON

LOW

QSFP1_CLK_INT_ODN M30 B501_PS_MIO32 Input Active LOW QSFP Clock Cleaner Interrupt. HIGH: Not Interrupt Present LOW: Interrupt Present

333M_CLK_EN T27 B501_PS_MIO36 Output Active LOW clock Enable Signal Note: If latest ECO’s are applied to the hardware, these signals are NOT connected to the clock generator. It is safer to tie them LOW to ensure PCIE clock presence. HIGH: PL DDR4 Clock is OFF LOW: PL DDR4 Clock is ON

LOW

33M_PSCLK_EN N30 B501_PS_MIO37 Output Active HIGH PS clock Enable Signal Note: If latest ECO’s are applied to the hardware, this signal is NOT connected to the clock generator. It is safer to tie it HIGH to ensure PS clock presence. HIGH: 33MHz PS Clock is ON LOW: 33MHz PS Clock is OFF

HIGH

PL_CLK_EN R27 B501_PS_MIO38 Output Active HIGH PL 100MHz and 200 MHz Reference Clock Enable Signal Note: If latest ECO’s are applied to the hardware, this signal is NOT connected to the clock generator. It is safer to tie it HIGH to ensure PL clock presence. HIGH: PL Reference Clocks are ON LOW: PL Reference Clocks are OFF

HIGH

NVME*_PERST_N (where * is 0, 1, 2, 3)

C8 F8 H9 J8

B93_IO/L8_N/HDGC/AD4_N B93_IO/L6_N/HDGC/AD6_N B93_IO/L3_N/AD9_N B93_IO/L2_P/AD10_P

Output Active LOW reset signal. Note: Endpoints differ in how they implement this reset signal. HIGH: Device is NOT in Reset LOW: Devices is in Reset

HIGH



8. CLOCK SYSTEM

Femto clock conditioner

[U117]

Prog CLK gen[U133]

Prog CLK gen[U116]

8-CH Clock Fanout[U114]

8-CH Clock Generator

[U115]

XilinxMPSoC


PCIe X16 Endpoint[J1]

NVMe M.2[J110]

DuelNVME U.2

[J113]

NVME SerDes

NVME SerDes

NVME SerDes

4-Lane SerDes

4-Lane SerDes

DDR

RefClks

4-Lane SerDes

4-Lane SerDes

4-Lane SerDes

4-Lane SerDes

NVMe M.2[J111]

NVME SerDes

PCIe X8 Host[J100]

PCIe X8(No Connect)

QSFP

25MHz[Y15]

49.152MHz[Y16]

33.333MHz[Y22]

25MHz[Y17]

A

B

32.768KHz[Y19]

32.768KHz

[Y21]

1G Ethernet PHY[U2]

25MHz[Y13]

100MHz

SS Select jumper

[J114]

Figure 29 System Clocks Block Diagram



8.1 8-CH Clock Generator [U115]

Part Manufacturer: IDT

Part Number: 9FGL0841BKILF

Device Pin Pin Name Schematic Net Name Pin Name Pin Device

U115

1 SS_EN_TRI NVME_SS_SEL B501_PS_MIO28 L28

U1

48 CKPWRGD_PD_N NVME_CLK_GEN_PD_BUF_N B500_PS_MIO23 AG35

14 OE0_N NVME0_CLK_EN_BUF_N B500_PS_MIO24 AH33

17 OE1_N

25 OE2_N NVME1_CLK_EN_BUF_N B500_PS_MIO25 AG34

28 OE3_N

34 OE4_N NVME2_CLK_EN_BUF_N B501_PS_MIO26 L27

37 OE5_N

43 OE6_N NVME3_CLK_EN_BUF_N B501_PS_MIO27 L29

46 OE7_N

15 DIF0_P CLK_NVME0_GTH_P B228_MGTREFCLK0_P AB12

16 DIF0_N CLK_NVME0_GTH_N B228_MGTREFCLK0_N AB11

23 DIF2_P CLK_NVME1_GTH_P B229_MGTREFCLK0_P Y12

24 DIF2_N CLK_NVME1_GTH_N B229_MGTREFCLK0_N Y11

32 DIF4_P CLK_NVME2_GTY_P B128_MGTREFCLK0_P AB34

33 DIF4_N CLK_NVME2_GTY_N B128_MGTREFCLK0_N AB35

41 DIF6_P CLK_NVME3_GTY_P B129_MGTREFCLK0_P W32

42 DIF6_N CLK_NVME3_GTY_N B129_MGTREFCLK0_N W33

18 DIF1_P CLK_NVME0_CON_P A1 2A1

J113 19 DIF1_N CLK_NVME0_CON_N A2 2A2

26 DIF3_P CLK_NVME1_CON_P A1 1A1

27 DIF3_N CLK_NVME1_CON_N A2 1A2

35 DIF5_P CLK_NVME2_CON_P REFCLK_P 55 J110

36 DIF5_N CLK_NVME2_CON_N REFCLK_N 53




44 DIF7_P CLK_NVME3_CON_P REFCLK_P 55


Table 18 8-CH CLK Generator [U115] Signal Connections

Spread Spectrum Clock Select Jumper [J114]

1:2 = -0.5% Spread

2:3 = -0.25% Spread

NC = No Spread

1

1

1

Figure 30 Spread Spectrum Jumper

During initial power up, the signal NVME_SS_SEL sets the amount of spread spectrum clocking to apply. The signal can be set with a jumper

or by the MPSoC if the jumper is disconnected.

8.2 Programable CLK Generator [U133]


Part Number: 9FGV1004B200NBGI


U133

19 OUT3_P CLK_PL_DDR4_REF_CLK_P B65_IO/L13_P/T2L/N0/GC/QBC AR27

U1 20 OUT3_N CLK_PL_DDR4_REF_CLK_N B65_IO/L13_N/T2L/N1/GC/QBC AT27

8 OEB 333M_CLK_EN B501_PS_MIO36 T27

Table 19 Programable CLK Generator [U133] Signal Connections



8.3 Programable CLK Generator [U116]


Part Number: 9FGV1004B201NBGI


U116

17 OUT2_P CLK_PL_REF_CLK0_P B94_IO/L8_P/HDGC C4

U1

16 OUT2_N CLK_PL_REF_CLK0_N B94_IO/L8_N/HDGC C3

19 OUT3_P CLK_PL_REF_CLK1_P B90_IO/L5_P/HDGC/AD7_P N13

20 OUT3_N CLK_PL_REF_CLK1_N B90_IO/L5_N/HDGC/AD7_N M13

11 OUT0_P CLK_PS_REF B503_PS_REF_CLK AC27

Table 20 Programable CLK Generator [U116] Signal Connections

8.4 8-CH Clock Fanout [U114]


Part Number: 9DBL0841BKILF


U114

14 OE0_N

PCIE_BP_CLK1_EN_BUF_N B501_PS_MIO31 M28

U1

17 OE1_N

25 OE2_N

28 OE3_N

34 OE4_N

PCIE_HOST_CLK_EN_BUF_N B501_PS_MIO30 L30 37 OE5_N

43 OE6_N

15 DIF0_P CLK_PCIE_0_P B227_MGTREFCLK0_P AD12

16 DIF0_N CLK_PCIE_0_N B227_MGTREFCLK0_N AD11

18 DIF1_P CLK_PCIE_1_P B226_MGTREFCLK0_P AF12

19 DIF1_N CLK_PCIE_1_N B226_MGTREFCLK0_N AF11

23 DIF2_P CLK_PCIE_2_P B225_MGTREFCLK0_P AH12

24 DIF2_N CLK_PCIE_2_N B225_MGTREFCLK0_N AH11

26 DIF3_P CLK_PCIE_3_P B224_MGTREFCLK0_P AK12




27 DIF3_N CLK_PCIE_3_N B224_MGTREFCLK0_N AK11

32 DIF4_P CLK_PCIE_HOST_0_P B230_MGTREFCLK0_P V12

33 DIF4_N CLK_PCIE_HOST_0_N B230_MGTREFCLK0_N V11

35 DIF5_P CLK_PCIE_HOST_1_P B231_MGTREFCLK0_P T12

36 DIF5_N CLK_PCIE_HOST_1_N B231_MGTREFCLK0_N T11

41 DIF6_P CLK_PCIE_HOST_CONN_P REFCLK_P A13 J100

42 DIF6_N CLK_PCIE_HOST_CONN_N REFCLK_N A14

A14 REFCLK_N CLK_PCIEREF_BP_N REFCLK_P A13 J1

A13 REFCLK_P CLK_PCIEREF_BP_P REFCLK_N A14

Table 21 8-CH Clock Fanout [U114] Signal Connections

8.5 Femto clock conditioner [U117]


Part Number: 8T49N240-002NLGI


U117

N28 B501_PS_MIO33 QSFP_CLK_RST_N RST_N 31

U1

M30 B501_PS_MIO32 QSFP1_CLK_INT_ODN INT_N 29

R32 B130_MGTREFCLK0_P CLK_QSFP0_P Q0_P 5

R33 B130_MGTREFCLK0_N CLK_QSFP0_N Q0_N 6

L32 B131_MGTREFCLK0_P CLK_QSFP1_P Q1_P 9

L33 B131_MGTREFCLK0_N CLK_QSFP1_N Q1_N 8

Table 22 Femto clock conditioner [U117] Signal Connections



9. REMAINING MPSOC SYSTEMS CONNECTIONS

PCIe X8 Host (J100)

PL SO-DIMM (J107)

PS SO-DIMM (J106)

ATX Power (J2)

JTAG (J104)

PCIe X16 Card Edge (J1)

Zu19 MPSOC

USB to UART (J102)

QSFP1 (J9)

Ethernet (J120)

QSFP0 (J8)

NVME1 (J113-A)

NVME2 (J110)

NVME3 (J111)

NVME0 (J113-B)

Figure 31 System Assembly drawing



9.1 Power

Below is a list of every supply input on the MPSoC, and the net name of the power rail connected to

it.

MPSoC Supply Name Schematic Net Name Rail Voltage

B500_VCCO_PSIO0 3V3_STG3 3.3V




B504_VCCO_PSDDR 1V2_STG3 1.2V

B64_VCCO 1V2_STG3 1.2V











MGTAVCC_L 0V9 0.9V

MGTAVCC_RN 0V9 0.9V

MGTAVCC_RS 0V9 0.9V

MGTAVTT_L 1V2_STG2 1.2V

MGTAVTT_RN 1V2_STG2 1.2V

MGTAVTT_RS 1V2_STG2 1.2V

MGTAVTTRCAL_L 1V2_STG2 1.2V

MGTAVTTRCAL_R 1V2_STG2 1.2V

MGTVCCAUX_L 1V8_STG2 1.8V

MGTVCCAUX_RN 1V8_STG2 1.8V

MGTVCCAUX_RS 1V8_STG2 1.8V

PS_MGTRAVCC 0V85_MGTRAVCC 0.85V

PS_MGTRAVTT 1V8_STG3 1.8V

VCC_PSADC 1V8_PSADC 1.8V

VCC_PSAUX 1V8_STG2 1.8V

VCC_PSDDR_PLL 1V8_DDR_PLL 1.8V

VCC_PSINTFP 0V85 0.85V

VCC_PSINTFP_DDR 0V85 0.85V

VCC_PSINTLP 0V85 0.85V

VCC_PSPLL 1V2_STG2_PSPLL 1.2V

VCCADC 1V8_ADC 1.8V



VCCAUX 1V8_STG2 1.8V

VCCAUX_IO 1V8_STG2 1.8V

VCCBRAM 0V85 0.85V

VCCINT 0V85 0.85V

VCCINT_IO 0V85 0.85V

VREFP 1V25_VREF 1.25V

Table 23 MPSoC Power Connection



9.2 NOR Flash 1GBIT [U75, U76]


U1

AL30 B500_PS_MIO7 QSPI_UPR_CS_N S_N C2

U75

AJ34 B500_PS_MIO12 CLK_QSPI_UPR C B2

AK33 B500_PS_MIO8 QSPI_UPR_DQ0 DQ0 D3

AK34 B500_PS_MIO9 QSPI_UPR_DQ1 DQ1 D2

AK30 B500_PS_MIO10 QSPI_UPR_DQ2 W_N/DQ2 C4

AK32 B500_PS_MIO11 QSPI_UPR_DQ3 DQ3/HOLD_N D4

AL32 B500_PS_MIO5 QSPI_LWR_CS_N S_N C2

U76

AM33 B500_PS_MIO0 CLK_QSPI_LWR C B2

AL33 B500_PS_MIO4 QSPI_LWR_DQ0 DQ0 D3

AM29 B500_PS_MIO1 QSPI_LWR_DQ1 DQ1 D2

AM31 B500_PS_MIO2 QSPI_LWR_DQ2 W_N/DQ2 C4

AM30 B500_PS_MIO3 QSPI_LWR_DQ3 DQ3/HOLD_N D4

Table 24 NOR Flash 1GBIT [U75, U76] Signal Connections



9.3 Dual NVME U.2 [J113]


Pin Name Pin

NVME_CLK_GEN_PD_N B500_PS_MIO23 AG35 Clock gen enable (active-Low)

NVME_SS_SEL B501_PS_MIO28 L28

Table 25 Dual NVME U.2 Clock Generator Control Signals

9.3.1 NVME0


U1

C9 B93_IO/L12_N/AD0_N CLK_NVME0_SMBUS_CLK D2 2D2

J113

D9 B93_IO/L12_P/AD0_P NVME0_SMBUS_DAT D1 2D1

C8 B93_IO/L8_N/HDGC/AD4_N NVME0_PERST_N B1 2B1

D8 B93_IO/L8_P/HDGC/AD4_P NVME0_CLKREQ B2 2B2

D7 B93_IO/L7_N/HDGC/AD5_N NVME0_C1 C1 2C1

E7 B93_IO/L7_P/HDGC/AD5_P NVME0_C2 C2 2C2

AD4 B228_MGTHRX0_P NVME0_RX0_P B4 2B4

AD3 B228_MGTHRX0_N NVME0_RX0_N B5 2B5

AC2 B228_MGTHRX1_P NVME0_RX1_P A4 2A4

AC1 B228_MGTHRX1_N NVME0_RX1_N A5 2A5

AB4 B228_MGTHRX2_P NVME0_RX2_P B7 2B7

AB3 B228_MGTHRX2_N NVME0_RX2_N B8 2B8

AA2 B228_MGTHRX3_P NVME0_RX3_P A7 2A7

AA1 B228_MGTHRX3_N NVME0_RX3_N A8 2A8

AC6 B228_MGTHTX0_P NVME0_TX0_P D4 2D4

AC5 B228_MGTHTX0_N NVME0_TX0_N D5 2D5

AB8 B228_MGTHTX1_P NVME0_TX1_P C4 2C4

AB7 B228_MGTHTX1_N NVME0_TX1_N C5 2C5




AA6 B228_MGTHTX2_P NVME0_TX2_P D7 2D7

AA5 B228_MGTHTX2_N NVME0_TX2_N D8 2D8

Y8 B228_MGTHTX3_P NVME0_TX3_P C7 2C7

Y7 B228_MGTHTX3_N NVME0_TX3_N C8 2C8

U115 18 DIF1_P CLK_NVME0_CON_P A1 2A1


U1

AH33 B500_PS_MIO24 NVME0_CLK_EN_N OE0_N 14

U115 OE1_N 17

AB12 B228_MGTREFCLK0_P CLK_NVME0_GTH_ P DIF0_P 15

AB11 B228_MGTREFCLK0_N CLK_NVME0_GTH_N DIF0_N 16

GND A3 1A3

J113

GND A6 1A6

GND A9 1A9

GND B3 1B3

GND B6 1B6

GND B9 1B9

GND C3 1C3

GND C6 1C6

GND C9 1C9

GND D3 1D3

GND D6 1D6

GND D9 1D9

Table 26 NVME0 Signal Connections



9.3.2 NVME1


U1

A8 B93_IO/L11_N/AD1_N CLK_NVME1_SMBUS_CLK D2 1D2

J113

B8 B93_IO/L11_P/AD1_P NVME1_SMBUS_DAT D1 1D1

F8 B93_IO/L6_N/HDGC/AD6_N NVME1_PERST_N B1 1B1

G8 B93_IO/L6_P/HDGC/AD6_P NVME1_CLKREQ B2 1B2

F7 B93_IO/L5_N/HDGC/AD7_N NVME1_C1 C1 1C1

G7 B93_IO/L5_P/HDGC/AD7_P NVME1_C2 C2 1C2

Y4 B229_MGTHRX0_P NVME1_RX0_P B4 1B4

Y3 B229_MGTHRX0_N NVME1_RX0_N B5 1B5

W2 B229_MGTHRX1_P NVME1_RX1_P A4 1A4

W1 B229_MGTHRX1_N NVME1_RX1_N A5 1A5

V4 B229_MGTHRX2_P NVME1_RX2_P B7 1B7

V3 B229_MGTHRX2_N NVME1_RX2_N B8 1B8

U2 B229_MGTHRX3_P NVME1_RX3_P A7 1A7

U1 B229_MGTHRX3_N NVME1_RX3_N A8 1A8

W6 B229_MGTHTX0_P NVME1_TX0_P D4 1D4

W5 B229_MGTHTX0_N NVME1_TX0_N D5 1D5

V8 B229_MGTHTX1_P NVME1_TX1_P C4 1C4

V7 B229_MGTHTX1_N NVME1_TX1_N C5 1C5

U6 B229_MGTHTX2_P NVME1_TX2_P D7 1D7

U5 B229_MGTHTX2_N NVME1_TX2_N D8 1D8

T8 B229_MGTHTX3_P NVME1_TX3_P C7 1C7

T7 B229_MGTHTX3_N NVME1_TX3_N C8 1C8

U115 26 DIF3_P CLK_NVME1_CON_P A1 1A1


U1 AG34 B500_PS_MIO25 NVME1_CLK_EN_N

OE2_N 25

U115 OE3_N 28

Y12 B229_MGTREFCLK0_P CLK_NVME1_GTH_P DIF2_P 23




Y11 B229_MGTREFCLK0_N CLK_NVME1_GTH_N DIF2_N 24

GND A3 2A3

J113

GND A6 2A6

GND A9 2A9

GND B3 2B3

GND B6 2B6

GND B9 2B9

GND C3 2C3

GND C6 2C6

GND C9 2C9

GND D3 2D3

GND D6 2D6

GND D9 2D9

Table 27 NVME0 Signal Connections



9.4 Dual NVMe M.2

9.4.1 NVME2 [J110]


U1

W41 B128_MGTYRX0_P NVME2_RX0_P SATA-B_N/PER0_P 43

J110

W42 B128_MGTYRX0_N NVME2_RX0_N SATA-B_P/PER0_N 41

V39 B128_MGTYRX1_P NVME2_RX1_P PER1_P 31

V40 B128_MGTYRX1_N NVME2_RX1_N PER1_N 29

U41 B128_MGTYRX2_P NVME2_RX2_P PER2_P 19

U42 B128_MGTYRX2_N NVME2_RX2_N PER2_N 17

T39 B128_MGTYRX3_P NVME2_RX3_P PER3_P 7

T40 B128_MGTYRX3_N NVME2_RX3_N PER3_N 5

Y34 B128_MGTYTX0_P NVME2_TX0_N SATA-A_P/PET0_P 49

Y35 B128_MGTYTX0_N NVME2_TX0_P SATA-A_N/PET0_N 47

W36 B128_MGTYTX1_P NVME2_TX1_P PET1_P 37

W37 B128_MGTYTX1_N NVME2_TX1_N PET1_N 35

V34 B128_MGTYTX2_P NVME2_TX2_P PET2_P 25

V35 B128_MGTYTX2_N NVME2_TX2_N PET2_N 23

U36 B128_MGTYTX3_P NVME2_TX3_P PET3_P 13

U37 B128_MGTYTX3_N NVME2_TX3_N PET3_N 11

U115 35 DIF5_P CLK_NVME2_CON_P REFCLK_P 55


U1

L27 B501_PS_MIO26 NVME2_CLK_EN_N OE4_N 34

U115 OE5_N 37

AB34 B128_MGTREFCLK0_P CLK_NVME2_GTY_AC_P DIF4_P 32

AB35 B128_MGTREFCLK0_N CLK_NVME2_GTY_AC_N DIF4_N 33

A7 B93_IO/L10_N/AD2_N CLK_NVME2_MFG_CLK MFG_CLOCK 58

J110 B7 B93_IO/L10_P/AD2_P NVME2_MFG_DAT MFG_DATA 56

H9 B93_IO/L3_N/AD9_N NVME2_PERST_N PERST_N 50

J9 B93_IO/L3_P/AD9_P NVME2_CLKREQ CLKREQ_N 52




H8 B93_IO/L2_N/AD10_N NVME2_PEWAKE_N PEWAKE_N 54

GND CONFIG_0 21

U1 E1 B94_IO/L4_P/AD12_P NVME2_CONFIG1 CONFIG_1/PEDET 69

GND CONFIG_2 75

GND CONFIG_3 1

NC DEVSLP 38

Y21 3 CLK CLK_M2_SUSCLK_1 SUSCLK 68

D42 Cathode - DAS/DSS_N/LED1_N 10

3V3_STG3

3V3 2

3V3 4

3V3 12

3V3 14

3V3 16

3V3 18

3V3 70

3V3 72

3V3 74

GND GND 3

GND GND 9

GND GND 15

GND GND 27

GND GND 33

GND GND 39

GND GND 45

GND GND 51

GND GND 57

GND GND 71

GND GND 73

NO CONNECT NC1 6




NO CONNECT NC2 8

NO CONNECT NC3 20

NO CONNECT NC4 22

NO CONNECT NC5 24

NO CONNECT NC6 26

NO CONNECT NC7 28

NO CONNECT NC8 30

NO CONNECT NC9 32

NO CONNECT NC10 34

NO CONNECT NC11 36

NO CONNECT NC12 40

NO CONNECT NC13 42

NO CONNECT NC14 44

NO CONNECT NC15 46

NO CONNECT NC16 48

NO CONNECT NC17 67

Table 28 NVMe M.2 [J110] Signal Connections



9.4.2 NVME3 [J111]


U1

R41 B129_MGTYRX0_P NVME3_RX0_P SATA-B_N/PER0_P 43

J110

R42 B129_MGTYRX0_N NVME3_RX0_N SATA-B_P/PER0_N 41

P39 B129_MGTYRX1_P NVME3_RX1_P PER1_P 31

P40 B129_MGTYRX1_N NVME3_RX1_N PER1_N 29

N41 B129_MGTYRX2_P NVME3_RX2_P PER2_P 19

N42 B129_MGTYRX2_N NVME3_RX2_N PER2_N 17

M39 B129_MGTYRX3_P NVME3_RX3_P PER3_P 7

M40 B129_MGTYRX3_N NVME3_RX3_N PER3_N 5

T34 B129_MGTYTX0_P NVME3_TX0_P SATA-A_P/PET0_P 49

T35 B129_MGTYTX0_N NVME3_TX0_N SATA-A_N/PET0_N 47

R36 B129_MGTYTX1_P NVME3_TX1_P PET1_P 37

R37 B129_MGTYTX1_N NVME3_TX1_N PET1_N 35

P34 B129_MGTYTX2_P NVME3_TX2_P PET2_P 25

P35 B129_MGTYTX2_N NVME3_TX2_N PET2_N 23

N36 B129_MGTYTX3_P NVME3_TX3_P PET3_P 13

N37 B129_MGTYTX3_N NVME3_TX3_N PET3_N 11

U115 44 DIF7_P CLK_NVME3_CON_P REFCLK_P 55


U1

L29 B501_PS_MIO27 NVME3_CLK_EN_N OE6_N 43

U115 OE7_N 46

W32 B129_MGTREFCLK0_P CLK_NVME3_GTY_AC_P DIF6_P 41

W33 B129_MGTREFCLK0_N CLK_NVME3_GTY_AV_N DIF6_N 42

D6 B93_IO/L9_N/AD3_N CLK_NVME3_MFG_CLK MFG_CLOCK 58

J110

E6 B93_IO/L9_P/AD3_P NVME3_MFG_DAT MFG_DATA 56

J8 B93_IO/L2_P/AD10_P NVME3_PERST_N PERST_N 50

F6 B93_IO/L1_N/AD11_N NVME3_CLKREQ CLKREQ_N 52

G6 B93_IO/L1_P/AD11_P NVME3_PEWAKE_N PEWAKE_N 54




GND CONFIG_0 21

U1 E5 B94_IO/L2_P/AD14_P NVME3_CONFIG1 CONFIG_1/PEDET 69

GND CONFIG_2 75

GND CONFIG_3 1

NC DEVSLP 38

Y21 3 CLK CLK_M2_SUSCLK_2 SUSCLK 68

D42 Cathode - DAS/DSS_N/LED1_N 10

3V3_QSFP_M2

3V3 2

3V3 4

3V3 12

3V3 14

3V3 16

3V3 18

3V3 70

3V3 72

3V3 74

GND GND 3

GND GND 9

GND GND 15

GND GND 27

GND GND 33

GND GND 39

GND GND 45

GND GND 51

GND GND 57

GND GND 71

GND GND 73

NO CONNECT NC1 6

NO CONNECT NC2 8




NO CONNECT NC3 20

NO CONNECT NC4 22

NO CONNECT NC5 24

NO CONNECT NC6 26

NO CONNECT NC7 28

NO CONNECT NC8 30

NO CONNECT NC9 32

NO CONNECT NC10 34

NO CONNECT NC11 36

NO CONNECT NC12 40

NO CONNECT NC13 42

NO CONNECT NC14 44

NO CONNECT NC15 46

NO CONNECT NC16 48

NO CONNECT NC17 67

Table 29 NVMe M.2 [J111] Signal Connections



9.5 QSFP28 100G Ethernet

9.5.1 QSFP0 [J8]


U1

B10 B91_IO/L10_N/AD10_N QSFP0_MODPRS_N MODPRS_N 27

J8

B12 B91_IO/L11_P/AD9_P

CLK_QSFP0_I2C_SCL_OD

SCL 11

B11 B91_IO/L11_N/AD9_N QSFP0_I2C_SDA_OD SDA 12

A10 B91_IO/L12_P/AD8_P QSFP0_MODSEL_N MODSEL_N 8

A9 B91_IO/L12_N/AD8_N QSFP0_INT_N_OD INT_N 28

C11 B91_IO/L9_N/AD11_N QSFP0_RESET_N RESET_N 9

D11 B91_IO/L9_P/AD11_P QSFP0_LPMODE LPMODE 31

D12 B91_IO/L8_N/HDGC QSFP0_LED1 Anode D57

E12 B91_IO/L8_P/HDGC QSFP0_LED2 Anode D59

3V3_QSFP_M2

VCC1 30

J8

VCC_TX 29

VCC_RX 10

U1

M34 B130_MGTYTX0_P QSFP0_TX1_P TX1_P 36

M35 B130_MGTYTX0_N QSFP0_TX1_N TX1_N 37

L36 B130_MGTYTX1_P QSFP0_TX2_P TX2_P 3

L37 B130_MGTYTX1_N QSFP0_TX2_N TX2_N 2

K34 B130_MGTYTX2_P QSFP0_TX3_P TX3_P 33

K35 B130_MGTYTX2_N QSFP0_TX3_N TX3_N 34

J36 B130_MGTYTX3_P QSFP0_TX4_P TX4_P 6

J37 B130_MGTYTX3_N QSFP0_TX4_N TX4_N 5

L41 B130_MGTYRX0_P QSFP0_RX1_P RX1_P 17

L42 B130_MGTYRX0_N QSFP0_RX1_N RX1_N 18

K39 B130_MGTYRX1_P QSFP0_RX2_P RX2_P 22

K40 B130_MGTYRX1_N QSFP0_RX2_N RX2_N 21




J41 B130_MGTYRX2_P QSFP0_RX3_P RX3_P 14

J42 B130_MGTYRX2_N QSFP0_RX3_N RX3_N 15

H39 B130_MGTYRX3_P QSFP0_RX4_P RX4_P 25

H40 B130_MGTYRX3_N QSFP0_RX4_N RX4_N 24

Table 30 QSFP0 [J8] Signal Connections

9.5.2 QSFP1 [J9]


U1

H13 B91_IO/L3_P/AD13_P QSFP1_MODPRS_N MODPRS_N 27

J9

G11 B91_IO/L2_N/AD14_N CLK_QSFP1_I2C_SCL_OD SCL 11

H11 B91_IO/L2_P/AD14_P QSFP1_I2C_SDA_OD SDA 12

H10 B91_IO/L1_N/AD15_N QSFP1_MODSEL_N MODSEL_N 8

J11 B91_IO/L1_P/AD15_P QSFP1_INT_N_OD INT_N 28

H14 B91_IO/L4_P/AD12_P QSFP1_RESET_N RESET_N 9

G13 B91_IO/L4_N/AD12_N QSFP1_LPMODE LPMODE 31

F10 B91_IO/L5_N/HDGC QSFP1_LED1 Anode D58

G10 B91_IO/L5_P/HDGC QSFP1_LED2 Anode D60

3V3_QSFP_M2

VCC1 30

J9

VCC_TX 29

VCC_RX 10

U1

H34 B131_MGTYTX0_P QSFP1_TX1_P TX1_P 36

H35 B131_MGTYTX0_N QSFP1_TX1_N TX1_N 37

G36 B131_MGTYTX1_P QSFP1_TX2_P TX2_P 3

G37 B131_MGTYTX1_N QSFP1_TX2_N TX2_N 2

F34 B131_MGTYTX2_P QSFP1_TX3_P TX3_P 33

F35 B131_MGTYTX2_N QSFP1_TX3_N TX3_N 34

E36 B131_MGTYTX3_P QSFP1_TX4_P TX4_P 6

E37 B131_MGTYTX3_N QSFP1_TX4_N TX4_N 5




G41 B131_MGTYRX0_P QSFP1_RX1_P RX1_P 17

G42 B131_MGTYRX0_N QSFP1_RX1_N RX1_N 18

F39 B131_MGTYRX1_P QSFP1_RX2_P RX2_P 22

F40 B131_MGTYRX1_N QSFP1_RX2_N RX2_N 21

E41 B131_MGTYRX2_P QSFP1_RX3_P RX3_P 14

E42 B131_MGTYRX2_N QSFP1_RX3_N RX3_N 15

D39 B131_MGTYRX3_P QSFP1_RX4_P RX4_P 25

D40 B131_MGTYRX3_N QSFP1_RX4_N RX4_N 24

Table 31 QSFP1 [J9] Signal Connections

The power to the QSFP is OFF by default. To enable power to the QSFP’s, the hardware signal QSFP_M2_PWREN_N must be tied LOW.

QSFP_M2_PWREN_N.


Pin Name Pin

QSFP_M2_PWREN_N B501_PS_MIO34 P27 QSFP power enable (active-Low)

Table 32 QSFP Power Enable Signal Connections

Each QSFP connector has two (2) status LEDs with light-pipes to carry the light to the front of the connector port.

Device Color Board

Label

MPSOC Description

Pin Name Pin

D57 GREEN N/A B91_IO/L8_N/HDGC D12 QSFP0 faceplate user defined status LED1

D58 GREEN N/A B91_IO/L8_P/HDGC E12 QSFP0 faceplate user defined status LED2

D59 GREEN N/A B91_IO/L5_N/HDGC F10 QSFP1 faceplate user defined status LED1

D60 GREEN N/A B91_IO/L5_P/HDGC G10 QSFP1 faceplate user defined status LED2

Table 33 QSFP LED Signal Connections



9.6 SoDIMM Card Slots

9.6.1 PS Card Slot [J106]


U1

BB39 B504_PS_DDR_ODT0 PS_DDR_ODT0 155

J106

AT37 B504_PS_DDR_ODT1 PS_DDR_ODT1 161

AM35 B504_PS_DDR_PARITY PS_DDR_PARITY 143

AM34 B504_PS_DDR_RAM_RST_N PS_DDR_RAM_RST_N 108

AR37 B504_PS_DDR_ACT_N PS_DDR_ACT_N 114

AM36 B504_PS_DDR_ALERT_N PS_DDR_ALERT_N 116

AN37 B504_PS_DDR_BA0 PS_DDR_BA0 150

AN36 B504_PS_DDR_BA1 PS_DDR_BA1 145

AP36 B504_PS_DDR_BG0 PS_DDR_BG0 115

AP35 B504_PS_DDR_BG1 PS_DDR_BG1 113

AY38 B504_PS_DDR_CKE0 PS_DDR_CKE0 109

AT38 B504_PS_DDR_CKE1 PS_DDR_CKE1 110

BA37 B504_PS_DDR_CK0_N PS_DDR_CK0_N 139

BA36 B504_PS_DDR_CK0_P PS_DDR_CK0_P 137

AV37 B504_PS_DDR_CK1_N PS_DDR_CK1_N 140

AV36 B504_PS_DDR_CK1_P PS_DDR_CK1_P 138

AY37 B504_PS_DDR_CS0_N PS_DDR_CS0_N 149

AU38 B504_PS_DDR_CS1_N PS_DDR_CS1_N 157

4.7k pull-up 1V2_STG3 PS_DDR_CS2_N 162

PS_DDR_CS3_N 165

U1 AJ31 B500_PS_MIO16 CLK_DDR4_I2C_SCL_OD 253

AJ30 B500_PS_MIO17 DDR4_I2C_SDA_OD 254

4.7k pull-Down GND

PS_DDR_I2C_SA0 256

PS_DDR_I2C_SA1 260

PS_DDR_I2C_SA2 166

4.7k pull-up 1V2_STG PS_DDR4_EVENT_N 134

U1

BA38 B504_PS_DDR_A0 PS_DDR_A0 144

BB36 B504_PS_DDR_A1 PS_DDR_A1 133

BA35 B504_PS_DDR_A2 PS_DDR_A2 132



AY35 B504_PS_DDR_A5 PS_DDR_A5 126

AP37 B504_PS_DDR_A6 PS_DDR_A6 127

AT36 B504_PS_DDR_A7 PS_DDR_A7 122

AR35 B504_PS_DDR_A8 PS_DDR_A8 125

AT35 B504_PS_DDR_A9 PS_DDR_A9 121

AU35 B504_PS_DDR_A10 PS_DDR_A10 146




AU36 B504_PS_DDR_A11 PS_DDR_A11 120

AW36 B504_PS_DDR_A12 PS_DDR_A12 119

AW37 B504_PS_DDR_A13 PS_DDR_A13 158

AW35 B504_PS_DDR_A14 PS_DDR_A14_WE_N 151

AW34 B504_PS_DDR_A15 PS_DDR_A15_CAS_N 156

AR34 B504_PS_DDR_A16 PS_DDR_A16_RAS_N 152

AL42 B504_PS_DDR_DM7 PS_DDR_DM0_N 12

AR39 B504_PS_DDR_DM4 PS_DDR_DM1_N 33

AU39 B504_PS_DDR_DM6 PS_DDR_DM2_N 54

AY42 B504_PS_DDR_DM8 PS_DDR_DM3_N 75




AL36 B504_PS_DDR_DM5 PS_DDR_DM7_N 241


AL41 B504_PS_DDR_DQS7_N PS_DDR_DQS0_N 11

AL40 B504_PS_DDR_DQS7_P PS_DDR_DQS0_P 13

AR40 B504_PS_DDR_DQS4_N PS_DDR_DQS1_N 32

AP40 B504_PS_DDR_DQS4_P PS_DDR_DQS1_P 34

AU41 B504_PS_DDR_DQS6_N PS_DDR_DQS2_N 53

AU40 B504_PS_DDR_DQS6_P PS_DDR_DQS2_P 55

AY40 B504_PS_DDR_DQS8_N PS_DDR_DQS3_N 74

AY39 B504_PS_DDR_DQS8_P PS_DDR_DQS3_P 76

AT32 B504_PS_DDR_DQS3_N PS_DDR_DQS4_N 177

AR32 B504_PS_DDR_DQS3_P PS_DDR_DQS4_P 179

BA30 B504_PS_DDR_DQS0_N PS_DDR_DQS5_N 198


AT30 B504_PS_DDR_DQS2_N PS_DDR_DQS6_N 219

AR30 B504_PS_DDR_DQS2_P PS_DDR_DQS6_P 221

AK37 B504_PS_DDR_DQS5_N PS_DDR_DQS7_N 240

AJ37 B504_PS_DDR_DQS5_P PS_DDR_DQS7_P 242

AY33 B504_PS_DDR_DQS1_N PS_DDR_DQS8_N 95


AK41 B504_PS_DDR_DQ63 PS_DDR_DQ0 8


AM38 B504_PS_DDR_DQ57 PS_DDR_DQ2 20


AJ42 B504_PS_DDR_DQ60 PS_DDR_DQ4 4







AN38 B504_PS_DDR_DQ39 PS_DDR_DQ8 28

AP42 B504_PS_DDR_DQ34 PS_DDR_DQ9 29

AR38 B504_PS_DDR_DQ37 PS_DDR_DQ10 41






AT42 B504_PS_DDR_DQ50 PS_DDR_DQ16 50


AV38 B504_PS_DDR_DQ55 PS_DDR_DQ18 62


AR42 B504_PS_DDR_DQ48 PS_DDR_DQ20 46




AW42 B504_PS_DDR_DQ68 PS_DDR_DQ24 70


BA40 B504_PS_DDR_DQ67 PS_DDR_DQ26 83

BB40 B504_PS_DDR_DQ64 PS_DDR_DQ27 84





AU33 B504_PS_DDR_DQ25 PS_DDR_DQ32 174




























AL37 B504_PS_DDR_DQ40 PS_DDR_DQ57 236















Table 34 PS SoDIMM Card Slot [J106] Signal Connections

9.6.2 PL Card Slot [J107]


U1

AK23 B65_IO/L23_P/T3U/N8/I2C/SCLK PL_DDR_ODT0 155

J107

AJ24 B65_IO/L24_P/T3U/N10 PL_DDR_ODT1 161

AM26 B65_IO/L15_P/T2L/N4/AD11_P PL_DDR_PARITY 143

AT25 B65_IO/L12_P/T1U/N10/GC PL_DDR_RAM_RST_N 108

AU26 B65_IO/L11_N/T1U/N9/GC PL_DDR_ACT_N 114

AT26 B65_IO/L12_N/T1U/N11/GC PL_DDR_ALERT_N 116

AT28 B65_IO/L18_N/T2U/N11/AD2_N PL_DDR_BA0 150

AM24 B65_IO/L21_P/T3L/N4/AD8_P PL_DDR_BA1 145

AR28 B65_IO/L18_P/T2U/N10/AD2_P PL_DDR_BG0 115

AN28 B65_IO/L17_N/T2U/N9/AD10_N PL_DDR_BG1 113




AM28 B65_IO/L17_P/T2U/N8/AD10_P PL_DDR_CKE0 109

AU28 B65_IO/L10_P/T1U/N6/QBC/AD4_P PL_DDR_CKE1 110

AT23 B65_IO/L19_N/T3L/N1/DBC/AD9_N PL_DDR_CK0_N 139

AR23 B65_IO/L19_P/T3L/N0/DBC/AD9_P PL_DDR_CK0_P 137

AP25 B65_IO/L20_N/T3L/N3/AD1_N PL_DDR_CK1_N 140

AP24 B65_IO/L20_P/T3L/N2/AD1_P PL_DDR_CK1_P 138

AN24 B65_IO/L21_N/T3L/N5/AD8_N PL_DDR_CS0_N 149

AK24 B65_IO/L24_N/T3U/N11 PL_DDR_CS1_N 157

4.7k pull-up 1V2_STG3 PL_DDR_CS2_N 162

PL_DDR_CS3_N 165

U1 AJ31 B500_PS_MIO16 CLK_DDR4_I2C_SCL_OD 253

AJ30 B500_PS_MIO17 DDR4_I2C_SDA_OD 254

4.7k pull-up 3V3_STG3 PL_DDR_I2C_SA0 256

4.7k pull-Down GND PL_DDR_I2C_SA1 260

PL_DDR_I2C_SA2 166

4.7k pull-up 1V2_STG3 PL_DDR4_EVENT_N 134

U1

AU25 B65_IO/L11_P/T1U/N8/GC PL_DDR_A0 144

AN26 B65_IO/L15_N/T2L/N5/AD11_N PL_DDR_A1 133

AR24 B65_IO/L14_P/T2L/N2/GC PL_DDR_A2 132

AP26 B65_IO/T2U/N12 PL_DDR_A3 131

AN23 B65_IO/L22_N/T3U/N7/DBC/AD0_N PL_DDR_A4 128

AU24 B65_IO/L7_P/T1L/N0/QBC/AD13_P PL_DDR_A5 126

AP27 B65_IO/L16_N/T2U/N7/QBC/AD3_N PL_DDR_A6 127

AV26 B65_IO/L8_P/T1L/N2/AD5_P PL_DDR_A7 122

AW27 B65_IO/L9_N/T1L/N5/AD12_N PL_DDR_A8 125

AV27 B65_IO/L9_P/T1L/N4/AD12_P PL_DDR_A9 121

AR25 B65_IO/L14_N/T2L/N3/GC PL_DDR_A10 146

AW26 B65_IO/L8_N/T1L/N3/AD5_N PL_DDR_A11 120

AN27 B65_IO/L16_P/T2U/N6/QBC/AD3_P PL_DDR_A12 119

AV24 B65_IO/L7_N/T1L/N1/QBC/AD13_N PL_DDR_A13 158

AM23 B65_IO/L22_P/T3U/N6/DBC/AD0_P PL_DDR_A14_WE_N 151

AW25 B65_IO/T1U/N12/SMBALERT PL_DDR_A15_CAS_N 156

AV28 B65_IO/L10_N/T1U/N7/QBC/AD4_N PL_DDR_A16_RAS_N 152

AM19 B64_IO/L19_P/T3L/N0/DBC/AD9_P PL_DDR_DM0_N 12

AT22 B64_IO/L13_P/T2L/N0/GC/QBC PL_DDR_DM1_N 33

AU23 B64_IO/L7_P/T1L/N0/QBC/AD13_P PL_DDR_DM2_N 54

AW24 B65_IO/L1_P/T0L/N0/DBC PL_DDR_DM3_N 75

AJ18 B66_IO/L19_P/T3L/N0/DBC/AD9_P PL_DDR_DM4_N 178

AY17 B66_IO/L1_P/T0L/N0/DBC PL_DDR_DM5_N 199

AV17 B66_IO/L13_P/T2L/N0/GC/QBC PL_DDR_DM6_N 220




AY12 B66_IO/L7_P/T1L/N0/QBC/AD13_P PL_DDR_DM7_N 241

BA23 B64_IO/L1_P/T0L/N0/DBC PL_DDR_DM8_N 96

AK19 B64_IO/L22_N/T3U/N7/DBC/AD0_N PL_DDR_DQS0_N 11

AK20 B64_IO/L22_P/T3U/N6/DBC/AD0_P PL_DDR_DQS0_P 13

AP21 B64_IO/L16_N/T2U/N7/QBC/AD3_N PL_DDR_DQS1_N 32

AN21 B64_IO/L16_P/T2U/N6/QBC/AD3_P PL_DDR_DQS1_P 34

AY18 B64_IO/L10_N/T1U/N7/QBC/AD4_N PL_DDR_DQS2_N 53

AY19 B64_IO/L10_P/T1U/N6/QBC/AD4_P PL_DDR_DQS2_P 55

BB26 B65_IO/L4_N/T0U/N7/DBC/AD7_N PL_DDR_DQS3_N 74

BA26 B65_IO/L4_P/T0U/N6/DBC/AD7_P PL_DDR_DQS3_P 76

AK17 B66_IO/L22_N/T3U/N7/DBC/AD0_N PL_DDR_DQS4_N 177

AJ17 B66_IO/L22_P/T3U/N6/DBC/AD0_P PL_DDR_DQS4_P 179

BB15 B66_IO/L4_N/T0U/N7/DBC/AD7_N PL_DDR_DQS5_N 198

BA15 B66_IO/L4_P/T0U/N6/DBC/AD7_P PL_DDR_DQS5_P 200

AT18 B66_IO/L16_N/T2U/N7/QBC/AD3_N PL_DDR_DQS6_N 219

AR18 B66_IO/L16_P/T2U/N6/QBC/AD3_P PL_DDR_DQS6_P 221

AV13 B66_IO/L10_N/T1U/N7/QBC/AD4_N PL_DDR_DQS7_N 240

AU13 B66_IO/L10_P/T1U/N6/QBC/AD4_P PL_DDR_DQS7_P 242

BA20 B64_IO/L4_N/T0U/N7/DBC/AD7_N PL_DDR_DQS8_N 95

AY20 B64_IO/L4_P/T0U/N6/DBC/AD7_P PL_DDR_DQS8_P 97

AJ22 B64_IO/L24_P/T3U/N10 PL_DDR_DQ0 8

AK22 B64_IO/L24_N/T3U/N11 PL_DDR_DQ1 7

AM21 B64_IO/L20_P/T3L/N2/AD1_P PL_DDR_DQ2 20

AM20 B64_IO/L20_N/T3L/N3/AD1_N PL_DDR_DQ3 21

AJ21 B64_IO/L23_P/T3U/N8 PL_DDR_DQ4 4

AJ20 B64_IO/L23_N/T3U/N9 PL_DDR_DQ5 3

AL22 B64_IO/L21_P/T3L/N4/AD8_P PL_DDR_DQ6 16

AL21 B64_IO/L21_N/T3L/N5/AD8_N PL_DDR_DQ7 17

AT20 B64_IO/L14_P/T2L/N2/GC PL_DDR_DQ8 28

AP22 B64_IO/L15_N/T2L/N5/AD11_N PL_DDR_DQ9 29

AP19 B64_IO/L18_P/T2U/N10/AD2_P PL_DDR_DQ10 41

AU19 B64_IO/L14_N/T2L/N3/GC PL_DDR_DQ11 42

AN22 B64_IO/L15_P/T2L/N4/AD11_P PL_DDR_DQ12 24

AP20 B64_IO/L17_P/T2U/N8/AD10_P PL_DDR_DQ13 25

AR19 B64_IO/L18_N/T2U/N11/AD2_N PL_DDR_DQ14 38

AR20 B64_IO/L17_N/T2U/N9/AD10_N PL_DDR_DQ15 37

AW20 B64_IO/L9_P/T1L/N4/AD12_P PL_DDR_DQ16 50

AV21 B64_IO/L11_N/T1U/N9/GC PL_DDR_DQ17 49

AW19 B64_IO/L9_N/T1L/N5/AD12_N PL_DDR_DQ18 62

AV22 B64_IO/L8_P/T1L/N2/AD5_P PL_DDR_DQ19 63




AU20 B64_IO/L12_P/T1U/N10/GC PL_DDR_DQ20 46




BA28 B65_IO/L6_P/T0U/N10/AD6_P PL_DDR_DQ24 70

BA25 B65_IO/L3_N/T0L/N5/AD15_N PL_DDR_DQ25 71

BB24 B65_IO/L2_P/T0L/N2 PL_DDR_DQ26 83

AY27 B65_IO/L5_P/T0U/N8/AD14_P PL_DDR_DQ27 84

BB28 B65_IO/L6_N/T0U/N11/AD6_N PL_DDR_DQ28 66

BB25 B65_IO/L2_N/T0L/N3 PL_DDR_DQ29 67

AY25 B65_IO/L3_P/T0L/N4/AD15_P PL_DDR_DQ30 79

AY28 B65_IO/L5_N/T0U/N9/AD14_N PL_DDR_DQ31 80

AN17 B66_IO/L21_N/T3L/N5/AD8_N PL_DDR_DQ32 174

AL16 B66_IO/L23_P/T3U/N8 PL_DDR_DQ33 173

AM16 B66_IO/L23_N/T3U/N9 PL_DDR_DQ34 187

AP16 B66_IO/L24_N/T3U/N11 PL_DDR_DQ35 186

AN18 B66_IO/L21_P/T3L/N4/AD8_P PL_DDR_DQ36 170

AL18 B66_IO/L20_P/T3L/N2/AD1_P PL_DDR_DQ37 169

AM18 B66_IO/L20_N/T3L/N3/AD1_N PL_DDR_DQ38 183

AN16 B66_IO/L24_P/T3U/N10 PL_DDR_DQ39 182

BA16 B66_IO/L2_P/T0L/N2 PL_DDR_DQ40 195

BB16 B66_IO/L2_N/T0L/N3 PL_DDR_DQ41 194

AY14 B66_IO/L5_N/T0U/N9/AD14_N PL_DDR_DQ42 207


AW17 B66_IO/L3_P/T0L/N4/AD15_P PL_DDR_DQ44 191


AY15 B66_IO/L5_P/T0U/N8/AD14_P PL_DDR_DQ46 203


AR17 B66_IO/L17_P/T2U/N8/AD10_P PL_DDR_DQ48 216

AT17 B66_IO/L17_N/T2U/N9/AD10_N PL_DDR_DQ49 215

AT15 B66_IO/L14_P/T2L/N2/GC PL_DDR_DQ50 228

AT16 B66_IO/L18_P/T2U/N10/AD2_P PL_DDR_DQ51 229

AU18 B66_IO/L15_P/T2L/N4/AD11_P PL_DDR_DQ52 211

AV18 B66_IO/L15_N/T2L/N5/AD11_N PL_DDR_DQ53 212

AU15 B66_IO/L14_N/T2L/N3/GC PL_DDR_DQ54 224

AU16 B66_IO/L18_N/T2U/N11/AD2_N PL_DDR_DQ55 225


AW14 B66_IO/L11_N/T1U/N9/GC PL_DDR_DQ57 236

BA10 B66_IO/L9_P/T1L/N4/AD12_P PL_DDR_DQ58 249

BB10 B66_IO/L9_N/T1L/N5/AD12_N PL_DDR_DQ59 250




AW15 B66_IO/L11_P/T1U/N8/GC PL_DDR_DQ60 232


BB11 B66_IO/L8_N/T1L/N3/AD5_N PL_DDR_DQ62 245




AY22 B64_IO/L2_N/T0L/N3 PL_DDR_DQ66 101

BA21 B64_IO/L3_N/T0L/N5/AD15_N PL_DDR_DQ67 105

BB20 B64_IO/L5_P/T0U/N8/AD14_P PL_DDR_DQ68 88

AY23 B64_IO/L2_P/T0L/N2 PL_DDR_DQ69 87



Table 35 PL SoDIMM Card Slot [J107] Signal Connections



9.7 PCIe X16 Endpoint [J1]


U1

AL23 B65_IO/L23_N/T3U/N9 /PERST1_N/I2C/SDA

PCIE_BP_RESET_N PERST_N A11

J1

J13 B90_IO/L12_P/AD0_P PCIE_BP_WAKE_ODN WAKE_N B11

J14 B90_IO/L11_N/AD1_N PCIE_BP_CLKREQ_ODN CLKREQ_N B12

K14 B90_IO/L11_P/AD1_P CLK_PCIE_BP_SMCLK_OD SMCLK B5

K10 B90_IO/L10_N/AD2_N PCIE_BP_SMDAT_OD SMDAT B6

Short to PRSNT2D_N PRSNT1_N A1

NO CONNECT PRSNT2A_N B17

NO CONNECT PRSNT2B_N B31

NO CONNECT PRSNT2C_N B48

Short to PRSNT1_N PRSNT2D_N B81

NO CONNECT TRST_N B9

NO CONNECT TCK A5

TDI and TDO short together TDI A6

TDO A7

NO CONNECT TMS A8

NO CONNECT RSVD1 A19




NO CONNECT RSVD5 B30


U114 6 CLK_IN_P CLK_PCIEREF_BP_P REFCLK_P A13

7 CLK_IN_P CLK_PCIEREF_BP_N REFCLK_N A14

U1

AD12 B227_MGTREFCLK0_P CLK_PCIE_0_AC_P DIF0_P 15

U114 AD11 B227_MGTREFCLK0_N CLK_PCIE_0_AC_N DIF0_N 16

AF12 B226_MGTREFCLK0_P CLK_PCIE_1_AC_N DIF1_P 18




AF11 B226_MGTREFCLK0_N CLK_PCIE_1_AC_P DIF1_N 19

AH12 B225_MGTREFCLK0_P CLK_PCIE_2_AC_P DIF2_P 23

AH11 B225_MGTREFCLK0_N CLK_PCIE_2_AC_N DIF2_N 24

AK12 B224_MGTREFCLK0_P CLK_PCIE_3_AC_P DIF3_P 26

AK11 B224_MGTREFCLK0_N CLK_PCIE_3_AC_N DIF3_N 27

AE2 B227_MGTHRX3_P PCIE_TX_0_P PET0_P B14

J1

AE1 B227_MGTHRX3_N PCIE_TX_0_N PET0_N B15

AF4 B227_MGTHRX2_P PCIE_TX_1_P PET1_P B19

AF3 B227_MGTHRX2_N PCIE_TX_1_N PET1_N B20

AG2 B227_MGTHRX1_P PCIE_TX_2_P PET2_P B23

AG1 B227_MGTHRX1_N PCIE_TX_2_N PET2_N B24

AH4 B227_MGTHRX0_P PCIE_TX_3_P PET3_P B27

AH3 B227_MGTHRX0_N PCIE_TX_3_N PET3_N B28

AJ2 B226_MGTHRX3_P PCIE_TX_4_P PET4_P B33

AJ1 B226_MGTHRX3_N PCIE_TX_4_N PET4_N B34

AK4 B226_MGTHRX2_P PCIE_TX_5_P PET5_P B37

AK3 B226_MGTHRX2_N PCIE_TX_5_N PET5_N B38

AL2 B226_MGTHRX1_P PCIE_TX_6_P PET6_P B41

AL1 B226_MGTHRX1_N PCIE_TX_6_N PET6_N B42

AM4 B226_MGTHRX0_P PCIE_TX_7_P PET7_P B45

AM3 B226_MGTHRX0_N PCIE_TX_7_N PET7_N B46

AN2 B225_MGTHRX3_P PCIE_TX_8_P PET8_P B50

AN1 B225_MGTHRX3_N PCIE_TX_8_N PET8_N B51

AP4 B225_MGTHRX2_P PCIE_TX_9_P PET9_P B54

AP3 B225_MGTHRX2_N PCIE_TX_9_N PET9_N B55

AR2 B225_MGTHRX1_P PCIE_TX_10_P PET10_P B58

AR1 B225_MGTHRX1_N PCIE_TX_10_N PET10_N B59

AT4 B225_MGTHRX0_P PCIE_TX_11_P PET11_P B62

AT3 B225_MGTHRX0_N PCIE_TX_11_N PET11_N B63




AU2 B224_MGTHRX3_P PCIE_TX_12_P PET12_P B66

AU1 B224_MGTHRX3_N PCIE_TX_12_N PET12_N B67

AV4 B224_MGTHRX2_P PCIE_TX_13_P PET13_P B70

AV3 B224_MGTHRX2_N PCIE_TX_13_N PET13_N B71

AW2 B224_MGTHRX1_P PCIE_TX_14_P PET14_P B74

AW1 B224_MGTHRX1_N PCIE_TX_14_N PET14_N B75

BA2 B224_MGTHRX0_P PCIE_TX_15_P PET15_P B78

BA1 B224_MGTHRX0_N PCIE_TX_15_N PET15_N B79

AD8 B227_MGTHTX3_P PCIE_RX_0_P PER0_P A16

AD7 B227_MGTHTX3_N PCIE_RX_0_N PER0_N A17

AE6 B227_MGTHTX2_P PCIE_RX_1_P PER1_P A21

AE5 B227_MGTHTX2_N PCIE_RX_1_N PER1_N A22

AF8 B227_MGTHTX1_P PCIE_RX_2_P PER2_P A25

AF7 B227_MGTHTX1_N PCIE_RX_2_N PER2_N A26

AG6 B227_MGTHTX0_P PCIE_RX_3_P PER3_P A29

AG5 B227_MGTHTX0_N PCIE_RX_3_N PER3_N A30

AH8 B226_MGTHTX3_P PCIE_RX_4_P PER4_P A35

AH7 B226_MGTHTX3_N PCIE_RX_4_N PER4_N A36

AJ6 B226_MGTHTX2_P PCIE_RX_5_P PER5_P A39

AJ5 B226_MGTHTX2_N PCIE_RX_5_N PER5_N A40

AK8 B226_MGTHTX1_P PCIE_RX_6_P PER6_P A43

AK7 B226_MGTHTX1_N PCIE_RX_6_N PER6_N A44

AL6 B226_MGTHTX0_P PCIE_RX_7_P PER7_P A47

AL5 B226_MGTHTX0_N PCIE_RX_7_N PER7_N A48

AM8 B225_MGTHTX3_P PCIE_RX_8_P PER8_P A52

AM7 B225_MGTHTX3_N PCIE_RX_8_N PER8_N A53

AN6 B225_MGTHTX2_P PCIE_RX_9_P PER9_P A56

AN5 B225_MGTHTX2_N PCIE_RX_9_N PER9_N A57

AP8 B225_MGTHTX1_P PCIE_RX_10_P PER10_P A60




AP7 B225_MGTHTX1_N PCIE_RX_10_N PER10_N A61

AR6 B225_MGTHTX0_P PCIE_RX_11_P PER11_P A64

AR5 B225_MGTHTX0_N PCIE_RX_11_N PER11_N A65

AT8 B224_MGTHTX3_P PCIE_RX_12_P PER12_P A68

AT7 B224_MGTHTX3_N PCIE_RX_12_N PER12_N A69

AU6 B224_MGTHTX2_P PCIE_RX_13_P PER13_P A72

AU5 B224_MGTHTX2_N PCIE_RX_13_N PER13_N A73

AW6 B224_MGTHTX1_P PCIE_RX_14_P PER14_P A76

AW5 B224_MGTHTX1_N PCIE_RX_14_N PER14_N A77

AY4 B224_MGTHTX0_P PCIE_RX_15_P PER15_P A80

AY3 B224_MGTHTX0_N PCIE_RX_15_N PER15_N A81

Table 36 PCIe X16 Endpoint [J1] Signal Connections



9.8 PCIe X8 Host (X16 Connector) [J100]


U1

L10 B90_IO/L9_N/AD3_N PCIE_HOST_RESET_ODN PERST_N A11

J100

M10 B90_IO/L9_P/AD3_P PCIE_HOST_WAKE_ODN WAKE_N B11

L13 B90_IO/L8_N/HDGC/AD4_N PCIE_HOST_CLKREQ_ODN CLKREQ_N B12

L14 B90_IO/L8_P/HDGC/AD4_P CLK_PCIE_HOST_SMCLK_OD SMCLK B5

K12 B90_IO/L7_N/HDGC/AD5_N PCIE_HOST_SMDAT_OD SMDAT B6

GND PRSNT1_N A1

U1 L12 B90_IO/L7_P/HDGC/AD5_P

PCIE_HOST_PRSNT_N PRSTN2_1_N B17

PCIE_HOST_PRSNT_N PRSNT2_2_N B31



NO CONNECT TRST_N B9

NO CONNECT TCK A5

NO CONNECT TDI A6

NO CONNECT TDO A7

NO CONNECT TMS A8






NO CONNECT PWRBRK_N/RSVD B30

U114 41 DIF6_P CLK_PCIE_HOST_CONN_AC_P REFCLK_P A13

42 DIF6_N CLK_PCIE_HOST_CONN_AC_N REFCLK_N A14

U1

V12 B230_MGTREFCLK0_P CLK_PCIE_HOST_0_AC_P DIF4_P 32

U114 V11 B230_MGTREFCLK0_N CLK_PCIE_HOST_0_AC_N DIF4_N 33

T12 B231_MGTREFCLK0_P CLK_PCIE_HOST_1_AC_P DIF5_P 35

T11 B231_MGTREFCLK0_N CLK_PCIE_HOST_1_AC_N DIF5_N 36




R6 B230_MGTHTX0_P PCIE_HOST_TX0_P PET0_P B14

J100

R5 B230_MGTHTX0_N PCIE_HOST_TX0_N PET0_N B15

P8 B230_MGTHTX1_P PCIE_HOST_TX1_P PET1_P B19

P7 B230_MGTHTX1_N PCIE_HOST_TX1_N PET1_N B20

N6 B230_MGTHTX2_P PCIE_HOST_TX2_P PET2_P B23

N5 B230_MGTHTX2_N PCIE_HOST_TX2_N PET2_N B24

M8 B230_MGTHTX3_P PCIE_HOST_TX3_P PET3_P B27

M7 B230_MGTHTX3_N PCIE_HOST_TX3_N PET3_N B28

L6 B231_MGTHTX0_P PCIE_HOST_TX4_P PET4_P B33

L5 B231_MGTHTX0_N PCIE_HOST_TX4_N PET4_N B34

K4 B231_MGTHTX1_P PCIE_HOST_TX5_P PET5_P B37

K3 B231_MGTHTX1_N PCIE_HOST_TX5_N PET5_N B38

J6 B231_MGTHTX2_P PCIE_HOST_TX6_P PET6_P B41

J5 B231_MGTHTX2_N PCIE_HOST_TX6_N PET6_N B42

H4 B231_MGTHTX3_P PCIE_HOST_TX7_P PET7_P B45

H3 B231_MGTHTX3_N PCIE_HOST_TX7_N PET7_N B46

NO CONNECT PET8_P B50

NO CONNECT PET8_N B51


















U1

T3 B230_MGTHRX0_N PCIE_HOST_RX0_N PER0_N A17

T4 B230_MGTHRX0_P PCIE_HOST_RX0_P PER0_P A16

R1 B230_MGTHRX1_N PCIE_HOST_RX1_N PER1_N A22

R2 B230_MGTHRX1_P PCIE_HOST_RX1_P PER1_P A21

P3 B230_MGTHRX2_N PCIE_HOST_RX2_N PER2_N A26

P4 B230_MGTHRX2_P PCIE_HOST_RX2_P PER2_P A25

N1 B230_MGTHRX3_N PCIE_HOST_RX3_N PER3_N A30

N2 B230_MGTHRX3_P PCIE_HOST_RX3_P PER3_P A29

M3 B231_MGTHRX0_N PCIE_HOST_RX4_N PER4_N A36

M4 B231_MGTHRX0_P PCIE_HOST_RX4_P PER4_P A35

L1 B231_MGTHRX1_N PCIE_HOST_RX5_N PER5_N A40

L2 B231_MGTHRX1_P PCIE_HOST_RX5_P PER5_P A39

J1 B231_MGTHRX2_N PCIE_HOST_RX6_N PER6_N A44

J2 B231_MGTHRX2_P PCIE_HOST_RX6_P PER6_P A43

G1 B231_MGTHRX3_N PCIE_HOST_RX7_N PER7_N A48

G2 B231_MGTHRX3_P PCIE_HOST_RX7_P PER7_P A47

NO CONNECT PER8_P A52

NO CONNECT PER8_N A53


















Table 37 PCIe X8 Host (X16 Connector) [J100] Signal Connections



9.9 1G Ethernet PHY [U2]-Ethernet 1G [J120]


U1

AD31 B502_PS_MIO62 ENET_RESET*1 RESET_N 42

U2

AD30 B502_PS_MIO63 ENET_INT INT_N/PME2_N 38

AD32 B502_PS_MIO64 CLK_ENET_TX GTX_CLK 24

AE29 B502_PS_MIO65 ENET_TX_D0 TXD0 19

AD33 B502_PS_MIO66 ENET_TX_D1 TXD1 20



AE32 B502_PS_MIO69 ENET_TX_CTRL TX_EN 25

AF30 B502_PS_MIO70 CLK_ENET_RX RX_CLK/PHYAD2 35

AF31 B502_PS_MIO71 ENET_RX_D0 RXD0/MODE0 32

AF32 B502_PS_MIO72 ENET_RX_D1 RXD1/MODE1 31

AG30 B502_PS_MIO73 ENET_RX_D2 RXD2/MODE2 28

AG33 B502_PS_MIO74 ENET_RX_D3 RXD3/MODE3 27

AF33 B502_PS_MIO75 ENET_RX_CTRL RX_DV/CLK125_EN 33

AH31 B502_PS_MIO76 CLK_ENET_MDIO MDC 36

AG31 B502_PS_MIO77 ENET_MDIO MDIO 37

4.7kohm to 3V3_STG3 CLK125_NDO/LED_MODE 41

12.1Kohm to GND ISET 48

*1- ENET_RESET signal is inverted from the output of U1 to the input of U2, making the signal active high.

Table 38 Ethernet Signal Connections



9.10 USB to Dual UART [U123]-USB Micro [J33]


U123

13 TXD_ECI UART0_RX B500_PS_MIO18 AE34

U1 12 RXD_ECI UART0_TX B500_PS_MIO19 AE35

21 TXD_SCI UART1_TX B500_PS_MIO20 AH34

20 RXD_SCI UART1_RX B500_PS_MIO21 AF35

3 D_P USB_UART0_DATA_P DATA_P 3 J33

4 D_N USB_UART0_DATA_N DATA_N 2

Table 39 USB [J33] to Dual UART Signal Connections



10. ERRATA OF KNOWN ISSUES

10.1 TBD

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