signal integrity overview bw - iteso course/lectures/signal... · fr4 is us$2/sq ft (d. reed, 2003)...
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Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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An Overview on Signal Integrity
Dr. José Ernesto Rayas Sánchez
2Dr. J.E. Rayas Sánchez
Outline
Review of market and technology trends
A Signal Integrity (SI) definition
An introduction to SI terminology
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
3Dr. J.E. Rayas Sánchez
Technology Trends
The minimum dimension of transistors has been continuously decreasing: 25 µm in 1960 to 0.13µm in 2005
The number of transistors per chip has continue to double every 1.5 year (Moore’s law)
CPU operating frequency has continuously increase
Denser and faster buses have appeared
Faster memories are required
Cost of interconnects remain a small fraction (<5%) of the system cost
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Decreasing Dimension of Transistors
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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Decreasing Dimension of Transistors (cont)
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Decreasing Dimension of Transistors (cont)
State-of-the-art silicon transistors can operate above 1 THz
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
7Dr. J.E. Rayas Sánchez
Moore’s Law
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CPU Operating Frequency
(H. Heck, 2005)
Processor Frequency
0.1
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005 2010Year
Freq
uenc
y [M
Hz]
4004
80088080
8085808680888018680286
80386486DX
486DX2486DX4
Pentium®Pentium® Pro
Pentium® IICeleron®
Pentium® IIIPentium® 4
Frequency
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
9Dr. J.E. Rayas Sánchez
Denser and Faster Buses
486DX2 Processor (~1992) Pentium® 4 Processor (2003)
▪ 3 major buses ▪ 4 major buses▪ 33 MHz max frequency ▪ 66-800 MHz max frequency▪ 4 byte bus width ▪ 4-16 byte bus width
CPU100 MHz
L2 Cache
PCI Chipset PCI SlotsFPM/EDODRAM
32 bit33 MHz
32 bit33 MHz
32 bit12 MHz
(H. Heck, 2005)
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Denser and Faster Buses (cont)System Bus Frequency
0.1
1
10
100
1000
1970 1975 1980 1985 1990 1995 2000 2005 2010Year
Freq
uenc
y [M
Hz]
4004
800880808085
8086808880186
8028680386486DX486DX2486DX4
Pentium®Pentium® ProPentium® II
Celeron®Pentium® IIIPentium® 4
System Bus Frequency
(H. Heck, 2005)
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
11Dr. J.E. Rayas Sánchez
Faster and Denser Memories
1
10
100
1000
10000
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
Year
Peak
Ban
dwid
th [M
B/s
]
(H. Heck, 2005)
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Cost of Interconnects
Interconnect makes up < 5% of the system cost– Most technical problems can be solved with $– High volume PC market can’t afford extra cost
Designing Multi-GHz interconnects to fit in sub $1000 PCs is a huge challenge
(H. Heck, 2005)
Motherboard & Connectors (< 5% of total)
Monitor +Video Card
Hard DiskCPU
Sound +Speakers
MemoryCase
MotherboardComponents
Power Supply
CDROM
Fax/ModemO/S
Approximate Cost Breakdown of a PC
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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Cost of Interconnects (cont)
FR4 has been the standard choice for PCBs in the last four decadesOther dielectrics have better performance: polyethylene (PE), polytetrafluoroethylene (PTFE)PTFE-based laminates can cost up to US$100 per squared footFR4 is US$2/sq ft
(D. Reed, 2003)
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High-Speed Digital Design
Physical design becomes crucial: connectors, backplanes, packages, PCB structures, material properties, etc.
Analog techniques (analog electronics, RF and microwave engineering) are used to solve most signal integrity problems
© Copyright 2003 Agilent Technologies, Inc.
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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High-Speed Digital Design (cont)
Eye Diagrams (for a 25-inch channel)1 Gbps, 200 psec/div 2.5 Gbps, 80 psec/div
5 Gbps, 40 psec/div 7.5 Gbps, 27 psec/div
© Copyright 2003 Agilent Technologies, Inc.
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What is Signal Integrity (SI)?
It is an engineering practice that aims at ensuring reliable high-speed data transmission and reception, without polluting the electromagnetic spectrum and without damaging any device
SI effectively combines concepts and techniques from the following disciplines:
– microwave and RF engineering– electromagnetics– physical design– analog electronics– communications, and – digital design
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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SI Problems Appear at Different Levels
(M. Nakhla, 2004)
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SI Problems Appear at Different Levels (cont)
(A. Weisshaar, 2004)
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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Effective Signal Integrity Practices
Tracking down the cause of signal integrity problems after the hardware has been created can be extremely complicated
(R. Mellitz, 2003)
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Signal Integrity Issues
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
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Tools and Concepts for Signal Integrity Issues
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CAD Tools for SI
CAD tools allow addressing many signal integrity issues during simulation
Appropriate simulation strategies improve the understanding of highly complex signal integrity phenomena
If the simulation is accurate enough, many signal integrity problems can be solved before they actually exist
Signal Integrity and High-Speed InterconnectsJanuary-May 2006
Dr. J. E. Rayas Sánchezhttp://iteso.mx/~erayas [email protected]
23Dr. J.E. Rayas Sánchez
Conclusions
System performance and functionality increase over time
In the PC market, sales decrease sharply when the price exceeds the volume desktop price barrier
Interconnect components account for < 5% of system cost
Interconnects impose severe limitations in system performance
Interconnect engineers must satisfy increased performance demands without increasing the cost of the solution
SI problems are challenging, but many tools and concepts can be used to alleviate them