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Silicon Laboratories, Inc. Rev 1.0 1

Clock Tree Design Considerations

Hardware design in high-performance applications such as communications, wireless infrastructure,servers, broadcast video, and test and measurement equipment is becoming increasingly complex assystems integrate more functionality and require ever-increasing levels of performance. This trendextends to the board-level clock tree that provides reference timing for the system. A one size fits allstrategy does not apply when it comes to clock tree design. Optimizing the clock tree to meet bothperformance and cost requirements depends on a number of factors, including the system architecture,integrated circuit (IC) timing requirements (frequencies, signal formats, etc.) and the jitter requirements ofthe end application.

Reference Timing When to Use a Crystal vs. a Clock

One of the first design considerations is to inventory the hardware designs reference clock requirementsand select the type of reference clocks that will be used for the processors, FPGAs, ASICs, PHYs, DSPsand various other components in the system. Quartz crystals are typically used if the IC has an integratedoscillator and on-chip phase-locked loops (PLLs) for internal timing. Crystals are cost-effectivecomponents that exhibit excellent phase noise and are widely available. They can also be placed in closeproximity to the IC, simplifying board layout. However, one of the drawbacks of crystals is that theirfrequency can vary significantly over temperature, exceeding the parts-per-million (ppm) stabilityrequirements of many serializer-deserializer (SerDes) applications. In many stability-sensitive high-speedSerDes applications, crystal oscillators (XOs) are recommended because they guarantee tighter stabilitythan passive crystals.

Clock generators and clock buffers are typically used when several reference frequencies are required. Insome applications, FPGA/ASICs have multiple time domains for the data path, control plane and memory

controller interface and require multiple unique reference frequencies. A clock generator or buffer is alsopreferred when the IC cannot accommodate a crystal input, when the IC must be synchronized to anexternal reference (source-synchronous application), or when a high-frequency reference not easilygenerated by a crystal is required.

Free-Running versus Synchronous Clock Trees

Once the hardware design clock inventory has been completed and the crystals have been selected forsome of the components, the next step is to select the timing architecture for the remaining clocks: free-running or synchronous. For applications that require one or more independent reference clocks withoutany special phase-lock or synchronization requirements, XOs, clock generators and clock buffers are thepreferred choice. Processors, memory controllers, SoCs and peripheral components (e.g., USB and PCIExpress switches) typically use a combination of XOs, clock generators and clock buffers for referencetiming in free-running, asynchronous applications. XOs are preferable when the application requires oneto two timing sources, while clock generators and buffers are better suited for applications that needseveral individual clocks. Clock generators can synthesize multiple clocks at different frequencies, butsacrifice some jitter performance in comparison to clock buffer +XO clock trees. Clock buffers can beused in conjunction with a XO reference to distribute multiple clocks at the same frequency and providethe lowest jitter implementation for a multi-output clock tree.

Synchronous clocking is used in applications that require continuous communication and network-levelsynchronization, such as Optical Transport Networking (OTN), SONET/SDH, mobile backhaul,


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synchronous Ethernet and HD SDI video transmission. These applications require transmitters andreceivers to operate at the same frequency. Synchronizing all SerDes reference clocks to a highlyaccurate network reference clock (e.g., Stratum 3 or GPS) guarantees synchronization across all nodes.In these applications, low-bandwidth PLL-based clocks provide wander and jitter filtering (jitter cleaning)to ensure that network-level synchronization is maintained. In networking line card PLL applications,specialized jitter attenuating clocks or discrete PLLs with voltage-controlled oscillators (VCOs) are thepreferred clock solution for SerDes clocking. For optimal performance, a jitter attenuating clock should beplaced at the end of the clock tree, directly driving the SerDes device. Clock generators and buffers canbe used to provide other system references.

Dual XOs

Div

Div

XO + Clock Buf fer

1-2 reference clocks Low jitter clock fanout

Single frequency

Div

Div

Crystal + Clock Generator

Clock synthesis

Multiple frequencies

PLL

Free-Running Clock Trees

Synchronous Clock Tree

Reference

Clock

Div

Div

PLL

Div

Low

BWPLL

Div

Div

Jitter/Wander Attenuation

Frequency Translation

Clock Generator

Jitter Cleaning Clock

Clock Buffer/ Translator

Clock Distribution

Format/Level Translation

Frequency Translation Figure 1. Clock Tree Examples

Clock Jitter

Clock jitter is a critical specification for timing components because excessive clock jitter can compromisesystem performance. There are three common types of clock jitter, and, depending on the application,one type of jitter will be more important than another.

Cycle-to-cycle jitter measures the maximum change in clock period between any two adjacent clockcycles, typically measured over 1,000 clock cycles.

Period jitter is the maximum deviation in clock period with respect to an ideal period over a largenumber of cycles (10,000 clock cycles typical). Both cycle-to-cycle jitter and period jitter are useful incalculating setup and hold timing margins in digital systems, and are often figures of merit for CPUand SoC devices.

Phase jitter is the figure of merit for high-speed SerDes applications. It is a ratio of noise power tosignal power calculated by integrating the clock single sideband phase noise across a range offrequencies offset from a carrier signal. Phase jitter is especially critical in FPGA and high-speedSerDes clocking applications in which excessive phase jitter can degrade the bit error rate of thehigh-speed serial interface.

During clock tree design and component selection, it is important to evaluate devices based on maximumjitter performance. Typical jitter specifications do not guarantee device performance over all conditions,including process, voltage, temperature and frequency variation. Maximum jitter provides a morecomprehensive specification inclusive of these additional factors.

In addition, take special care to review jitter test conditions on timing device data sheets. Clock jitterperformance varies across a wide range of conditions including device configuration, operating frequency,


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signal format, input clock slew rate, power supply and power supply noise. Look for devices that fullyspecify jitter test conditions since they guarantee operation over a wider operating range.

Selection Criteria for Clock and Oscillator Components

Once the basic clock tree architecture is determined, the next step is component selection. Table 1

summarizes the selection criteria that should be used for choosing clock and oscillator components forboth free-running and synchronous clock trees. Look for features that simplify clock tree design tominimize bill-of-material (BOM) cost and complexity.

Table 1. Timing Component Selection Criteria

Function XO VCXO Clock Generator Clock Buffer Jitter Cleaning Clock

Free-Run Operation Yes No Yes Yes Yes

Synchronous Operation No Yes Yes Yes Yes

Clock Multipl i cation No Yes Yes No Yes

Clock Divis ion No No Yes Yes YesJi tter Cleaning No Yes No No Yes

Des ign Complexi ty Low High Medium Low Medium

Integration Low Low High High High

Small

form

factor

Small

form

factor

Any-freque ncy, a ny-

output clock

synthesis

Format/level

translation

Any-freque ncy clock

synthesis

Format translation Integrated input mux Integrated VCXO

VDD level

translation

Glitchless switching

between clocks a t

different

frequencies

Integrated l oop fil ter

Cl ock di vi si on Hi tl es s swi tchi ng

Synchronous output

clock disableHoldover

Integrated power supply fi ltering

Features That Simplify

Clock Tree Design

Estimating Clock Tree Jitter

Before a clock tree design is complete, the total clock tree jitter should be estimated to determine if thereis sufficient system-level design margin. It is important to note that total clock tree RMS jitter is much lessthan the simple sum of data sheet jitter specifications from multiple components. The clock tree jitter canbe defined by the following:

() = 12 +22 ++2Where=Total RMS jitter, =individual device RMS jitter.

Note: This equation can be applied to calculating total period jitter and phase jitter, assuming the jitterdistributions are Gaussian and uncorrelated. The equation should not be applied to cycle-to-cycle jitter,which is expressed as a peak jitter number and not RMS.


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Component jittercan be estimated using data sheet jitter specifications or calculated from phase noisedata. Silicon Labs offers an easy-to-use utility for converting clock phase noise to jitter. Seehttp://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspxfor more details. Be sure to usemaximum jitter specifications to generate a conservative estimate of total clock tree jitter.

Simplifying Clock Trees

Many clock trees require special features in addition to basic clock generation and distribution. Forexample, the application may require format/level translation (e.g. 3.3 V LVPECL to 2.5 V LVDS),switching between two clocks at different frequencies, clock division, pin-selectable output enable controland CMOS drive strength (output impedance) control for electromagnetic interference (EMI) reduction. Ifdesigned discretely, implementing these functions adds significant cost and complexity to the clock treedesign. Silicon Labs has developed a family of Si5330x universal buffers/translators that integrateformat/level translation, clock muxing, clock division and other key clock tree building block functions.

These devices replace multiple LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single clockbuffer IC. In addition to simplified clock tree design (see Figure 2), the Si5330x devices minimize BOMcost and complexity, simplify procurement and improve system performance.

Div

Div

Clock

Buffer

N x 125 MHz

2.5V LVDS

Si53302-Based Clock Distributi on

Clock

Generator156.25 MHz

125 MHz

Traditional Clock Distribution

Mux

Logic

Translation

N x 125 MHz 3.3V LVPECL

Clock

Division

125 MHz

Format/Level

Translation

Div

Div

Integrated clock buffer, frequency flexible 2:1 mux, format/level translation

5 x 125 MHz 2.5V LVDS

5 x 125 MHz 3.3V LVPECL156.25 MHz

125 MHz

VDDO

VDDO

VDD

Format Select (LVPECL, L VDS, CML, HCSL, CMOS)

Format Select (LVPECL, LVDS, CML, HCSL, CMOS)

Figure 2. Si5330x Clock Buffer IC Simpli fies Clock Tree Designs

Silicon Labs offers one of the industrys broadest portfolios of frequency flexible clock generators, clockbuffers, jitter cleaning clocks and XO/VCXOs. Through this comprehensive offering, Silicon Labs providesthe industrys highest performance and most highly integrated clock tree solutions.

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Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, smallsize, analog intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach andworld-class engineering team. Patent:www.silabs.com/patent-notice

2012, Silicon Laboratories Inc. ClockBuilder, DSPLL, Ember, EZMac, EZRadio, EZRadioPRO, EZLink, ISOmodem, Precision32,ProSLIC, QuickSense, Silicon Laboratories and the Silicon Labs logo are trademarks or registered trademarks of SiliconLaboratories Inc. ARM and Cortex-M3 are trademarks or registered trademarks of ARM Holdings. ZigBee is a registered trademarkof ZigBee Alliance, Inc. All other product or service names are the property of their respective owners.
http://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspxhttp://www.silabs.com/patent-noticehttp://www.silabs.com/patent-noticehttp://www.silabs.com/patent-noticehttp://www.silabs.com/patent-noticehttp://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspx

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