silberschatz, galvin and gagne 2002 9.1 applied operating system concepts chapter 9. memory...
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Silberschatz, Galvin and Gagne 20029.1Applied Operating System Concepts
Chapter 9. Memory Management
Logical versus Physical Address Space
Swapping
Contiguous Allocation
Paging
Segmentation
Segmentation with Paging
Silberschatz, Galvin and Gagne 20029.2Applied Operating System Concepts
Multistep Processing of a User Program
User programs go through several steps before being run on memory.
Silberschatz, Galvin and Gagne 20029.3Applied Operating System Concepts
Binding Symbolic Identifier – Binary Number
Compile time binding 주소가 이때 알려져 있어야 함 absolute ( 최종 , 절대주소 )code generated must recompile code if starting location changes.
Load time binding Loader 책임 하에 address 부여 ? ( 현재 빈 공간은 ?) Compiler 는 relocatable code 를 만들었어야 ( 어느 공간이라도 올라가야 – given base address)
Execution time binding 수행이 시작된 이후로도 프로세스를 메모리에서 계속 옮김 ? CPU 가 주소를 생성할 때마다 binding 을 점검 (address mapping table) binding run time. need hardware support (e.g., base and limit registers, MMU).
Silberschatz, Galvin and Gagne 20029.4Applied Operating System Concepts
Add A, B
A: 100
B: 330
Jump C
C: exit
Add 10, 20
10: 100
20: 330
Jump 30
30: exit
memory
Source Binaryon
Disk
Reference 될때load
Any Place
CPU 가 준 주소를MMU 가 변환
CPU 가 issue 하는 번지
Mapping
Memory 내 번지
10
500
Silberschatz, Galvin and Gagne 20029.5Applied Operating System Concepts
Address Mapping Table
CPU 가 제시한 주소 : 실제 메모리 내 주소logical physical
CPU
Memory0 번지 500 번지
500:
0
500 번지 20000 번지
Silberschatz, Galvin and Gagne 20029.6Applied Operating System Concepts
Logical vs. Physical Address Space
Logical address address generated by the CPU also referred to as “virtual address”.
Physical address address seen by the memory unit.
Silberschatz, Galvin and Gagne 20029.7Applied Operating System Concepts
Memory-Management Unit (MMU)
MMU (Memory-Management Unit) is a Hardware device that maps virtual address to physical address.
In MMU scheme the value in the relocation register is added to every address generated by a user process at the time it is sent to memory (from CPU).
The user program deals with logical addresses never sees the real physical addresses.
Silberschatz, Galvin and Gagne 20029.8Applied Operating System Concepts
Dynamic relocation using a relocation register
Silberschatz, Galvin and Gagne 20029.9Applied Operating System Concepts
Some Terminologies
Dynamic Loading
Dynamic Linking
Overlays
Swapping
Silberschatz, Galvin and Gagne 20029.10Applied Operating System Concepts
Dynamic Loading
Routine is not loaded until it is called
Better memory-space utilization
Useful when large amounts of code are needed to handle infrequently occurring cases.
No special support from the operating system is required
implemented through program design.
Dynamic Linking 이 없이는 매번 같은 곳으로 올라와야
( 다음 페이지 )
Loading – occupy memory space
Silberschatz, Galvin and Gagne 20029.11Applied Operating System Concepts
Dynamic Linking
올라올 때마다 매번 동일한 주소가 비어있어야 ? -- no!
아무 주소로도 올라올 수 있어야… (to where, from where, is where)
Linking postponed until execution time.
Small piece of code, stub, used to locate the appropriate memory-resident library routine.
Stub replaces itself with the address of the routine, and executes the routine.
Operating system needed to check
if routine is in processes’ memory address.
Linking – Symbolic address v.s. Physical address
Silberschatz, Galvin and Gagne 20029.12Applied Operating System Concepts
Overlays
Keep in memory only those part when actually needed.
Useful when process is larger than memory.
Coded by user – “Manual Overlay”.
Silberschatz, Galvin and Gagne 20029.13Applied Operating System Concepts
Overlays for a Two-Pass Assembler
Silberschatz, Galvin and Gagne 20029.14Applied Operating System Concepts
Swapping
Swapping A process can be swapped temporarily out of memory to a backing store and then brought back into memory sometime later.
Backing store disk – fast, large enough to accommodate all images for all users
Roll out, roll in lower-priority process is swapped out so higher-priority process can be loaded and executed. swapping variant used for priority-based scheduling algorithms; Major part of swap time is transfer time; total transfer time is proportional to the amount of memory swapped.
Silberschatz, Galvin and Gagne 20029.15Applied Operating System Concepts
Schematic View of Swapping
hwp
web
Silberschatz, Galvin and Gagne 20029.16Applied Operating System Concepts
Contiguous Allocation ( 한 덩어리로 load)
Main memory usually into two partitions: Resident operating system, usually
held in low memory with interrupt vector. User processes then held in high memory.
Single-partition allocation to protect user processes from each other, and OS. Relocation register
contains value of smallest physical address. Limit register
contains range of logical addresses – each logical address bound by limit register.
OS
user process
Silberschatz, Galvin and Gagne 20029.17Applied Operating System Concepts
Hardware Support for Relocation and Limit Registers
Silberschatz, Galvin and Gagne 20029.18Applied Operating System Concepts
Contiguous Allocation (Cont.)
Multiple-partition allocation Hole
block of available memory holes of various size are scattered throughout memory. When a process arrives, it is allocated memory from a hole large
enough to accommodate it. Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
holehole
process 9
hole
process 10partitions
Silberschatz, Galvin and Gagne 20029.19Applied Operating System Concepts
Dynamic Storage-Allocation Problem
First-fit Allocate the first hole that is big enough.
Best-fit Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces many small leftover holes.
Worst-fit Allocate the largest hole; must also search entire list. Produces the largest leftover hole.
Buddy system 2 의 배수
How to satisfy a request of size n from a list of free holes.
First-fit and best-fit better than worst-fit
in terms of speed and storage utilization.
Silberschatz, Galvin and Gagne 20029.20Applied Operating System Concepts
Fragmentation
External fragmentation total memory space exists to satisfy a request, but it is not contiguous.
Internal fragmentation allocated memory may be slightly larger than requested memory; this
size difference is memory internal to a partition, but not being used.
Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large
block. Compaction is possible only if relocation is dynamic, and is done at
execution time. I/O problem
Latch job in memory while it is involved in I/O. Do I/O only into OS buffers, instead
Graceful degradation? (Very expensive especially at peak load?) .
Silberschatz, Galvin and Gagne 20029.21Applied Operating System Concepts
Paging
Entire program image resides on disk
Divide (memory, disk) into fixed size –
(page frame – ‘ 틀’ -- in memory, page -- ‘ 내용’ -- in disk)
When the program starts, just load 1st page only
Rest of the pages are loaded in memory on-demand page mapping table
Pages can be placed anywhere in memory
A particular page X of the program can be either
already loaded in memory page-frame Y
or
never been loaded before, it is in disk
Whenever CPU presents an address, MMU looks up page mapping table
Y
disk address
X
Silberschatz, Galvin and Gagne 20029.22Applied Operating System Concepts
Paging Example
Page name as issued by CPU
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Paging
Paging is a scheme that permits address space to be noncontiguous
Basic Method Divide physical memory into fixed-sized blocks called frames
(size is power of 2, between 512 bytes and 8192 bytes). Divide logical memory into blocks of same size called pages. Keep track of all free frames. Set up a page table to translate logical to physical addresses. Internal fragmentation.
Silberschatz, Galvin and Gagne 20029.24Applied Operating System Concepts
Address Translation Scheme
Address generated by CPU is divided into: Page number (p)
used as an index into a page table which contains base address of each page in physical memory.
Page offset (d) combined with base address to define the
physical memory address that is sent to the memory unit.
p d
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Address Translation Architecture
Silberschatz, Galvin and Gagne 20029.26Applied Operating System Concepts
Paging Example
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Paging Example
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Free Frames
Before allocation After allocation
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Implementation of Page Table
Page table is kept in main memory.
Page-table base register (PTBR) points to the page table.
Page-table length register (PRLR) indicates size of table.
Every memory access requires two memory accesses.
One for the page table and one for the data/instruction.
To speed up, a special fast-lookup hardware cache called associative registers or
translation look-aside buffers (TLBs)
Silberschatz, Galvin and Gagne 20029.30Applied Operating System Concepts
Table 내용의 대비
Page # Frame #
record
You need frame # here
Page #
Frame #
Page Table
TLB
극히 일부만
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Associative Register Two types of memory
1. 일반 memory: ( 예 : 컴퓨터 메모리 )
– give address -- return record
2. Associative memory: ( 예 : 전화번호부 )
– give field of record -- return record– Parallel search 를 안하면 너무 느리다 ( 또는 index 구비 )– 따라서 implementation 이 비싸진다 .
Associative registers (TLB)– parallel search Since only part of page table is in TLB
(register – fast – expensive-keep only active pages)
Address translation (A´, A´´) Try associative register first (portion of page table) If A´ is in associative register, get frame # out. Otherwise get frame # from page table in main memory context switch 때 flush (remove old entries)
Page # Frame #
record
You need frame # here
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Paging Hardware With TLB
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Effective Access Time
Associative lookup = time unit
memory cycle time = 1 microsecond
Hit ratio = percentage found in the associative registers
Effective Access Time (EAT)
<hit> <miss>
EAT = (1 + ) + (2 + )(1 – )
= 2 + –
Silberschatz, Galvin and Gagne 20029.34Applied Operating System Concepts
Memory Protection
Protection bit with each frame. ( 예 : rwx)
Valid-invalid bit - each entry in the page table: “valid” indicates the page is legal (not a valid page). “invalid” indicates otherwise (access not allowed)
디스크 정보 memory copy
memory copy is not valid any more(it’s value has been changed by other process)
Silberschatz, Galvin and Gagne 20029.35Applied Operating System Concepts
Valid (v) or Invalid (i) Bit In A Page Table
Silberschatz, Galvin and Gagne 20029.36Applied Operating System Concepts
Two-Level Page-Table Scheme
Program has a large address space.
Use 32 bit address
1 million page table entries (if page size – 4K)
4 MB page table (if each entry -- 4B)
전체 page table 을 disk 에
Page table 자체를 page 단위로 on-demand load
Silberschatz, Galvin and Gagne 20029.37Applied Operating System Concepts
Two-Level Page-Table Scheme
Silberschatz, Galvin and Gagne 20029.38Applied Operating System Concepts
Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a page offset consisting of 12 bits.
Since the page table is paged, the page number is further divided into: a 10-bit page number. a 10-bit page offset.
Thus, a logical address is as follows:
where pi is an index into the outer page table, and
p2 is the displacement within the page of the outer page table.
page number page offset
pi p2 d
10
10
12
Silberschatz, Galvin and Gagne 20029.39Applied Operating System Concepts
Address-Translation Scheme
Address-translation scheme for a two-level 32-bit paging architecture
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Multilevel Paging and Performance
Address space 가 더 커지면 세번째 disk block 이 (like B-tree)
(not data block, but next level page table)
Since each level is stored as a separate table in memory, covering a logical address to a physical one may take three, four memory accesses.
if address is 64 bits
Even though time needed for one memory access is quintupled, caching permits performance to remain reasonable.
Cache hit rate of 98 percent yields:
effective access time = 0.98 x 120 + 0.02 x 520
= 128 nanoseconds.
which is only a 28 percent slowdown in memory access time.
Silberschatz, Galvin and Gagne 20029.41Applied Operating System Concepts
Inverted Page Table
문제 : page table 매우 큰 이유 page 개수에 (disk size) 비례한 table 크기
one “page-table-entry per page”,
그러나 한 순간에는 소수의 페이지만 ( 필요 .AND. Memory Resident)
Cure: let “one page-table- entry per page frame” ( 다음 페이지 그림 참조 )
one page table system-wide
page frame 수만큼의 entry 만 필요 (fixed size)
table entry 의 내용은 =(process ID, page #)
table 의 index 가 frame #
단점 It is associative search and need to search entire table.
조치 Either use hash table to limit the search (slower)
Or use associative registers (expensive)
(3)
(1)
(2)
(4)
(5)
Silberschatz, Galvin and Gagne 20029.42Applied Operating System Concepts
Inverted Page Table Architecture
Silberschatz, Galvin and Gagne 20029.43Applied Operating System Concepts
Shared Pages
Shared code Re-entrant Code, Non-self-modifying Code: eg inc memory_address
One copy of read-only (re-entrant) code shared among processes
(eg, text editors, compilers, window systems). Shared code must appear in same location in the logical address space
of all processes.
Private code and data Each process keeps separate copy of data. (eg hwp – file, 글자크기 ..) Private data can appear anywhere in logical address space (base 주소 ).
hwpcode
P 고건
P.C. 글자크기 font
P 이석호
P.C. 글자크기 font
P 조유근 P.C. 글자크기 font
ㅣ oop 에서 명령어 자체를 ( 즉 address 를 ) increment 하면 ?
Silberschatz, Galvin and Gagne 20029.44Applied Operating System Concepts
Shared Pages ExampleEditor is shared
Editor consists of 3 pages -- ed1, ed2, ed3
Silberschatz, Galvin and Gagne 20029.45Applied Operating System Concepts
Segmentation
A program is a collection of segments.
A segment is a logical unit such as:
main (),
function,
global variables,
stack,
symbol table, arrays
Silberschatz, Galvin and Gagne 20029.46Applied Operating System Concepts
User’s View of a Program
mainmemory DISK
variable size
Silberschatz, Galvin and Gagne 20029.47Applied Operating System Concepts
Segmentation Architecture
Logical address consists of a two tuple:
< segment-number, offset >,
Segment table maps two dimensional physical addresses each table entry has:
base – contains the starting physical address where the segments reside in memory.
limit – specifies the length of the segment.
Segment-table base register (STBR) points to the segment table’s location in memory.
Segment-table length register (STLR) indicates number of segments used by a program;
segment number s is legal if s < STLR.
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Segmentation Architecture (Cont.)
Protection Protection bits associated with segments Each entry :
validation bit = 0 illegal segment R / W / X / A bits
Sharing shared segments same segment number
Allocation first fit / best fit external fragmentation
Since segments vary in length, memory allocation is
a dynamic storage-allocation problem.
S L valid rwxa disk_ 주소
Segmentlength
여러 종류의 fault -- segment system
Silberschatz, Galvin and Gagne 20029.49Applied Operating System Concepts
Segmentation Hardware
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Example of Segmentation
Question: What if (segment size >> memory size) ?
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Sharing of Segments
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MULTICS Address Translation Scheme
Silberschatz, Galvin and Gagne 20029.53Applied Operating System Concepts
Segmentation with Paging – MULTICS
The MULTICS system solved problems of external fragmentation and lengthy search times
by paging the segments.
Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment but rather the base address of a page table for this
segment.
Silberschatz, Galvin and Gagne 20029.54Applied Operating System Concepts
Segmentation with Paging – Intel 386
segmentation with paging for memory management with a two-level paging scheme.