silicon south west, “testing times” the economics of verification mike bartley, tvs
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Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS. How can verification deliver value?. What is verification? The economics of verification 100% verification is IMPOSSIBLE How to do verification successfully. The various RTL verification techniques. - PowerPoint PPT PresentationTRANSCRIPT
Test and Verification Solutions 116th April 2010
Silicon South West, “Testing Times”
The Economics of Verification
Mike Bartley, TVS
2Test and Verification Solutions 216th April 2010
How can verification deliver value?
• What is verification?
• The economics of verification
• 100% verification is IMPOSSIBLE
• How to do verification successfully
3Test and Verification Solutions 316th April 2010
The various RTL verification techniques
Verification
DynamicStatic
ReviewsCode
AnalysisFormal Simulation
Emulationetc
DynamicFormal
4Test and Verification Solutions 416th April 2010
Verification consumes the greatest design time
Source: EE Times 2006 EDA Users Survey
5Test and Verification Solutions 516th April 2010
Poor verification costs money in re-spins
Source = Global IC (ASSP/ASIC)Service Management Report 2007,IBS
90nm 65 45
Functional 20% 22% 26%
Analog Mixed Signal
21% 23% 17%
Reasons for respins I ssues Found on First Spin I Cs/ ASI Cs
43%20%
17%14%
12%11%11%
10%10%
7%4%
3%
0% 10% 20% 30% 40% 50%
Functional Logic ErrorAnalog Tuning Issue
Signal Integrity IssueClock Scheme Error
Reliability IssueMixed Signal Problem
Too Much PowerHas Path(s) Too SlowHas Path(s) Too Fast
IR Drop IssuesFirmware Error
OtherSource: Aart de Geus, Chairman and CEO of Synopsys.
Based on a survey of 2000 users by Synopsys
• “Half of all chip developments require a re-spin, three quarters due to functional bugs”, The 2004/2002 IC/ASIC Functional Verification Study by Collett International Research
6Test and Verification Solutions 616th April 2010
Economic impact of Verification
• Inefficient verification– It is your biggest design task!– Delays to market
• Ineffective verification– Your biggest cause for re-spins (and recalls)
• Economics of early release– Better, faster verification– Tape-out early with measurable risk
7Test and Verification Solutions 716th April 2010
• Consider an adder– 16 bits → 8.5 billion tests > 2500 years @ 1 test/second
• 2x x 2x x 2y possible input conditions per transition
Impossible to prove the absence of bugs
Why is 100% verification impossible?
NextStateLogic
OutputLogic
Y
X Z
8Test and Verification Solutions 816th April 2010
What we want from verification
• Demonstrate absence of bugs
• Build confidence to ship the product– Defining measurable exit signoff criteria
• Demonstrate correctness of prioritised features
• Mitigate risk
• And stop when cost of further verification outweighs the advantages of increased confidence
9Test and Verification Solutions 916th April 2010
Beginning verification earlier brings benefits
A separate verification team enables this
• What usually happens?
Design Verif
Time
Effo
rt
Design
Verification
Effo
rt
Time
Design Verification
Time
Effo
rt
Design
Verification
Effo
rt
Time
10Test and Verification Solutions 1016th April 2010
Team independence in verification
• How hard does somebody try to break their own design?• Verification engineers require different skills and attitudes• Reconvergent paths (Bergeron 2000)
Specification
Interpretation
Interpretation
RTL coding
Verification
SpecificationInterpretation RTL coding
Verification
Research shows this is the single biggest contributor to higher quality
11Test and Verification Solutions 1116th April 2010
Good engineering principles delivers benefits
• Processes– Stable, clear specifications under change control– Configuration and defect management– Maximise re-use– Well defined signoff targets
• People– Verification engineers require different skill sets– Independence
• Appropriate tools and methodologies
12Test and Verification Solutions 1216th April 2010
And what about software!
• 20% hardware, 80% software?• Is the Toyota Prius recall the software
equivalent of the Intel FPU bug?
13Test and Verification Solutions 1316th April 2010
Summary
• About TVS• About DVClub
– “Design IP – help or hindrance to verification”, April 26th
• What is verification• Why you should care• Managing it
• Questions?