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Principles OfPrinciples Of
Digital DesignDigital DesignChapter 4Chapter 4
Simplification of Boolean Functions
Karnaugh MapsDon’t Care ConditionsTechnology MappingOptimization, Conversions, Decomposing, Retiming
2Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Boolean Cubes for Boolean Cubes for nn = 1, 2, 3, = 1, 2, 3, andand 4 4
0010 0011
0000 0001
0110 0111
1000 1001
1010 1011
1100 1101
0100 0101
1110 1111
010 011
110 111
100 101
000 00110 11
00 01
0 1
n = 1
n = 2
n = 3
n = 4
3Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Boolean Functions and Boolean CubesBoolean Functions and Boolean CubesEach Boolean n-cube represents a Boolean function of nvariablesEach vertex represents a mintermEach m-subcube represents 2m minterms, m < n, with the same n – m literalsEach m-subcube of 1-minterm represent a product of n – mliterals
== ll11ll22……llnn –– m m ((xx′′nn –– m m + 1 + 1 xx′′nn –– mm + 2 + 2 …… xx′′nn + + xx′′nn –– mm + 1 + 1 xx′′nn –– mm + 2 + 2 …… xxnn + + …… + + xxnn –– mm + 1 + 1 xxnn –– mm + 2 + 2 …… xxnn))== ll11ll22……llnn –– m m
For any Boolean function a prime implicant is a subcube not contained in any other prime implicantAs essential prime implicant is a subcube that contains a 1-minterm that is not included in any other prime implicant
4Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Representation of Carry and Sum Representation of Carry and Sum Functions with Boolean CubesFunctions with Boolean Cubes
ci xi yi ci + 1 si
00001111
00011001
101010
1 1
0 00 10 11 00 11 01 01 1
010 011
110 111
100 101
000 001
010 011
110 111
100 101
000 001
Carry Function ci + 1 Sum Function si
Truth Table
5Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Map RepresentationMap Representation
(Karnaugh) maps define Boolean functions
Map representation is equivalent to truth tables, Boolean expressions and Boolean cube representation
Map aid in visually identifying prime implicants and essential prime implicants in each Boolean function
Maps are used for manual optimization of Boolean functions
6Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Boolean Subcubes and Corresponding Boolean Subcubes and Corresponding Karnaugh Maps for Karnaugh Maps for nn = 1, 2, 3, = 1, 2, 3, andand 4 4
m0 m1
m3m2
yx 10x
1
0
n = 1
n = 2
m0 m1 m3 m2
m4 m5 m7 m6
m13
m9
m15
m11
m12 m14
m10m8n = 3
n = 4
1
0m0 m1
m5m4
m3 m2
m6m7
10110100
01
00
10
11
zwxy
10110100yz
x
7Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
22––variable Mapvariable Map
0 1
32
y
0 1
32
10
1
0
yx x10
1
0
Subcube x
Subcube y
Subcube x′x′yx′y′
xy′ xy
Map Organization Example of 1-subcubes
Example:Example:
x y AND OR0 0
111
01
XOR
1
010
0 0
1
0 10 11 0
Truth Table
0 1
32
10
1
0
yx
0 1
32
10
1
0
yx
0 1
32
10
1
0
yx
11
1 11 1
XORAND OR
8Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
ThreeThree––variable Mapvariable Map
1
00 1
54
3 2
67
10110100yz
x
x′y′z x′yz x′yz′x′y′z′
xy′z xyz xyz′xy′z′
Map Organization
1
00 1
54
3 2
67
10110100yz
x
Subcube x
Subcube z′
Subcube z
Example of 2-subcubes
1
00 1
54
3 2
67
10110100yz
x
Subcube xz′
Subcube yz
Subcube x′y′
Example of 1-subcubes
9Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Map Representation of Carry and Map Representation of Carry and Sum FunctionsSum Functions
ci xi yi ci + 1 si
00001111
00011001
101010
1 1
0 00 10 11 00 11 01 01 1
1
00 1
54
3 2
67
10110100xiyi
1
1 1 1
Truth Table
Carry Function ci + 1 Sum Function si
ci
1
00 1
54
3 2
67
10110100xiyi
ci
1 1
11
10Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
FourFour––variable Mapvariable Map
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
x′y′z′w′ x′y′z′w x′y′zw x′y′zw′
x′yz′w′ x′yz′w x′yzw x′yzw′
xyz′w′ xyz′w xyzw xyzw′
xy′z′w′ xy′z′w xy′zw xy′zw′
Map Organization
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
Subcube w′
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
Subcube y′w
Subcube x′y
Subcube xz
Subcube x′
Example of 2-subcubes Example of 3-subcubes
11Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Representation of GreaterRepresentation of Greater--than and than and LessLess--than Functions in Mapsthan Functions in Maps
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
y1y0
1
1 1
1 1
x1x0
x1 x0 y1 y0 Equal
0 0 0 1000010000100001
0 0 10 1 0011110000
1 0 11 01 1 1
1
1 10 00 11 01 10 00 11 01 1
1 0
Greater Than
Less Than
0
0
0000
0 1 00 0 00 0 10 0 11 1 01 1 01 0 01 0 11 1 01 1 0
10
0111
00
000
11
1GG == xx11yy11′′ + x+ x00yy11′′yy00′′ + x+ x11xx00yy00′′
Greater-than Function
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
1 1 1
1 1
1
Less-than Function
y1y0
LL == xx11′′ yy11 + x+ x11′′xx00′′yy00 + x+ x00′′yy11yy00
x1x0
Truth Table
12Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
FiveFive––variable Mapvariable Map
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
x′y′z′w′v′ x′y′z′wv′16 17 19 18
20 21 23 22
28 29 31 30
25 2724 26
10110100
x′y′zwv′ x′y′zw′v′ x′y′z′w′v x′y′z′wv x′y′zwv x′y′zw′v
x′yz′w′v′ x′yz′wv′ x′yzwv′ x′yzw′v′ x′yz′w′v x′yz′wv x′yzwv x′yzw′v
xyz′w′v′ xyz′wv′ xyzwv′ xyzw′v′ xyz′w′v xyz′wv xyzwv xyzw′v
xy′z′w′v′ xy′z′wv′ xy′zwv′ xy′zw′v′ xy′z′w′v xy′z′wv xy′zwv xy′zw′v
Map Organization
v = 0 v = 1
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
16 17 19 18
20 21 23 22
28 29 31 30
25 2724 26
10110100
v = 0 v = 1
x′
vw
zw′xz′
Example of 3-subsubes and 4-subcubes
13Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
SixSix––variable Mapvariable Map
v = 1
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zwxy
m0
Map Organization
32 33 35 34
36 37 39 38
44 45 47 46
41 4340 42
16 17 19 18
20 21 23 22
28 29 31 30
25 2724 26
48 49 51 50
52 53 55 54
60 61 63 62
57 5956 58
01
00
10
11
10110100
m4
m12
m8
m1
m5
m13
m9
m3
m7
m15
m11
m2
m6
m14
m10
m16
m20
m28
m24
m17
m21
m29
m25
m19
m23
m31
m27
m18
m22
m30
m26
m48
m42
m60
m56
m49
m53
m61
m57
m51
m55
m63
m59
m50
m54
m62
m58
m32
m36
m44
m40
m33
m37
m45
m41
m35
m39
m47
m43
m34
m38
m46
m42
v = 0
u = 0
u = 1
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zw
32 33 35 34
36 37 39 38
44 45 47 46
41 4340 42
16 17 19 18
20 21 23 22
28 29 31 30
25 2724 26
48 49 51 50
52 53 55 54
60 61 63 62
57 5956 58
01
00
10
11
10110100
v = 0 v = 1
xy
u = 0
u = 1
Example of 4-subcubes
z′w′
x′v
xz
14Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Boolean Simplification with Map Boolean Simplification with Map MethodMethod
Truth table, canonical form or
standard form
Determine prime implicants
Generate map
Select essential prime implicants
Find minimal cover
Standard form
15Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Boolean Simplification with Map Boolean Simplification with Map MethodMethod
Example: Example: Maps methodMaps method
Problem:Problem: UsingUsing the map method, simplify the Boolean functionthe map method, simplify the Boolean function
F = F = ww′′yy′′zz′′ + + wzwz + xyz + + xyz + ww′′yy
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zw
1
11
11
1
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zw
1 1 1
11
11
1 1 1
xy xy
1 1
1 1
Map Organization Prime Implicants in the Map
PI List: PI List: ww′′zz′′, , wzwz, yz, , yz, ww′′yyEPI List:EPI List: ww′′zz′′, , wzwzCover List:Cover List: (1)(1) ww′′zz′′, , wzwz, yz, yz
(2)(2) ww′′zz′′, , wzwz, , ww′′yy
16Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Selection of Prime ImplicantsSelection of Prime ImplicantsExample: Example: Selection of prime implicantsSelection of prime implicants
Problem:Problem: Simplify the Boolean functionSimplify the Boolean function
F = F = ww′′xx′′yyzz′′ + + ww′′xxyy + + wxzwxz + + wwxx′′yy′′ + + ww′′xx′′yy′′zz′′
0 1 3 2
4 5 7 6
13
9
15
11
12 14
108
10110100
01
00
10
11
zw
1
1 1
11
1 1
xy
1
PI List: PI List: ww′′xx′′zz′′, , ww′′xyxy, , wxzwxz, , wxwx′′yy′′, , xx′′yy′′zz′′, , wywy′′zz, xyz, , xyz, ww′′yzyz′′EPI List:EPI List: emptyemptyCover List:Cover List: (1)(1) ww′′xx′′zz′′, , ww′′xyxy, , wxzwxz, , wxwx′′yy′′
(2)(2) xx′′yy′′zz′′, , wywy′′zz, xyz, , xyz, ww′′yzyz′′
17Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
DonDon’’tt––Care ConditionsCare Conditions
Completely specified functions have a value assigned for every minterm
Incompletely specified functions do not have values assigned for some minterms which are called don’t–care minterms (d–minterms) or don’t–care conditions
Don’t–care minterms can be assigned any value during simplifications in order to simplify Boolean expressions
18Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
DonDon’’tt––Care ConditionsCare ConditionsExample: Example: DonDon’’tt––care conditionscare conditions
Problem:Problem: Derive Boolean expressions for the Derive Boolean expressions for the 99’’s complement of a BCD digits complement of a BCD digit
6754
2310
9
13
11
15 1412
108
10110100
01
00
10
11
x1x0
1 1
6754
2310
9
13
11
15 1412
108
10110100
01
00
10
11
x1x0
Digits Nine’s Complements
BCD BCDx3 x2 x1 x0
Decimalx3 x2 x1 x0
1100000000
9 0 08 0
11110000
701100110
6543210 0
1010101010
0000000011
Decimal
0 0 0 01 0
00111100
210
110011
3
0
0101010
45678
0 19
x3x2
X X X
X
X
X
6754
2310
9
13
11
15 1412
108
10110100
01
00
10
11
x1x0
x3x2
x3x2
6754
2310
9
13
11
15 1412
108
10110100
x1x0
01
00
10
11
x3x2
X X
1 1
X
X
X
X
X X X
X
X
X
X X X
X
X
X
1 1
1 1
1 1
y3 = x3′ x2′ x1′ y2 = x2 ⊕ x1
1
1
1
1
1Nine’s–Complement Table
y1 = x1 y0 = x0′
Map Representation
19Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Technology Mapping for Gate ArraysTechnology Mapping for Gate Arrays
Gate arrays contain only one type of m-input gate (such as 3-input NOR, 3-input NAND)
Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type of gate
Technology mapping consist of three tasksConversion replaces each operator with an operator Conversion replaces each operator with an operator representing the gate function given in the gate arrayrepresenting the gate function given in the gate arrayOptimization eliminates unnecessary invertersOptimization eliminates unnecessary invertersDecomposition replaces a Decomposition replaces a nn--input gate with an input gate with an mm--input gate input gate available in the gate arrayavailable in the gate array
20Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Conversion and OptimizationConversion and OptimizationRule 1:
Rule 2:
Rule 3:
Rule 4:
Conversion Rules
Rule 5:
Optimization Rules
Conversion Procedure:Replace Replace ANDAND andand OROR gates with gates with NAND NAND or or NORNOR gates by gates by using Rules 1 using Rules 1 –– 4, and eliminate double inverters whenever 4, and eliminate double inverters whenever possible possible
21Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Translation of Standard Terms to Translation of Standard Terms to NAND NAND and and NORNOR SchematicsSchematics
Form Type Standard Form Implementation NAND Implementation NOR
Implementation
Sum of products
Product of sums
22Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Conversion to Conversion to NAND (NOR)NAND (NOR) GatesGatesExample: Example: Conversion to Conversion to NAND (NOR)NAND (NOR) gatesgates
Problem:Problem: Derive the Derive the NAND NAND andand NORNOR implementations of the carry functionimplementations of the carry function
xxii
yyii
ccii
xxii
yyii
ccii
ccii + + 11 ccii + + 11
1.4
1.4
1.4
2.4
2.4
2.4
1.82.8
ccii + + 11 = = xxiiyyii+ + xxiiccii + + yyiicciiccii + + 11 = = ((xxii + + yyii)()(xxii + + ccii)()(yyii + + ccii))
0 1 3 2
4 5 7 6
00
xiyi
ci 01 11 10
10
NAND Implementation1 1 11
Map Definition Carry Function ci + 1
xxii
yyii
ccii
xxii
yyii
ccii
ccii + + 11 ccii + + 11
1.4
1.4
1.4
1.8
2.4
2.4
2.4
2.8Standard Forms
NOR Implementation
23Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Decomposition of 10Decomposition of 10––input input AND AND Gate Gate into 3into 3––input input ANDAND GatesGates
2.4 2.4 2.4
2.4
2.4
2.4 2.4
2.4
2.4
2.4
Level Number
Numberof Inputs
Number of Gates
1 [10 / 3] = 3
[4 / 3] = 1
[2 / 3] = 1
2
3
10
3 + (10 – 3([10 / 3])) = 4
1 + (4 – 3([4 / 3])) = 2
Input and Gate Computation on Each Level
Alternative DecompositionOne Possible Decomposition
24Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Technology Mapping for Gate Arrays
xiyi
ci
Technology Mapping for Gate ArraysExample: Example: Technology mapping for gate arraysTechnology mapping for gate arrays
Problem:Problem: Implement the sum function using 3Implement the sum function using 3––input input NAND NAND gatesgates
0 1 3 2
4 5 7 6
10110100
1
0
Map Definition Sum Function si
1
1
1
1
xxii yyiiccii
ssii
xxii yyiiccii
ssii
AND–OR Implementation Conversion to NAND Network
xxii yyiiccii
ssii
xxii yyiiccii
ssii
OR Gate Decomposition Optimized NAND Network
25Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Design RetimingDesign RetimingExample: Example: Design retimingDesign retiming
Problem:Problem: Implement 4Implement 4––bit carrybit carry--looklook--ahead functionahead functioncc44 = g= g33 + p+ p33 gg2 2 + p+ p33 pp22 gg1 1 + p+ p33 pp22 pp11 gg0 0 + p+ p33 pp22 pp11 pp00 cc00
using 3using 3––inputinput NAND NAND gates
gg33
gg22
gg11
pp33
cc00
pp11pp22pp00
pp22pp33
pp33
pp11pp22
gg00
pp33
cc44
gatesAND-OR Implementation
cc44
gg33
gg22
gg11
pp33
cc00
pp11pp22
pp00
pp22pp33
pp33
pp11pp22
gg00
pp33
cc44
Decomposition of AND-OR Implementation
gg33
gg22
gg11
pp33
cc00
pp11pp22
pp00
pp22pp33
pp33
pp11pp22
gg00
pp33
Performance Optimized Decomposition
cc44cc44
gg33
gg22
gg11
pp33
cc00
pp11pp22
pp00
pp22pp33
pp33
pp11pp22
gg00
pp33
Performance Optimized NAND ImplementationDelay = 6.4ns
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
gg33
gg22
gg11
pp33
cc00
pp11pp22
pp00
pp22pp33
pp33
pp11pp22
gg00
pp33
NAND Implementation of AboveDelay = 8.2ns
1.8
1.8
1.8
1.8
1.8
1.8
1.8
26Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Technology Mapping Procedure for Technology Mapping Procedure for Gate ArraysGate Arrays
Start
Convert
Decompose
Eliminateinvertors
Retime
yes
no
I/Odelay OK?
Done
27Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Technology Mapping for Custom Technology Mapping for Custom LibrariesLibraries
Libraries contain gates with different functions and different delays
Technology mapping means covering schematic with library gates
Minimize delay on critical paths
Minimize cost on non-critical paths
28Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Technology Mapping for Custom Technology Mapping for Custom LibrariesLibraries
Example: Example: Technology mapping for custom librariesTechnology mapping for custom libraries
Problem:Problem: Convert the expressionConvert the expression ww′′ zz′′ + + zz((ww + y+ y)) into a logic schematic using any of the gates into a logic schematic using any of the gates defined in the digital logic gates, multipledefined in the digital logic gates, multiple--input gates, and complex gates librariesinput gates, and complex gates libraries
yy
wwzz
FF
1.4
2.0
yy
wwzz
FF
2.4
2.4
2.4
2.4
Alternative A (Delay = 5.4ns, Cost = 20)AND–OR Implementation (Delay = 7.2ns, Cost = 28)
yy
wwzz
FF
1.4
1.4
1.4
1.4
yy
wwzz
FF
2.0
1.4
1.4
NAND Implementation (Delay =5.2ns, Cost = 22) Alternative B (Delay = 3.8ns, Cost = 20)
yy
wwzz
FF
Two Possible Conversions
1.4
1.4
1.4
1.4AA
BB yy
wwzz
FF
2.0
1.41.4
Cost Optimized Alternative B (Delay = 3.8ns, Cost = 18)
29Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Conversion Procedure for Custom Conversion Procedure for Custom LibrariesLibraries
Start
Select a pathConvert to NAND schematic Select gate Select a library
componentRecord
replacement gain
Select maximum gain replacementRecompute DelayAll paths
considered?
Done
yesyes
no no
All gatesconsidered?
All components considered?
no
yes
30Copyright © 2004-2005 by Daniel D. Gajski Slides by Philip Pham, University of California, Irvine
Chapter SummaryChapter Summary
Simplification of Boolean functions byMap method (visual)Map method (visual)
Technology mapping for gate arraysDecompositionDecompositionConversionConversionOptimizationOptimizationRetimingRetiming
Technology mapping for custom libraries by schematic covering with complex gates with
Time optimization on circuit pathsTime optimization on circuit pathsCost optimization on nonCost optimization on non--critical pathscritical paths