simulation and design methodology for

7/30/2019 Simulation and Design Methodology For

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Simulation and Design

Methodology

for

Hybrid

SET-CMOS Integrated Logic at

22-nmRoom-Temperature Operation


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INTRODUCTION THE heterogeneous 3-D integration and

functional integration nano electronic

devices.

which are limited by increased power

dissipation and thermal heating due tocontinuous scaling.

Therefore, in this research, we have set

down an organized design methodology

for hybrid SET-CMOS circuits with a

complete set of electrical and physical

parameters for the 22-nm technology

node at room temperature.


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WHAT IS S-ET ?( SINGLE ELECTRON TRANSISTOR)

The most fundamental 3-terminal single

electron device are called SET

SET has one which as coulomb blockade (CB)

island


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PRINCIPLE OPERATION

It relies on single electron tunneling

through a nano scale junction

The electron tunnels are transferred1 by 1 through the channel


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SET CIRCUIT


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COULOMB BLOCKADEEFFECTS

Coulomb blockade or single-electron chargingeffect, which allows for the precise control smallnumber of electrons

It reduces the number off electrons in aswitching transition

Which reduces power dissipation

Raising the higher level off circuit integration


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DESIGN CONSIDERATIONS FOR ASET LOGIC (INVERTER) The relations between the electrical and

physical parameters that must be satisfied for itsimplementation are as follows

i) The charging energy EC= e2/2C

. ii) The operating temperature Te2/(2kBC).

iii) The voltage level e/C.

iv) The device maximum operating frequency 1/(RtC) but when CL > C, CL affects the

frequency. v) The SET inverting voltage gain is given by AV

= Cg/Cj nevertheless, it is also a function oftemperature.


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SET inverter circuit


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Design Parameters VS= Vihigh" = VOhigh" = 800 mV

Vilow" = VOlow" = 0 V,

gain = 1, T= 300 K,

Rt= 1 M.

Derived parameters: Cj= 0.03 aF, Cg= 0.045 aF,Cb= 0.05 aF (all within the fabrication

capability).


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SET inverter transientanalysis.


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SET Parameters VS= Vihigh" = 800 mV

Vilow" = 0 V

gain = 1, T= 300 K

Rt= 1 M

Cj= 0.03 aF

Cg= 0.045 aF and Cb= 0.05aF


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HYBRID SET-CMOS INTEGRATEDLOGIC DESIGN ANDSIMULATION the SET is fabricated on the pre-metal dielectric

(PMD) of a CMOS-IC

which is useful to minimize the interconnect

delay.

where a SET-inverter drives a 22-nm CMOS

inverter with interconnect parasitics The SET

inverter

H b id T M d d i i h


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Hybrid SET-CMOS cascaded inverter with

interconnects parasitic.

(a) Model (b) Circuit diagram


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Hybrid SET-CMOS - parasiticsimulation


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COMPARISON BETWEEN SETAND CMOS LOGICParameters CMOS

cascaded

inverter

SET casded

inverter

Total power 130nW 4nW

-3dB

bandwidth

81 GHz 210 GHz

delay 7.8 ps 3.1 ps


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CONCLUSION We present a simulation method in the CADENCE

environment capable of simulating very large-scale hybridSETCMOS circuits efficiently. The simulation results forSET and

hybrid SET-CMOS logic are based on analytically derivedSET parameters that are within the fabrication range fordevices operational at room temperature and that takeinto account the interconnect parasitics at the

22-nm node.

We successfully designed and simulated a SETCMOSinterface capable of efficiently driving a CMOS logic withinterconnect, for a stable high output voltage of 800 mVand a bandwidth of approximately 1.1 GHz. Thebandwidth and, hence, the delay can be improved withdesign tradeoffs and by connecting SETs in parallel.


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simulation and design methodology for

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