single event transient and single event upset …single event transient and single event upset...
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Single Event Transient and Single Event Upset Single Event Transient and Single Event Upset Single Event Transient and Single Event Upset Single Event Transient and Single Event Upset
electrical simulation under Cadence electrical simulation under Cadence electrical simulation under Cadence electrical simulation under Cadence
based on MUSCA SEP based on MUSCA SEP based on MUSCA SEP based on MUSCA SEP 3333 current sources current sources current sources current sources
in 0,18/0,35 CIS processin 0,18/0,35 CIS processin 0,18/0,35 CIS processin 0,18/0,35 CIS process
H. BugnetH. BugnetH. BugnetH. Bugnet, C. Predine, F. Barbier (e2v)G. Hubert (ONERA)
CNES Workshop “Radiation Effects on Optoelectronics Detectors” November 26th 2014
Slide 2
2
OutlineOutlineOutlineOutline
• Introduction on radiation and Single EventsIntroduction on radiation and Single EventsIntroduction on radiation and Single EventsIntroduction on radiation and Single Events
•Current generation mechanisms and Soft Error in sequential electronics
•Presentation of the approach
•AND cell � SET study
•Register (DFF) � SEU study
•Conclusion and perspective
Slide 3
3
Radiation space environment (Esa slide, Radiation space environment (Esa slide, Radiation space environment (Esa slide, Radiation space environment (Esa slide, A. FernA. FernA. FernA. Fernáááándezndezndezndez----LeLeLeLeóóóónnnn))))
Introduction on radiation and Single Events
� Cumulative effects
� Dose effects � oxide thickness
�Vt shifts (reduced <0.35um)
� Noise & leakage � (Dark Current)
� Instantaneous effects,
� SEL Single Event Latchup
� can be destructive, power off req.
� SEU Single Event Upset
� SET Single Event Transient
� SEU + SET lead to Soft Error and SEFI
Slide 4
4
Introduction on radiation and Single EventsExample of SEE counter measures :
e2v CIS for MTG-FCI VisDA (prime TAS-F for ESA, EUMETSA T)
� Imager with analog outputs
� Specific Layout (DRC) to � SEE tolerance
� Archi. : Triple Modular Redundancy
� Heavy ions tests have shown :
� No Latch Up up to 67.7 MeV.cm2/mg
� No SEFI up to 67.7 MeV.cm2/mg
� Soft Error rate drastically reduced comparing to regular standard cells
� Complicated work to test and assess the SEE tolerance (requires monitoring chip under beam !)
� All results (fortunately very promising) come after the design phase…
� This talk aims to propose an alternative way to emulate heavy ions during design phase
Slide 5
5
OutlineOutlineOutlineOutline
• Introduction on radiation and Single Events
•Current generation mechanisms and Soft Error in Current generation mechanisms and Soft Error in Current generation mechanisms and Soft Error in Current generation mechanisms and Soft Error in sequential electronicssequential electronicssequential electronicssequential electronics
•Presentation of the approach
•AND cell � SET study
•Register (DFF) � SEU study
•Conclusion and perspective
Slide 6
6
Principle of SET generation : CMOS inverter casePrinciple of SET generation : CMOS inverter casePrinciple of SET generation : CMOS inverter casePrinciple of SET generation : CMOS inverter case
• Positive/Negative voltage pulse generated resp. on PMOS/NMOS drain
Current gen. mechanisms and SE in sequential electronics
no consequenceDrain PMOS @1 (ON)
0 interpreted as 1Drain PMOS @0 (OFF)
1
0 t
Ion strike on drain of a PMOS : P+/Nwell diffusion
vss
1 0
OFF
ON
Built in electric field
out
vdd
1
1
0
0
Positive pulse (V) on a 0
vss
e-h+
• Diffusions (drains and sources of MOS transistor) ���� separate pairs (built in field)• Ion strike on OFF transistor drains, only, can lead to dangerous transients
Ion strike on drain of a NMOS :N+ /Pwell diffusion
100
1
1
0
0
e- h+
ON
OFF
Negative pulse (V) on a 1
1
Built in electric field
1
out
1
1
0
vss
vdd
vss
1 interpreted as 0
no consequence
DrainNMOS @1 (OFF)
Drain NMOS @0 (ON)
1
0 t
• SET can be shaped in and transmitted by circuitry
Slide 7
7
Soft errors in sequential logicSoft errors in sequential logicSoft errors in sequential logicSoft errors in sequential logic
• SET can propagate in combinatorial logic…
• …and might (might not : timing/duration, amplitude) produce error
D
DFF
Q
Combinatorial
Logic
D
DFF
Q
Clock
Data1
Data2D
DFF
Q
Clock
Ion strike ���� SET
Out
Clock
! Soft Error (SET) !
• Soft errors originate from SET and SEU
• Ck (or Reset) should be treatedshould be treatedshould be treatedshould be treated, gravity high but assoc. circuitry area small (lower probability)
Current gen. mechanisms and SE in sequential electronics
Glitches on D Out levels
! Soft Error (SEU) !
Ion strike ���� SEU
Slide 8
8
OutlineOutlineOutlineOutline
• Introduction on radiation and Single Events
•Current generation mechanisms and Soft Error in sequential electronics
•Presentation of the approachPresentation of the approachPresentation of the approachPresentation of the approach
•AND cell � SET study
•Register (DFF) � SEU study
•Conclusion and perspectives
Slide 9
9
Methodology : Musca (current cMethodology : Musca (current cMethodology : Musca (current cMethodology : Musca (current calc.)alc.)alc.)alc.) + Cadence (electric+ Cadence (electric+ Cadence (electric+ Cadence (electrical simu.)al simu.)al simu.)al simu.)
Presentation of the approach
GDSII File
Scanned Area(around drains)
Current
sources
CadenceBatch of electrical simulation (Spectre)+ Processing
Impact pointsproducing SEU
MUSCA Scanned Area definitionHeavy ion strike Current sources generation
Process Deck :
Foundry, ITRS(LET, incidence angle…)
Ion characteristics
Slide 10
10
OutlineOutlineOutlineOutline
• Introduction on radiation and Single Events
•Current generation mechanisms and Soft Error in sequential electronics
•Presentation of the approach
•AND cell AND cell AND cell AND cell � SET studySET studySET studySET study
•Register (DFF) � SEU study
•Conclusion and perspectives
Slide 11
11
SET results on AND cellSET results on AND cellSET results on AND cellSET results on AND cell
0
5
10
15
20
0 2 4 6 8
Sé r ie1
• Electrical simulation :
• 3v3 standard cell loaded with 2 NAND
• Parasitic view of the cell simulation
• Static simulations (No input changes when ion strikes)
AND cell � SET study
out
Time (ns)
Voltage (V)
Threshold
SET for a 00
1
VOL
VIL
VOH
VIH
SET for a 1VDD
A
B out1 out2out
Negative/positive pulse :SET “greater” than threshold
Slide 12
12
• localization of ions impacts vs SET amplitude (V)
SET Number of glitches vs threshold for AND cellSET Number of glitches vs threshold for AND cellSET Number of glitches vs threshold for AND cellSET Number of glitches vs threshold for AND cell
AND cell � SET study
• Cumulative mapping for inputs (0,0) ; (0,1) ; (1,0) ; (1,1)
Slide 13
A=1
B=0
OUTA=1 B=0
SET duration histogram at the output of the 2nd NAND
0
5
10
15
20
25
30
35
40
40 120
200
280
360
440
520
600
680
760
840
920
1000
1080
Bin SET duration (ps)
Nu
mb
er o
f eve
nts
13
Inputs logic level influence on pulse durationInputs logic level influence on pulse durationInputs logic level influence on pulse durationInputs logic level influence on pulse duration(LET 60MeV.cm(LET 60MeV.cm(LET 60MeV.cm(LET 60MeV.cm2222/mg)/mg)/mg)/mg)
AND cell � SET study
BA=00 BA=01
BA=10 BA=11
Large SET only in this case
Width @ Vdd/2
SET duration histogram at the output of the 2nd NAND
0
5
10
15
20
25
30
40 120
200
280
360
440
520
600
680
760
840
920
1000
1080
Bin SET duration (ps)
Nu
mb
er o
f eve
nts
SET duration histogram at the output of the 2nd NAND
0
5
10
15
20
25
30
35
40
45
40 120
200
280
360
440
520
600
680
760
840
920
1000
1080
Bin SET duration (ps)
Nu
mb
er o
f eve
nts
SET duration histogram at the output of the 2nd NAND
0
2
4
6
8
10
12
40 120
200
280
360
440
520
600
680
760
840
920
1000
1080
Bin SET duration (ps)
Nu
mb
er o
f eve
nts
Slide 14
14
OutlineOutlineOutlineOutline
• Introduction on radiation and Single Events
•Current generation mechanisms and Soft Error in sequential electronics
•Presentation of the approach
•AND cell � SET study
•Register (DFF) Register (DFF) Register (DFF) Register (DFF) ���� SEU studySEU studySEU studySEU study
•Conclusion and perspectives
Slide 15
15
Presentation of the cellPresentation of the cellPresentation of the cellPresentation of the cell
• Symbol and principle schematic (ck is high), loaded for elec. simulations
out
rst_n
rst_n
out_intin
stg2 stg3
stg1 net091
Latch 1 Latch 2
ckn
ck
ck
ckn
Memory Write
in rstn outck
• Layout ����
stg1 stg2 stg3
ck
out1
outout2
Register (DFF) � SEU study
in
clk
out
rst_n
• Static simu. � data + clock unchanged during ion strike
Slide 16
16
• Area corrupted (SEU) is dependent of :
� clock state mem. state or opened write state
� value memorized (1 or 0)
• Ion strikes : pairs drift and separate in stg1 NMOS diffusion
� negative current
� negative SET + Feed Back
• Corruption of 1 ! (1 changed in a 0) : propagates to out
out
rst_n
rst_n
out_intin
stg2 stg3
stg1 net091
1→0
1
10→1
1→0
1→0
ion location
Latch 1 Latch 2
ckn
ck
ck
ckn
SEU in lacth1 (stg1) of the register when SEU in lacth1 (stg1) of the register when SEU in lacth1 (stg1) of the register when SEU in lacth1 (stg1) of the register when clock is Highclock is Highclock is Highclock is High
Register (DFF) � SEU study
Slide 17
17
current
stg1
stg2
out
time(ns)
(V)
(V)
(uA
)
Electrical curves when clock is highElectrical curves when clock is highElectrical curves when clock is highElectrical curves when clock is high
Register (DFF) � SEU study
out
rst_n
rst_nout_intin stg2 stg3
stg1net091
1→0
1
1
0→1
1→0ckn
ck
ck
ckn
1→0
SEU occurred !
Slide 18
18
Number of SEU versus low LETNumber of SEU versus low LETNumber of SEU versus low LETNumber of SEU versus low LET
• LET 10 MeV.cmLET 10 MeV.cmLET 10 MeV.cmLET 10 MeV.cm2222/mg/mg/mg/mg
• LET 20 MeV.cmLET 20 MeV.cmLET 20 MeV.cmLET 20 MeV.cm2222/mg/mg/mg/mg
Overlapping SEU Clk_High/Clk_Low
Overlapping SEU Clk_High/Clk_Low
Register (DFF) � SEU study
Only NMOS diff. sensitive !Only NMOS diff. sensitive !Only NMOS diff. sensitive !Only NMOS diff. sensitive !
0 to 11 to 0
1 to 0 (NMOS) 0 to 1 (NMOS)
Slide 19
19
Number of SEU versus high LETNumber of SEU versus high LETNumber of SEU versus high LETNumber of SEU versus high LET
• LET 30 MeV.cmLET 30 MeV.cmLET 30 MeV.cmLET 30 MeV.cm2222/mg/mg/mg/mg
1 to 0 0 to 1
• LET 60 MeV.cmLET 60 MeV.cmLET 60 MeV.cmLET 60 MeV.cm2222/mg/mg/mg/mg
1 to 0 0 to 1
Register (DFF) � SEU study
Slide 20
20
SEU cross section comparison :SEU cross section comparison :SEU cross section comparison :SEU cross section comparison :MuscaMuscaMuscaMusca & Electrical & Electrical & Electrical & Electrical SimuSimuSimuSimu. . . . vsvsvsvs MeasureMeasureMeasureMeasure
• Measurement on this register (BER on scan of 376 registers) to compare with simulation :
• Simulation Fits pretty well (except @ low LET)
�@ low LET 10000 ions/sec/cm2 (and 1MHz clock ) : physical calibration Musca to get absolute tool
� Scan area should be enlarged (underestimation of saturation cross section)
Register (DFF) � SEU study
SEU cross section vs LET for rad register
0,001
0,01
0,1
1
10
100
0 10 20 30 40 50 60 70 80
LET (MeV cm2/mg)
SE
U c
ross
sec
tio
n (
um
2)
Musca & electrical simu.
Measure
1 or 2 extra rows should be added
Slide 21
21
Increasing the Increasing the Increasing the Increasing the LETLETLETLET threshold to SEUthreshold to SEUthreshold to SEUthreshold to SEU
Register (DFF) � SEU study
out
rst_n
rst_n
out_intin stg2
stg1net091
ckn
ck
ck
ckn
1→0
• Increasing capacitance (+7fF)capacitance (+7fF)capacitance (+7fF)capacitance (+7fF) (netlist) on critical nets
� improve SEU th. but degradation in maximum speed…
stg3
• LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (without capacitorswithout capacitorswithout capacitorswithout capacitors))))
0 to 1
output output
1 to 0
• LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (LET 10 MeV.cm2/mg (with capacitorswith capacitorswith capacitorswith capacitors) : no more events) : no more events) : no more events) : no more events
Slide 22
22
Increasing the threshold to SEUIncreasing the threshold to SEUIncreasing the threshold to SEUIncreasing the threshold to SEU
Register (DFF) � SEU study
• Cross section comparisonsCross section comparisonsCross section comparisonsCross section comparisons
SEU cross section vs LET for rad register
0,001
0,010
0,100
1,000
10,000
0 10 20 30 40 50 60 70
LET (MeV cm2/mg)
SE
U c
ross
sec
tio
n (
um
2)
Musca & electrical simu. with cap. Musca & electrical simu.
• Threshold Threshold Threshold Threshold wwwwith capacitors above 10MeV.cmith capacitors above 10MeV.cmith capacitors above 10MeV.cmith capacitors above 10MeV.cm2222/mg with cap./mg with cap./mg with cap./mg with cap.
Slide 23
23
OutlineOutlineOutlineOutline
• Introduction on radiation and Single Events
•Current generation mechanisms and Soft Error in sequential electronics
•Presentation of the approach
•AND cell � SET study
•Register (DFF) � SEU study
•Conclusion and perspectivesConclusion and perspectivesConclusion and perspectivesConclusion and perspectives
Slide 24
24
Conclusion Conclusion Conclusion Conclusion …………
• ““““GoodGoodGoodGood”””” agreement agreement agreement agreement ���� SEU XSEU XSEU XSEU X----sections simu. vs measurementsections simu. vs measurementsections simu. vs measurementsections simu. vs measurement
• Sensitive areas can be identified Sensitive areas can be identified Sensitive areas can be identified Sensitive areas can be identified
� treatmenttreatmenttreatmenttreatment checked checked checked checked
� relative tool need calibration relative tool need calibration relative tool need calibration relative tool need calibration
• Better understanding of Better understanding of Better understanding of Better understanding of Soft Error mechanismsSoft Error mechanismsSoft Error mechanismsSoft Error mechanisms…………
• Predictive Chain for Soft Error caused by Heavy ions developed Predictive Chain for Soft Error caused by Heavy ions developed Predictive Chain for Soft Error caused by Heavy ions developed Predictive Chain for Soft Error caused by Heavy ions developed
through:through:through:through:
and collaborationand collaborationand collaborationand collaboration
Slide 25
25
………… and perspectivesand perspectivesand perspectivesand perspectives
• Enabling Enabling Enabling Enabling effective SETeffective SETeffective SETeffective SET----SEU radSEU radSEU radSEU rad----hardening validation hardening validation hardening validation hardening validation before Siliconbefore Siliconbefore Siliconbefore Silicon
���� VVVValidation of mitigation techniques at gate level alidation of mitigation techniques at gate level alidation of mitigation techniques at gate level alidation of mitigation techniques at gate level
���� Should be used at design start !Should be used at design start !Should be used at design start !Should be used at design start !
• ApproachApproachApproachApproach’’’’s flexibility enables s flexibility enables s flexibility enables s flexibility enables quantifying (roughly ) process changes quantifying (roughly ) process changes quantifying (roughly ) process changes quantifying (roughly ) process changes
���� EPI thickness (e. g. QE improvement) EPI thickness (e. g. QE improvement) EPI thickness (e. g. QE improvement) EPI thickness (e. g. QE improvement)
���� other CMOS processesother CMOS processesother CMOS processesother CMOS processes
• SEU/SET radSEU/SET radSEU/SET radSEU/SET rad----hard cells developmenthard cells developmenthard cells developmenthard cells development with this tool with this tool with this tool with this tool
���� silicon tests soonsilicon tests soonsilicon tests soonsilicon tests soon
• Benefit for future Benefit for future Benefit for future Benefit for future e2ve2ve2ve2v space products hardeningspace products hardeningspace products hardeningspace products hardening
���� e. ge. ge. ge. g. . . . charges transfer CMOS TDI charges transfer CMOS TDI charges transfer CMOS TDI charges transfer CMOS TDI ((((pixel performances silicon proven today)pixel performances silicon proven today)pixel performances silicon proven today)pixel performances silicon proven today)
Thank you for your attention !Thank you for your attention !Thank you for your attention !Thank you for your attention !