single phase on-line ups using mc9s12e128
TRANSCRIPT
HCS12Microcontrollers
freescale.com
Single Phase On-Line UPS Using MC9S12E128
Designer Reference Manual
DRM064Rev. 009/2004
Single Phase On-Line UPS Using MC9S12E128Designer Reference Manual
by: Ivan Feno, Pavel Grasblum and Petr SteklFreescale Semiconductor Czech System LaboratoriesRoznov pod Radhostem, Czech Republic
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
DateRevision
LevelDescription
PageNumber(s)
09/2004 0 Initial release N/A
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Contents
Chapter 1 Introduction
1.1 Application Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2 The UPS Topologies and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.2.2 Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.2.3 On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.3 MC9S12E128 Advantages and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 System Description
2.1 System Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3 UPS Control
3.1 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.1.1 Battery Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.1.2 Power Factor Correction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1.3 dc/dc Step-Up Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1.4 Output Inverter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.1.5 PI and PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.1.6 Phase-Locked Loop (PLL) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4 Hardware Design
4.1 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.2 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.2.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.2.2 Battery Charger Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.2.3 Flyback Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.2.4 Design of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.2.5 Voltage and Current Sensing, Current Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.2.6 Main Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.2.7 Battery Charger Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.3 Auxiliary Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.3.1 Auxiliary SMPS Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.4 dc/dc Step-Up Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4.1 dc/dc Converter Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4.2 dc/dc Converter Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.5 Power Factor Correction and Output Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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4.5.1 PFC Booster Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.5.2 PFC Booster Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.5.3 Output Inverter Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684.5.4 Output Inverter Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 5 Software Design
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2 Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2.1 Software Variables and Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2.2 Process PLL Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.3 Process RMS Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.4 Process Mains Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.5 Process Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.6 Process Sine Wave Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.7 Process Button Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.8 Process LED Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.9 Process Application State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.10 Process PFC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.2.11 Process Sine Wave Reference (PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.2.12 Process dc Bus Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.2.13 Process dc/dc Step-Up Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.2.14 Process Inverter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.2.15 Process Battery Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.3 Main Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.3.1 Initialization of Peripherals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.3.2 Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.3.3 Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.3.4 Interrupt Time Execution and MCU Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.4 Software Constant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.4.1 PI and PID Controller Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 6 Tests and Measurements
6.1 Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.2 Load Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.3.1 Overall Efficiency at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.3.2 Overall Efficiency at Non-linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.3.3 Output Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906.3.4 Output Voltage THD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916.3.5 Power Factor Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926.3.6 Response on Step Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926.3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Chapter 7 System Set-Up and Operation
7.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.1.1 Setting of Mains Line System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997.2 Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.2.1 Application Software Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.2.2 Application PC Master Software Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.2.3 Application Build. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017.2.4 Programming the MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027.3 Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027.3.1 On-line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027.3.2 Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037.3.3 Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix A. SchematicsA.1 Schematics of Power Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105A.2 Schematics of User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115A.3 Schematics of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117A.4 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119A.5 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123A.6 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix B. References
Appendix C. Glossary
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1-1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141-2 Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151-3 On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162-1 System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192-2 UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202-3 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202-4 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212-5 MC9S12E128 Controller Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212-6 Overall View of the UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223-1 Battery Charger Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263-2 PFC Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273-3 Hysteresis Control of Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283-4 Push-Pull Converter PWM Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283-5 dc/dc Step-Up Converter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293-6 Sine Wave Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303-7 Inverter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313-8 Simulated PID Controller Response on Input Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313-9 Quality Control of Non-Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323-10 Calculation of Phase Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344-1 System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354-2 UPS Power Stage Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364-3 Battery Charger Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384-4 Battery Charger Transformer Winding Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404-5 3-Stage Charging Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414-6 Auxiliary SMPSs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424-7 Isolated Flyback Converter for Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444-8 Flyback Power Transformer Layout of Windings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474-9 dc/dc Converter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484-10 dc/dc Converter Simulation Model Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494-11 Simulated Magnetizing Voltage and Magnetic Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514-12 Simulated Primary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534-13 Simulated Secondary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544-14 Simulated Drain-to-Source and Gate-to-Source MOSFETs Voltages. . . . . . . . . . . . . . . . . . 554-15 dc/dc Power Transformer Layout of Windings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564-16 Inverter MOSFET Power Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584-17 Rectifier Diode Voltage and Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594-18 Secondary Voltage and Rectified Current Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614-19 PFC Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624-20 PFC Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634-21 Output Inverter Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694-22 Inverter IGBT Gate Drive Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705-1 Main Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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5-2 Application State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775-3 Background Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795-4 Structure of PMF Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805-5 Structure of ATD Conversion Complete Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815-6 TIM0 CH4 Input Capture Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825-7 Structure of TIM0 CH5 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825-8 Structure of TIM0 CH6 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835-9 CPU Load of UPS Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846-1 Non-Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876-2 Overall Efficiency at Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886-3 Output Voltage and Current at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886-4 Overall Efficiency at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896-5 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896-6 Output Frequency in Synchronized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906-7 Output Frequency in Free-running Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906-8 Output Voltage and Current at Non-linear Load — Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . 916-9 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916-10 Power Factor Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926-11 Load Step from 20% to 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936-12 Load Step from 20% to 100% — Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936-13 Load Step from 100% to 20% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946-14 Load Step from 100% to 20% — Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947-1 UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987-2 UPS Input and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997-3 UPS Serial Ports and External Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997-4 Execute Make Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017-5 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037-6 UPS Project in FreeMaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047-7 Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067-8 Auxiliary Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077-9 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087-10 Control Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097-11 dc/dc Step-Up Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107-12 Analog Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117-13 PFC and Inverter IGBT Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127-14 PFC and Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137-15 PFC Current Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147-16 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Tables
2-1 On-Line UPS Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234-1 Battery Charger Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374-2 Input Design Parameters of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394-3 Required Parameters of Flyback Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404-4 Measured Values on the Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404-5 dc/dc Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474-6 dc/dc Transformer Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564-7 Digital PFC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614-8 PFC Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664-9 Design Parameters for Core P/N: T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664-10 dc-bus Capacitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684-11 Output Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684-12 MKP 338 4 X2 Capacitor Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714-13 Output Filter Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724-14 Design Parameters for Core P/N: T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725-1 Software Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755-2 Execution Time of Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845-3 Size of UPS Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846-1 Summary of Measured Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95A-1 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119A-2 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123A-3 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Single Phase On-Line UPS Using MC9S12E128
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Draft For Review - September 30, 2004
Tables
Single Phase On-Line UPS Using MC9S12E128
12 Freescale Semiconductor Internal Use Only Freescale Semiconductor
Draft For Review - September 30, 2004
Chapter 1 Introduction
1.1 Application Outline
This reference design describes the design of a single phase on-line uninterruptable power supply (UPS). UPSs are used to protect sensitive electrical equipment such as computers, workstations, servers, and other power-sensitive systems.
This reference design focuses on the digital control of key parts of the UPS system. It includes control of a power factor correction (PFC), a dc/dc step-up converter, a battery charger, and an output inverter. The dc/dc converter and the output inverter are fully digitally controlled. The PFC and the battery charger are implemented by a mixed approach, where an MCU controls the signals for PFC current and battery current demands. The digital control is based on Freescale Semiconductor’s MC9S12E128 microcontroller, which is intended for UPS applications.
The reference design incorporates both hardware and software parts of the system including hardware schematics.
1.2 UPS Topologies and Features
UPSs are divided into several categories according to their features, which come from the hardware topologies used. The three basic categories are:
• Passive standby UPS• Line-interactive UPS• On-line UPS
The category of the UPS defines the basic behaviors of the UPS, mainly the quality of the output voltage and the capability to eliminate different failures on the power line (power sags, surge, under voltage, over voltage, noise, frequency variation, and so on).
NOTEAlthough specific tools, suppliers, and methods are mentioned in this document, Freescale Semiconductor does not recommend or endorse any particular methodology, tool, or vendor.
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Introduction
1.2.1 Passive Standby UPS Topology
The common topology of the passive standby UPS is depicted in Figure 1-1.
Figure 1-1. Passive Standby UPS Topology
During normal operation, while the mains line (the power cord for the ac line) is available, the load is directly connected to the mains. The battery is charged by the charger, if necessary. If a power failure occurs, the switch switches to the opposite position, and the load is powered from the batteries. An inverter converts the battery dc voltage level to an ac mains level. The inverter generates a square wave output.
The advantage of passive standby topology is its low cost and high efficiency. The disadvantage is limited protection against power failures. Because the load is connected to the mains line through the filter only, the load is saved against short sags and surges.
DC
AC
~ =
+ -
DC
AC
~=
LINE FILTER
BATTERY
CHARGER
BATTERY
INVERTER
SWITCH
Normal operationBackup operation
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14 Freescale Semiconductor
UPS Topologies and Features
1.2.2 Line-Interactive UPS Topology
The improved topology, called line-interactive, is showed in Figure 1-2. The functionality of the line-interactive UPS is similar to passive standby topology. During normal operation, the load is connected directly to the mains line (the power cord to the ac line). Besides the input filter, there is a transformer with taps connected between the mains line and the load. The transformer usually has three taps. It ensures that the output voltage can be increased or decreased relative to the mains line by typically 10 to 15%.
The features of the line-interactive topology are similar to passive standby UPSs. The cost is still quite low and efficiency is high. The protection against power failures is improved by the possibility of keeping the output voltage within limits during under voltage or over voltage using the tap transformer.
Figure 1-2. Line-Interactive UPS Topology
DC
AC
~ =
+ -
DC
AC
~=
BATTERY
CHARGER
BATTERY
INVERTER
SWITCH
BYPASS
Normal operationBackup operation
LINE FILTER AVR
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Introduction
1.2.3 On-Line UPS Topology
Another topology, called on-line, is shown in Figure 1-3. This topology is also called double conversion. This name arises from the operating principle of an on-line UPS. When the UPS works in normal operation mode, while the mains line (or the power cord for the ac line) is available, the input voltage is rectified to the dc bus. The power factor correction ensures a sinusoidal current in phase with the input voltage. Then the UPS behaves as a resistive load. The output inverter converts the dc bus voltage back to a pure sinusoidal voltage.
The dc/dc converter is connected to the dc bus and converts the battery voltage to the dc bus level. The converter is activated during a power failure, and delivers the energy stored in the batteries to the dc bus. The dc bus voltage is again converted to a pure sine voltage.
A battery charger is used to charge the batteries. The charger can be powered from the mains line or from the dc bus.
Figure 1-3. On-Line UPS Topology
As can be seen, the complexity of the on-line UPS is much greater than the other two topologies described in this section. This means that the cost is higher, and the efficiency is lower due to double conversion.
However, the on-line UPS brings a much higher quality of delivered energy. The UPS generates a pure sine wave output with tight limits (typically ±2%). Besides the power failures eliminated by previous topologies, the on-line UPS avoids all the failures relating to frequency disturbance, such as frequency variation, harmonic distortion, line noise, or other shape distortions.
DC
AC
~ =
+ -
RECTIFIER PFC
BATTERY
CHARGER
BATTERY
DC-DC
CONVERTER
BYPASS
DC
=DC
=
DC
AC
~=
INVERTER
IN
OUT
Normal operationBackup operation
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MC9S12E128 Advantages and Features
1.3 MC9S12E128 Advantages and Features
The MC9S12E Family is a 112-/80-pin low-cost 16-bit MCU family very suitable for UPS, SMPS, and motor control applications. All members of the MC9S12E Family contain on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM, up to 16K bytes of RAM, three asynchronous serial communications interface modules (SCI), a serial peripheral interface (SPI), an inter-IC bus (IIC), three 4-channel 16-bit timer modules (TIM), a 6-channel 15-bit pulse-width modulator with fault protection module (PMF), a 6-channel 8-bit pulse width modulator (PWM), a 16-channel 10-bit analog-to-digital converter (ATD), and two 1-channel 8-bit digital-to-analog converters (DAC).
The basic features of the key peripherals dedicated for UPS applications are listed below:• Two 1-channel digital-to-analog converters (DAC) with 8-bit resolution• Analog-to-digital converter (ATD)
– 16-channel module with 10-bit resolution– External conversion trigger capability
• Three 4-channel timers (TIM)– Programmable input capture or output compare channels– Simple PWM mode– Counter modulo reset– External event counting– Gated time accumulation
• 6 PWM channels (PWM)– Programmable period and duty cycle– 8-bit 6-channel or 16-bit 3-channel– Separate control for each pulse width and duty cycle– Center-aligned or left-aligned outputs– Programmable clock select logic with a wide range of frequencies– Fast emergency shutdown input
• 6-channel pulse width modulator with fault protection (PMF)– Three independent 15-bit counters with synchronous mode– Complementary channel operation– Edge and center aligned PWM signals– Programmable dead time insertion– Integral reload rates from 1 to 16– Four fault protection shut down input pins– Three current sense input pins
The MC9S12E Family is powerful enough to control on-line and line-interactive UPS topologies. The passive standby topology can be controlled by a simpler MCU (from the HC08 Family).
Digital control has many advantages over separate analog control. Digital control is more flexible and allows easier tuning and changing of the UPS parameters. The intercommunication and interaction between all modules can implemented very efficiently because all modules are controlled by a single MCU.
The UPS control area is very wide. Each topology can be implemented by different circuits. The circuits may differ by different control requirements. This reference design shows one of the ways to implement digital control of an on-line UPS. The design mainly focuses on low cost. A low-cost 16-bit MCU is used with simple analog circuits. Using a mixed approach to battery charging can also be cheaper than full digital control, depending on chosen circuit topology.
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Introduction
Single Phase On-Line UPS Using MC9S12E128
18 Freescale Semiconductor
Chapter 2 System Description
2.1 System Concept
The system concept of the UPS is shown in Figure 2-1. Input consists of a rectifier (D1, D5) and a power factor correction (L1, D2, Q2). The power factor correction is controlled by a mixed approach. The dc-bus voltage control loop of PFC is controlled by the MCU. The output of the voltage controller defines the amplitude of the input current. Based on the required amplitude, the MCU generates a current reference signal. The current reference signal inputs to an external logic, which performs current controller working in hysteresis mode.
Figure 2-1. System Concept of UPS
Output is provided by an output inverter (Q1, Q3, D3, D4). The inverter converts the dc bus voltage back to a sinusoidal voltage using pulse-width modulation. The output inverter is fully controlled by the MCU and generates a pure sinusoidal waveform, free of any disturbance.
GND
OUT
GND
GND
OUT
IN
IN
GND
Filter
DC-DC Converter
DC-AC
Charger(FlybackConverter)
PFC
Q2
L1
Q1
Q3
+C2
L2
BT1
+ C1
Q4
D4
T1
L3
D5
D6
- +
D2KBU8J D3
D9
D8
D7
D1
Q5
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Freescale Semiconductor 19
System Description
The battery BT1 supplies a load during the backup mode. There are two 12-V batteries connected in serial. The battery voltage level 24-V is converted to ±390-V by the dc/dc step-up converter (Q4, Q5, D6-D9, L2, L3, and T1) using a push-pull topology fully controlled by the MCU.
The last part of a UPS is a battery charger. The battery charger maintains a fully charged battery. It uses a flyback topology controlled by a mixed approach. The flyback converter is controlled by a dedicated circuit and the required output voltage and current limit are set by the MCU. A dedicated circuit is used due to the lower cost compared to direct MCU control. Where a different battery charger topology is used, there is still enough MCU power to provide digital control.
Figure 2-2. UPS Power Stage
The UPS consists of four PCBs. Most components are situated on the power stage (see Figure 2-2). These are all the power components (diodes, transistors, inductors, capacitors, relays, and so on) and analog sensing circuits. The power stage is connected to the mains line (power cord for the ac line) through an input line filter, realized on the next PCB (Figure 2-3).
Figure 2-3. Input Filter
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System Concept
Figure 2-4 shows the user interface PCB. It includes two buttons (ON/OFF, BYPASS), four status LEDs (on-line, on-battery, bypass, and error), and six LEDs indicating output power or remaining battery capacity. There are also two serial RS232 ports, which can used for communication with the PC. The user interface provides an extension of the serial ports, which are implemented on the MC9S12E128 controller board.
Figure 2-4. User Interface
Figure 2-5. MC9S12E128 Controller Board
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System Description
Figure 2-5 shows a controller board for the MC9S12E128. The MC9S12E128 controller board is designed as a versatile development card for developing real-time software and hardware products to support a new generation of applications in UPS, servo and motor control, and many others.
The power of the 16-bit MC9S12E128, combined with Hall-effect/quadrature encoder interface, circuitry for automatic current profiling, over-current logic and over-voltage logic, and two isolated RS232 interfaces, makes the MC9S12E128 controller board ideal for developing and implementing many motor controlling algorithms, UPS, SMPS, as well as for learning the architecture and instruction set of the MC9S12E128 processor.
For more detailed information on the MC9S12E128 controller board, see [33].
An overall view of the assembled UPS is shown in Figure 2-6.
Figure 2-6. Overall View of the UPS Demo
2.2 System Specification
The UPS is designed to meet the features and parameters mentioned in Table 2-1.
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System Specification
Table 2-1. On-Line UPS Specification
Features Parameters
Architecture and Concept
Single Phase On-Line UPS using MC9S12E128
The UPS should be a regenerative 1-phase online type UPS with an automatic bypass feature when self check fails or is overloaded. The UPS is controlled manually from a front panel switch and from PC application software.
Functional Modes
On-line: If the input power is available, the UPS supplies a load and eliminates all possible defects on the line (online double conversion)
Battery: If the input power is not available, the UPS supplies a load from batteries. The backup time is given by battery capacity.
Bypass: The UPS directly connects its output and input, so the load is directly connected to the input line. The transition to this mode is set manually or automatically during overload or fault
Fault: If any fault is detected, the UPS signals fault, and if it is possible, the bypass is activated.
Input
45 to 65 Hz Operating Frequency Range
120 V (at 25% of load) — 280 V Operating Voltage Range for nominal mains 230 V
85 V to 135 V Operating Voltage Range for nominal mains 110 V
Power factor at input > 0.95 at nominal voltage
Conversion efficiency > 85% at nominal output power
Output
Number of output ports 6 in 2 segments
Output voltage selectable 110/120/200/220/230/240 V
Output power 725 – 750 VA at 230 V mains input voltage
Output power 325 – 350 VA at 110 V mains input voltage
Output waveform: true sine wave < 5% THD
Output frequency 50/60 Hz +/-0.3%
Output load regulation +/-2% (at steady state and linear load)
BatteryBattery 2*12 V
Battery 7.2 Ah
Communication2x RS232 port for communication with host PC with opto-isolation implemented on MC9S12E128 Controller Board
Visual Interface
4 LED indicators (on-line, battery, bypass, fault)
battery level gauge 6 levels (<5/20/40/60/80/100%)
load level gauge 6 levels (20/40/60/80/100/>100%)
Control Interface 2x buttons for user control (on/off, bypass)
Audible warning
Fault
Overload
low battery
lasts 5 minute
Implementation Coding in C language according to ANSI C standard for software running on MCUs
Coding in assembler if needed for software running on MCUs
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System Description
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24 Freescale Semiconductor
Chapter 3 UPS Control
3.1 Control Techniques
Generally, a UPS consists of several different converters. So the control techniques differ with the converter topologies used. The presented implementation of on-line UPS includes following topologies:
• Battery charger: flyback converter (mixed control)• PFC: boost converter (mixed control)• dc/dc step up converter: push-pull converter (full digital control)• Output inverter: half bridge inverter (full digital control)
3.1.1 Battery Charger Control
The battery charger uses a flyback converter topology. As described in Chapter 4 Hardware Design, the flyback converter is controlled by a dedicated circuit in order to reduce cost. The interface between the flyback converter and the MCU incorporates one digital output, which allows the setting of two output voltage levels, and an analog output, which sets the current limit.
Using a dedicated circuit greatly simplifies the control algorithm. The functionality of the converter itself is ensured by the dedicated circuit. Therefore, the battery charger software focuses on the charging algorithm, whose software block diagram is shown in Figure 3-1.
The algorithm reads the current flowing to the batteries. The current value is compared with the maximal and float thresholds. If the value is close to the maximal value, the battery charger state is set to bulk charging and the output voltage level is set to the higher value (PU7 set to logic 1). If the actual current value is between the maximal and float thresholds, the battery charger is considered to be in the absorption state. The output voltage is still kept at a high level. As soon as the current value reaches the float threshold, the battery charger goes to the float state, and the output voltage is set to the lower level.
The current limit is set during initialization, according to the number of batteries and their capacity.
The control algorithm is called every 50 ms.
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UPS Control
Figure 3-1. Battery Charger Algorithm
MC9S12E128
PU7
PWM10
AN02
AN03
Battery Voltage
Output Voltage
Battery current
Charging Current Limit
I = IBAT max
I > 0.05CBATI > 0.05CBATI > 0.05CBATI > 0.05CBAT
yes
yes
no
no
Bulk modeSet HV level
Float modeSet LV level
Absorption modeSet HV level
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Control Techniques
3.1.2 Power Factor Correction Control
The control algorithm of the PFC is depicted in Figure 3-2. The algorithm includes two control loops. The inner control loop maintains a sinusoidal input current. The outer loop controls the dc bus voltage. The result of the outer control loop is the desired amplitude of the input current.
Figure 3-2. PFC Control Algorithm
The current control loop is partially performed by an external circuit. This control technique is also called “indirect PFC control”. The external circuit compares the actual input current with a sine wave reference. If the actual current crosses the lower border of sine waveform, the PFC transistor is switched on. As soon as the input current reaches the upper border, the PFC transistor is switched off. The resulting input current can be seen in Figure 3-3. Maximal switching frequency (50 kHz) corresponds to the hysteresis defined by resistors R664 and R675. (see Figure 4-20)
MC9S12E128
PU8
DA0
AN08
AN07
FAULT0
FAULT1
IOC04
Top DC Bus Voltage
Top DC Overvoltage
Zero Cross
Bottom DC Bus Voltage
Bottom Overvoltage
SIN REFERENCE
PFC ENABLE
PI Controller
SINUS
GENERATION
PLL LOCK
UREQ +
-
F
I
L
T
E
R
+
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 27
UPS Control
Figure 3-3. Hysteresis Control of Input Current
The software part of the current loop generates the sine wave reference. The sine wave reference is synchronized to be in phase with the input voltage. The sine wave generator is calculated every 50 µs. The sine waveform is generated directly by the D/A converter within the range of the voltage reference.
The voltage control loop is fully implemented by software. The sensed dc bus voltage is compared with the required dc bus voltage, 390 V. The difference inputs to the PI controller. The PI controller output directly defines the amplitude of the input current. The PI controller constants were experimentally tuned to get an aperiodic responds to the input step. The constants are P = 100 and TI = 0.016 s. The voltage control loop is calculated every 1 ms.
The two hardware faults are immediately able to disable the PWM outputs in case of a dc bus over voltage. The digital output, PU8, enables/disables the external logic providing the current loop.
3.1.3 dc/dc Step-Up Converter Control
The dc/dc converter uses push-pull topology, which requires the PWM signals as shown in Figure 3-4. These signals can be generated by one pair of PMF outputs with the following configuration:
• even output is set to positive polarity• odd output is set to negative polarity• duty cycle of even output is set to X%• duty cycle of odd output is set to 100 - X%
where X is a value from 0 to 50% – dead time
The required PWM patterns are shown in Figure 3-4.
Figure 3-4. Push-Pull Converter PWM Patterns
SineReference
HysteresisLevels
Input current
PWM 4
PWM 3
Single Phase On-Line UPS Using MC9S12E128
28 Freescale Semiconductor
Control Techniques
The control algorithm is depicted in Figure 3-5. Both dc bus voltages pass the digital filter, and their sum is compared with the required value of the dc bus voltage. Based on the error, the PI controller sets the desired duty cycle of the switching transistors.
During mains line operation, the required value of the dc bus is set to 720 V (2 x 360 V). Because the dc bus is kept by the PFC at 780 V (2 x 390 V), the dc/dc converter is automatically switched off. In case of mains failure, the dc bus voltage will start to fall. As soon as the voltage reaches the value 720 V, the dc/dc converter is activated. At 720 V, there is still 20 V reserve in amplitude to generate a maximum output voltage of 240 V RMS. As soon as the operation from batteries is recognized, the required value of the dc bus voltage is increased back to 780 V.
The PI controller maintains the constant voltage on the dc bus independent of the load until the mains is restored or the battery is fully discharged. If the battery is discharged, the UPS output is deactivated and UPS stays in STANDBY ON BATTERY mode. After 1 minute, the UPS is switched off.
The PI controller constants were experimentally tuned in the same way as the PFC. The constants are P = 39 and TI = 0.0033 s. The control loop is calculated every 1 ms.
Figure 3-5. dc/dc Step-Up Converter Control Algorithm
MC9S12E128
PMF3
PMF4
AN08
AN07
FAULT0
FAULT1
Top DC Bus Voltage
Top DC Overvoltage
Bottom DC Bus Voltage
Bottom DC Overvoltage
Output Transistors
PI Controller
UREQ +
+
+
-
F
I
L
T
E
R
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 29
UPS Control
3.1.4 Output Inverter Control
The output inverter is implemented by two IGBT transistors in half bridge topology. The inverter is fully digitally controlled and generates a pure sine wave voltage.
The sine waveform is generated using the pulse-width modulation technique. The sine reference is stored in a look-up table. The table values are periodically taken from the table, and then multiplied by the required amplitude. The resulting value gives the duty cycle of the PWM output. The pointer to the table is incremented by a value, which corresponds to the desired output frequency. All values over one period give sinusoidal modulated square wave output (see Figure 3-6). If such a signal passes through a LC filter, the pure sine wave voltage is generated on the inverter output.
Figure 3-6. Sine Wave Modulation
The control algorithm can be seen in Figure 3-7. The main control loop comprises of the PID controller and a feed forward control technique. The required value entering the PID controller is generated by a sine wave generator, optionally synchronized with input voltage. The same value is added directly to the output of the PID controller. It is called the feed forward technique, and it improves the responds of control loop. The amplitude of the sine wave reference is corrected by RMS correction, which keeps the RMS value of the output voltage independent of any load. The RMS correction uses the PI controller. The PI constants were experimentally tuned, and set to P = 0 and TI = 0.00936.
The PID controller was tuned using simulation in MATLAB. The results of the simulation can be seen in Figure 3-8 and Figure 3-9, with P = 0.6, TI = 0, TD = 0.00071 s, and N = 31. The value N represents the filter level of D portion EQ 3-5.
The result of the PID controller, including feed forward, is scaled relative to actual dc bus voltage. Then the exact duty cycle is set to the PMF module.
+DCBUS
-DCBUS
Single Phase On-Line UPS Using MC9S12E128
30 Freescale Semiconductor
Control Techniques
Figure 3-7. Inverter Control Algorithm
Figure 3-8. Simulated PID Controller Response on Input Step
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 31
UPS Control
Figure 3-9. Quality Control of Non-Linear Load
3.1.5 PI and PID Controller
The PI controller in a continuous time domain is expressed by following equation:
(EQ 3-1)
Similarly, the PID controller can be expressed as:
(EQ 3-2)
In a Laplace domain it can be written as:
(EQ 3-3)
(EQ 3-4)
To improve the response of the PID controller to noisy signals, the derivative portion is often replaced by a derivative portion with filter:
(EQ 3-5)
For implementation of algorithms on MCU the equations EQ 3-3 and EQ 3-4 have to be expressed in discrete time domain like:
(EQ 3-6)
u t( ) K e t( ) 1TI----- e τ( ) τd
0
t
∫+=
u t( ) K e t( ) 1TI----- e τ( ) τd
0
t
∫ TDddt-----e t( )+ +=
u s( ) K e s( ) 1sTI--------e s( )+=
u s( ) K e s( ) 1sTI--------e s( ) sTDe s( )+ +=
sTD
sTD
1sTD
N---------+
-------------------≈
u kh( ) P kh( ) I kh( ) D kh( )+ +=
Single Phase On-Line UPS Using MC9S12E128
32 Freescale Semiconductor
Control Techniques
where
(EQ 3-7)
(EQ 3-8)
(EQ 3-9)
(EQ 3-10)
and
3.1.6 Phase-Locked Loop (PLL) Algorithm
The PLL algorithm provides synchronization with the mains line. This synchronization is necessary for the PFC algorithm and can be optionally used for the inverter output.
The algorithm consists of two parts:• Frequency lock• Phase lock
e(kh) = Input error in step kh
w(kh) = Desired value in step kh
m(kh) = Measured value in step kh
u(k) = Controller output in step kh
P(kh) = Proportional output portion in step kh
I(kh) = Integral output portion in step kh
D(kh) = Derivative output portion in step kh
TI = Integral time constant
T, h = Sampling time
K = Controller gain
t = Time
s = Laplace variable
N = Filter constant
P kh( ) K e kh( )⋅=
I kh( ) I kh h–( ) KhTI
-------e kh( )+=
D kh( )TD
TD Nh+---------------------D kh h–( )
KTDN
TD Nh+---------------------e kh h–( )–=
e kh( ) w kh( ) m kh( )–=
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 33
UPS Control
The PLL algorithm measures a period from last two zero crossing signals. Because calculation of the phase increment to the sine wave table requires a division instruction EQ 3-11, the phase over one-half period is calculated instead:
(EQ 3-11)
where
If phase increment just corresponds to the measured period we should get a phase of 180º. If there is some difference, the phase increment must be adjusted (see Figure 3-10). Based on the sign of the phase difference, the phase increment is incremented or decremented by the value which is equal to the phase difference multiplied by the PLL constant.
If the phase difference falls below some limit for last 20 periods, the PLL is locked to the line frequency and a frequency locked status bit is set.
Figure 3-10. Calculation of Phase Difference
Now the PLL is running with the same frequency as the mains line, but the phase is still different. As soon as the frequency status bit is set, the actual phase is adjusted to 0º or 180º according to the previous polarity of the input voltage. The polarity of the input voltage is sensed in the middle of each period.
T = period of sine wave algorithm (50 µs)
32767 = 180º in sine wave look up table
Period = measured period of main line voltage
Phase Increment 32767T
Period-----------------=
ZerocrossingSignal
ActualPhase
PhaseDifference
Actual PhaseIncrement
Actual Period
0º 180º
Single Phase On-Line UPS Using MC9S12E128
34 Freescale Semiconductor
Chapter 4 Hardware Design
4.1 System Configuration
The single phase on-line UPS reference design is 750 VA UPS representing an on-line topology. The UPS comprises four PCBs (power stage, user interface, input filter, and controller board). The power stage together with the MC9S12E128 controller board is shown in Figure 1-2
Figure 4-1. System Concept of UPS
The UPS reference design provides both a ready-to-use hardware and a ready-made software development platform for an on-line UPS, under 1000 VA output power, and controlled by a single 16-bit MCU.
The UPS power stage consists of several system blocks shown as:• Battery Charger• Auxiliary Power Supplies• Control Board Interface• dc/dc Step-Up Converter• PFC + Inverter
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 35
Hardware Design
Figure 4-2. UPS Power Stage Block Schematic
4.2 Battery Charger
4.2.1 Operational Description
The battery charger is intended for charging the UPS batteries and supplying all UPS control circuits. The battery charger provides a three-state charging algorithm fully controlled by the MCU. Its operating parameters are listed in Table 4-1.
+VBAT-VBAT
-VBAT+VBAT
GNDA
+5V_A
GNDA GND
GNDGNDA
+15V
GNDA
GND +5V_A+5V_D
+5V_REF
GND
+15V_PFC
-5V_BOT
GND_PFC
GND_BOT
GND_TOP-5V_TOP
+15V_BOT
+15V_TOP+15V
+5V_A+5V_D
+VBAT
L
N
PE
PFC+Inverter
V_D
CB
_BO
TV
_DC
B_T
OP
V_I
NI_
IN
I_O
UT
PFC
_ZC
TEM
P
V_O
UT_
BO
T+5
V_D
+5V
_AV
_OU
T_TO
P
+5V
_RE
F
+15V
FAU
LT1
GN
DA
GN
D
FAU
LT0
PWM_TOPPWM_BOT
+15V
_TO
PG
ND
_TO
P
+15V
_BO
T
-5V
_TO
P
GN
D_B
OT
GN
D_P
FC
-5V
_BO
T
+15V
_PFC
N
L1
RLY_IN
RLY_OUT2RLY_OUT1
OUT1OUT2
N_OUT
PE
FAN+FAN-
FAN_PWM
RLY_BYPASS
L2
DC
B_P
OS
DC
B_N
EG
UN
I-3 P
FC_E
N
DIV
1D
IV2
DA
0D
A1
J100J100
1 2
J101PSH02_02P
J101PSH02_02P
F100
2A/fast
F100
2A/fast
J109J109
12
J110
PSH02_02P
J110
PSH02_02P
1 32 4
F101
FUSE AUTO 40A
F101
FUSE AUTO 40A
Battery Charger
GNDAGND
+5V_A
N
IBAT_CONTROL
IBAT
/POWER_ON
VBAT
+VBAT-VBAT
HV_BAT_LEVEL
L
J103J103
Control Board Interface
GNDAGND+5V_D+5V_A
PWM10PWM12
TIM14TIM15TIM16TIM17
Faul
t0Fa
ult1
AD2
AD4
AD6
AD1
AD3
AD5
UNI-3 DCBI
UNI-3_PWM2UNI-3_PWM3UNI-3_PWM4UNI-3_PWM5
UNI-3 DCBV
UNI-3 PHAIS
+15V
UNI-3 PHCISUNI-3 PFC_EN
UNI-3 PFC_ZC
UNI-3 SERIAL
UNI-3 BEMFZCAUNI-3 BEMFZCCUNI-3 BEMFZCB
DA0DA1
12
J111
PSH02_02P
J111
PSH02_02P
MH100
PE CONNECTION
MH100
PE CONNECTION
J102J102
DC-DC Step Up
GNDGNDA
+VBAT DCB_NEGDCB_POS
PWM5PWM4
-VBAT
F102
6.3A/fast
F102
6.3A/fast
Auxiliary Power Supplies
GN
DA
+5V
_D+5
V_A
GN
D
POWER_EN/POWER_EN
+15V
-5V
_TO
P
GN
D_B
OT
GN
D_P
FC
-5V
_BO
T
GN
D_T
OP
+15V
_BO
T
+15V
_PFC
+15V
_TO
P
+5V
_RE
F
+VBAT
J107J107
J104J104
J105J105
J108J108
J106J106
Single Phase On-Line UPS Using MC9S12E128
36 Freescale Semiconductor
Battery Charger
NOTEThe output values are set to the values recommended by the battery manufacturer. The current limits can be set to any value by SW.
4.2.2 Battery Charger Topology
The battery charger uses a flyback topology, frequently used for its simplicity for output power below 100 W. The charger consists of a flyback converter, battery voltage and current sensing, current limitation, and mains line voltage detection. The schematic of the battery charger is shown in Figure 4-3.The flyback converter uses the dedicated circuit TOP249 for control, which incorporates a MOSFET transistor and control circuit in one package. Using this dedicated circuit allows connection of the control signals to the secondary side of the flyback converter without galvanic isolation. The second advantage of the solution is that UPS power is independent of MCU control, and the UPS is able to run without batteries.
Table 4-1. Battery Charger Parameters
Input voltage 80 to 280 V / 50 to 60 Hz
Output voltageHigh voltage levelLow voltage level
29.4 V27.4 V
Output currentMax. value
Absorption - float threshold1.8 A0.36 A
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 37
/POWER_ON
VBAT
+VBAT
-VBAT
HV_BAT_LEVEL
GND
GND
GNDA
27.4V @ Q4 OFF
29.4V @ Q4 ON
5.05V @ 39V
/100V
R3051k8
R30439k
1
D
G
SQ302MMBF0201NLT1
R3092k4
R3105K6
R307620
R328
68K
R312200
TP300
Vbat
R33010k
C315
100n
R30324k
Figure 4-3. Battery Charger Schematics
IBAT2
LINE_OK
GND_TR
IBAT1
LINE_OK
IBAT1 IBAT2
N
IBAT
L
IBAT_CONTROL
GND
+5V_A
GND
GND
GND_CH
GND_CH
GND_CH
GND
GND_TR
GND
4.875V @ 2.34A
R322
220
L301
47uH
R3291K
R3191k6
D303P6KE200
R31133k
-+
D302B250R
C313
100nF
+
C302
220uF/450V
C301
4.7nF
R326
3k9
ISO300SFH615A-2
1
23
4
+
C304
220uF/50V
C300
220n
R327
560
sense
sense
R3000.1
+
C306
100u/50
R3241k
R3157.5k
U302TL431ACD
61
8R318
100k
D
G
S
Q301MMBF0201NLT
R3211k6
C310
470nF
T300
TR02/MC145
1
7
6
13
5
9
R331100
R3021M
C314
N/P
C309
470nF
D309
5V1
R31327R
C312
10nF/100V
C308
100nF
D300
1N4148
Q300
BC847
D304
1N4148
R3231k
R316220
D308
BAV103
+C30747uF/10V
R31733K
R3061M
+
- U301BMC33502
5
67
C303
100nF
CONTROL
L
C
XF
U300
TOP249Y4
7 2
5 3
1
R314
100
D305BYV26C
+
C305
220uF/50V
D307
BAV103
R325
33K
R30168k
C311
470nF
C316
100n
R320
100K
D301BYW29E-200
R3083K6
L300
47uH
+
-U301AMC33502
3
21
84
Battery Charger
4.2.3 Flyback Converter Operation
The flyback converter consists of the transformer T300, the MOSFET transistor U300 include control circuit and the feedback circuit (R303, R305, R309, R312, Q301, ISO300, and U302).
When the MOSFET transistor (U300) is switched on, the magnetic field energy is accumulated in the magnetic core of the transformer T300. During this time the output diodes (D301, D304) are reverse biased. As soon as the transistor is switched off, the accumulated magnetic field energy is released through the forward biased output diodes (D301, D304) to the output capacitors (C304, C305), and through the output filter (L300, L301, C306) to the load.
The output voltage is sensed by the divider (R303, R305, R309, R312). The voltage from the divider is compared with the internal reference of U302. The U302 creates the control signal—the current flowing through the opto coupler (ISO300)—which galvanically isolates the primary and secondary side of the flyback converter.
The control signal is connected to the control pin of the control circuit (U300). According to the control signal, the duty cycle of the MOSFET transistor (U300) is set. The MOSFET transistor is switched with a fixed frequency of 66 kHz.
The resistor R312 can be shorted by the transistor Q301. This allows setting the output voltage to either 29.4 or 27.4 V by the MCU.
4.2.4 Design of Flyback Converter
The design of flyback converter using TOP249 is described in detail in [10], [11] and [12]. The following input parameters were considered during the converter design:
The calculated parameters of the flyback transformer are specified in Table 4-3. The measured values on the manufactured sample are listed in Table 4-4. To decrease leakage inductance, the interleaved winding layout is used for the primary winding. The complete transformer winding layout is shown in Figure 4-4.
Table 4-2. Input Design Parameters of Flyback Converter
Input voltage 80 to 280 V / 50 to 60 Hz
Max. output voltage 29.4 V
Max. output current 1.8 A
Switching frequency 66 kHz
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 39
Hardware Design
Figure 4-4. Battery Charger Transformer Winding Layout
Table 4-3. Required Parameters of Flyback Transformer
Magnetizing inductance referred to the primary 328 mH + 3 0 – 20%
Magnetizing inductance referred to the secondary 31µH + 30 – 20%
Total leakage inductance referred to the primary <3.5 µH
Primary dc resistance <0.1 Ω
Secondary dc resistance <0.001Ω
Test Voltage primary-to-secondary 2.5k V ac
Table 4-4. Measured Values on the Sample
Pin #L [µH]
@1kHz, 1VL [µH]
@100kHz, 1VESR [Ohm]
@100kHz, 1VDCR [Ohm]
L [µH] @100kHz, 1Vpin # 9 and 13 shorted
1-6 331.2 330.5 2.142 0.095 2.88
5-7 5.2 5.22 0.061 0.018 -
9-13 29.8 29.74 0.194 0.0005 -
L4
L3
L2L1
1 7
814
12T Cu 3x0.56mm
5T Cu 2x0.315mm2.5kV insulation layer
2.5kV insulation layer
2.5kV insulation layer
2.5kV insulation layer
20T Cu 4x0.315mm
20T Cu 4x0.315mm
L1
L2
L3
L4
Core
Coil formerYoke
B66358-G-X187
B66359-J1014-T1B66359-A2000
B66358-G500-X1871pcs
1pcs2pcs
1pcsETD29/16/10 N87ETD29/16/10 N87
(EPCOS components)
Single Phase On-Line UPS Using MC9S12E128
40 Freescale Semiconductor
Battery Charger
4.2.5 Voltage and Current Sensing, Current Limitation
The battery voltage is sensed by the divider (R304, R307, and R310). The divider scales the maximum measurable battery voltage of 39 V to the A/D converter range of 5 V. The battery current is sensed as the voltage drops on resistor R300. The voltage drop is amplified by U301B to get 5 V at 2.4 A.
The current limitation is provided by U301A. The U301A compares the actual battery current with the limit, which is set by the MCU. The MCU generates a PWM signal, which is filtered to the analog value.
4.2.6 Main Line Detection
The mains line detection ensures that the UPS is internally switched on (STANDBY ON LINE state) if the mains line is available. The detection circuit detects the functionality of the flyback converter, and if the mains line is detected, the power supplies are switched on. The detection circuit consists of rectified diodes D307, D308, and transistor Q302.
4.2.7 Battery Charger Algorithm
There are many algorithms (constant voltage, constant current, two stage, three stage, etc.), that can be used for charging lead acid batteries. The algorithms differ by the complexity of battery charger implementation and by influence on the battery life.
Because the battery charger is controlled by the MCU, any battery charger algorithm can be implemented. The UPS reference design uses the three stage charging algorithm (see Figure 4-5).
Figure 4-5. 3-Stage Charging Algorithm
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 41
Hardware Design
As the name of algorithm suggests, charging consists of three stages. The charging starts with the current limit 0.25 of battery capacity. The battery charger works in current mode until the battery voltage reaches the high level voltage (2.45 V/cell). This stage is called bulk charging. As soon as the battery voltage reaches the high level, the current starts to fall, and the absorption stage begins. Once the battery current falls under 0.05 of battery capacity, the battery charge voltage is set to the low level (2.28 V/cell). The last stage is called the float stage.
NOTEThe voltage levels and current thresholds come from the battery manufacturer. The values may also vary with the temperature if temperature measurement is implemented.
4.3 Auxiliary Power Supplies
Signal circuits, control circuits, digital circuits, and driving circuits are supplied by auxiliary SMPSs (Figure 4-6). Since the drive circuits have to be galvanically isolated from each other, a small isolated flyback converter (Figure 4-7) is used to generate separate voltage sources for all power semiconductor drivers.
Figure 4-6. Auxiliary SMPSs
/POWER_EN
+VBAT
POWER_EN
GND GND GNDGND
+5V_D
GNDA
+5V_A
GNDGND
GNDA
+15V
GNDGND GNDGNDGND
+15V
GNDA
+5V_REF
GND
L202
470uH
U203MC78L05ACP
VIN3
VO1
GN
D2
TP207
+5V_A
U202LM2575-5
1
2
3
4
5
R2142.4k
12
TP208
Vref
D211KA3528LSGT
R2161.8K
12
TP204
+5V_D
D2101N5819
C200100nF
R200510
12
L203
680uH
L200
10uH
R21233k
TP200
+15V
R213
100
C221100nF
+
C21822uF/50V
U200LM2575-15
1
2
3
4
5
L205
10uH
D
G
SQ200MMBF0201NLT1
+
C22022u/20V
+
C21622uF/50V
D214KA3528LSGT
+
C217220uF/10V
+
C21922u/20V
R21520K
12
+
C215220uF/10V
D2131N5819
Single Phase On-Line UPS Using MC9S12E128
42 Freescale Semiconductor
Auxiliary Power Supplies
Supply voltages for the microcontroller and other digital circuits (+5V_D) are generated by U202. U200 is used to stabilize +15V for the flyback converter, relays, dc/dc MOSFETs drivers, and cooling fans and it is used as a down-converter for U203 in order to lower the power loss dissipated by U203. The IC supplies 5 V for op amps, comparators, and the heatsink temperature sensor. The output voltage is further filtered and used as a reference for the signal and control circuits. In order to switch-on and switch-off all the control and signal circuits, U200 and U202 are controllable by POWER_EN and /POWER_EN signals. POWER_EN signal is driven by the microcontroller to control the switch-off process. /POWER_EN signal is grounded when the “ON” button is depressed. All the power supplies are put into an operational state, the micro starts to execute the program, and the POWER_EN signal is then put into the active state to hold the supplies operational even when the button is released.
Figure 4-7 shows the isolated flyback converter schematic that provides the inverter and PFC drivers with a power supply. MOSFET Q201 is driven by UC3843 in a classic current-mode configuration without the feedback loop. The supply is designed to deliver constant power to the output while access power is dissipated in zener diodes D202-D203, D206-D207, and D209 in case of drivers-in-standby. Respective zener diodes are used specifically to split the secondary voltage to 5-V and 15-V levels.
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 43
-5V_BOT
+15V_TOP
+15V_PFC
GND_PFC
-5V_TOP
D_PFC
GND_TOP
+15V_BOT
GND_BOT TP212-5V_BOT
TP201+15V_TOP
D202
BZV55/15V
D206
BZV55/15V
TP213GND_PFC
+ C210100uF/10V
+ C202220uF/25V
TP202
+15V_BOT
D207BZV55/5V1
+C214220uF/25V
TP209GND_TOP
+ C207220uF/25V
TP210-5V_TOP
D209
BZV55/15V
8
D203
BZV55/5V1
R205
220
+C203100uF/10V
TP211GND_BOT
TP203+15V_PFC
Figure 4-7. Isolated Flyback Converter for Drivers
GN
GND GND GNDGND GNDGND GND
GND
+15V
6z.
8z.5z.
8z.
R209
1k
D204
MMBD914LT1
G
S
D D1
Q201NTF3055 C208
100pF
C213
100pF
R207
33
C204
47nF
R203
15k
R201
220D201
LL4448
T1
TR01/MC145
1
2
12
11
8
7
6
5
R2088.2k
R204220
+ C206330uF
12
D208
LL4448
R211
220
C205
100pF
C201
100pF
C211100pF
C212100pF
R202
15k
R2101.8
L201
330u
D205
LL444
R2068.2k
C209
100nF
U201
UC3843
COMP1
RT/CT4
GND5
ISENSE3
VREF8
VFB2
OUT6
VCC7
Auxiliary Power Supplies
4.3.1 Auxiliary SMPS Design Considerations
Auxiliary SMPS design (Figure 4-6) follows producer general considerations for LM2575 and 78L05 switched and linear regulators.
Because the isolated flyback converter is based on a standard UC384X IC, the design is focused on transformer design. The transformer is used as an energy reservoir. During the switch-on the energy is accumulated, and during the switch off the energy is delivered to the output capacitor and the load.
Respective output voltages are 2 x 20-V for HCPL315J output inverter driver - generated by L2 and L3 (+15 and –5 V are good driving margins in 800-V application), and 15-V for HCPL3150 PFC driver - generated by L4 (single supply 15 V is sufficient for 400-V application). First, the output power is defined. When driver circuits with HCPL315J and HCPL3150 drivers are considered, a value of 1.2 W is obtained. When efficiency is considered, a value of 2 W is obtained. For such power, a switching frequency 300 kHz is chosen. Let’s consider a 0.5 maximum duty. It means that during half of the switching period, all energy for the whole cycle must be accumulated in the transformer.
The average necessary input charge is given by EQ 4-1. When we consider the triangular shape of the transformer primary current, we get EQ 4-2 for the charge taken by the transformer.
(EQ 4-1)
(EQ 4-2)
Because the voltage is equal, the equality of these charges also provides equal energies. When we compare both equations, we get
(EQ 4-3)
Rearranging EQ 4-3 we get EQ 4-4 for the peak primary current:
(EQ 4-4)
The peak secondary current for a 20-V output is calculated using EQ 4-6 (all the output power is considered), and the secondary winding inductance L2 is then given by EQ 4-7.
(EQ 4-5)
(EQ 4-6)
(EQ 4-7)
Q IAV T⋅PIN
VIN
--------- T⋅= =
Q i td∫tON IP⋅
2-----------------= =
PIN
VIN
--------- T⋅tON I1P⋅
2-------------------=
IPP 2PIN
VIN
--------- TtON
--------⋅ ⋅ 2215------ 3.3µ
1.5µ-----------⋅ ⋅ 586mA= = =
L1
VIN
di---------dt
150.586------------- 1.5µ⋅ 38µH= = =
I1P 2POUT
VOUT
------------- TtOFF
----------⋅ ⋅ 21.620------- 3.3µ
1.8µ-----------⋅ ⋅ 293mA= = =
L2
VOUT
di-------------dt
200.293------------- 1.8µ⋅ 123µH= = =
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 45
Hardware Design
Let’s choose a RM8 core made from N97 ferrite material, with Ae = 64mm2 and AL = 3300 nH. Respective winding turns are as follows:
(EQ 4-8)
(EQ 4-9)
Therefore, N1 primary to N2 secondary ratio is given as follows:
(EQ 4-10)
For supplying the PFC driver, 15-V supply voltage is necessary and the turns ratio between both secondaries is used to calculate the number of turns for the PFC driver.
(EQ 4-11)
Rounding the number up or down would cause large unbalanced secondary voltages. Secondary turns are then scaled to obtain appropriate secondary-to-secondary ratio. Afterwards, primary turns are also altered. In this case, N2 = 8t gives exact value of N4 = 6t as follows:
(EQ 4-12)
Now, the primary turns are scaled to maintain primary-to-secondary ratio:
(EQ 4-13)
To maintain a discontinued conduction mode, the switching frequency has to be also altered to the value of 200 kHz. And the maximum flux has to be checked - simulation shows flux of amplitude 160 mT. Figure 4-8 shows the layout of the windings on the transformer bobbin.
N1LP
AL
------- 38µ3300n--------------- 3.4 4t≈= = =
N2LS
AL
------- 123µ3300n--------------- 6.1 6t≈= = =
pN1
N2
------ 46--- 0.667= = =
N41520------ N2⋅ 15
20------ 6⋅ 4.5t= = =
N41520------ N2⋅ 15
20------ 8⋅ 6t= = =
N1 p N2⋅ 0.667 8⋅ 5.34 5t≈= = =
Single Phase On-Line UPS Using MC9S12E128
46 Freescale Semiconductor
dc/dc Step-Up Converter
Figure 4-8. Flyback Power Transformer Layout of Windings
4.4 dc/dc Step-Up Converter
4.4.1 dc/dc Converter Operational Description
A dc/dc converter is intended for dc bus supply when the UPS run from batteries. Parameter specifications are listed in Table 4-5. The converter transforms the battery voltage of 24 V to a dc bus voltage of +400 V, –400 V. Low-cost considerations led to push-pull topology as shown in Figure 4-9. The circuit consists of a push-pull inverter (Q500-Q503), power transformer T500, bridge rectifier (D500, D502, D504, D505) and filter L501, L502. The rectifier directly supplies the dc bus voltage +400,–400V.
Table 4-5. dc/dc Converter Specifications
Parameter Value
Input voltage nominal 24 V
Input voltage minimal 21 V
Input voltage maximal 30 V
Output voltage nominal +390 V -390 V
Output voltage minimal +350 V -350 V
Output power nominal 580 W
Output current nominal 0.74 A
Input current nominal 27 A
Switching frequency 50 kHz
L1
L3
L4
L2
1
12
6
7
2.5kV insulation layer
2.5kV insulation layer
2.5kV insulation layer
2.5kV insulation layer5T Cu 0.25mm
8T Cu 0.25mm
8T Cu 0.25mm
6T Cu 0.25mm
L1
L2
L3
L4
CoreCoil formerClamp
B65811-J-R97B65812-C1512-T1B65812-A2203
1set1pcs2pcs
RM8 N97
(EPCOS components)
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 47
DCB_NEG
DCB_POS
PWM5
GND_BAT
GND_BAT
GND_BAT
R50910k
12
TP502PWM_52
1
4
Figure 4-9. dc/dc Converter Schematic
-OUT
+OUT
+Bat+VBAT
PWM4
-VBAT
GND_BAT
GND_BAT
GND_BAT
GND_BAT
+15V
GND_BAT
GND_BAT
GND
+15V
GND_BAT
GND_BAT
GND_BAT
D500
FFPF05U120STU
R500
10
1 2
OutBInB
GND
InA
NC NC
OutA
VCCU500 MC33152D
2
3
5
6
7
81
4
D
G
S
Q500NTP45N06
+C504
680u/50V
12
+C512
680u/50V
12 R502
1k/5W1 2
C50122n/400V
1 2
L500330u
C500100n
L501
650u/1A
+
C50947uF
1 2
R503100R/1W
1 2
+C513
680u/50V
12
R506
10
1 2
D504
FFPF05U120STU
+C505
680u/50V
12
L503
330u
D502FFPF05U120STU
R504100R/1W
12
D
G
S
Q502NTP45N06
R5011k/5W
1 2
R507
10
1 2R50810k
12
C511100n
+C502
680u/50V
12
D503
MUR180
D505
FFPF05U120STU
C50622n/400V
1 2
+C503
680u/50V
12
TP501PWM_4
L502
650u/1A
OutB InB
GND
InA
NCNC
OutA
VCCU501 MC33152D
3
5
6
7
8
+
C51047uF
1 2
D501
MUR180
R505
10
1 2
D
G
S
Q503NTP45N06
T500TR03/MC145
1
4 6
10
13
15
9
18
C5081n
12
C507
1n12
D
G
S
Q501NTP45N06
fier Snubbers
DC Bus
0
2
L13
20n
1
2
/ON
2
C7
22n
R5
50m
R19
1000L14
20n
1
2
R8
0.3
C8
22n
V5
390
V4
390
R21
1000
R9
0.3
R28524meg
R6
50m
R29524meg
C12
10n
The converter performance and features are analyzed by simulation with the model shown in Figure 4-10.
Figure 4-10. dc/dc Converter Simulation Model Schematic
2u2u
80m
Power Transformer Model
Rectifier Model
Chokes and Recti
Inverter Model
Current Sensing
0
0
0
0
S
V2
Implementation = 1
L16
560u
1
D6
D1N4149
D8
mur2100e
R18
4700
R15m
C115p
C910p
L9
20n
1
2
R13
20
R22
2kK K1
COUPLING = 1K_Linear
L2
30.8u
1 2
R15
100
L8
10u
1 2
D10
D1N4149
D3
mur2100e/ON
L12
20n
1
2
K K2
COUPLING = 1K_Linear
C5
10p
L17
560u
1
R25m
C1010p
C3
10p
R23
2k
R25
3
R720m
M1
NTP45N06
M4
NTP45N06
R3
0.5
D11
D1N4149
M3
NTP45N06S
V3
Implementation = 2R10
20
M2
NTP45N06
R14
100
D1
mur2100e/ON
R20
4700
L3
26.7n
1
2
L21
2n
1
2
L10
20n
1
2
L5
9.98m
1
2
R16
4700
V1
23.2
L15
15n
1
2
L20
1.6m
1 2
R4
0.5R17
4700
D4
mur2100e/ON
L18
2n
1
2
R11
20
D12D1N4149
R27
220
D7
mur2100e/ON
L4
26.7n
1
2
L6
9.98m
1
2
C1
1n
L19
80u
1
2
R2422
D2
mur2100e/ON
R12
20
L11
20n
1
2
C410p
C610p
L1
30.8u
1 2
L7
10u
1 2
C2
1n
D9
D1N4149R26
1k
Hardware Design
The inverter is supplied by a set of a low-ESR capacitors, C502-C505 and C512-C513, to lower the battery bus ripple current and hence the EMI signature of the converter input. Inverter MOSFETs Q500-Q503 are driven by MC33152 drivers. MOSFETs drain voltage ringing is damped by RC cells R504-C507 and R503-C508. Because of the voltage source character of the inverter, the rectifier has to be a current type, which is why smoothing chokes L501 and L502 are used. Over voltage spikes across the rectifier diodes, due to the diodes reverse-recovery and transformer leakage, are clamped by RCD snubbers consisting of a R501- C501- D501 for the positive side, and R502 - C506 - D503 for the negative side.
4.4.2 dc/dc Converter Design Considerations
4.4.2.1 Power Transformer
The first task in power transformer design is to choose an appropriate transformer core. Based on manufacturer power-handling-capability core tables the core size is selected. Subsequently, the maximum core flux density travel ∆B must be determined from the core manufacturer data sheet, and then an approximate number of turns can be calculated. Since the number of turns is usually an integer, the number is rounded and the real flux density travel is calculated. If ∆B is below a maximum limit with respect to the switching frequency (core material dependent), winding turns and the cross-sectional areas are calculated for all respective windings.
For 580W output, an ETD44 core is selected. Now, the integral of the Faraday induction law EQ 4-14 gives the relation for the magnetic charge put into the core EQ 4-15:
(EQ 4-14)
where
(EQ 4-15)
where
ui = induced voltage
ψ = linkage flux in the core
N = number of turns
Φ = flux in the core
Β = flux density in the core
∆Β = flux density travel
S = core cross-sectional area
uidψdt------- N
dφdt------ N S
dBdt-------⋅===
ui td∫ N S ∆B⋅ ⋅=
Single Phase On-Line UPS Using MC9S12E128
50 Freescale Semiconductor
dc/dc Step-Up Converter
Initially, the magnetic charge has to be calculated. Since the induced voltage during an active part of the converter operational cycle is constant and it equals the input voltage, the magnetic charge in the core is given by EQ 4-16.
(EQ 4-16)
where
(EQ 4-17)
Simulation results can also be used to obtain the magnetic charge. Figure 4-11 shows simulated magnetizing voltage and magnetic charge. Magnetic charge is obtained by the time integral of the magnetizing voltage. Peak-to-peak reading of the magnetic charge is 218 µV.
Rearranging EQ 4-15, the number of primary turns can be calculated:
(EQ 4-18)
Figure 4-11. Simulated Magnetizing Voltage and Magnetic Charge
VIN = input voltage
δ = switching duty cycle
T = switching period (f = 50kHz)
ui∫ td V= IN δ⋅ T⋅
ui td∫ 24 0.45 206–×10 216 µVs=⋅ ⋅=
N1
ui td∫S ∆B⋅--------------- 216
6–×10
1736–×10 0.4⋅
----------------------------------- 3.12 t===
Time
15us 20us 25us 30us 35us 40us 45us1 V(L1:1,L1:2) 2 S(V(L1:1,L1:2))
-40V
-20V
0V
20V
40V1
-300u
-200u
-100u
0
100u2
>>
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 51
Hardware Design
Let’s choose 3 turns. However, the flux density travel ∆B has to be checked:
(EQ 4-19)
From EPCOS Siferit N97 specification (FAL0625-W @60°C), the core power loss is 10 W, indicating a good core utilization. However, forced convection should be considered. The negative loss temperature coefficient of the N97 material is advantageous since it contributes to a temperature stability of the core (FAL0624-N).
Now, the number of turns of the secondaries can be calculated. For primary to secondary ratio and a forward type of converter, equation EQ 4-20 is valid:
(EQ 4-20)
For efficiency η = 0.93 and maximum duty δ(MAX) = 0.98, EQ 4-20 yields
(EQ 4-21)
Primary to secondary ratio is rounded to 18, and the secondary winding number of turns yields
(EQ 4-22)
Once the winding turns are determined, the cross sectional area of a winding can be calculated. For the ETD44 core, winding current density can be selected in the range 5-10A/mm2. Let J = 8A/mm2. Primary cross-sectional area is given by EQ 4-23
(EQ 4-23)
where
Ι1 = nominal primary winding current obtained by integrating the square of the simulated winding current (Figure 4-12).
∆Bui td∫
S N1⋅-------------- 216
6–×10
173 6–×10 3⋅------------------------------ 416 mT===
pVOUT
VIN η δMAX⋅ ⋅-----------------------------------=
pVOUT
VIN η δMAX⋅ ⋅----------------------------------- 350
21 0.93 0.97⋅ ⋅------------------------------------ 18.47===
N2 p N1⋅ 18 3⋅ 54t= = =
S1I1
J---- 19.1
8---------- 2.39 mm
2= = =
Single Phase On-Line UPS Using MC9S12E128
52 Freescale Semiconductor
dc/dc Step-Up Converter
Figure 4-12. Simulated Primary Winding Current
Secondary cross-sectional area is given by EQ 4-24:
(EQ 4-24)
where
Ι2 = nominal secondary winding current obtained by integrating the square of the simulated winding current (Figure 4-13).
Time
2.3000ms 2.3040ms 2.3080ms 2.3120ms 2.3160ms 2.3200ms 2.3240ms 2.3280ms2.2965ms1 -I(R1) 2 S(I(R1)*I(R1))
-20A
0A
20A
40A
60A1
895m
900m
905m
910m
915m2
>>
S2I2
J---- 0.74
8---------- 0.093 mm
2= = =
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 53
Hardware Design
Figure 4-13. Simulated Secondary Winding Current
For a 50kHz switching frequency the skin effect depth is given by EQ 4-25:
(EQ 4-25)
In this case the best solution for the primary is the use of a copper foil. An ETD44 bobbin has a width of 30 mm. Because of the necessary creepage, the foil width is set to 25 mm. Based on the result of EQ 4-23, the foil thickness yields 100 µm and has excellent skin performance when compared with skin depth at the current switching frequency.
From the result of EQ 4-24, the secondary winding wire diameter yields 0.338 mm. The nearest wire diameter in production is 0.315mm. A wire with a larger diameter is not helpful any more because of the increased ac resistance due to the skin effect.
The primary winding of the push-pull converter transformer uses a center-tapped windings as well as the secondary windings. As the power transformer is a part of the push-pull converter, there are some restrictions required, especially with respect to the leakage inductance. With inverter transistor turn-off, the drain voltage in push-pull is not clamped by the circuit topology itself. For ideal case (zero leakage), the drain voltage is clamped through the transformer coupling when the rectifier diodes are re-opened.
Time
2.3000ms 2.3040ms 2.3080ms 2.3120ms 2.3160ms 2.3200ms 2.3240ms 2.3280ms2.2965ms1 -I(R3) 2 S(I(R3)*I(R3))
-1.5A
-1.0A
-0.5A
-0.0A
0.5A
1.0A
1.5A1
1.276m
1.280m
1.284m
1.288m
1.292m
1.296m
1.300m2
>>
δ 0.066
f------------- 0.066
503×10
--------------------- 295 µm= = =
Single Phase On-Line UPS Using MC9S12E128
54 Freescale Semiconductor
dc/dc Step-Up Converter
Figure 4-14. Simulated Drain-to-Source and Gate-to-Source MOSFETs Voltages
However, when leakage is non-zero, coupling between the primary and the secondary is not so close and the transformer acts more than an inductive load. As a result, inverter transistors receive voltage spikes and ringing at the drain voltage, usually leading to the use of MOSFETs with a higher break-down drain voltage (Figure 4-14). Due to the necessity to decrease the leakage inductance, an interleaved winding layout has to be used, as seen in Figure 4-15.
Time
9.600us 9.800us 10.000us 10.200us 10.400us 10.600us 10.800us9.458usV(M1:d) V(M2:d) V(M3:g) V(M2:g)
0V
20V
40V
60V
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 55
Hardware Design
Figure 4-15. dc/dc Power Transformer Layout of Windings
The transformer specification is presented by Table 4-6. The magnetizing inductance values are obtained from the manufacturer. The AL constant, total leakage, is obtained initially from numeric parametric simulation results, and afterwards is verified experimentally on the sample. Resistance values are measured values. Test voltages come from general standards defined for the inductive components used in SMPS. Measurements on the sample show that it is possible to achieve a relative leakage less than 0.6%.
Table 4-6. dc/dc Transformer Specification
4.4.2.2 Inverter MOSFETs
As mentioned above, MOSFETs voltage rating is given by voltage spikes that can possibly occur during MOSFET switch-off. Of course it depends on the input voltage, load conditions, and transformer properties. For push-pull a number of twice the input voltage is usually sufficient. The current rating of the MOSFETs (chip size) is always a compromise because a small chip has large RDS(ON) that causes high conduction losses. On the other hand, a large chip has low RDS(ON), but the chip capacitances are higher, and, in the case of hard-switched topologies, the energy stored in the capacitances is not recovered in the switching process, but instead, energy is dissipated in the chip. This is especially the case in applications where the supply voltage is greater than 200 V.
L4 L3
L6 L2 L1 L5
1 9
1018
3T Cu stripe 25x0.15mm
29T Cu 0.315mm
29T Cu 0.315mm2.5kV insulation layer
2.5kV insulation layer
500V insulation layer
2.5kV insulation layer
2.5kV insulation layer
2.5kV insulation layer
29T Cu 0.315mm
29T Cu 0.315mm
3T Cu stripe 25x0.15mm
L1
L2
L3
L4
L5
L6
CoreCoil formerYoke
B66365-G-X197B66366-B1018-T1B66366-A2000
2pcs1pcs2pcs
ETD44/22/15 N97
(EPCOS components)
Magnetizing inductance referred to the secondaryMagnetizing inductance referred to the primary
Total leakage inductance referred to the secondaryPrimary DC resistance
Secondary DC resistanceTest Voltage secondary-to-secondary and primary-to-secondary
Test Voltage primary-to-primary
2.5mH+30-20%30 H+30-20%
<20uH<1mOhm<0.6Ohm2kV AC
150V AC
µ
Single Phase On-Line UPS Using MC9S12E128
56 Freescale Semiconductor
dc/dc Step-Up Converter
The primary factor for chip selection are the effective drain current and the switching frequency. Then a suitable device is selected. Power loss components are calculated and compared with the designed maximum power loss per package.
Simulation results (Figure 4-12) show a value of 19.1 A (transistor and primary winding currents are the same). Dynamically, a current level as high as 50 to 60 A is observed when a load transient occurs and the regulator attempts to hold the output voltage level. Of course the transistor has to withstand such conditions for a number of milliseconds.
A couple of ON Semi’s twin NTP45N06 could be a solution. RDS(ON) for the transistor is 26 mΩ. If a single NTP45N06 switches the current with an effective value of 19.1 A, conduction losses are as high as 9.5 W. To lower the conduction losses and to ensure the transistor switching robustness in dynamic conditions, let’s consider the twin NTP45N06 which decrease overall conduction losses to the half (power loss per package decreases to a quarter - 2.4 W). However, the switching and the capacitance losses have to be considered, due to the increased overall chip area, and hence the overall chip capacitance.
Switching losses are given by EQ 4-26 (ref. [2]).
(EQ 4-26)
(EQ 4-27)
where
Note that VDS can reach a level close to 60V as depending on the particular duty cycle, input voltage, and output load conditions. The same is true for ISW parameter, and the loss value can be impacted.
CAUTIONIf the output load conditions or large transformer leakage cause over voltage spikes at the drain and the maximum drain voltage is reached, the voltage is clamped by MOSFET internal avalanche process (see Figure 4-14 — fourth wave oscillation on green waveform). If the energy of the spikes is high enough, chip temperature will exceed the maximum limit and the semiconductor structure is destroyed. Please always observe the drain-to-source voltage when testing the prototype. If this is the case, increase the MOSFET voltage class or redesign the power transformer in order to decrease the leakage.
VDS = drain-to-source voltage at the switching instance
QGD = “miller part” of the gate charge
QGS2 = “post-threshold voltage” gate charge
fSW = switching frequency
ISW = drain current at the instant of switch off
IG = available mean driver current
PSW VDS QGD QGS2+( ) fSW
ISW
IG
--------⋅ ⋅ ⋅=
PSW 24 3nC 15nC+( ) 503×10 30
0.9------- 0.72 W=⋅ ⋅ ⋅=
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 57
Hardware Design
Turn-on capacitance losses PCAP for the NTP45N06 are given by EQ 4-28.
(EQ 4-28)
(EQ 4-29)
where
The sum of the switching and the capacitance losses is less than 0.8W per transistor at nominal conditions, resulting in 1.6 W for the single NTP45N06 solution and 3.2W for the twin solution. When all the loss contributions are compared, prevalence of the conduction losses is clear. The twin NTP45N06 solution results in an overall loss of 3.2W per package (the conduction component is 2.4 W, the switching component 0.8W). Therefore, the twin solution doesn’t contribute significantly to lower a converter efficiency. Power loss 3.2 W per package means moderate package utilization for TO220, with a good power loss margin.
The power losses can also be calculated by simulation of the model. Figure 4-16 shows the MOSFET instantaneous power and energy obtained by instantaneous power integration. The average power is then calculated by the definition of the power - the energy loss referred to the switching period.
Figure 4-16. Inverter MOSFET Power Analysis
fSW = switching frequency
WCAP = capacitance energy (see ref. [1])
COSS(EFF) = effective output capacity of the MOSFET (see ref. [2])
PCAP fSW WCAP⋅ fSW12--- COSS EFF( ) VDS
2⋅ ⋅ ⋅= =
PCAP 503×10
12--- 380
12–×10 602⋅ ⋅× 34 mW= =
Time
2.208ms 2.212ms 2.216ms 2.220ms 2.224ms 2.228ms 2.232ms1 W(M3) 2 S(W(M3))
-200W
0W
200W
400W1
>>7.92m
7.96m
8.00m
8.04m2
Single Phase On-Line UPS Using MC9S12E128
58 Freescale Semiconductor
dc/dc Step-Up Converter
The use of a single transistor with a higher rated drain current is also possible, however, the copper lead utilization is rather high even though manufacturers define the value around 75 A as a limit for TO220 package leads.
4.4.2.3 Rectifier Diodes
Rated diode voltage is given by the voltage waveform applied to the diode. However, diode voltage waveforms are different from that of the MOSFETs since the rectifier diodes are placed in a different topology. As the rectifier is current-loaded there is no natural clamp for over voltage spikes at the instant of a diode reverse recovery. That is why a suitable snubber has to be implemented in order to cut-off the excess energy that could possibly overheat the diode chip by internal avalanche.
As dc/dc converter nominal output voltage is 2x390V (Figure 4-18 shows secondary voltage of the power transformer), and during dynamic conditions it can reach 2 x 420 V, the possibility of selecting the diode voltage rating is constrained. Figure 4-17 shows waveforms of the rectifier diode voltage and current. In this case, diodes with a break-down voltage of 1200V are selected.
Figure 4-17. Rectifier Diode Voltage and Current Waveform
When choosing the rectifier current rating, similarly as with the MOSFETs, the anode effective current and switching frequency have to be considered. Simulation results for the nominal anode effective current shows a value of 0.54 A and a 1.3 W power loss. Because the power loss is rather high for a practical usage of the DO241 package, diodes with a fully-isolated TO220 package are chosen. One possibility is to use of the Fairchild ultrafast diode FFPF05U120S with 5-A rated current, 1200 V rated voltage, and 100ns reverse recovery time, which is good enough for 50 kHz switching frequency.
Time
2.3100ms 2.3150ms 2.3200ms 2.3250ms 2.3300ms2.3075ms1 V(D1:1,D1:2) 2 I(D1)
-1.0KV
-0.5KV
0V
0.5KV1
>>-0.5A
0A
0.5A
1.0A
1.5A2
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 59
Hardware Design
4.4.2.4 Filter Chokes
A basic design consideration when implementing a filter choke is to look at the rectified current ripple. For an output current level in the range of 0.5 to 2 A, the relative ripple ri can be considered in the range of 50 to 20%. Let ri equal 30% for nominal conditions. Then the filter choke inductance value is given by EQ 4-30:
(EQ 4-30)
(EQ 4-31)
where
Filter choke performance is analyzed by simulation, and the results (Figure 4-18) verified a good design procedure. Choke PCV2-564-02 from Coilcraft, with 560 µH inductance and 2 A saturation current, is chosen.
VL = voltage across the choke when active cycle
∆Τ = the time during active cycle
∆i = current ripple
VIN = nominal input voltage
VLOSS = voltage drop on resistive components (RDS(ON), transformer primary, etc.)
p = transformer primary to secondary ratio
VOUT = nominal output voltage
δMAX = maximal switching duty cycle
ri = relative current ripple
IOUT = nominal output current
L VL∆T∆i-------⋅ VIN VLOSS–( ) p VOUT–⋅[ ]
δMAX T⋅ri IOUT⋅---------------------⋅= =
L 24 1.6–( ) 18 390–⋅[ ] 0.98 106–×10⋅
0.3 0.74⋅----------------------------------- 583 µH=⋅=
Single Phase On-Line UPS Using MC9S12E128
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Power Factor Correction and Output Inverter
Figure 4-18. Secondary Voltage and Rectified Current Waveforms
4.5 Power Factor Correction and Output Inverter
4.5.1 PFC Booster Operational Description
This section deals with a design of the power factor correction booster (PFC). The PFC forms the input stage of the UPS. It is a switchmode power converter, which provides an a.c. input current waveform that is sinusoidal and in phase with the line voltage. The power factor is maintained so as to be close to one.
The continuous current - boost converter topology was chosen for the PFC circuitry design, as shown in Figure 4-19. The PFC specifications are listed in Table 4-7. A power circuit consists of a current sensing transformer CT1, input inductor L505, rectifying bridge D606, power switch Q606, voltage doubler diodes D604, D608, and filtering capacitors C603, C602, C607, and C608. The PFC control algorithm implemented uses an indirect digital control approach. To decrease MCU load the input current controller is built externally.
Table 4-7. Digital PFC Specifications
Parameter Value Unit
Input Voltage Min. 80 V[r.m.s.]
Input Voltage Max. 270 V[r.m.s.]
Output d.c. Voltage 390 V
Output Power Nominal 525 W
Input Current Nominal 2.3 A[r.m.s]
Switching frequency 30 to 60 kHz
Time
1.900ms 1.905ms 1.910ms 1.915ms 1.920ms 1.925ms 1.930ms 1.935ms 1.940ms1 I(L16) I(L17) 2 V(R3:2,R4:2)
-800mA
-400mA
0A
400mA
800mA1
-1.0KV
-0.5KV
0V
0.5KV
1.0KV2
>>
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Freescale Semiconductor 61
Hardware Design
Figure 4-19. PFC Power Stage
The output voltage level is controlled using a digital controller algorithm executed by the MCU. The MCU generates a sinusoidal reference waveform for the discrete current controller. The current controller circuit can be seen in Figure 4-20. The controller performs hysteretic current control. Comparators U606A and U606C compare the actual input current value I_IN with the upper and the low limits set by the DA1 and DA0 signals, respectively. Comparator U606B turns on and off power switch Q606 according to the U606A and U606C outputs. The UPS input current corresponds to the shape of the reference signals DA0 and DA1 generated by the MCU. The PFC operation is disabled if the PFC_EN signal is tied low by MCU control.
Alternatively (if signal DA0 is not available), the low hysteresis limit can be adjusted by the configurable voltage divider. The resulting hysteresis is then defined by the combination of resistors R664, R673, R674, and R675. The voltage divider can be configured according to the DIV1 and DIV2 signals.
NOTESelecting whether the low hysteresis limit is taken from DA0 signal or from the configurable voltage divider has to be done by resoldering the zero resistors R666 and R667. If R666 is populated, the DA0 signal is selected. If R667 is populated, the configurable divider is selected. By default R666 is populated and R667 is not.
N
L1 DCB_POS
N
DCB_NEG
GND
GATE_PFC
GND_PFC
I_IN1 I_IN2
+C602
330uF/450V
L505
2.5mH
+ C608330uF/450V
CT1
1:100
9 7
1 2
D604
RHRP8120
C603
MKP10/22nF/630VDC
- +
D606KBPC606
D608
RHRP8120
C607
MKP10/22nF/630VDC
Q606IRG4IBC20W
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62 Freescale Semiconductor
GND
GND
PWM_PFC
GATE_PFC
GND_PFC
D62815V
D
S0LT1
C628100n
Figure 4-20. PFC Current Controller
DA1
DA0
UNI-3 PFC_EN
DIV1 DIV2
I_IN
+5V_D
+5V_A
GNDA
GNDA
GNDA GNDA
GNDA
+5V_D
GNDA
GNDA
+5V_A
GNDA
GND
GNDA
+5V_D
+15V_PFC
GND_PFC
GND
PWM_PFC
All On 55% 75% 85%60%
C627
100n
U601
HCPL3150
2 7
3 6
5
81
4
D
G
SQ611MMBF0201NLT1
D609
BAT42
C630100n
R661
470
R6733.3k
-
+
V+
V-
U606C
LM339M
9
8
312
14
R67410k
R66910k
R667
0
R665
100
R662
470
R668
100
C609100nF
R606
10
C629100n
R6759.1k
G
Q61MMBF0201N
R6641.6k
R65910k
TP611
PFC_CTRL
R663
100
-
+
V+
V-
U606B
LM339M
7
6
312
1
R67010k
R65733
R660
10k
R666
0
R65810k
-
+
V+
V-
U606A
LM339M
5
4
312
2
R607
100
R6714.7k
D
G
SQ612MMBF0201NLT1
D
G
SQ609MMBF0201NLT1
C631100n
Hardware Design
4.5.2 PFC Booster Design Considerations
In this section we will discuss the design considerations of the PFC booster critical components.
4.5.2.1 PFC Boost Inductor L1
The input inductor must be selected with respect to two parameters, the input current ripple and the switching frequency. It is designed for maximum input power, minimum input voltage, when the sine wave current peak is at a maximum.
The maximum input current value is then calculated from the maximum output power Pout max and minimum input voltage Vin min. We also have to include efficiency of the boost converter. For a continuous current boost converter, the efficiency is estimated at 95%. The maximum current value is calculated as follows:
(EQ 4-32)
If we know the input current maximum value we can calculate a current ripple. We chose the current ripple to be 15% of the input peak current. For the given peak current value it is:
(EQ 4-33)
When the PFC switch is turned on, the following equation has to be met:
(EQ 4-34)
where
Turn on time Ton can be expressed from EQ 4-34 as follows:
(EQ 4-35)
When the PFC switch is turned off, the following equation has to be met:
(EQ 4-36)
where
L1 = inductance of the input boost inductor
∆I = p-p input current ripple
Ton = turn-on time of the PFC switch
Vin = instantaneous input voltage value
Toff = turn-off time of the PFC switch
Vout = output voltage
Iin max 2Pout max
Vin min η⋅-----------------------⋅ 2
525184 0.95⋅------------------------⋅ 4.2A= = =
I∆ Iin max 0.15⋅ 0.645A= =
L1I∆
Ton
--------⋅ Vin=
TonI L1⋅∆Vin
----------------=
L1I∆–
Toff
---------⋅ Vin Vout–=
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64 Freescale Semiconductor
Power Factor Correction and Output Inverter
Again, turn off time Toff can be expressed:
(EQ 4-37)
Switching period T equals the sum of Ton and Toff times:
(EQ 4-38)
Frequency is an inverse value of the period. The switching frequency of the PFC is then given by the formula:
(EQ 4-39)
Switching losses of the IGBT transistor are proportional to the switching frequency. To maintain switching losses within acceptable limits we have to design the input inductor L1 with respect to a maximum switching frequency. From EQ 4-39, we can calculate the level of input voltage (Vin) when the switching frequency reaches its maximum value. We get the maximum switching frequency at
(EQ 4-40)
If we substitute EQ 4-40 for EQ 4-39 we can solve the equation and find the value of the required input inductance value for the given ripple current (∆I), output voltage (Vout) and maximum switching frequency (fmax):
(EQ 4-41)
If we enumerate the equation for desired values we get:
(EQ 4-42)
To limit the maximum frequency at 60 kHz at ripple current 0.645 A, we choose the input PFC inductance L1 = 2.5 mH.
4.5.2.2 L1 Inductor Core Selection
As soon as we know the required inductance, we can proceed to select the core material and size. For the PFC application, we will consider an iron powder material.
Size of the core can be established based by an iterative process using manufacturer’s catalog data. We have chosen Micrometals as a material supplier. They offer a design software, which makes this process easier. We used this software to find the best fitting core.
In the window “PFC Boost Design Requirements” we entered the in following parameters (see Table 4-8).
ToffI L1⋅∆–
Vin Vout–------------------------=
T T= on Toff+I L1⋅∆Vin
----------------I L1⋅∆
Vin Vout–------------------------–
I L1 Vout⋅ ⋅∆
Vout Vin⋅ Vin2–
-------------------------------------= =
fsw1T---=
Vout Vin⋅ Vin2–
I L1 Vout⋅ ⋅∆-------------------------------------=
VinVout
2----------=
L1Vout
4 I fmax⋅∆⋅---------------------------=
L1390
4 0.645 60 103⋅ ⋅ ⋅
-------------------------------------------- 2.5 103–H⋅ 2.5mH= = =
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 65
Hardware Design
:
We ran the calculation and got a list of suitable cores, that met our selection criteria. From the list we selected core: T175-8/90. The software calculates all important data (number of turns, wire diameter, losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
The core T175-8/90 meets all of our criteria, is an acceptable size, with moderate losses and good linearity.
4.5.2.3 dc-Bus Capacitor Design
When designing a dc-bus capacitor, we must consider its rated voltage, capacitance, size, and cost. Because there is no upper limit to the capacitance (the higher capacitance the better), we should focus on finding the possible smallest capacitance, which still meets our requirements on dc-bus voltage ripple and output voltage quality. The correct design of capacitor is very important and can significantly influence final manufacturing cost of the product. The cost of capacitor rises exponentially with its rated voltage and capacitance.
Table 4-8. PFC Inductor Parameters
Parameter Value Unit
INDUCTANCE AT MAX CURRENT 2500 µH
MAXIMUM CURRENT 5 A
PEAK REGULATOR INPUT VOLTAGE 113 V
REGULATOR dc OUTPUT VOLTAGE 390 V
FREQUENCY 60 kHz
TEMPERATURE 55 °C
CORE SHAPE TOROID -
WINDING TYPE FULL WINDOW -
Table 4-9. Design Parameters for Core P/N: T175-8/90
Parameter Value Unit
Al 48 nH
TURNS 287 -
WIRE 1.00 mm
FILL 38.9 %
Rdc 0.4971 Ω
Core Loss 0.28 W
Cu Loss 6.21 W
Temp. Rise 41.8 °C
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Power Factor Correction and Output Inverter
The dc-bus capacitor is a storage of energy for output power factor circuit and feeds an output inverter. The dc-bus voltage should be set above the peak at maximum r.m.s. input voltage. For input RMS voltage Vin = 270 V, the peak voltage is Vin peak max = 381 V. To achieve good regulation of the dc-bus voltage, the dc-bus voltage should be at least 10% above the peak at nominal r.m.s. input voltage, i.e. for Vin nom = 230 V RMS: Vdc-bus min = 1.1x1.41x230 = 356 V. Having Vin peak max and Vdc-bus min, we can determine the dc-bus nominal voltage. We chose Vdc-bus nom = 390 V.
The dc-bus capacitor voltage should at least be rated at 450 V dc.
If ac input is lost, it is desired that the dc-bus capacitor is large enough to hold up the dc-bus voltage at value Vdc-bus hup, allowing the output inverter voltage to remain within specifications for a time Thup.
The maximum nominal output voltage is Vout nom = 230 V RMS. The dc-bus voltage has to be higher than the output voltage peak value Vout peak = 325 V. The hold-up time we define as a half-period of the output ac voltage frequency Thup = 10ms. The minimum dc-bus capacitor value can calculated:
(EQ 4-43)
where
Iav is the average capacitor current during the drop from Vdc-bus nom to Vout peak.
The Iav current can be calculated according to the formula:
(EQ 4-44)
where
Pout is the inverter output power
η is the inverter efficiency
We can enumerate equation EQ 4-44 and obtain:
(EQ 4-45)
The minimum output capacitor value can be calculated if we enumerate formula EQ 4-43:
(EQ 4-46)
The minimum output capacitance of the dc-bus capacitor is 266µF.
The next parameter we need to know for selecting the output capacitor is the ripple current rating. The dc-bus capacitor current consists of a dc-component plus an ac-component (100/120 Hz). The dc-component flows to the load, ac-component flows into the capacitor C0. The ripple current amplitude is equal to the peak load current. The ripple current can be then calculated:
(EQ 4-47)
The peak load current Iload is:
(EQ 4-48)
C0Iav Thup⋅
Vdc busnom– Voutpeak–-----------------------------------------------------=
Iav2Pout
η Vdc busnom– Voutpeak+( )--------------------------------------------------------------=
Iav2 525⋅
0.85 390 325+( )---------------------------------------- 1.728A= =
C01.728 10 10 3–⋅ ⋅
390 325–--------------------------------------- 266 10
6–F⋅= =
IrippleIload
2----------=
IloadPout
2 Vdc busnom– η⋅ ⋅------------------------------------------- 525
2 390 0.85⋅ ⋅------------------------------- 0.792A= = =
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Hardware Design
Ripple current is then: Iripple = 0.792/1.41 = 0.562 A.
The waveform applied to the dc-bus capacitor is a near-rectangular waveform at the switching frequency. Therefore the dc-bus capacitor should have a low impedance at the switching frequency. A low-ESR electrolytic capacitor should be considered for this application.
Considering all the above requirements, we selected following dc-bus capacitor:
4.5.3 Output Inverter Operational Description
This section deals with the design of the output inverter of the single-phase UPS. The purpose of the output inverter is to convert dc-voltage of the dc-bus to an output single-phase sinusoidal voltage of the required amplitude and frequency.
The topology of the inverter circuitry is shown in Figure 4-21. The power circuit consists of IGBT power switches Q605 and Q608, which are connected across dc-bus capacitors C602, C608. An emitter terminal of Q605 and a collector terminal of Q608 are connected to a sinusoidal filter (inductor L506 and a capacitor C605). Output of the sinusoidal filter is then connected to the by-pass relay RE2 and EMC filter (L205, C604, C602). Output relays RE1, RE3, connect the inverter output to output terminals of the UPS. The nominal specifications of the output inverter are listed in theTable 4-11.
Table 4-10. dc-bus Capacitor Parameters
Parameter Value Unit
Manufacturer BC Components (Vishay)
Catalogue Number 2222 157 47331
Rated Capacitance 330 µF
Rated Voltage 450 V d.c.
ESR @ 100 Hz 300 mΩ
Ripple Current@ 120 Hz 2.19 A
Table 4-11. Output Inverter Specifications
Parameter Value Unit
Input Voltage Min. 2x340 V[d.c.]
Input Voltage Max. 2x430 V[d.c.]
Output a.c. Voltage 80 - 270 V [r.m.s.]
Output Apparent Power Nominal(1)
1. Nominal output apparent power for nominal output voltage 230 V r.m.s.
750 VA
Output Current Nominal 3.3 A[r.m.s]
Switching frequency 20 kHz
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N_OUT
PE
OUT1
OUT2
Figure 4-21. Output Inverter Power Circuit
DCB_POS
N
DCB_NEG
GND_BOT
GND_TOP
GATE_BOT
I_OUT1I_OUT2
GATE_TOP
V_OUT
+15V
+15V
GND
GND
GND
GND
+15V
o
o
o
RE3MZPA001
5
4
3
1 2
+ C608330uF/450V
o
o
o
RE2MZPA001
5
4
3
1 2
o
o
o
RE1MZPA001
5
4
3
1 2
CT2
CS21068 5
1 2 3 4
+C602
330uF/450V
D605
BAT42
R604
100
Q608
HGTG10N120BND
R602
100
C6064.7nF/Y1
D
G
SQ603MMBF0201NLT1
C604
4.7nF/Y1
C605
6.8uF/400V
D
G
SQ604MMBF0201NLT1
D
G
SQ602MMBF0201NLT1
D603
BAT42
D602
BAT42
Q605
HGTG10N120BND
L506
5mH
R603
100
L507
TL34P
1
3
2
4
RLY_OUT2
L2
RLY_BYPASS
RLY_OUT1
Hardware Design
The power IGBTs Q605 and Q608 switch in a complementary manner (if Q605 is on, Q608 is off, and vice versa). Using the power IGBTs, the dc-bus voltage is pulse-width modulated at 20kHz switching frequency to obtain an output voltage with a low frequency a.c. component (50/60 Hz). The junction of C602 and C608 is a zero-volts reference for the generated output waveform. The junction of the capacitors is galvanically connected to the mains N-terminal and is labelled as system ground.
Switching pulses to gates Q605 and Q608 are generated by the dual IGBT gate opto-drive HCPL-315J (U615). The opto-drive provides the circuitry with galvanic isolation between the MCU and each of the IGBTs. Its topology is shown in the Figure 4-22. The IGBT gates are floating during the inverter operation in a voltage range +/- 430 V dc. Each channel of the dual opto-drive IC is supplied from a galvanically isolated voltage supply of +15V dc.
Figure 4-22. Inverter IGBT Gate Drive Circuitry
The by-pass relay RE2 connects the UPS output to either the inverter or the mains voltage.
The relays RE1 and RE3 connect the UPS output socket banks to the output voltage.
A current transformer CT2 is put into the output current path. Together with current-to-voltage converter circuitry, it makes up the sensing circuitry of the output load current.
NOTEPlease note that during operation, the voltage on the power IGBTs is a sum of the voltages on the dc-bus capacitors, i.e., it can reach up to 2 x 430 V = 960 V! The IGBTs must be rated for a collector-emitter voltage of 1200 V.
GND_BOT
GND_TOP
GATE_TOP
GATE_BOT
+15V_TOP
-5V_BOT
GND_BOT
-5V_TOP
GND
+15V_BOT
GND_TOP
D62415V
C632100nF
D62615V
R613
100
R610
100
R608
330
D613
BAT42
D612
BAT42
R611
330
C611100nF
C633100nF
D6255V
D610
BAT42
C610100nF
R612
33
U615
HCPL-315J
10
1415161
23
678
11
9VO2
VEE1VO1
VCC1N/CANODE1CATHODE1
ANODE2CATHODE2N/C
VCC2
VEE2
D611
BAT42
D6275V
R609
33
PWM_TOP
PWM_BOT
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Power Factor Correction and Output Inverter
4.5.4 Output Inverter Design Considerations
In this section we will discuss the design considerations of the critical components of the output inverter.
The sinusoidal output filter is a low-pass LC-filter consisting of an inductor L506 and a capacitor C605. The resonant frequency of the circuit has to be selected with respect to the output voltage control loop. Based on the Simulink simulation results we have selected a resonant frequency in the range: 600 to 900 Hz.
Having the resonant frequency we are able to select values of the inductor and capacitor. To achieve the required resonant frequency of the filter we have plenty of variants of L and C distribution. The values of the components have to be selected with consideration of their size, cost and availability. Considering the components available in the market, we have chosen following combination:
• L506 = 5 mH• C605 = 6.8 µF
The resonant frequency of such a circuit is 863 Hz and falls in our range.
4.5.4.1 C605 Capacitor Selection
The capacitor parameters have to fulfil safety requirements for rated ac voltage. Low ESR and ESL parameters are required to achieve a low output voltage ripple. For the output sinusoidal filter we selected MKP 338 4 X2 capacitor from Vishay BC components. See Table 4-12.
4.5.4.2 L506 Inductor Core Selection
As soon as we know the required inductance, we can proceed to select the core material and size. Because the inductor current contains a high frequency ripple, we will consider an iron-powder core.
Size of the core can be established by an iterative process using the manufacturer’s catalog data. We have chosen Micrometals as the material supplier. Again as with the PFC inductor design, we used the Micrometals software to find the best fitting core.
For the design of the output filter inductor, we can use either “dc biased” design or “PFC boost”. The calculations of both are similar, however, the “PFC Boost” calculations account for a periodic change to the switching duty-cycle. We can thus more accurately represent the losses in the inductor core. Therefore we selected “PFC Boost” design. In the parameter window of the design, we entered the parameters shown in Table 4-13.
Table 4-12. MKP 338 4 X2 Capacitor Reference Data
Parameter Value
Capacitance 6.8 µF
Capacitance tolerance 20%
Rated (ac) voltage, 50 to 60 Hz 300V
Rated (dc) voltage 630V
Rated temperature 105°C
Safety class X2; across the line
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 71
Hardware Design
NOTENote that we swapped the input and output peak voltage values in the design parameters. In a real inverter, the dc voltage is the input parameter and the ac voltage is the output parameter. To make an analogy with PFC, we have to swap these parameters in the input table.
We ran the calculation and got a list of suitable cores that met our selection criteria. From the list we selected core: T200-30B. The software calculates all important data (number of turns, wire diameter, losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
The core T200-30B meets all of our criteria, is an acceptable size, with moderate losses and low price.
Table 4-13. Output Filter Inductor Parameters
Parameter Value Unit
Inductance at max current 5000 µH
Maximum current 4.6 A
Peak regulator input voltage 340 V
Regulator dc output voltage 400 V
Frequency 20 kHz
Temperature 55 °C
Core shape Toroid -
Winding type Full window -
Table 4-14. Design Parameters for Core P/N: T175-8/90
Parameter Value Unit
Al 51 nH
Turns 388 -
Wire 1.00 MM.
Fill 38.5 %
Rdc 0.8868 Ohms
Core loss 1.46 W
Cu loss 9.38 W
Temperature rise 46.4 °C
Single Phase On-Line UPS Using MC9S12E128
72 Freescale Semiconductor
Chapter 5 Software Design
5.1 Introduction
This section describes the design of the software blocks for the UPS. The software is described in terms of:
• Data flow• Main software flowchart• State diagram
For more information on the control technique used, see Chapter 3 UPS Control.
5.2 Data Flow
The control algorithm obtains values from the user interface and sensors, processes them, and generates PWM signals for the dc/dc step-up converter, output inverter, and sine wave reference for PFC, as can be seen on the data flow analysis shown in Figure 5-1.
5.2.1 Software Variables and Defined Constants
Important system variables, named in the data flow, are listed in Table 5-1. The table includes the name, range used, and representation in real quantities.
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 73
[]
ery ChargeControl
atState
I_bat
Application StateMachine
ButtonProcessing
LEDProcessing
buttonStatus
appState
Figure 5-1. Main Data Flow
InverterControl
DC BusScaling
Mains LineDetectionRMS
Correction
PLLAlgorithm
Sine WaveReference
Ramp
Sine WaveReference
PFC Control
PWMB_duty_cycle
PWM_to_DCB_scale
amplitude_ref
phase_outphase_pfc
phase_out_inc
v_dcb_req
v_dcb[]
i_n_ref
pfc_ref_h
PWMC_duty_cycle
v_dcb_req_rmp
phase_pfc_inc
counter_actual
amplitude_correction
v_sin_ref
v_out_freq_detect v_dcb
v_out_rms
v_out
DC/DC Step UpControl
Ramp
v_dcdc_req_rmp
v_dcdc_req
v_dcdc_sumBatt
B
V_bat
Data Flow
Type: S8 = signed 8-bit, U8 = unsigned 8-bit, S16 = signed 16-bit, U16 = unsigned 16-bit.
Table 5-1. Software Variables
Name Type <Range>; [Scale] Description
amp_ControllerPar Structure - PI controller parameters for RMS correction
amplitude_correction U16 <0, 39936>; [0V, 400V] output of RMS correction
amplitude_ref U16 <0, 39936>; [0V, 400V] required amplitude of output sine wave
appState enum - state of application state machine
BatState enum - state of battery charger
counter_actual U16<0,5580>; [0 s, 7.14 ms (70 Hz)]
period of input voltage zero crossing
dcdc_duty U16 <0, 121>; [0%, 96.8%] duty cycle of dc/dc step-up converter
i_bat S16 <0, 1023>; [0 A, 2.34 A] battery charging current
i_out S16<-32768, 32767>;[-13 A, 13 A]
actual output current
i_out_rms S16<-32768, 32767>;[-13 A, 13 A]
RMS value of output current
pfc_ref_h U8 <0, 152>; [0 A, 5 A] required actual input (PFC) current
phase_diff S16<-32768, 32767>;[-180º, 180º]
phase difference between expected and actual phase of PLL
phase_measured S16<-32768, 32767>;[-180º, 180º]
calculated phase
phase_out S16<-32768, 32767>;[-180º, 180º]
actual phase of generated output voltage
phase_out_inc U16<33554, 58720>;[40 Hz, 70 Hz]
increment to sine wave table (output voltage)
phase_pfc S16<-32768, 32767>;[-180º, 180º]
actual phase of input voltage calculated by PLL
PWMB_duty_cycle U16 <0, 625>; [-100%, 100%] duty cycle of output inverter
PWMC_duty_cycle U16 <0, 121>; [0%, 96.8%] duty cycle of dc/dc step-up converter
temperature U16 <0, 205>; [0 ºC, 100 ºC] temperature of power stage heatsink
v_bat U16 <0, 1023>; [0 V, 39 V] battery voltage
v_dcb[] U16 <0, 1023>; [0 V, 450 V] dc bus voltage
v_dcdcControllerPar Structure - PI controller parameters for dc/dc controller
v_in U16 <0, 1023>; [0 V, 324 V] RMS value of input voltage
v_out S16<-19968, 19968>;[-400 V, 400 V]
actual output voltage
v_out_freq_detect U16<33554, 58720>;[40 Hz, 70 Hz]
detected input frequency
v_out_rms U16<-19968, 19968>;[-400 V, 400 V]
RMS value of output voltage
v_pfcControlerPar Structure - PI controller parameters for PFC controller
v_sine_ref S16<-19968, 19968>;[-400 V, 400 V]
required value of output voltage (sine wave reference including amplitude correction)
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5.2.2 Process PLL Algorithm
The PLL algorithm synchronizes the pointer to the PFC sine wave reference with the input line voltage. The algorithm uses the variable counter_actual as an input and calculates the phase_pfc, phase_pfc_inc, phase_out and phase_out_inc. The variables relating to the output inverter are generated if the output is synchronized with the output.
5.2.3 Process RMS Correction
Because the output inverter PID controller is not able to keep a constant RMS value of output voltage due to slight or missing integral part of the controller, the RMS correction must be calculated. The RMS controller compares the actual RMS value v_out_rms with the required RMS value calculated from amplitude_ref. The output of PI controller is correction to the amplitude, stored in amplitude_correction.
5.2.4 Process Mains Line Detection
This process sets the mains line system to 230 V, 50 Hz or 115 V, 60 Hz according to state of START/STOP switch on the MC9S12E128 controller board. The detected values amplitude_ref and v_out_freq_detected are used for the output inverter to generate the correct output and for the PFC PLL to determine that the PLL algorithm is synchronized.
5.2.5 Process Ramp
The ramp process changes an input value in a time period with a predefined slope. A different ramp can be defined for a rising and falling slope.
5.2.6 Process Sine Wave Reference
The sine wave reference process generates the sine wave reference waveform v_sin ref based on the actual phase phase_out, phase increment corresponding to the generated frequency phase_out_inc, and amplitude amplitude_ref + amplitude_correction.
5.2.7 Process Button Processing
The button processing reads the status of the ON/OFF and BYPASS buttons. It recognizes a short and long push. The results are saved in variable buttonStatus.
5.2.8 Process LED Processing
The process handles the LEDs on the user interface. Each LED can be switched on, off, or to flash. The LED status bar works in two modes. In output power mode, the status bar displays the actual output power. In battery mode it shows remaining battery capacity.
5.2.9 Process Application State Machine
This process provides the state machine of UPS. The state machine defines the following states:• Init• Standby on battery• Standby on line• Run on battery
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Data Flow
• Run on line• Run on bypass• Error• UPS off
After RESET, the state machine enters into the Standby on battery state if the mains line is available. Then if the user pushes the ON/OFF button, the state machine continues on to the Run on line state. During mains line failure, the state machine goes to the Run on battery state. The state machine stays there until the batteries are discharged, the user switches the UPS off, or the main line is restored. If the batteries are discharged the state machine goes to the Standby on battery state. If the state machine stays in this state one minute, the UPS is switched off (UPS state) to avoid total discharge of the batteries. In the case of some fault, the state machine goes into the Error state.
If the state machine goes from one to another state, a respective transition function is called.
Figure 5-2. Application State Machine
5.2.10 Process PFC Control
The PFC control process consists of the PI controller, which controls the dc bus voltage v_dcb[] to the required value v_dcb_req (v_dcb_req_rmp). The result defines the amplitude of the input current (i_n_ref).
INIT
STANDBY
BATTERY
STANDBY
ONLINERUN ON LINE
RUN
ON BATTERYERROR
RUN BYPASS
UPS OFF
CPU RESET
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5.2.11 Process Sine Wave Reference (PFC)
This process generates a rectified sine wave waveform based on the required amplitude i_n_ref, actual phase phase_pfc, and the required frequency phase_pfc_inc. The result pfc_ref_h is sent to the D/A converter and is used as the reference for the external current controller.
5.2.12 Process dc Bus Scaling
The scaling process calculates the correction constant PWM_to_DCB_scale for inverter duty cycle. The duty cycle, which outputs from the PID controller, is related to constant dc bus voltage. If the actual dc bus is different, the duty cycle has to be recalculated to the actual dc bus. For example, if the output duty cycle is 50% (195 V) for 390 V of dc bus voltage and the actual dc bus voltage is equal to 380 V, the resultant duty cycle has to be recalculated to 51.3% to maintain 195 V.
5.2.13 Process dc/dc Step-Up Control
The process is similar to the PFC control process. The input value is v_dcdc_req (v_dcdc_req_rmp) and the result is PWMC_duty_cycle.
5.2.14 Process Inverter Control
The inverter control process performs PID controller including feed forward technique. The inputs are v_sin_ref, v_out, and PWM_to_DCB_scale, and the output is the duty cycle PWMB_duty_cycle.
5.2.15 Process Battery Charge Control
The battery charger control process charges the batteries. The charging current i_bat and battery voltage v_bat are read, and according to the actual battery current, the state of the charging algorithm BatState is set to BULK CHARGE MODE, ABSORPTION MODE, or FLOAT MODE.
5.3 Main Software Flowchart
The software is written in C language using Metrowerks CodeWarrior software. Some time-critical parts such as sine wave generation and arithmetical functions are written in assembler.
The software consists of the following parts:• Initialization of peripherals and variables• Background group• 5 periodic interrupts (2 x 50 µs, 1 x 1 ms, 1 x 10 (8.3) ms, 1 x 50 ms)• 3 event interrupts (PMF faults, LVI, SCI)
5.3.1 Initialization of Peripherals and Variables
After RESET, the program goes into the initialization routine. The routine initializes the following peripherals:
• PLL• I/O pins• Analog to digital converter• Digital to analog converter• Pulse-width modulator with fault protection• Timer 0
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Main Software Flowchart
• Pulse-width modulator• Voltage regulator
Subsequently, the communication with the PC is initialized, and the program variables are set to default values.
Then the program enters the never-ending loop providing the application state machine (see main function listing below).
void main () InitPeripherals(); PCMaster_Config(); EnableInterrupts; /* enable interrupts to make this routine
interruptible (defined int PCMaster-S12.h) */ PCMasterInit(); // init PCMaster functions InitVariables();while(1)
appStateFcn[appState]();FanControl();
The structure of the background loop can also be seen in Figure 5-3.
Figure 5-3. Background Loop
RESET
Background loop
END
of Background loop
Peripheral and variable
inicialization
Application state machine
execution
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5.3.2 Periodic Interrupts
The software uses five periodic interrupts. They are:• PMF reload interrupt (called every 50 µs)• ATD conversion complete interrupt (called every 50 µs)• TIM0 CH4 input capture interrupt (called every 8.3 or 10 ms)• TIM0 CH5 output compare interrupt (called every 1 ms)• TIM0 CH6 output compare interrupt (called every 50 ms)
5.3.2.1 PMF Reload Interrupt
The PMF Reload Interrupt is part of the UPS main control loop. The source of the interrupt is a reload event of counter B (output inverter). The structure of the interrupt can be seen on Figure 5-4.
Figure 5-4. Structure of PMF Interrupt
The interrupt starts by reading a slow ATD conversion. A slow ATD conversion means that the quantities are not converted every 50 µs. There is a table which defines the order of quantities to be converted. The results of a slow ATD conversion are ready from previous interrupt.
After saving the conversion results, a fast ATD conversion is set and started. A fast ATD conversion means that the quantities are converted every interrupt (50 µs). The output voltage and current are sensed in the fast ATD conversion.
PMF B Reload Interrupt
(50 s)
Start fast ATD Conversion
Read samples
of slow ATD Conversion
Lost detection
of Line Zero Crossing
Input voltage polarity detection
Output power and
RMS Value Calculation
PFC reference sine wave
generation
Inverter reference sine wave
generation
END
of Interrupt RoutineService
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Main Software Flowchart
While the fast ATD conversion is running the following tasks are performed:• Detection of missing zero crossing on the input line• Detection of input voltage polarity• RMS value calculation and output power calculation (multiplication and addition)• Generation of rectified sine waveform for the PFC• Generation of sine wave reference for the output inverter
The execution time for these tasks is shorter than the conversion time in a fast ATD conversion.
5.3.2.2 ATD Conversion Complete Interrupt
As soon as the fast conversion is completed and the PMF reload interrupt executed, the ATD conversion complete interrupt is called. This interrupt performs the inverter control and starts the next slow ATD conversion (see Figure 5-5). Because this interrupt is bounded by the PMF reload interrupt, the execution period is also 50 µs.
Both interrupts, together with the TIM0 CH5 output compare interrupt, comprise the main part of the UPS control algorithm. The PMF reload and ATD conversion complete interrupts have the highest priority and are uninterruptible.
Figure 5-5. Structure of ATD Conversion Complete Interrupt
5.3.2.3 TIM0 CH4 Input Capture Interrupt
The source of this interrupt is a zero crossing on the input voltage. So the interrupt is executed every 8.3 ms or 10 ms. The interrupt performs a phase locked loop algorithm, which synchronizes the generation of PFC and output inverter sine wave references with the input voltage.
ATD Conv. Complete Interrupt
(50 s)
END
of Interrupt RoutineService
Start fast ATD conversion
Output inverter controller
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Figure 5-6. TIM0 CH4 Input Capture Interrupt
5.3.2.4 TIM0 CH5 Output Compare Interrupt
The source of this interrupt is the output compare event, set to generate event every 1 ms. This interrupt comprises the second part of the control algorithm. The structure of the interrupt is shown in Figure 5-7.
Figure 5-7. Structure of TIM0 CH5 Output Compare Interrupt
The interrupt performs following tasks:• Voltage control loop of the PFC• dc/dc step-up converter control loop• Filtering and scaling of analog values measured in the slow ATD conversion• finishing the RMS and output power calculations (multiplication by constant and square root)• RMS correction algorithm
This routine has a lower priority and can be interrupted by the PMF reload and ATD complete interrupts.
TIM 0 ch 4 IC Interrupt
(Line Zero Crossing)
END
of Interrupt RoutineService
PFC PLL algorithm
TIM 0 ch 5 OC Interrupt
(1 ms)
Filtering and scaling
of analog values
PFC control loop
DC/DC step up converter
control loop
Output power and
RMS values calculation
RMS correction
END
of Interrupt RoutineService
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Main Software Flowchart
5.3.2.5 TIM0 CH6 Output Compare Interrupt
The last periodic interrupt is called every 50 ms. The time base is derived from TIM0 CH6 output compare event, which is set to generate this period. The interrupt performs background tasks which require periodic execution but with a very low priority. The tasks are:
• Software timers• User interface handling (buttons, LED diodes)• Battery charger algorithm
Figure 5-8. Structure of TIM0 CH6 Output Compare Interrupt
5.3.3 Event Interrupts
The event interrupts are called on an event. The UPS application uses following event interrupts:• SCI interrupt (performing the communication with PC)• PMF fault interrupt• Voltage regulator — low voltage inhibit interrupt
5.3.4 Interrupt Time Execution and MCU Load Estimation
The time execution of periodic interrupts was measured by oscilloscope. The result can be seen in Figure 5-9.
TIM 0 ch 6 OC Interrupt
(50 ms)
END
of Interrupt RoutineService
Software timers
User interface handling
Battery charging
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Figure 5-9. CPU Load of UPS Application
Trace 1 (blue) represents a PMF reload interrupt; Trace 2 (cyan) is an ATD complete interrupt; Trace 3 shows 1 ms interrupt; Trace 4 (green) is 50 ms. The total MCU load is 65.16%. The execution time of each interrupt can be seen in Table 5-2, and the size code in Table 5-3.
Table 5-2. Execution Time of Periodic Interrupts
Name Execution
PeriodExecution
Time
PMF reload interrupt 50 µs 15.8 µs
ATD conversion complete interrupt 50 µs 14.2 µs
TIM0 CH4 input capture interrupt 8.3 ms or 10 ms 7.8 µs
TIM0 CH5 output compare interrupt 1 ms 50 µs
TIM0 CH6 output compare interrupt 1 ms 35.8 µs
Table 5-3. Size of UPS Application Code
Memory Type Size in Bytes
FLASH 10087
RAM 2502
Stack 512
Trace
Trace
Trace
Trace
PMF Reload Interrupt
ATD Complete Interrupt
1 ms Interrupt
50 ms
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Software Constant Calculations
5.4 Software Constant Calculations
This section describes the calculation of some software constants from real values to software implementation.
5.4.1 PI and PID Controller Constants
Because the MCU works with integer arithmetic only each constant KREAL in the real system is expressed in the software as:
(EQ 5-1)
To keep the maximal precision of calculation, the SCALE should be set in order to push the GAIN into the upper half of the variable range.
Example:
Let’s convert a constant 25 in U16 representation. The upper half of the U16 range is from 32768 to 65536. The get this constant to optimal range we set the SCALE to 5. Then the GAIN = 25 . 2(16-5) = 51200.
NOTENote that the SCALE is shared for all constants in the PI/PID controller. So in case of a highly different order in the constants, a compromise has to be made.
The controller implementation is explained in 3.1.5 PI and PID Controller. From EQ 3-7 results, the proportional constant is equal to the gain of the system.
The integral constant of the controller can be expressed as:
(EQ 5-2)
where
See EQ 3-8. The derivative constants are defined as:
(EQ 5-3)
(EQ 5-4)
TI = Integral time constant
h = Sampling time
K = Controller gain
KREALGAIN
216 SCALE–( )
-----------------------------=
KhTI
-------
kd1TD
TD Nh+---------------------=
kd2KTDN
TD Nh+---------------------=
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where
NOTEThe proportional constant of the output inverter controller is called q1 in the software.
Example:
Let’s have constants for the PFC controller. The PFC uses the PI controller, where the controller gain K(P) = 100 and Integral time constant TI = 0.0016 s. The controller is calculated every 1 ms.
From EQ 5-2 we can calculate integral constant as: .
Since the scale is common for both constants, we choose SCALE = 8. Then we get a proportional gain 100 . 2(16-8) = 25600 and an integral gain 6.25 . 2(16-8) = 1600. In the source code we can see:
#define PFC_P_GAIN_BASE 25600#define PFC_I_GAIN_BASE 1600#define PFC_SCALE 8
h = Sampling time
TD = Derivative time constant
N = Filter constant
100 1 103–⋅ ⋅
0.0016------------------------------- 6.25=
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Chapter 6 Tests and Measurements
6.1 Test Equipment
All tests were done using the following equipment:• 2x multimeter 34401A, Hewlett Packard• Scope TDS3014B, Tektronix• 3-phase precision power meter LMG 310, Zimmer Electronic Systems
6.2 Load Parameters
The parameters were measured for both linear and non-linear loads. The loads were calculated according to standard IEC 62040-1. The reference load was calculated for a nominal output power of 750 VA. The parameters of the loads are:
• Linear load: R = 100 Ω• Non-linear load: R = 160 W, RS = 2.8 W, C = 780 mF (see Figure 6-1)
Figure 6-1. Non-Linear Load
D1
D2
D3
D4
+C1937 uF
P1160
Rs
2.8
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Tests and Measurements
6.3 Test Results
6.3.1 Overall Efficiency at Linear Load
The total efficiency at a linear load is 91%. See Figure 6-2. The picture shows the display of 3-phase precision power meter indicating the input power (P1), output power (P2), losses (LOSS) and calculated efficiency (EFF).
Figure 6-2. Overall Efficiency at Linear Load
Figure 6-3. Output Voltage and Current at Linear Load
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6.3.2 Overall Efficiency at Non-linear Load
The total efficiency at a non-linear load is 90%. See Figure 6-4.
Figure 6-4. Overall Efficiency at Non-linear Load
Figure 6-5. Output Voltage and Current at Non-linear Load
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Tests and Measurements
6.3.3 Output Frequency Measurement
The next two pictures show the generation of output frequency. The left multimeter shows input frequency, and the right one shows output frequency. Figure 6-6 shows the synchronized output with input. Figure 6-7 shows a free running mode. In this case the precision of the output frequency is given by the precision of the MCU crystal.
Figure 6-6. Output Frequency in Synchronized Mode
Figure 6-7. Output Frequency in Free-running Mode
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Test Results
6.3.4 Output Voltage THD
Output voltage THD was measured for three cases:• Without load: THD = 0.4%• With full linear load: THD = 1%• With full non-linear load: THD = 5%
The next two pictures show details of output voltage and current at a non-linear load.
Figure 6-8. Output Voltage and Current at Non-linear Load — Detail
Figure 6-9. Output Voltage and Current at Non-linear Load
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Tests and Measurements
6.3.5 Power Factor Measurement
The power factor measured can be seen in Figure 6-10. The figure shows input voltage U3, input current I3, and power factor λ3.
Figure 6-10. Power Factor Measurement
6.3.6 Response on Step Load
The following four pictures show the response of the output controller a on step load from 20% to 100%, and vice versa, for a linear load.
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Test Results
Figure 6-11. Load Step from 20% to 100%
Figure 6-12. Load Step from 20% to 100% — Detail
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Figure 6-13. Load Step from 100% to 20%
Figure 6-14. Load Step from 100% to 20% — Detail
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Test Results
6.3.7 Summary
All measured parameters are summarized in Table 6-1
Table 6-1. Summary of Measured Parameters
ParameterLoad
Linear Non-linear
Efficiency 91% 90%
Output voltage THD without load 0.4%
Output voltage THD 1% 5%
Power factor 0.99
Precision of generated frequency < 0.01%
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Chapter 7 System Set-Up and Operation
WARNINGThis application operates in an environment that includes dangerous voltages. The application includes batteries and dangerous voltage may appear even if the application is not connected to the mains line.An isolating transformer should be used during debugging. If an isolating transformer is not used, power stage grounds and oscilloscope grounds will be at different potentials, unless the oscilloscope is floating. Note that probe grounds, such as in the case of a floating oscilloscope, are subject to dangerous voltages. Take note of the following points and recommendations
7.1 Hardware Setup
The UPS demo is mounted into a metal case which provides safe operation. The case cover is made from transparent plastic, which allows the UPS construction to be seen (see Figure 7-1).
• Switch off the high-voltage supply before moving scope probes or making connections.
• Avoid inadvertently touching live parts, and use plastic covers where possible.
• When the high voltage is applied, using only one hand to operate the test setup will reduce the possibility of electrical shock.
• Avoid using the application in laboratory environments that have grounded tables or chairs.
• Wear safety glasses, avoid ties and jewelry, use shields, and make use of personnel trained in high-voltage laboratory techniques.
• The power module heatsink can reach temperatures hot enough to cause burns.
• When powering down, due to storage in the bus capacitors, dangerous voltages are present until the power-on LED is off.
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Figure 7-1. UPS DemoWARNING
Do not touch any part of the board inside the metal case regardless of whether the UPS is running from mains line or batteries. There is a high risk of electric shock caused by high voltage, which may cause serious injury or death.
To prepare the UPS for operation, follow these steps:1. Connect the power supply cable to the INPUT LINE socket.2. Connect the load supply cable to any OUTPUT SECTION socket. Be sure that the load power is
within the limit of the UPS demo.3. In the case of remote operation from a PC, connect a serial cable between the PC and the J2
connector of the UPS (on the right-hand side in Figure 7-3 and Figure 7-5).4. Switch MAINS INPUT LINE switch ON.
If the mains line is available, the UPS will go into standby on-line mode. In this mode, the MCU works and the batteries are charged, but the output is still switched off.
5. In the case of remote operation, run the FreeMaster software on the PC and load the project file, UPS.pmp.
The UPS is ready for operation.
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Figure 7-2. UPS Input and Outputs
7.1.1 Setting of Mains Line System
Because the UPS can not detect the mains line system if it starts to run from batteries, the system can be predefined by the START/STOP switch on the MC9S12E128 controller board. If the switch is in the RUN position, the UPS generates outputs 230 V, 50 Hz. In STOP position, the UPS generates 115 V, 60 Hz.
Figure 7-3. UPS Serial Ports and External Battery Connector
MAINS LINESWITCH
MAIN LINEINPUT
OUTPUTSECTION 1
OUTPUTSECTION 2
External BatteryConnector
Serial Ports
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7.2 Software Setup
7.2.1 Application Software Files
The application software files are:• ...\software\UPS\OnlineUPS\on_line_ups.mcp, application project file• ...\software\UPS\OnlineUPS\sources\main.c, main program• ...\software\UPS\OnlineUPS\sources\main.h,
header file for main code• ...\software\UPS\OnlineUPS\sources\PCMaster.c, library of FreeMaster functions• ...\software\UPS\OnlineUPS\sources\PCMaster.h,
library of FreeMaster functions definitions file• ...\software\UPS\OnlineUPS\sources\PCMasterConfig.h,
configuration file for FreeMaster• ...\software\UPS\OnlineUPS\sources\projectglobals.h, global definitions file of HCS12
stationary• ...\software\UPS\OnlineUPS\sources\projectvectors.c, source file of interrupt routines• ...\software\UPS\OnlineUPS\sources\projectvectors.h, header file for interrupt routines• ...\software\UPS\OnlineUPS\sources\START12.C, start up code for HCS12 stationary• ...\software\algorithms\sin.asm,
library with sine wave generation functions• ...\software\algorithms\sin.h,
header file for sine wave generation functions• ...\software\algorithms\sinlut.asm,
sinus look up table for sine wave generation functions• ...\software\algorithms\upsmath.asm,
library of mathematical functions written in assembler• ...\software\algorithms\upsmath.c,
library of mathematical functions written in C language• ...\software\algorithms\upsmath.h,
header file for library of mathematical functions
7.2.2 Application PC Master Software Control Files
The application PC master software control files are:• ...\software\UPS\OnlineUPS\PCMaster\UPS.pmp,
PC master software project file• ...\software\UPS\OnlineUPS\PCMaster\source,
directory with PC master software control page files
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Software Setup
7.2.3 Application Build
To build the online UPS application, open the on_line_ups.mcp project file and execute the Make command, as shown in Figure 7-4. This will build and link the application with all the required Metrowerks libraries.
Figure 7-4. Execute Make Command
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7.2.4 Programming the MCU
Because the UPS power supply is controlled by the MCU, the following sequence must be used to program the MCU:
1. Switch the UPS OFF by the ON/OFF switch2. Switch the MAINS LINE switch to OFF3. Wait one minute until the UPS has totally switched off4. Disconnect the power supply cable from the socket5. Remove the transparent plastic cover6. Disconnect the cable from J4 on the user interface7. Connect a BDM cable to the MC9S12E128 controller board8. Connect the cable to any test point named GND on the UPS power stage (e.g., TP206)9. Load the code to the MCU
10. Remove the cable from GND test point and wait until the UPS has totally switched off11. Connect the cable back to J4 on the user interface12. Re-install the transparent plastic cover
WARNINGThe BDM connector is not galvanically isolated. Therefore, be sure that the UPS is disconnected from the mains line during programming.
7.3 Application Control
The UPS can be controlled by the MAINS LINE switch (Figure 7-2) and by the two ON/OFF or BYPASS buttons. The status of the UPS is indicated by four LEDs and an LED bar graph.
7.3.1 On-line Operation
If the mains line is available and the UPS is set up as is described in 7.1 Hardware Setup, the UPS is in standby on-line mode. To switch the UPS on, quickly push the ON/OFF button. As soon as the button is released the UPS goes into run on-line mode. All UPS outputs are active and the UPS supplies the load. The run on-line mode is indicated by the green status LED. The actual load is indicated by LED bar graph. Optionally, a bypass can be activated by quickly pushing the BYPASS button. In bypass mode the load is connected directly to the mains line. The bypass mode is indicated by the yellow LED.
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Application Control
Figure 7-5. UPS User Interface
In the case of a mains line failure, the UPS automatically goes into run on battery mode. If the UPS is in bypass mode at the moment of the failure, the UPS is switched off. Run on battery mode is indicated by the orange LED and the UPS regularly beeps. If the batteries are discharged the UPS switches the outputs off and goes into standby on battery mode. In this mode the UPS stays for one minute, then switches itself off.
Then user can switch the UPS by pushing the ON/OFF button for more than four seconds, during this time the UPS constantly beeps.
7.3.2 Battery Operation
If the mains line is not available, the UPS goes directly into run-on-battery mode after the ON/OFF button is pressed for less than four seconds and released. The bypass is not available during battery operation. The UPS can be switched off by the user in the same way as in on-line operation. If the mains line is restored during battery operation, the UPS goes automatically into the run on-line mode.
BypassButton
ON/OFFButton
StatusLEDs
LED Bargraph
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 103
System Set-Up and Operation
7.3.3 Remote Operation
If the UPS is connected to the PC it can be controlled by the FreeMaster software. The FreeMaster’s control page offers the same interface, so that the UPS can be controlled from in the same way. The remote control works in parallel with the user interface.
Figure 7-6. UPS Project in FreeMaster
In addition to remote control, the FreeMaster displays the values of some variables. There is also a recorder and scope showing the output voltage and temperature of the power stage.
Single Phase On-Line UPS Using MC9S12E128
104 Freescale Semiconductor
Application Control
Appendix A. Schematics
A.1 Schematics of Power Stage
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 105
1
1
D
C
B
A
e:
Rev
Sheet of
e:
POPI Status:
01
Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
2 10ay, October 01, 2003
00165_01
Motorola General Business2003
Figure 7-7. Block Schematic
5
5
4
4
3
3
2
2
D
C
B
A
+VBAT-VBAT
-VBAT+VBAT
GNDA
+5V_A
GNDA GND
GNDGNDA
+15V
GNDA
GND +5V_A+5V_D
+5V_REF
GND
+15V_PFC
-5V_BOT
GND_PFC
GND_BOT
GND_TOP-5V_TOP
+15V_BOT
+15V_TOP+15V
+5V_A+5V_D
+VBAT
Title
Size
Design File Nam
Modify Date:
Schematic Nam
Copyright Motorola
Author:
750 VA UPS
A3
Wednesd
Pavel Grasblum
L
N
PE
PFC+Inverter
V_D
CB
_B
OT
V_D
CB
_T
OP
V_IN
I_IN
I_O
UT
PF
C_Z
C
TE
MP
V_O
UT
_B
OT
+5V
_D
+5V
_A
V_O
UT
_T
OP
+5V
_R
EF
+15V
FA
ULT
1
GN
DA
GN
D
FA
ULT
0
PWM_TOPPWM_BOT
+15V
_T
OP
GN
D_T
OP
+15V
_B
OT
-5V
_T
OP
GN
D_B
OT
GN
D_P
FC
-5V
_B
OT
+15V
_P
FC
N
L1
RLY_IN
RLY_OUT2RLY_OUT1
OUT1OUT2
N_OUT
PE
FAN+FAN-
FAN_PWM
RLY_BYPASS
L2
DC
B_P
OS
DC
B_N
EG
UN
I-3 P
FC
_E
N
DIV
1D
IV2
DA
0D
A1
J100J101
PSH02_02P
1 2
F100
2A/fast
J109
J110
PSH02_02P
12
F101
FUSE AUTO 40A
1 32 4
Battery Charger
GNDAGND
+5V_A
N
IBAT_CONTROL
IBAT
/POWER_ON
VBAT
+VBAT-VBAT
HV_BAT_LEVEL
L
J103
Control Board Interface
GNDAGND+5V_D+5V_A
PWM10PWM12
TIM14TIM15TIM16TIM17
Fault0
Fault1
AD2
AD4
AD6
AD1
AD3
AD5
UNI-3 DCBI
UNI-3_PWM2UNI-3_PWM3UNI-3_PWM4UNI-3_PWM5
UNI-3 DCBV
UNI-3 PHAIS
+15V
UNI-3 PHCISUNI-3 PFC_EN
UNI-3 PFC_ZC
UNI-3 SERIAL
UNI-3 BEMFZCAUNI-3 BEMFZCCUNI-3 BEMFZCB
DA0DA1
J111
PSH02_02P
12
MH100
PE CONNECTION
J102
DC-DC Step Up
GNDGNDA
+VBAT DCB_NEGDCB_POS
PWM5PWM4
-VBAT
F102
6.3A/fast
Auxiliary Power Supplies
GN
DA
+5V
_D
+5V
_A
GN
D
POWER_EN/POWER_EN
+15V
-5V
_T
OP
GN
D_B
OT
GN
D_P
FC
-5V
_B
OT
GN
D_T
OP
+15V
_B
OT
+15V
_P
FC
+15V
_T
OP
+5V
_R
EF
+VBAT
J107
J104
J105
J108
J106
-5V_TOP
GND_BOT
GND_PFC
-5V_BOT
GND_TOP
+15V_BOT
+15V_PFC
+15V_TOP
-5V_BOT
+15V_TOP
+15V_PFC
-5V_TOP
GND_TOP
+15V_BOT
GND_BOT TP212-5V_BOT
06
V55/15V
/15V
TP213GND_PFC
07V55/5V1
TP209GND_TOP
TP210-5V_TOP
5V
5V1
TP211GND_BOT
Figure 7-8. Auxiliary Power Supplies
GNDA
+5V_D
+5V_A
GND
/POWER_EN
+15V
+5V_REF
+VBAT
POWER_EN
GND
GND GND
+5V_A
+5V_D
GND
GNDA
GND
GND_PFCGND_PFC
GND GND GNDGND GND
GND
GND
+5V_D
GNDA
+5V_A
+15V
GND_BOT
+15V_BOT
GND_TOP
-5V_TOP
+15V_TOP
-5V_BOT
GND_PFC
+15V_PFC
GNDGND
GNDA
+15V
GNDGND GNDGNDGND
+15V
GND
GND
+5V_REF
+15V
GNDA
+5V_REF
GND
GND GNDA
6z.
8z.5z.
8z.
GROUND CONNECTION
U203MC78L05ACP
VIN3
VO1
GN
D2
L202
470uH
TP207
+5V_A
R209
1k
U202LM2575-5
1
2
3
4
5
D204
MMBD914LT1
G
S
D D1
Q201NTF3055 C208
100pF
TP206
GND
C213
100pF
R2142.4k
12
TP208
Vref
D211KA3528LSGT
R207
33
C204
47nF
R201
220
R203
510R
TP201+15V_TOP
R2161.8K
12
D2
BZ
D202
BZV55
D201
LL4448
L204
1u
TP204
+5V_D
R208N/P
T1
TR01/MC145
1
2
12
11
8
7
6
5
+ C210100uF/16V
R204220
D210MBRA140
C200100nF
+ C202100uF/16V
R200510
12
L203
680uH
TP202
+15V_BOT
L200
220uH
+ C206330uF/35V
12
D208
LL4448
R211
220
R21233k
D2BZ
+C214100uF/16V
C205
100pF
TP200
+15V
C201
100pF
R213
100
C211100pF
Q200BC846
R202
15k
C212100pF
C221100nF
+
C21822uF/50V
U200LM2575-ADJ
1
2
3
4
5
+ C207100uF/16V
L205
220uH
R2101.8
+
C22022u/20V
L201
330u
D209
BZV55/1
+
C21622uF/50V
D214KA3528LSGT
D205
LL4448
+
C217220uF/35V
+
C21922u/20V
D203
BZV55/
R205
220
R20616K
+
C215220uF/35V
R21520K
12
C209
100nF
+C203100uF/16V
D213MBRA140
TP203+15V_PFC
U201
UC3843
COMP1
RT/CT4
GND5
ISENSE3
VREF8
VFB2
OUT6
VCC7
1
1
D
C
B
A
VBAT
+VBAT
-VBAT
_BAT_LEVEL
GND
GNDA
Name:
Rev
Sheet of
ame:
POPI Status:
01
PS Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
4 10sday, August 19, 2004
Battery Charger
Motorola General Business
lum
2003
Name:
Rev
Sheet of
ame:
POPI Status:
01
PS Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
4 10sday, August 19, 2004
Battery Charger
Motorola General Business
lum
2003
Name:
Rev
Sheet of
ame:
POPI Status:
01
PS Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
4 10sday, August 19, 2004
Battery Charger
Motorola General Business
lum
2003
27.4V @ Q4 OFF
29.4V @ Q4 ON
5.05V @ 39V
R3105K6R3105K6
R30439kR30439k
R307620R307620
C315
100n
C315
100n
Figure 7-9. Battery Charger
5
5
4
4
3
3
2
2
D
C
B
A
IBAT2
LINE_OK
GND_TR
IBAT1
LINE_OK
IBAT1 IBAT2
GNDA
GND
+5V_A
N
IBAT
/POWER_ON
HV
L
IBAT_CONTROL
GND
GNDA
+5V_A
GND
+5V_A
GND
GND
GND
GND_CH
GND_CH
GND_CH
GND
GND_TR
GND
Title
Size
Design File
Modify Date:
Schematic N
Copyright Motorola
Author:
750 VA U
A3
Thur
Pavel Grasb
Title
Size
Design File
Modify Date:
Schematic N
Copyright Motorola
Author:
750 VA U
A3
Thur
Pavel Grasb
Title
Size
Design File
Modify Date:
Schematic N
Copyright Motorola
Author:
750 VA U
A3
Thur
Pavel Grasb
4.875V @ 2.34A
Q300
BC847
Q300
BC847
R314
100
R314
100
R3191k6R3191k6
D304
1N4148
D304
1N4148
R316220R316220
D307
BAV103
D307
BAV103
R30324kR30324k
sense
sense
R3000.1
sense
sense
R3000.1
R3061MR3061M
C316
100n
C316
100n
C314
N/P
C314
N/P
C309
470nF
C309
470nF
+
C305
220uF/50V
+
C305
220uF/50V
D
G
SQ302MMBF0201NLT1
D
G
SQ302MMBF0201NLT1
C312
10nF/100V
C312
10nF/100V
R3083K6R3083K6
3
21
84
+
-U301AMC33502
+
-U301AMC33502
1
23
4
ISO300SFH615A-2ISO300SFH615A-2
R327
560
R327
560
R3241kR3241k
R3092k4R3092k4
+C30747uF/10V
+C30747uF/10V
4
7 2
5 3
1CONTROL
L
C
XF
U300
TOP249Y
CONTROL
L
C
XF
U300
TOP249Y
TP300
Vbat
TP300
VbatD301BYW29E-200D301BYW29E-200
+
C304
220uF/50V
+
C304
220uF/50VD305BYV26CD305BYV26C
R30168kR30168k
C311
470nF
C311
470nF
L300
47uH
L300
47uH
D303P6KE200
D303P6KE200
-+
D302B250R
-+
D302B250R
C313
100nF/100V
C313
100nF/100V
C300
220n
C300
220n
R3211k6R3211k6
+
C302
220uF/450V
+
C302
220uF/450V
61
8
U302TL431ACDU302TL431ACD
R3231kR3231k
R328
68K
R328
68K
L301
47uH
L301
47uH
R3157.5kR3157.5k
R318
100k
R318
100k
1
7
6
13
5
9
T300
TR02/MC145
T300
TR02/MC145
D309
5V1
D309
5V1
D308
BAV103
D308
BAV103
R3291KR3291K
R31327RR31327R
D300
1N4148
D300
1N4148
R31733KR31733K
C303
100nF
C303
100nF
R325
33K
R325
33K
R312200R312200
R322
220
R322
220
R31133kR31133k
C301
4.7nF
C301
4.7nF
+
C306
100u/50 +
C306
100u/50
D
G
S
Q301MMBF0201NLT1
D
G
S
Q301MMBF0201NLT1
R3021MR3021M
R320
100K
R320
100K
C310
470nF
C310
470nF
R3051k8R3051k8
R331100R331100
C308
100nF
C308
100nF
5
67
+
- U301BMC33502
+
- U301BMC33502
R33010kR33010k
1
1
D
C
B
A
Rev
of
01
znov
R., Czech Republic, Europe
5 10Motorola General Business
Figure 7-10. Control Board Interface
5
5
4
4
3
3
2
2
D
C
B
A
GNDA
GND
+5V_D
+5V_A
PWM10
PWM12
TIM14TIM15TIM16TIM17
Fault0Fault1
AD2AD4AD6
AD1AD3AD5
UNI-3 DCBI
UNI-3_PWM2UNI-3_PWM3UNI-3_PWM4UNI-3_PWM5
UNI-3 DCBVUNI-3 PHAIS+15VUNI-3 PHCIS
UNI-3 PFC_ZCUNI-3 PFC_ENUNI-3 SERIAL
DA0DA1
UNI-3 BEMFZCB UNI-3 BEMFZCCUNI-3 BEMFZCA
GNDA
GND
GNDA
GNDA+5V_A
+5VGND
+5VGND
GND
GNDA
+5V_D
+5V_A
+15V
+5V_D
+15V
+5V_D
GND
GNDA
GNDA
Title
Size
Design File Name:
Modify Date: Sheet
Schematic Name:
Copyright Motorola POPI Status:
Author:
750 VA UPS Power Stage
Motorola MCSL Ro1. maje 1009756 61 Roznov p.
A
Wednesday, October 01, 2003
Control Board Interface
Pavel Grasblum
2003
J401
UNI-3
246810121416182022242628303234363840
13579
111315171921232527293133353739
J400
ADC and DAC HEADER
2468
101214
135791113
J402
FAULTS HEADER
2468
10
13579
J403
PWM and Timer HEADER
1234567891011121314151617181920212223242526
PWM5
502M_5
Figure 7-11. dc/dc Step-Up Converter
-OUT
+OUT
+Bat
GND
GNDA
+VBAT
DCB_NEG
DCB_POS
PWM4
-VBAT
GNDA
GND
GND
GND_BAT
GND_BAT
GND_BAT
GNDA
GND_BAT
GND_BAT
GND_BAT
+15V
GND_BAT
GND_BAT
GND
+15V
GND_BAT
GND_BAT GND_BAT
GND_BAT
GND_BAT
D500
FFPF05U120STU
R500
10
1 2
OutBInB
GND
InA
NC NC
OutA
VCCU500 MC33152D
2
3
5
6
7
81
4
R50910k
12
D
G
S
Q500NTP45N06
+C504
680u/50V
12
+C512
680u/50V
12 R502
1k/5W1 2
C50122n/400V
1 2
C500100n
TP504GNDA
L500330u
L501
650u/1A
+C50947uF
1 2
R503100R/1W
1 2
+C513
680u/50V
12
R506
10
1 2
+C505
680u/50V
12
D504
FFPF05U120STU
L503
330u
R504100R/1W
12
D502FFPF05U120STU
D
G
S
Q502NTP45N06
TP500GND
R5011k/5W
1 2
R507
10
1 2R50810k
12
C511100n
+C502
680u/50V
12
D503
MUR180
D505
FFPF05U120STU
TPPW
C50622n/400V
1 2
+C503
680u/50V
12
OutB InB
GND
InA
NCNC
OutA
VCCU501 MC33152D
2
3
5
6
7
8 1
4
L502
650u/1A
TP501PWM_4
+
C51047uF
1 2
R505
10
1 2
D501
MUR180
D
G
S
Q503NTP45N06
TP503GND_BAT
C5081n
12
T500TR03/MC145
1
4 6
10
13
15
9
18
C507
1n12
D
G
S
Q501NTP45N06
1
1
D
C
B
A
V_OUT_BOT
+5V_D
+5V_A
V_OUT_TOP
+5V_REF
+15V
GNDA
GND
GNDA
+15V
+5V_D
+5V_A
+5V_REF
GNDA
GND
GNDA
e:
Rev
Sheet of
e:
POPI Status:
01
PS Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
7 10arch 08, 2004Motorola General Business2003
Analog_Sensing
V6
R645
1K
1 2
R624
0R
1 2
R672
11K
12
C62233n
Figure 7-12. Analog Sensing Circuits
5
5
4
4
3
3
2
2
D
C
B
A
V_DCB_TOP_DIV
V_DCB_BOT_DIV
V_DCB_TOP_DIV
V_DCB_BOT_DIVV_DCB_BOT
V_DCB_TOPV_IN
I_IN
I_OUT
PFC_ZC
TEMP
FAULT1
FAULT0
GNDA
GNDA
GNDA
GNDAGNDA
+5V_AGNDA
GNDA
GNDA
GNDA
+5V_D
+5V_DGNDA
GNDA
+5V_A
GNDA GNDA
GNDA
+5V_REF
+5V_REF
+5V_REF
GNDA
GNDA
+5V_REF
+5V_REF
+5V_D
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
+5V_A
I_IN1
I_OUT1 I_OUT2
V_INP
DCB_POS
DCB_NEG
V_INP
V_OUT
I_IN2
Title
Size
Design File Nam
Modify Date:
Schematic Nam
Copyright Motorola
Author:
750 VA U
A3
Monday, M
Pavel Grasblum
R646
330k
Q600LM35CA
+Vs3
+Vout2
GN
D1
R654
10k
R632
1K
1 2
+
-U605ALM393D
3
21
84
C600
100n
D614MBR0540
TP600I_OUT
D620
BZV55/3
C62533n
TP607REF_POS
R648
330k
R679
180
D619MBR0540
C613
100n
C623100n
C634
100n
R64911k
R627330k
R63311k
R622470k
R644
10k
C61733n
TP603+DCB_DIV
+
-U605BLM393D
5
67
R635300k
D615MBR0540
TP604
V_IN
R62011k
R616
180
R652
1K
1 2
D616BZV55/5V1
R641
10k
C61210n
D622
BAT42
R615100k
R63633K
-
+
V+
V-
U606D
LM339M
11
10
312
13
D618MBR0540
C616100n
R647
330k
C624100n
TP606
PFC_ZC
R629300k
R623
1K
1 2
TP608TEMP
R628330k
D617BZV55/5V1
R643330k
R619300k
D623
BAT42
R655
10k
R617100k
+ C61422uF
12
+ C61910uF/10V
C62033n
+
-
U604AMC33502D
3
21
84
R637
680k
TP605V_OUT_POS
R638300k
TP602V_OUT_NEG
R626330k
+
-U604BMC33502D
5
67
C626
100n
R678
180
R650
10K
13
2
R62111k
R634300k
C62115n
TP601-DCB_DIV
TP609REF_NEG
D600
1N4007
R642
10k
R625300k
R614
130R
R653
10K
13
2
R651
680k
R60010
1 2
TP610
I_IN
R639300k
R680
33
R618330k
R656
10k
D621
BAT42
R630300kR631
130k
R640
10k
1
1
D
C
B
A
+15V_TOP
GND_TOP
+15V_BOT
-5V_TOP
GND_PFC
-5V_BOT
+15V_PFC
GND
GND_BOT
15V_TOP
15V_BOT
-5V_TOP
GND_TOP
GND_PFC
-5V_BOT
15V_PFC
GND
GND_BOT
Rev
Sheet ofOPI Status:
01
tage
torola MCSL Roznovaje 1009 61 Roznov p. R., Czech Republic, Europe
8 10Motorola General Business
ves
Figure 7-13. PFC and Inverter IGBT Drivers
5
5
4
4
3
3
2
2
D
C
B
A
PWM_TOP
PWM_BOT
GND_BOT
-5V_BOT
GND_TOP
-5V_TOP
+15V_PFC
GND_PFC
+15V_TOP
+15V_BOT
+
+
+
GND
GND
GND_BOT
GATE_PFC
GND_PFC
GATE_TOP
GND_TOP
GATE_BOT
PWM_PFC
Title
Size
Design File Name:
Modify Date:
Schematic Name:
Copyright Motorola P
Author:
750 VA UPS Power S
Mo1. m756
A4
Monday, March 08, 2004
Pavel Grasblum
2003
IGBT_Dri
D62415V
R606
10
C632100nF
D62615V
R613
100
D62815V
R610
100
D613
BAT42
R608
330
D612
MBR0540
U601
HCPL3150
2 7
3 6
5
81
4
R611
330
C611100nF
R607
100
D6255V
C633100nF
D610
MBR0540
C610100nF
R612
33
U615
HCPL-315J
VO210
VEE114
VO115
VCC116
N/C1
ANODE12
CATHODE13
ANODE26
CATHODE27
N/C8
VCC211
VEE29
C609100nF
D609
MBR0540
D611
BAT42
D6275V
R609
33
1
1
D
C
B
A
OUT1
OUT2
N_OUT
PE
V
GND
V
GND
e:
Rev
Sheet of
:
POPI Status:
01
PS Power Stage
Motorola MCSL Roznov1. maje 1009756 61 Roznov p. R., Czech Republic, Europe
9 10arch 08, 2004Motorola General Business2003
Inverter
D605
BAT42
604
nF/Y1
R604
4K7
Q604BC846
o
o
o
RE1MZPA001
5
4
3
1 2
D602
BAT42
Q602BC846
R602
4K7
C6064.7nF/Y1
o
o
o
RE3MZPA001
5
4
3
1 2
Figure 7-14. PFC and Inverter
5
5
4
4
3
3
2
2
D
C
B
A
N
L1
+15V
RLY_IN
RLY_OUT2
FAN+
FAN-
FAN_PWM
GND
RLY_BYPASS
L2
DCB_POS
DCB_NEG
RLY_OUT1
GND
+15V
+15
+15V
GND
+15
+15V
GND
GND
+15V
GND
GND
GATE_PFC
GND_BOT
GATE_BOT
GND_TOP
GATE_TOP
GND_PFC
I_OUT1I_OUT2
DCB_POS
DCB_NEG
V_INP
V_OUT
I_IN1 I_IN2
Title
Size
Design File Nam
Modify Date:
Schematic Name
Copyright Motorola
Author:
750 VA U
A3
Monday, M
Pavel Grasblum
C603
MKP10/22nF/630VDC
D604
RHRP8120
CT1
1:100
9 7
1 2
+C60110u/15V
D607BAT42
L507
TL34P
1
3
2
4
R601
68
C
4.7
Q608
HGTG10N120BND
Q603BC846
C605
3.3uF/400V
D608
RHRP8120
C607
MKP10/22nF/630VDC
ooo
ooo
RE4
MZPA002
75
4 6 8
312
CT2
CS2106
8 5
1 2 3 4
L504
330u
+C602
330uF/450V
Q605
HGTG10N120BND
L506
6mH
D601
MBRS130
Q607BC846
D603
BAT42
R603
4K7
- +
D606KBPC606
G
S
D D1
Q601NTF3055
+ C608330uF/450V
R605
4K7
o
o
o
RE2MZPA001
5
4
3
1 2
L505
2.5mH
Q606IRG4IBC20W
1
1
D
C
B
A
GND
GND
PWM_PFC
Rev
Sheet ofOPI Status:
01
tage
orola MCSL Roznovaje 1009 61 Roznov p. R., Czech Republic, Europe
10 10Motorola General Business
trol
C628100n
D
S0T1
Figure 7-15. PFC Current Control Circuit
5
5
4
4
3
3
2
2
D
C
B
A
DA1
DA0
DIV1 DIV2
UNI-3 PFC_EN
I_IN
GNDA
GNDA GNDA GNDA
GNDA
+5V_D +5V_D
+5V_D
GNDA
GNDA
GNDA GNDA
GND
+5V_A
+5V_A
Title
Size
Design File Name:
Modify Date:
Schematic Name:
Copyright Motorola P
Author:
750 VA UPS Power S
Mot1. m756
A4
Monday, March 08, 2004
Ivan Feno
2003
PFC_Con
85%75%60%
All On 55%
3.3K 10k 9.1k
MMBF0201NLT1 MMBF0201NLT1
R674N/P
R668100
R65910k
R65810k
C63110n
R661
470
R665N/P
R675N/P
TP611
PFC_CTRL
R65733
R6714.7k
D
G
SQ611N/P
R66910k
C62910n
-
+
V+
V-
U606B
LM339M
7
6
312
1
-
+
V+
V-
U606A
LM339M
5
4
312
2
C627
100n
R673N/P
R662
470
R6641.6k
R67010k
R666
N/P
D
G
SQ609MMBF0201NLT1
C630N/P
R667
0
G
Q61MMBF0201NL
R663100
R660
10k
D
G
SQ612N/P
-
+
V+
V-
U606C
LM339M
9
8
312
14
Application Control
A.2 Schematics of User Interface
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 115
1
1
D
C
B
A
BEEP
LED_ON
LED_BAT
LED_BYPASS
D_FAULT
GND
GND
GND
GND
GND
Rev
Sheet ofPOPI Status:
01
otorola MCSL Roznov maje 10096 61 Roznov p. R., Czech Republic, Europe
1 103Motorola General Business
R1
1300
BZ1
SA003
D4
L53LYD
R3
1300
R7
1300
D3
L53ND
D2
L53LGD
D1
L53LID
R5
270
Figure 7-16. UPS User Interface
5
5
4
4
3
3
2
2
D
C
B
A
LE
LED_LEV1
LED_LEV2
LED_LEV3
LED_LEV4
LED_LEV5
LED_LEV6
LED_ON
LED_LEV6
LED_LEV1
BT_ON/OFF
BEEP
LED_BATBT_BYPASS
LED_LEV4LED_LEV2
BT_BYPASS
BT_ON/OFF
LED_BYPASS
LED_LEV3
LED_FAULT
LED_LEV5
+5V_D
GND
GND
+5V_D
+5V_D
GND
+5V_D
GND
+5V_D
GND GND GND GND GND GND
Title
Size
Design File Name:
Modify Date:
Schematic Name:
Copyright Motorola
Author:
UPS 750 VA User Interface
M1.75
A4
Wednesday, September 10, 20
00165B01
Pavel Grasblum
2003
SW1
Switch/P-0SYB
J4PSH02_02W
12
SW2
Switch/P-0SEB
R10
1300
R6
1300
R210k
R9
1300
D5
L53LID
D8
L53LGD
R11
1300
J2
CON/CANNON9
594837261
J6
HEADER 5X2
246810
13579
R12
1300
R410k
D6
L53LGD
R8
1300
D9
L53LGD
D10
L53LID
D7
L53LGD
J5
CON/CANNON9
594837261
J3
HEADER 5X2
246810
13579
J1
HEADER 13x2
1234567891011121314151617181920212223242526
Application Control
A.3 Schematics of Input Filter
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 117
1
1
D
C
B
A
Rev
of
01
znov
., Czech Republic, Europe
2 2
otorola General Business
L_OUT
N_OUT
PEMH1
GROUND CONNECTION
J103
J104
5
5
4
4
3
3
2
2
D
C
B
A
Title
Size
Design File Name:
Modify Date: Sheet
Schematic Name:
Copyright Motorola POPI Status:
Author:
750 VA UPS Input Filter
Motorola MCSL Ro1. maje 1009756 61 Roznov p. R
A
Monday, September 15, 2003
00165C01
M
Pavel Grasblum
2003
L
N
PE
J100
MH2
GROUND CONNECTION
L100
TL34P
1
3
2
4
R100
SG-190
J102
C100B
1uF/X1
C102
4.7nF/Y1
C100
100nF/X1
C101
100nF/X1
R102
SIOV-S20K275
R101
SIOV-S20K275J101
C103
4.7nF/Y1
R103330k
Application Control
A.4 Parts List of UPS Power Stage
Table A-1. Parts List of UPS Power Stage (Sheet 1 of 5)
Reference Qty Description Manufacturer Part number
CT1 1current transformer — custom design
TRONIC 3044202
CT2 1 current transformer COILCRAFT CS2106
C200, C209, C221, C303, C308, C610, C611, C632, C633
9 100-nF ceramic SMD 0805 any available
C201, C205, C208, C211, C212, C213 6 100-pF ceramic SMD 0805 any available
C202, C203, C207, C210, C214 5100-µF/16-V radial electrolytic 5 x 11 mm
any available
C204 1 47-nF ceramic SMD 0805 any available
C206 1330-µF/35-V radial electrolytic 10 x 20 mm
any available
C215, C217 2220-µF/35-V radial electrolytic 10 x 20 mm
any available
C216, C218 2 22-µF/50-V 5 x 11 mm any available
C219, C220 2 22-µ/20-V tantalum size D any available
C300 1 220n ceramic SMD 0805 any available
C301 1 4.7-nF polyester Vishay MKT1820
C302 1 220-µF/450-V electrolytic EPCOS B43504
C304, C305 2 220-µF/50-V electrolytic Rubycon ZL series
C306 1 100-µ/50-V electrolytic Jamicon
C307 1 47-µF/10-V electrolytic Jamicon
C309, C310, C311 3 470-nF ceramic SMD 0805 any available
C312 1 10-nF/100-V ceramic any available
C313 1 100-nF/100-V ceramic any available
R208, C314, C630, R665, R666, R673, R674, R675
8 no populated -
C315, C316, C600, C613, C616, C623, C624, C626, C627, C628, C634
11 100n ceramic SMD 0805 any available
C500, C511 2 100n ceramic SMD 1206 any available
C501, C506 2 22n/400-V metallized WIMA MKP10
C502, C503, C504, C505, C512, C513 6 680µ/50-V Rubycon ZL series
C507, C508 2 1n/100-V WIMA MKS 2
C509, C510 247-µF/25-V radial electrolytic 5 x 11 mm
any available
C601 1 10-µ/15-V tantalum size D any available
C602, C608 2 330-µF/450-V electrolytic EPCOS B43504
C603, C607 2 22-nF/630-Vdc WIMA MKP10
C604, C606 2 4.7-nF/Y1 any available
C605 1 3.3-µF/400-V WIMA MKP10
C609 1 100-nF ceramic SMD 1206 any available
C612, C629, C631 3 10n ceramic SMD 0805 any available
C614 122-µF/16-V radial electrolytic 5 x 11 mm
any available
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 119
System Set-Up and Operation
C617, C620, C622, C625 4 33n ceramic SMD 0805 any available
C619 110-µF/25-V radial electrolytic 5 x 11 mm
any available
C621 1 15n ceramic SMD 0805 any available
D201,D205,D208, D304 4 LL4448 signal diode Fairchild LL4448
D202,D206,D209 3 zener diode 15-V Philips BZV55/15V
D203,D207,D616,D617 4 zener diode 5.1-V Philips BZV55/5V1
D204 1 high-speed switching diode ON Semiconductor MMBD914LT1
D210,D213 2 schottky diode ON Semiconductor MBRA140
D211,D214 2 LED diode SMD green Kingbright KA3528SGT
D300 1 high-speed diode Philips 1N4148
D301 1 ultra fast diode Vishay BYW29E-200
D302 1 bridge rectifierDiotec Semiconductor
B250R
D303 1 transient voltage suppressor Vishay P6KE200
D305 1 ultra fast diode Vishay BYV26C
D307,D308 2 general purpose diode Philips BAV103
D309 1 zener diode 5V1 Philips BZV55/5V1
D500,D502,D504,D505 4 fast recovery diode Fairchild FFPF05U120STU
D501,D503 2 ultra fast diode ON Semiconductor MUR180
D600 1 diode Philips 1N4007
D601 1 schottky diode ON Semiconductor MBRS130
D602,D603,D605,D607,D611,D613,D621,D622,D623
9 schottky diode Philips BAT42
D604,D608 2 hyperfast diode Fairchild RHRP8120
D606 1 bridge rectifierDiotec Semiconductor
KBPC606
D609,D610,D612,D614,D615,D618,D619
7 schottky diode ON Semiconductor MBR0540
D620 1 zener diode 3V6 Philips BZV55/3V6
D624,D626,D628 3 zener diode 15 V Philips BZV55/15V
D625,D627 2 zener diode 5.1 V Philips BZV55/5V1
F100 1 fast fuse 2 A any available
F101 1 car fuse 40 A any available
F102 1 fast fuse 6.3 A any available
ISO300 1 optocupler Vishay SFH615A-2
J100,J102,J103,J104,J105,J106,J107,J108,J109
9 FASTON
J101,J110,J111 3 connector EZK (distributor) PSH02_02P
J400 1 header 7 x 2 any available
J401 1 connector EZK (distributor) PFL_20X2
J402 1 header 5 x 2 any available
J403 1 header 13 x 2 any available
L200,L205 2 220-µH axial inductor 130 mA FASTRON
Table A-1. Parts List of UPS Power Stage (Sheet 2 of 5)
Reference Qty Description Manufacturer Part number
Single Phase On-Line UPS Using MC9S12E128
120 Freescale Semiconductor
Application Control
L201,L500,L503,L504 4 330µ radial inductor 500 mA FASTRON
L202 1 470 µH FASTRON 09P/F-471k
L203 1 680 µH FASTRON 09P/F-681k
L204 1 1-µ axial inductor 1.2 A FASTRON
L300,L301 2 radial inductor 47 µH Coilcraft PCV-1-473-03
L501, L502 2 560µ / 1 A Coilcraft PCV-2-564-02
L505 1 2.5 mH custom design see 4.5.2.1
L506 1 5 mH custom design see 4.5.4.2
L507 1 toroid choke Tesla Blatna TL34P
Q200, Q602, Q603, Q604, Q607 5 general-purpose bipolar transistor ON Semiconductor BC846
Q201, Q601 2 Power MOSFET transistor ON Semiconductor NTF3055
Q300 1 general-purpose bipolar transistor ON Semiconductor BC847
Q301, Q302, Q609, Q610 4 Power MOSFET transistor ON Semiconductor MMBF0201NLT1
Q500, Q501, Q502, Q503 4 Power MOSFET transistor ON Semiconductor NTP45N06
Q600 1 temperature sensorNational Semiconductor
LM35CA
Q605, Q608 2 IGBT Fairchild HGTG10N120BND
Q606 1 IGBTInternational Rectifier
IRG4IBC20W
Q611, Q612 2 no populated
RE1, RE2, RE3 3 relay CARLO GAVAZZI MZPA001
RE4 1 relay CARLO GAVAZZI MZPA002
R200, R203 2 510 SMD 0805 any available
R201, R204, R205, R211, R316, R322 6 220 SMD 0805 any available
R202 1 15k SMD 0805 any available
R206 1 16k SMD 0805 any available
R207, R657, R680 3 33 SMD 0805 any available
R209, R323, R324, R329, R623, R632, R645, R652
8 1k SMD 0805 any available
R210 1 1.8 SMD 0805 any available
R212, R317, R325 3 33k SMD 0805 any available
R213, R314, R331, R663, R668 5 100 SMD 0805 any available
R214 1 2.4k SMD 0805 any available
R215 1 20k SMD 0805 any available
R216 1 1.8k SMD 0805 any available
R300 1 precision shunt resistorIsabellenhütte Heusler GmbH KG
PMA-C - R100 - 1
R301 1 68k, 2W any available
R302, R306 2 1M size 0207 any available
R303 1 24k SMD 0805 any available
R304 1 39k SMD 0805 any available
R305 1 1k8 SMD 0805 any available
R307 1 620 SMD 0805 any available
R308 1 3K6 SMD 0805 any available
Table A-1. Parts List of UPS Power Stage (Sheet 3 of 5)
Reference Qty Description Manufacturer Part number
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 121
System Set-Up and Operation
R309 1 2k4 SMD 0805 any available
R310 1 5K6 SMD 0805 any available
R311, R636 2 33k, size 0207 any available
R312 1 200 SMD 0805 any available
R313 1 27R SMD 0805 any available
R315 1 7.5k SMD 0805 any available
R318, R320, R615, R617 4 100k SMD 0805 any available
R319, R321 2 1k6 SMD 0805 any available
R326 1 3k9 SMD 0805 any available
R327 1 560 SMD 0805 any available
R328 1 68k SMD 0805 any available
R330, R508, R509, R640, R641, R642, R644, R654, R655, R656, R658, R659, R660, R669, R670
15 10k SMD 0805 any available
R500, R505, R506, R507, R606 5 10 SMD 1206 any available
R501, R502 2 1-k/5-W any available
R503, R504 2 100R/1W any available
R600 1 10 SMD 0805 any available
R601 1 68 SMD 0805 any available
R602, R603, R604, R605 4 4K7 SMD 0805 any available
R607, R610, R613 3 100 SMD 1206 any available
R608, R611 2 330 SMD 0805 any available
R609, R612 2 33 SMD 1206 any available
R614 1 130RSMD 0805 any available
R616, R678, R679 3 180 SMD 1206 any available
R618, R626, R627, R628, R643, R646, R647, R648
8 330k size 0207 any available
R619, R625, R629, R630, R634, R635, R638, R639
8 300k size 0207 any available
R620, R621, R633, R649, R672 5 11k SMD 0805 any available
R622 1 470k size 0207 any available
R624, R667 2 0R SMD 0805 any available
R631 1 130k size 0207 any available
R637, R651 2 680k SMD 0805 any available
R650, R653 2 10k SMD 4315 any available
R661, R662 2 470 SMD 0805 any available
R664 1 1.6k SMD 0805 any available
R671 1 4.7k SMD 0805 any available
T1 1 transformer customer design see 4.3.1
T300 1 transformer customer design see 4.2.4
T500 1 transformer customer design see 4.4.2.1
U200 1 switching regulator ON Semiconductor LM2575-ADJ
U201 1 switching regulator ON Semiconductor UC3843
U202 1 switching regulator ON Semiconductor LM2575-5
Table A-1. Parts List of UPS Power Stage (Sheet 4 of 5)
Reference Qty Description Manufacturer Part number
Single Phase On-Line UPS Using MC9S12E128
122 Freescale Semiconductor
Application Control
A.5 Parts List of User Interface
U203 1 linear regulator ON Semiconductor MC78L05ACP
U300 1 switching regulator Power Integrations TOP249Y
U301, U604 1 operational amplifier ON Semiconductor MC33502
U302 1 voltage reference Fairchild TL431ACD
U500,U501 2 MOSFET driver ON Semiconductor MC33152D
U601 1 opto driver Agilent HCPL3150
U605 1 dual comparators ON Semiconductor LM393D
U606 1 quad comparators ON Semiconductor LM339M
U615 1 opto driver Agilent HCPL-315J
Table A-2. Parts List of User Interface
Reference Qty Description Manufacturer Part number
BZ1 1 buzzer EZK (distributor) SA003
D1, D10 3 LED diode red Kingbright L53LID
D2,D5,D6,D7,D8,D9 6 LED diode green Kingbright L53LGD
D3 1 LED diode orange Kingbright L53ND
D4 1 LED diode yellow Kingbright L53LYD
J1 1 header 13 x 2 any available
J2,J5 2 connector CANNON 9 pin any available
J3,J6 2 header 5 x 2 any available
J4 1 connector any available
R1, R3, R6, R7, R8, R9, R10, R11, R12 9 1300 SMD 0805 any available
R2, R4 2 10k SMD 0805 any available
R5 1 270 SMD 0805 any available
SW1 1 Switch MECswitch 15501extender 16250cap 1D06
SW2 1 Switch MECswitch 15501extender 16250cap 1D02
Table A-1. Parts List of UPS Power Stage (Sheet 5 of 5)
Reference Qty Description Manufacturer Part number
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 123
System Set-Up and Operation
A.6 Parts List of Input Filter
Table A-3. Parts List of Input Filter
Reference Qty Description Manufacturer Part number
C100B 1 1−µF / X1 EPCOS B81133
C100, C101 2 100-nF / X1 EPCOS B81133
C102, C103 2 4.7-nF / Y1 MURATA DE2E3KH472MA3B
J100,J101,J102,J103,J104 5 faston 6.3 mm any available
L100 1 toroid choke Tesla Blatna TL34P
R100 1 inrush current limiterRhopoint Components
SG-190
R101, R102 2 EPCOS SIOV-S20K275
R103 1 330k, 0.6 W any available
Single Phase On-Line UPS Using MC9S12E128
124 Freescale Semiconductor
Application Control
Single Phase On-Line UPS Using MC9S12E128
Appendix B. References
1. Feno, I.: Analysis and Synthesis of the IGBT switching techniques and verification in Partial Series Resonant Converter. Ph.D. Dissertation, University of Zilina, Faculty of Electrical Engineering, August 2003.
2. A More Realistic Characterization Of Power MOSFET Output Capacitance Coss. Application Note AN-1001, International Rectifier.
3. Billings, K.: Switchmode Power Supply Handbook, second edition. McGraw-Hill, 1999.4. Pressman, A. I.: Switching Power Supply Design, second edition, McGraw-Hill, 1998.5. International Standard IEC62040-1-1, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in operator access areas.6. International Standard IEC62040-1-2, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in restricted access locations.7. International Standard IEC62040-2, Uninterruptable power systems (UPS) - Part 2:
Electromagnetic compatibility (EMC) requirements.8. International Standard IEC62040-3, Uninterruptable power systems (UPS) - Part 3: Method of
specifying the performance and test requirements.9. YUASA NP valve regulated lead acid battery manual. Yuasa Battery GMBH, 1999.
10. TOP242-250 Up to 290 W Extended power, design flexible, EcoSmart, integrated off-line switcher family, data sheet. Power Integrations, August 2003
11. AN-18, TOPSwitch Flyback Transformer Construction Guide. Power Integrations, 1996.12. AN-16, TOPSwitch Flyback Design Methodology. Power Integrations, 1996.13. MC9S12E-Family Device User Guide, data sheet. Motorola, 2003.14. HCS12 CPU V2.0 Reference Manual, Reference Manual. Motorola, 2003.15. HCS12 10-Bit, 16-Channel Analog to Digital Converter (ATD) Block Guide. Reference Manual.
Motorola, 2003.16. HCS12 Background Debug Module Block Guide. Reference Manual. Motorola, 2003.17. HCS12 Clocks and Reset Generator (CRG) Block Guide. Reference Manual. Motorola, 2003.18. Digital-to-Analog Converter: 8-Bit, 1-Channel. Reference Manual. Motorola, 2003.19. Debug Module. Reference Manual. Motorola, 2003.20. Port Integration Module: 9S12E128. Reference Manual. Motorola, 2003.21. HCS12 128K FLASH Block Guide. Reference Manual. Motorola, 2003.22. HCS12 Inter-Integrated Circuit (IIC) Block Guide. Reference Manual. Motorola, 2003.23. Interrupt (INT) Module V1 Block User Guide. Reference Manual. Motorola, 2003.24. Multiplexed External Bus Interface (MEBI) Module V3 Block User Guide. Reference Manual.
Motorola, 2003.25. Module Mapping Control (MMC) V4 Block User Guide. Reference Manual. Motorola, 2003.26. HCS12 Oscillator Block Guide. Reference Manual. Motorola, 2003.27. Pulse Modulator with Fault Protection: 15-Bit, 6-Channel. Reference Manual. Motorola, 2003.28. HCS12 8-Bit, 6-Channel Pulse Width Modulator (PWM) Block Guide. Reference Manual. Motorola,
2003.29. HCS12 Serial Communications Interface (SCI) Block Guide. Reference Manual. Motorola, 2003.30. HCS12 Serial Peripheral Interface (SPI) Block Guide. Reference Manual. Motorola, 2003.31. Timer: 16-Bit, 4-Channel. Reference Manual. Motorola, 2003.32. Voltage Regulator 3V3 Block User Guide V2. Reference Manual. Motorola, 2003.33. MC9S12E128 Controller Board, Design Reference Manual, Motorola 2004
Freescale Semiconductor 125
System Set-Up and Operation
Single Phase On-Line UPS Using MC9S12E128
126 Freescale Semiconductor
Application Control
Appendix C. Glossary
ac alternating current
ac/dc converter a converter that converts alternating voltage (ac) to direct voltage (dc)
ATD analog-to-digital converter
A/D analog-to-digital
AVR automatic voltage regulation
CW CodeWarrior; compilers produced by Metrowerks
DAC digital-to-analog converter
dc direct current
dc/ac converter a converter that converts direct voltage (dc) to alternating voltage (ac)
dc/dc converter converter that converts one level of direct voltage to another level of direct voltage
DT dead time; a short time that must be inserted between turning off one transistor in the inverter half-bridge and turning on the complementary transistor, to allow for the limited switching speed of the transistors.
duty cycle the ratio of the time the signal is on to the time it is off. Duty cycle is usually quoted as a percentage.
EMC electro magnetic compatibility
EMI electro magnetic interference
IC integrated circuit
IDE integrated development environment
IGBT Insulated gate bipolar transistor
input/output (I/O) input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal.
interrupt a temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine.
logic 1 a voltage level approximately equal to the input power voltage (VDD)
logic 0 a voltage level approximately equal to the ground voltage (VSS)
HCS12 a Freescale Semiconductor family of 16-bit MCUs
MCU microcontroller unit; a complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit
Single Phase On-Line UPS Using MC9S12E128
Freescale Semiconductor 127
System Set-Up and Operation
MW Metrowerks Corporation
PC personal computer
PCB printed circuit board
PCM PC master software for communication between PC and system
PFC power factor correction
PI Controller proportional-integral controller
PID Controller proportional-integral-derivative controller
PLL phase-locked loop; a clock generator circuit in which a voltage controlled oscillator produces an oscillation that is synchronized to a reference signal
PMP FreeMaster software project file
PVAL PWM value register of motor control PWM module of the MC9S12E128 microcontroller; it defines the duty cycle of the generated PWM signal.
PWM pulse width modulation
RESET to force a device to a known condition
RMS root mean square
SCI serial communications interface module; a module that supports asynchronous communication
SMPS switched mode power supply
software instructions and data that control the operation of a microcontroller
SPI serial peripheral interface module; a module that supports synchronous communication
SWI software interrupt; an instruction that causes an interrupt and its associated vector fetch
THD total harmonic distortion
timer A module used to relate events in a system to a point in time
UPS uninterruptable power supply
Single Phase On-Line UPS Using MC9S12E128
128 Freescale Semiconductor
DRM064Rev. 0, 09/2004
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