single phase sine pwm inverter using tms320f2812

5/26/2018 Single Phase Sine PWM Inverter Using TMS320F2812

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DSP HOW-TO GUIDE

Single Phase SINE PWM

INVERTER in TMS320F2812

DSP Kit


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Contents at a Glance

ABSTRACT ....................................................................... 4

1. BLOCK DIAGRAM ....................................................... 5

2. DSCTMS320F2812 .................................................. 5

3. TMS320F2812 ARCHITECTURE ................................... 6

3.1. C28x CPU .................................................................. 7

3.2. Memory Bus (Harvard Bus Architecture) ................... 8

3.3. General-Purpose Input/Output (GPIO) Multiplexer .... 9

3.4. 32-Bit CPU-Timers (0, 1, 2) ......................................... 9

3.5. Control Peripherals ................................................. 10

4. EVENT MANAGER ................................................... 11

4.1. Event Manager Architecture .................................... 11

4.2. PWM Characteristics ............................................... 12

4.3. Capture Unit ........................................................... 13

4.4. General-Purpose (GP) Timers .................................. 14

4.5. Full-Compare Units ................................................. 17

4.6. Programmable Deadband Generator ....................... 17


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4.7.EV Registers ............................................................. 18

5. PWM Waveform Generation .................................... 19

5.1. PWM ...................................................................... 19

5.1. How to Generate PWM ........................................... 19

5.2. Generation of PWM Output with Event Manager .... 20

5.2.1 Asymmetric and Symmetric PWM Generation ....... 21

5.2.2 Register Setup for PWM Generation ...................... 22

5.2.3 Asymmetric PWM Waveform Generation .............. 22

5.2.4 Symmetric PWM Waveform Generation ................ 24

5.3. Why Deab Band ...................................................... 26

6. Sinusoidal PWM ....................................................... 27

7. Single Phase Sine PWM Inverter ............................... 34

7.1. Program flow chart: ............................................... 35


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ABSTRACT

This Single Phase PWM Inverter Speed drive control implemented with hardware setup and software program in

code. Inverters are used in a wide range of applications, fro

small switching power supplies in computers, to large electr

utility applications that transport bulk power. The main featu

used in microcontroller is their peripherals to realize sinusoid

pulse width modulation (SPWM).

The main feature used in DSC microcontroller is their periphera

to realize pulse width modulation. This brings low cost, small siz

and flexibility to change the control algorithm without changes

hardware.


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1. BLOCK DIAGRAM

2. DSC TMS320F2812The Digital Signal Controller (DSC) TMS320F2812 of TEXA

Instrument is used for the implementation of the inverte

TMS320F2812 is a Digital Signal Controller from the C200

Platform and members of the TMS320C28x DSP generation, a

highly integrated, high-performance solutions for demandin

control applications. The TYRO TMS320F2812 EVALUATIO

BOARD is specially desgined for developers in dsp field as well

beginners. The F2812 kit is designed in such way that all th

possible features of the DSP will be easily used by the everyone.

The kit supports in Code Composer Studio3.3 and later, with

XDS100 v1 USB Emulator which is done USB port.


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3. TMS320F2812 ARCHITECTURE


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3.1. C28x CPU

The C28x DSP generation is the newest member of th

TMS320C2000 DSP platform.

The C28x is as efficient in DSP math tasks as it is in syste

control tasks that typically are handled by microcontroll

devices. This efficiency removes the need for a second processo

in many systems.

The 32 x 32-bit MAC capabilities of the C28x and its 64-b

processing capabilities, enable the C28x to efficiently hand

higher numerical resolution problems that would otherwis

demand a more expensive floating-point processor solution. Ad

to this the fast interrupt response with automatic context save

critical registers, resulting in a device that is capable of servicin

many asynchronous events with minimal latency.

The C28x has an 8-level-deep protected pipeline wi

pipelined memory accesses. This pipelining enables the C28x t

execute at high speeds without resorting to expensive high-spee

memories. Special branch-look-ahead hardware minimizes th

latency for conditional discontinuities. Special store condition

operations further improve performance.


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3.2. Memory Bus (Harvard Bus Architecture)

The program read bus consists of 22 address lines and 3

data lines. The data read and write busses consist of 32 addre

lines and 32 data lines each. The 32-bit-wide data busses enab

single cycle 32-bit operations. The multiple bus architectur

commonly termed Harvard Bus, enables the C28x to fetch a

instruction, read a data value and write a data value in a sing

cycle. All peripherals and memories attached to the memory buwill prioritize memory accesses. Generally, the priority of Memor

Bus accesses can be summarized as follows:

Highest:

Data Writes (Simultaneous data and program writes cannot occon the memory bus.)

Program Writes (Simultaneous data and program writes cann

occur on the memory bus.)

Data Reads & Program Reads (Simultaneous program reads an

fetches cannot occur on the memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cann

occur on the memory bus.)


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3.3. General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with genera

purpose I/O (GPIO) signals. This multiplexing enables use of a p

as GPIO if the peripheral signal or function is not used. On rese

all GPIO pins are configured as inputs. The user can the

individually program each pin for GPIO mode or peripheral sign

mode. For specific inputs, the user can also select the number

input qualification cycles to filter unwanted noise glitches.

3.4. 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers wit

presettable periods and with 16-bit clock prescaling. The time

have a 32-bit count-down register, which generates an interru

when the counter reaches zero. The counter is decremented

the CPU clock speed divided by the prescale value setting. Whe

the counter reaches zero, it is automatically reloaded with a 3

bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Rea

Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is nbeing used, CPU-Timer 2 is available for general use. CPU-Timer


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is for general use and can be connected to INT13 of the CPU. CPU

Timer 0 is also for general use and is connected to the PIE block.

3.5. Control Peripherals

The F281x and C281x support the following peripherals th

are used for embedded control and communication:

EV: The event manager module includes

a)general-purpose timers,b)full-compare/PWM units,c)capture inputs (CAP) andd)quadrature-encoder pulse (QEP) circuits.Two such event managers are provided which enable tw

three-phase motors to be driven or four two-phase motors. Thevent managers on the F281x and C281x are compatible to th

event managers on the 240x devices (with some mino

enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 1

channels. It contains two sample-and-hold units for simultaneousampling.


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4. EVENT MANAGER

4.1. Event Manager Architecture


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4.2. PWM Characteristics

Characteristics of the PWMs are as follows:

16-bit registers

Wide range of programmable deadband for the PWM outp

pairs

Change of the PWM carrier frequency for PWM frequen

wobbling as needed

Change of the PWM pulse widths within and after each PW

period as needed

External-maskable power and drive-protection interrupts

Pulse-pattern-generator circuit, for programmable generation asymmetric, symmetric, and four-space vector PWM waveforms

Minimized CPU overhead using auto-reload of the compare an

period registers

The PWM pins are driven to a high-impedance state when th

PDPINTx pin is driven low and after PDPINTx signal qualificatioThe PDPINTx pin (after qualification) is reflected in bit 8 of th

COMCONx register.


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PDPINTA pin status is reflected in bit 8 of COMCONA register.

PDPINTB pin status is reflected in bit 8 of COMCONB register.

EXTCON register bits provide options to individually trip contr

for each PWM pair of signals

4.3. Capture Unit

The capture unit provides a logging function for differe

events or transitions. The values of the selected GP timer count

is captured and stored in the two-level-deep FIFO stacks whe

selected transitions are detected on capture input pins, CAPx (x

1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture un

consists of three capture circuits.

Capture units include the following features:

One 16-bit capture control register, CAPCONx (R/W)

One 16-bit capture FIFO status register, CAPFIFOx

Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the timbase

Three 16-bit 2-level-deep FIFO stacks, one for each capture uni


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Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 f

EVB)one input pin per capture unit.

[All inputs are synchronized with the device (CPU) clock. In orde

for a transition to be captured, the input must hold at its curre

level to meet the input qualification circuitry requirements. Th

input pins CAP1/2 and CAP4/5 can also be used as QEP inputs t

the QEP circuit.]

User-specified transition (rising edge, falling edge, or bot

edges) detection

Three maskable interrupt flags, one for each capture unit

The capture pins can also be used as general-purpose interru

pins, if they are not used for the capture function.

4.4. General-Purpose (GP) Timers

There are two GP timers in each EV module. The GP timer

x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

A 16-bit timer-compare register, TxCMPR (double-buffere

with shadow register), for reads or writes


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A 16-bit timer-period register, TxPR (double-buffered wit

shadow register), for reads or writes

A 16-bit timer-control register,TxCON, for reads or write

Selectable internal or external input clocks

A programmable prescaler for internal or external cloc

inputs Control and interrupt logic, for four maskable interrupt

underflow, overflow, timer compare, andperiod interrupts

A selectable direction input pin (TDIRx) (to count up or dow

when directional up-/down-count mode is selected)

The GP timers can be operated independently

synchronized with each other. The compare register associate

with each GP timer can be used for compare function and PWM

waveform generation. There are three continuous modes

operations for each GP timer in up- or up/down-countin

operations. Internal or external input clocks with programmab

prescaler are used for each GP timer. GP timers also provide th

time base for the other eventmanager submodules: GP timer 1 fo

all the compares and PWM circuits, GP timer 2/1 for the captu

units and the quadrature-pulse counting operations. Doubl

buffering of the period and compare registers allowprogrammable change of the timer (PWM) period and th

compare/PWM pulse width as needed.


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Mainly The following registers are must to produce simp

pwm.

TxCNT - Timer x Counter Register

TxCMPR - Timer x Compare Register

TxPR - Timer x Period Register

TxCON - Timer x Control Register

Example: C code to generate the simple 10Khz Pwm.

void main(void)

{

InitSystem();

EALLOW;

GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 1;

EDIS;

DINT;

IER = 0x0000;IFR = 0x0000;

EvaRegs.GPTCONA.bit.TCMPOE = 1; // Drive T1/T2 PWM by compare logic

EvaRegs.GPTCONA.bit.T1PIN = 1; // Polarity of GP Timer 1 Compare = Active lo

EvaRegs.T1PR = 0x186A; // Timer1 period for 10 Khz

EvaRegs.T1CMPR = 0x0C35; // Timer1 compare 50 % duty cycle

EvaRegs.T1CNT = 0x0000; // Timer1 counter

EvaRegs.T1CON.all = 0x1042; // TMODE = continuous up mode & enable ti

for(;;);

}

Note: Period Register Formula will be available atchapter
http://localhost/var/www/apps/conversion/tmp/scratch_1/Period%20register.bmphttp://localhost/var/www/apps/conversion/tmp/scratch_1/Period%20register.bmphttp://localhost/var/www/apps/conversion/tmp/scratch_1/Period%20register.bmphttp://localhost/var/www/apps/conversion/tmp/scratch_1/Period%20register.bmp


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4.5. Full-Compare Units

There are three full-compare units on each event manage

These compare units use GP timer1 as the time base and genera

six outputs for compare and PWM-waveform generation usin

programmable deadband circuit. The state of each of the s

outputs is configured independently.

The compare registers of the compare units are doubl

buffered, allowing programmable change of the compare/PW

pulse widths as needed. These are compare register

T1CMPR,T2CMPR,CMPR1,CMPR2,CMPR3,T3CMPR,T4CMPR,CMP

4,CMPR5,CMPR6.

4.6. Programmable Deadband Generator

The deadband generator circuit includes three 4-bit counte

and an 16-bit compare register. Desired deadband values can b

programmed into the compare register for the outputs of th

three compare units. The deadband generation can b

enabled/disabled for each compare unit output individually. Th

deadband-generator circuit produces two outputs (with

without deadband zone) for each compare unit output signal.


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The output states of the deadband generator a

configurable and changeable as needed by way of thedoubl

buffered ACTRx register.

These are Deaband registers:DBTCONA,DBTCONB

4.7.EV Registers

The EV registers occupy two 64-word (16-bit) frames

address space. The EV module decodes the lower six-bits of th

address; while the upper 10 bits of the address are decoded b

the peripheral address decode logic, which provides a modu

select to the Event Manager when the peripheral address bu

carries an address within the range designated for the EV on thdevice.

On 281x devices (as with the C240 device),

EVA registers are located in the range 7400h to 7431h.

EVB registers are located in the range of 7500h to 7531h.

The undefined registers and undefined bits of the EV registers a

return zero when read by user software. Writes have no effect.


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5. PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generate

simultaneously by each event manager: three independent pai

(six outputs) by the three fullcompare units with programmab

deadbands, and two independent PWMs by the GP-tim

compares.

5.1. PWM

A PWM signal is a sequence of pulses with changing pulse

widths. The pulses are spread over a number of fixed-length

periods so that there is one pulse in each period. The fixed perio

is called the PWM (carrier) period and its inverse is called the

PWM (carrier) frequency

In a motor control system, PWM signals are used to control

the on and off time of switching power devices that deliver the

desired current and energy to the motor windings

5.1. How to Generate PWM


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To generate a PWM signal, an appropriate timer

needed to repeat a counting period that is the same as the PW

period. A compare register is used to hold the modulating values

The value of the compare register is constantly comparewith the value of the timer counter. When the values match,

transition (from low to high, or high to low) happens on th

associated output. When a second match is made between th

values, or when the end of a timer period is reached, anothe

transition (from high to low, or low to high) happens on th

associated output. In this way, an output pulse is generate

whose on (or off) duration is proportional to the value in th

compare register. This process is repeated for each timer perio

with different (modulating) values in the compare register. As

result, a PWM signal is generated at the associated output.

5.2. Generation of PWM Output with Event Manager

Each of the three compare units, together with GP timer 1 (

the case of EVA) or GP timer 3 (in the case of EVB), the dead-ban

unit, and the output logic in the event manager module, can b

used to generate a pair of PWM outputs with programmab

dead-band and output polarity on two dedicated device pin

There are six such dedicated PWM output pins associated wi


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the three compare units in each EV module. These six dedicate

output pins can be used to conveniently control 3-phase a

induction or brushless dc motors.

The flexibility of output behavior control by the compa

action control register(ACTRx) also makes it easy to contr

switched reluctance and synchronous reluctance motors in a wid

range of applications. The PWM circuits can also be used t

conveniently control other types of motors such as dc brush an

stepper motors in single or multi-axis control applications. EacGP timer compare unit, if desired, can also generate a PW

output based on its own timer.

5.2.1 Asymmetric and Symmetric PWM Generation

Both asymmetric and symmetric PWM waveforms can begenerated by every compare unit on the EV module. In addition,

the three compare units together can be used to generate 3-

phase symmetric space vector PWM outputs. PWM generation

with GP timer compare units has been described in the GP timer

sections. Generation of PWM outputs with the compare units is

discussed in this section.


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5.2.2 Register Setup for PWM Generation

All three kinds of PWM waveform generations with compare

units and associated circuits require configuration of the same

Event Manager registers.

The setup process for PWM generation includes the followin

steps:

Setup and load ACTRx

Setup and load DBTCONx, if dead-band is to be used

Initialize CMPRx

Setup and load COMCONx

Setup and load T1CON (for EVA) or T3CON (for EVB) to start thoperation

Rewrite CMPRx with newly determined values

5.2.3 Asymmetric PWM Waveform Generation

The edge-triggered or asymmetric PWM signal

characterized by modulated pulses which are not centered wit


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respect to the PWM period, as shown in figure. To generate a

asymmetric PWM signal, GP timer 1 is put in the continuous u

counting mode and its period register is loaded with a valu

corresponding to the desired PWM carrier period. The COMCONis configured to enable the compare operation, set the selecte

output pins to be PWM outputs, and enable the outputs.

If dead-band is enabled, the value corresponding to th

required dead-band time should be written by software into thDBT(3:0) bits in DBTCONx(11:8). This is the period for the 4-b


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dead-band timers. One deadband value is used for all PW

output channels.

By proper configuration of ACTRx with software, a norm

PWM signal can be generated on one output associated with

compare unit while the other is held low (or off) or high (or on),

the beginning, middle, or end of a PWM period. Such softwa

controlled flexibility of PWM outputs is particularly useful

switched reluctance motor control applications.

After GP timer 1 (or GP timer 3) is started, the compareregisters are rewritten every PWM period with newly determine

compare values to adjust the width (the duty cycle) of PWM

outputs that control the switch-on and -off duration of the powe

devices. Since the compare registers are shadowed, a new value

can be written to them at any time during a period. For the same

reason, new values can be written to the action and period

registers at any time during a period to change the PWM period

or to force changes in the PWM output definition.

5.2.4 Symmetric PWM Waveform Generation

A centered or symmetric PWM signal is characterized b

modulated pulses which are centered with respect to each PW


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period. The advantage of a symmetric PWM signal over a

asymmetric PWM signal is that it has two inactive zones of th

same duration: at the beginning and at the end of each PW

period. This symmetry has been shown to cause less harmonithan an asymmetric PWM signal in the phase currents of an a

motor, such as induction and dc brushless motors, whe

sinusoidal modulation is used. Figure shows two examples

symmetric PWM waveforms.

The generation of a symmetric PWM waveform with

compare unit is similar to the generation of an asymmetric PW

waveform. The only exception is that GP timer 1 (or GP timer

now needs to be put in continuous up-/down-counting mode.


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There are usually two compare matches in a PWM period

symmetric PWM waveform generation, one during the upwa

counting before period match, and another during downwa

counting after period match. A new compare value become

effective after the period match (reload on period) because

makes it possible to advance or delay the second edge of a PW

pulse. An application of this feature is when a PWM wavefor

modification compensates for current errors caused by the dea

band in ac motor control.Because the compare registers are shadowed, a new valu

can be written to them at any time during a period. For the sam

reason, new values can be written to the action and perio

registers at any time during a period to change the PWM perio

or to force changes in the PWM output definition.

5.3. Why Deab Band

In many motion/motor and power electronics application

two power devices, an upper and a lower, are placed in series o

one power converter leg. The turn-on periods of the two devicemust not overlap with each other in order to avoid a shoo


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through fault. Thus, a pair of non-overlapping PWM outputs

often required to properly turn on and off the two devices.

A dead time (deadband) is often inserted between th

turning-off of one transistor and the turning- on of the oth

transistor. This delay allows complete turning-off of one transist

before the turning - on of the other transistor. The required tim

delay is specified by the turning-on and turning-off characteristi

of the power transistors and the load characteristics in a specif

application.

6. Sinusoidal PWM

Sinusoidal pulse width modulation is a method of pulse widt

modulation used in inverters. An inverter produces an AC outp

voltage from a DC input by using switching circuits to simulatesine wave by producing one or more square pulses of voltage p

half cycle. If the widths of the pulses are adjusted as a means

regulating the output voltage, the output is said to be pulse widt

modulated.

With sinusoidal or sine weighted pulse width modulatio

several pulses are produced per half cycle. The pulses near th


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edges of the half cycle are always narrower than the pulses near th

center of the half cycle such that the pulse widths are proportional

the corresponding amplitude of a sine wave at that portion of th

cycle. To change the effective output voltage, the widths of all puls

are increased or decreased while maintaining the sinusoid

proportionality. With pulse width modulation, only the widths (o

time) of the pulses are modulated. The amplitudes (voltage) durin

the "on-time" is constant unless a multi-step circuit is used. The lin

to neutral voltage of a 3-phase inverter has two voltage levels.


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The easiest way to generate a sinusoidal waveform is to use

lookup table. You could also calculate the sine value on the fly,

but its just not worth spending the CPU time to do this. A lookup

table is used that contains all the points of a sine value. The sine

values are read from the table at periodic intervals, scaled to

match the allowable range of duty cycles, and then written to th

duty cycle registers.

The sine table values are stored in program memory. It

transferred data to data memory during initialization for fastaccess. Three registers are used as offsets to the table throug

indirect addressing. An array is defined the current location of th

lookup table. A counter variable is added to this array at eac

interval, the software will move through the table at affixe

frequency. The lookup table usually contains from 0 to 256 data.

The offset values are added to the sine table array values

each PWM interrupt . The 180 degrees phase shift is loaded int

phases. Once lookup table values are obtained from the tabl

they are multiplied by scaling values to determine the actu

amplitude of the modulation output.

Two inverted pulses are generated with dead band by usin

PWM Generator for a Single Phase PWM Inverter. The PW


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interrupt is enabled when internal counter reaches the perio

register value. When PWM interrupt occurring, a single data

taking from lookup table. The lookup table contains 256 samplin

data by using the sine formula,

Where, i - 0 to 256. 3.14.

The main program determines the voltage, amplitude andfrequency while PWM ISR realizes the PWM by setting the prope

compare registers values, dead band timer control register and

timer period register, etc.

The PWM ISR flow chart as shown in below,

u = sin ( 1.4 i / 180 )


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Spwm will trigger the IGBT in the following manner.,

Inverter in Power-Electronics refers to a class of pow

conversion circuits that operate from a dc voltage source or a d

current source and convert it into a symmetric ac voltage

current. It does reverse of what ac-to-dc converter does.

Calculate the Frequency & Amplitude

Using lookup table for cosine values

Load the values into CMPR registers

Enable Interrupt return

PWM ISR

Increment a counter for next data


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A DC to AC voltage converter consists of four bidirection

switches that is used to convert the voltage. Sinusoidal unipol

Pulse Width Modulation is used for triggering the gates of IGBT

The control circuit consists of the DSC controller and it is used t

produce required SPWM for triggering the IGBTs. The drivcircuit isolates the control circuit from power circuit. The outpu

for variable AC voltages are observed in the CRO.

A PWM period register is used to generate the PWM frequenc

range. The PWM period register calculation is,

Sinusoidal triangle PWM (SPWM) is the mostly used metho

Triangle wave is used as carrier and reference signal is sinusoid

wave, whose frequency is the desired frequency and amplitude idetermined by desired voltage amplitude, DC voltage and carri

amplitude. Two separate single-phase inverters where eac

inverter produces an output delayed by 180 (of the fundament

frequency) with respect to each other. The Single Pha

Sinusoidal PWM inverter output pulses are shown in below,


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Fig. 4 Single Phase Sinusoidal PWM inverter waveform outputs

Fig. 5 Sinusoidal PWM Output Pulses

To drive a PWM inverter, a single phase inverter bridge

driven by a microcontroller outputs. By changing the PWM du

cycles in a regular manner, the PWM outputs are modulated t

synthesize the sinusoidal waveform. The Single Phase PW

inverter Mode is accomplished with the PWM peripheroperated in complementary mode with dead time.


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7. Single Phase Sine PWM Inverter

In Single Phase Sine PWM Inverter, Totally four Pwm

required pwm1,pwm2,pwm3,pwm4 required to run a motor. Th

PWM pulse pattern are listed below

Pwm1active high.

Pwm2active low and inverted of pwm1.

Pwm3active high and 1800 phase shift of pwm1.

Pwm4active low and inverted of pwm3.

And keep 4s deadband between pwm1 & pwm2 and als

between pwm3 and pwm4. These pwm are feeding to driv

circut for controlling the lamp load or motor load.

One capture is used to read a speed. Example proximi

sensor. This sensor is installed at motor side, it feed the som

signal to DSC. The proximity sensor will produce a 50 Hz squa

wave for maximum motor speed. Accordingly ,we have t

claculate the speed by using any of the capture pin.

Four input keys are used to set the 50 hz frequency an

ammplitude in %. Restrict the amplitude as after 90% keep


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constant 90%. First two keys are used to vary ( increase

decrease ) a frequency, the next two keys are used to vary

increase or decrease ) amplitude.

7.1. Program flow chart:

The program has written as per the above explainatio

This project you can implement in directly to TMS320F2812 k

This programming concept you can use any of the c200

Controller, such a general concept implemented.

This project source code is available at our websit

Again the complete brief explanation is done at flow chart t

understand program. User can download that project once yo

registered. For more queries, please contact through forum.


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single phase sine pwm inverter using tms320f2812

Documents

pwm characteristics

sinusoidal pwm

symmetric pwm generation

generation of pwm output

tms320f2812 architecture

technical community

event manager architecture

control peripherals