FEATURE

By Tom Hill

Heterogeneous, reconfigurable DSP hardware platforms (hardware plat-forms that include both a DSP processor and an FPGA) supported by a platform-based design methodology enable traditional DSP designers not familiar with FPGAs to quickly evaluate the benefits an FPGA coprocessor can bring to their applications. Standards in the video, imaging, and telecommunications markets have driven the use of these platforms, providing off-the-shelf hardware that addresses the most important design challenges yet is still sufficiently customizable to allow for product differentiation. Platforms such as these limit degrees of freedom in hardware, and in doing so, provide greater automation in the design flow. This automation can help eliminate complexity, thus extending the advantages of heterogeneous platforms to the DSP design community.

DSP hardware platform benefits FPGAs and DSP processors have fundamentally different architectures. An algorithm that is well suited for implementation on one device may be very inefficient on the other. For instance, a hardware system based solely on DSP processors may require more area, cost, or power if the target application requires a large amount of parallel processing or a maximized multichannel throughput because discrete DSPs do not scale well for parallel processing.

An FPGA coprocessor can provide up to 550 parallel multiply and accumulate operations on a single device, delivering the same performance with fewer devices and lower power for many applications (Figure 1). On the other hand, while FPGAs excel at processing large amounts of

Heterogeneous, reconfigurable

hardware platforms that include

both a DSP and FPGA provide

an off-the-shelf hardware solution that

allows for product differentiation through

customization. These platforms limit

degrees of development freedom, and in

doing so, enable greater automation in

the design flow. This automation allows

traditional DSP developers to leverage

the performance and cost benefits offered

through the parallelism of an FPGA.

Heterogeneous hardware platforms capitalize on

DSP/FPGA capabilities

FEATURE

Figure 1

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data in parallel, they are not as optimized as DSP processors for tasks such as periodic coefficient updates, decision-making control tasks, or high-speed serial mathematical operations. Combining an FPGA with a DSP processor delivers successful solutions for a wide range of applications.

For example, a heterogeneous, reconfigurable DSP platform can be ideal for smart cameras that employ pattern recognition. An FPGA’s parallel processing capacity is well suited for image segmentation and feature extraction, while a video and imaging DSP processor is more capable of handling math-intensive tasks such as statistical pattern classification. A heterogeneous system improves exploitation of pipelining and parallel processing, which are essential to achieve high frame rates and low latency. Develop-ing this type of system requires proficiency in both FPGA and DSP processor designs plus the systems engineering skills necessary for partitioning – a breadth of skills few designers possess.

Heterogeneous platform-based design flow benefits A heterogeneous platform-based design flow extends the design automation concepts adopted by the individual processor and FPGA design flows to the entire platform. The basic function of a platform-based design – abstracting away the hardware and software interface details between the FPGA and DSP processor – allows a DSP designer with little or no FPGA design experience to evaluate and exploit the benefits of adding an FPGA. This design flow should automatically generate memory maps, header and driver files for the software interface, and hardware interface and interrupt logic. Refining the overall system should have limited consequences on individual hardware and software components (Figure 2).

Through this automation, a single developer no longer needs to master the broad range of technologies required to design FPGA hardware, DSP processor application code, and interface logic and software. In essence, the system design can be easily partitioned to utilize the discrete DSP processor and FPGA coprocessor.

Designing an FPGA coprocessor Designers can use many methods to implement a signal processing algorithm in any given technology. Target hardware often influences the algorithmic approach. When the target is a heterogeneous DSP hardware platform, selecting an implementation becomes a two-step process. The designer must first select the most appropriate hardware device and then determine which implementation method makes sense for that device.

On a DSP hardware platform, the processor will be the master and control the FPGA. The FPGA, in turn, will be used as either a coprocessor (where data is sourced to and synch-ed from the DSP processor) or as a pre- or post-processor (where the data is sourced from a high-speed interface). System data rates and operating parameters drive optimal FPGA usage.

DSP application developers will find the coprocessing flow, in which an FPGA can be used to accelerate performance-critical functions, to be the most natural programm-ing model. Tools such as Code Composer Studio for Texas Instruments DSPs include code profilers that identify the software hot spots that can be offloaded to the FPGA.

Combining an FPGA with a DSP processor delivers successful solutions for a wide range of applications.

It is not uncommon for 20 percent of the application code to consume 80 percent of the available processor MIPS. Automating the design flow for interfacing to an FPGA coprocessor will greatly assist embedded DSP programmers who lack strong FPGA design backgrounds.

To use these tools efficiently and design a heterogeneous DSP/FPGA platform effectively, designers need an interface to connect the FPGA to a separate DSP processor on the hardware platform. DSP platforms will typically support more general-purpose interfaces, such as the Texas Instruments 16/32/64-bit Tic6x DSP extended memory interface (suitable for system control and coprocessing tasks), and high-speed serial interfaces, such as Serial RapidIO or video interfaces (for pre- and post-processing operations).

As designers add FPGA coprocessors to the system, the software implementation will change from an algorithmic descrip-tion to data passing and function control. The FPGA coprocessor will appear as a hardware accelerator to the application software developer and will be accessible through function calls.

Figure 2

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Video on the goacross differentset-top devices

Media convergence is happening in your living room. Streaming movies, prime time shows via iTunes, and video podcasts all require heavy lifting. TI’s got you covered with their DaVinci technology digital media processor for video transcoding in media gateways, multipoint control units, digital media adapters, video security DVRs, and IP set-top boxes allowing con-sumers to seamlessly move content across their video end products. “Aha!” you say to yourself. “I want this.”

Wrapped with a completeoffering of development toolsand digital media software,the new TMS320DM6467DaVinci processor is a DSP-based System-on-Chip (SoC) specifically tuned for real-time, multiformat, HD video transcoding. Integrating an ARM926EJ-S core and 600 MHz C64x+ DSP core along with an HD video coprocessor, conversion engine, and targeted video port interfaces, the system solution delivers a 10x performance improvement over previous generation processors to perform simultaneous, multiformat HD encoding, decoding, and transcoding up to H.264 HP@L4 (1080p 30 fps, 1080i 60 fps, 720p 60 fps).

Texas Instruments • www.ti.comRSC# 35471

Making the grade:Programmable device offershigh capacity and reliabilityfor militaryProgrammable logic is now de rigeur in defense systems – but densityand extended temp range are absolute requirements in high-relapplications. QuickLogic offers the 1 million gate version of their PolarPro family, their low-power programmable logic technology in a Mil-spec temperature rating. The QL1P1000 incorporates embedded memory with built-in FIFO control and advanced clock management control units, yet offers enhanced design security.

The proprietary ViaLink technology used also offers significant benefits for battery-powered, mission-critical applications. PolarPro’s VLP low-power mode reduces current demand to less than 100 microamps, meaning smaller, lighter batteries can be usedfor easier portability. There’s also special packaging to reduce sensitivity to mechanical stresses such as shock and vibe. For demanding defense applications, this device makes the grade: the military grade. QuickLogic • www.quicklogic.comRSC# 35472

Completing the development environment FPGA vendors are investing heavily to provide an alternative FPGA development environment that is DSP centric and does not require traditional HDL-based design experience. Design flows that enable The MathWorks Simulink and MATLAB modeling environments to be used in FPGA designs have generally been the most popular. For Xilinx FPGA users, algorithms described in floating-point MATLAB can be synthesized into DSP functional blocks for the targeted FPGA using the AccelDSP synthesis tool. The System Generator for DSP simulation tool enables designers to use Simulink for combining these custom blocks with Xilinx optimized IP to form complete FPGA-based DSP systems. These tools allow for co-verification, where part of the software simulation is replaced with implementations running on hardware.

This allows designers to validate their implementations in hardware and accelerate their simulations.

FPGA vendors are also stepping up their efforts to support platform-based design – targeting specific applications such as video processing – through automatic genera-tion of the infrastructure between an FPGA coprocessor and a Texas Instruments DSP processor.

Tom Hill is System Generator product manager at Xilinx, in San Jose, California, where he oversees all product, strategic, and corporate marketing activities related to Xilinx’s DSP development tool, System Generator for DSP. Tom has more than 14 years of experience in the electronic design automation industry, including his most recent role at AccelChip, Inc. as technical marketing manager responsible for product direction and application of high-level design method­ologies and tools for DSP applications. Prior to AccelChip, he held positions as product manager, technical marketing manager, technical marketing engineer, and field applications engineer for various FPGA and ASIC synthesis tools vendors. Tom began his career as a hardware and ASIC design engineer at Allen-Bradley and Lockheed Martin. He holds a BS in Electrical Engineering from Cleveland State University.

Xilinx, Inc. 408-559-7778 • tom.hill@xilinx.com

www.xilinx.com

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