s&ip consortium course material soc overview and arm integrator prof. an-yeu (andy) wu...

S&IP Consortium Course Material

SoC Overview and ARM IntegratorSoC Overview and ARM Integrator

Prof. An-Yeu (Andy) Wu 吳安宇教授Graduate Institute of Electronics Engineering,

National Taiwan University

S&IP Consortium Course Material 2

OutlineOutlineIntroduction to SoCARM-based SoC and Development ToolsAvailable Lab modulesSummary


SoC: System on ChipSoC: System on ChipSystem

A collection of all kinds of components and/or subsystems that are appropriately interconnected to perform the specified functions for end users.

A System design is a “product creation process” whichStarts at identifying the end-user needsEnds at delivering a product with enough functional

satisfaction to overcome the payment from the end-user


SoC DefinitionSoC DefinitionSoC - Complex IC that integrates the major functi

onal elements of a complete end-product into a single chip or chipset

The SoC design typically incorporates General-purpose programmable processor (ARM)Special-purpose processor (DSP processor, TI C5x)On-chip memoryHW accelerating function units (MPEG, JPEG, Baseb

and Transceiver, Encryption Engine, etc.)Peripheral interfaces (GPIO and AMS blocks)Embedded software

Source: “Surviving the SoC revolution – A Guide to Platform-based Design,” Henry Chang et al, Kluwer Academic Publishers, 1999


Block Diagram of Digital Video Broadcasting(DVB-T) System

Video Coder

Audio Coder

Data Coder

Programm

eM

UX TransportM

UX

MPEG 2Source coding and Multiplexing

2

n

MUXAdaptation

EnergyDispersal

MUXAdaptation

EnergyDispersal

Splitter

OuterCoder

OuterCoder

OuterInterleaver

OuterInterleaver

InnerInterleaver

MapperFrame

Adaptation

Pilot & TPSSignals

OFDMGuard

IntervalInsertion

D/A Front EndInnerCoder

InnerCoder

ToAerial

Terrestrial ChannelAdapter

Channel Coding for FEC OFDM Modulation


SoCSoC 製成演進階段製成演進階段

第一階段第二階段第三階段

Logic

ROM

PLL

AD/DA

Soft I/F Core

uP Core

DSPCore SRAM

LogicROM

SRAM

Logic

ROM

PLL ApplicationSpecificAnalog

ApplicationSpecificIP Core AD/DA

Soft I/F Core

uP Core

DSPCore SRAM DRAM

Flash

LogicAnalogLogic

AnalogDRAMFlash

LogicLogic


SoC ArchitectureSoC Architecture


SoC ExampleSoC Example


SoC Example Emotion Engine in PS2SoC Example Emotion Engine in PS2


Emotion Engine and IPEmotion Engine and IP

Emotion Engine MIPS R3000A Based

Design MPEG decoder Vector generator

(co-processor) Reach 6.2G Flops


Embedded Processors Embedded Processors Dominate System DesignDominate System Design

Source: Wilson Research Group 2002 Survey & ADI Estimates * 16- and 32-bit (non-DSP) MPUs and MCUs

DSPsDSPs20%20%

Embedded Embedded MPUs/MCUs*MPUs/MCUs*

80%80%

Processor Type Used in Last 12 Months for Embedded System Design


TI OMAP5910 Dual-Core ProcessorTI OMAP5910 Dual-Core Processor

NewNew Trend in MPU/MCU/DSP


Digital CameraDesign AlternativesDigital CameraDesign Alternatives

Multi-core Implementation

System InterfacesHigh Speed

Converters

CCD input

System Interfaces

DSPDSP SharedMemory

SharedMemory

H/WAccel.

H/WAccel. RISCRISC

CCD inputHigh SpeedConverters

Blackfin Implementation


Size (mm2)

MF

LO

PS

/Wat

t

050010001500

1500

1000

500

ConventionalDSPs

TigerSHARC Performance LeadershipTigerSHARC Performance Leadership

High-end MPUs

adiuser

Same animation as with Blackfin, but use TigerSHARC this time.


DSPASIC or FPGA

ASIC or FPGA

Chip Rate Processing

TX

RX Symbol Rate Processing

TX

RX

CRCCRCChannel

Coding

Channel CodingRate

Matching

Rate MatchingInterleaving

InterleavingSpreading &

Modulation

Spreading &

Modulation

Channel Decoding

Channel DecodingRate Dematch

ing

Rate DematchingDe-Interleaving

De-InterleavingPath Search

Path Search

Code Gen.

Code Gen.

Channel Estimation

Channel Estimation

Control Ch. Despread


Data Ch. Despread

Data Ch. Despread CRC

CRC

3G Base Station Design Alternatives


Multiprocessing

Chip Rate Processing

TX

RX Symbol Rate Processing

TX

RX

CRCCRCChannel

Coding

Channel CodingRate

Matching

Rate MatchingInterleaving

InterleavingSpreading &

Modulation

Spreading &

Modulation

Channel Decoding

Channel DecodingRate Dematch

ing

Rate DematchingDe-Interleaving

De-InterleavingPath Search

Path Search

Code Gen.

Code Gen.

Channel Estimation

Channel Estimation



Data Ch. Despread

Data Ch. Despread CRC

CRC

ALL SOFTWARE SOLUTION

3G Base Station Design Alternatives


SoC ApplicationSoC ApplicationCommunication

Digital cellular phoneNetworking

ComputerPC/WorkstationChipsets

ConsumerGame boxDigital camera


Benefits of Using SoCBenefits of Using SoC

Integration on silicon die:Reduce overall system cost (reduce

interconnection of chips and PCB)Increase performanceLower power consumption Reduce size


Evolution of Silicon DesignEvolution of Silicon Design

Source: “Surviving the SoC revolution – A Guide to Platform-based Design,” Henry Chang et al, Kluwer Academic Publishers, 1999


SoC Challenges (1/2)SoC Challenges (1/2)Bigger circuit size (Size does matter)

Design data management, CAD capabilityForced to go for high-level abstraction (SystemC, Syste

mVerilog)Smaller device geometries, new processing (e.g.,

SOI)Short channel effect, sensitivity, reliabilityVery different, complicated device model

Higher density integrationShorter distance between devices and wires: cross-talk

couplingLow Power requirement

Standby leakage power is more significant, lower noise margin


SoC Challenges (2/2)SoC Challenges (2/2)Higher frequencies

Inductance Effect and Cross-talk Coupling noise become dominated.

Design Complexity Cs, DSPs, HW/SW, RTOS’s, digital/analog IPs, On-c

hips buses

IP ReuseVerification, at different levels

HW/SW co-verificationDigital/analog/memory circuit verificationTiming, power and signal integrity verification

Time-to-market


How to Conquer the ComplexityHow to Conquer the ComplexityUse a known real entity

A pre-designed component (IP reuse)A platform (architecture resue)

PartitionBased on functionalityHardware and software

ModelingAt different levelConsistent and accurate


Why ARM Processor?Why ARM Processor? A Star IP with Complete Development Tools Good performance Index: MIPS/mW/$ for portables. Good Business Model with IC Design Houses, SoC Desi

gn Service Houses, and Fabrication Companies (UMC, TSMC).

Major Market Shares: Become money/share-driven standard, e.g., AMBA on-chip system buses.

Even major IDM (Integrated Device Manufacturer) companies (Intel, TI) employ ARM as the general processing cores (StrongARM, OMAP)

Side information: The certified ARM training course costs NT 60,000 for 5-day complete training!!


ARM-based System DevelopmentARM-based System DevelopmentProcessor coresARM On-Chip Bus: AMBA, AXIPlatform: PrimeXsysSystem building blocks: PrimeCellDevelopment tools

Software developmentDebug toolsDevelopment kitsEDA modelsDevelopment boards


ARM Architecture VersionARM Architecture VersionCore Version Feature

ARM1 v1 26 bit address

ARM2, ARM2as, ARM3 v2 32 bit multiply coprocessor

ARM6, ARM60, ARM610,

ARM7, ARM710,

ARM7D, ARM7DI

v3 32 bit addressesSeparate PC and PSRsUndefined instruction and Abort modesFully staticBig or little endian

StrongARM, SA-110, SA-1100

ARM8, ARM810

v4 Half word and signed halfword/byte supportEnhanced multiplierSystem mode

ARM7TDMI, ARM710T, ARM720T, ARM740T

ARM9TDMI, ARM920T, ARM940T

v4T Thumb instruction set

T: Thumb instruction set

M: enhanced Multiplier

D: On-chip Debug

I: Embedded ICE Logic


ARM Architecture Version (cont.)ARM Architecture Version (cont.)

Core Version Feature

ARM1020T v5T Improved ARM/Thumb InterworkingCLZ instruction for improved division

ARM9E-S, ARM10TDMI, ARM1020E v5TE Extended multiplication and saturated maths for DSP-like functionality

ARM7EJ-S, ARM926EJ-S, ARM1026EJ-S v5TEJ Jazelle Technology for Java acceleration

ARM11, ARM1136J-S, v6 Low power neededSIMD (Single Instruction Multiple Data) media processing extensions

J: Jazelle

S: Synthesizable

F: integral vector floating point unit


ARM CoprocessorsARM Coprocessors VFP

Optional part of microarchitecture No overhead for markets that do not need floating point

A tightly-integrated coprocessor Enables maximum advantage of separate load/store and execution pipe

lines 8-Stage FMAC pipeline

Application specific coprocessors e.g. For specific arithmetic extensions Developed a new decoupled coprocessor interface Coprocessor no longer required to carefully track processor pipeline.

ARM

CoreCo-processor


ARM On-Chip BusARM On-Chip Bus

ARM CoreOn-Chip

RAM

DMAMaster

Bridge

AHB/ASB

UART

Timer

PIO

Keypad

APBMemory Interface

A typical AMBA system

AHB: Advanced High-performance Bus

ASB: Advanced System Bus

APB: Advanced Peripheral Bus

** AMBA: Advanced Microcontroller Bus Architecture


AXI (Advanced Extensible Interface)AXI (Advanced Extensible Interface)

The next generation AMBA interfaceFeatures

Separate address/control and data phasesSupport for unaligned data transfers using byte strobesBurst-based transactions with only start address issuedSeparate read and write data channels to enable low-cost

DMAAbility to issue multiple outstanding addressesOut-of-order transaction completionEasy addition of register stages to provide timing closure Includes optional extensions to cover signaling for low-

power operation


PrimeXsysPrimeXsys It is no longer the case that a single Intellectual Pr

operty (IP) or silicon vendor will be able to supply all of the IP that goes into a device.

With the PrimeXsys range, ARM is going one step further in providing a known framework in which the IP has been integrated and proven to work.

Each of the PrimeXsys platform definitions will be application focused – there is no ‘one-size-fits-all’ solution.

ARM will create different platform solutions to meet the specific needs of different markets and applications.


ARM PrimeXsys Wireless PlatformARM PrimeXsys Wireless Platform

Ingredients

Hardware building block

OS-PortsTool Support and Validation Methodology


Example: GPRS PhoneExample: GPRS Phone


Example: VideophoneExample: Videophone


PrimeCell (1/2)PrimeCell (1/2)ARM PrimeCell peripherals are re-usable soft IP

macrocellsFeature

Fully packaged, ready-to-use soft IP macrocellsGeneric AMBA bus-compliant on-chip system compon

entsEasy integration into AMBA bus-based SoC designsFully tested and supported software device drivers


PrimeCell (2/2)PrimeCell (2/2)

A typical AMBA SoC design using PrimeCell Peripherals. Ancillary or general-purpose peripherals are connected to the Advanced Peripherals Bus (APB), while main high-performance system components use the Advanced High-performance Bus (AHB).


ARM’s Point of View of SoCsARM’s Point of View of SoCsIntegrating Hardware IPSupplying Software with the Hardware

ARM has identified the minimum set of building blocks that is required to develop a platform with the basic set of requirements to:Provide the non-differentiating functionality, pre-

integrated and pre-validated;Run an OS;Run application software;Allow partners to focus on differentiating the final

solution where it actually makes a difference.


ARM-based System DevelopmentARM-based System DevelopmentProcessor coresARM On-Chip Bus: AMBA, AXIPlatform: PrimeXsysSystem building blocks: PrimeCellDevelopment tools

Software developmentDebug toolsDevelopment kitsEDA modelsDevelopment boards


Main Components in ADS (1/2)Main Components in ADS (1/2) ANSI C compilers – armcc and tcc ISO/Embedded C++ compilers – armcpp and tcpp ARM/Thumb assembler - armasm Linker - armlink Project management tool for windows - CodeWarrior Instruction set simulator - ARMulator Debuggers - AXD, ADW, ADU and armsd Format converter - fromelf Librarian – armar ARM profiler – armprof C and C++ libraries ROM-based debug tools (ARM Firmware Suite, AFS) Real Time Debug and Trace support Support for all ARM cores and processors including ARM

9E, ARM10, Jazelle, StrongARM and Intel XscaleADS: ARM Developer Suite


The Structure of ARM ToolsThe Structure of ARM Tools

C/C++ source C libraries asm source

object libraries

C compiler assembler

linker Librarian

.oELF object file

With DWARF2 debug tables

.axfELF/DWARF2 image

debug

ARMsd

ARMulator

System models

developmentboard

ELF: Executable and linking formatDWARF: Debug With Arbitrary Record Format


ARM Emulator: ARMulator (1/2)ARM Emulator: ARMulator (1/2)A suite of programs that models the behavior of

various ARM processor cores and system architecture in software on a host system

Can be operates at various levels of accuracyInstruction accurateCycle accurateTiming accurate


ARM Emulator: ARMulator (2/2)ARM Emulator: ARMulator (2/2)Benchmarking before hardware is available

Instruction count or number of cycles can be measured for a program.

Performance analysis.

Run software on ARMulatorThrough ARMsd or ARM GUI debuggers, e.g., AXDThe processor core model incorporates the remote de

bug interface, so the processor and the system state are visible from the ARM symbolic debugger

Supports a C library to allow complete C programs to run on the simulated system


ARM µHAL APIARM µHAL APIµHAL is a Hardware Abstraction Layer that is de

signed to conceal hardware difference between different systems

ARM µHAL provides a standard layer of board-dependent functions to manage I/O, RAM, boot flash, and application flash.System Initialization SoftwareSerial PortGeneric TimerGeneric LEDsInterrupt ControlMemory ManagementPCI Interface


µHAL ExamplesµHAL Examples

µHAL API provides simple & extended functions that are linkable and code reusable to control the system hardware.

User application AFS utilities

AFS board-specific HAL routinesAFS support

routines

Development board

C and C++ libraries

General

Specific

AFS: ARM Firmware Suit


Debug AgentDebug AgentA debug agent performs the actions requested b

y the debugger, for example:setting breakpointsreading from memorywriting to memory.

The debug agent is not the program being debugged, or the debugger itself

Examples: ARMulator, Angel, Multi-ICE


Debug TargetDebug Target Different forms of the debug target

early stage of product development, software prototype, on a PCB including one or more processors final product

The form of the target is immaterial to the debugger as long as the target obeys these instructions in exactly the same way as the final product.

The debugger issues instructions that can: load software into memory on the target start and stop execution of that software display the contents of memory, registers, and variables allow you to change stored values.


ARM Debug Architecture (1/2)ARM Debug Architecture (1/2)Two basic approaches to debug

from the outside, use a logic analyzerfrom the inside, tools supporting single stepping, brea

kpoint setting

Breakpoint: replacing an instruction with a call to the debugger

Watchpoint: a memory address which halts execution if it is accessed as a data transfer address

Debug Request: through ICEBreaker programming or by DBGRQ pin asynchronously


ARM Debug Architecture (2/2)ARM Debug Architecture (2/2)In debug state, the core’s internal state and the

system’s external state may be examined. Once examination is complete, the core and system state may be restored and program execution is resumed.

The internal state is examined via a JTAG-style serial interface, which allows instructions to be serially inserted into the core’s pipeline without using the external data bus.

When in debug state, a store-multiple (STM) could be inserted into the instruction pipeline and this would dump the contents of ARM’s registers.


In Circuit Emulator (ICE)In Circuit Emulator (ICE)The processor in the target system is removed

and replaced by a connection to an emulatorThe emulator may be based around the same

processor chip, or a variant with more pins, but it will also incorporate buffers to copy the bus activity to a “trace buffer” and various hardware resources which can watch for particular events, such as execution passing through a breakpoint


Multi-ICE and Embedded ICEMulti-ICE and Embedded ICEMulti-ICE and Embedded ICE are JTAG-based

debugging systems for ARM processorsThey provide the interface between a debugger

and an ARM core embedded within an ASICreal time address-dependent and data-dependent

breakpointssingle steppingfull access to, and control of the ARM corefull access to the ASIC systemfull memory access (read and write)full I/O system access (read and write)


Debugging with Multi-ICEDebugging with Multi-ICE

The system being debugged may be the final system


ARM ModelingARM Modeling

Concept

Silicon

Instruction set simulators (ISS)

Co-verification model

Gate Level netlist model

Hardware modeling

System model

Design signoff models

Behavioral/RTL model

Bus Interface model

Accuracy

Efficiency


Integrate All The Modules in The IntegratorIntegrate All The Modules in The Integrator

Core Module (CM)Logic Module (LM)Integrator ASIC Development PlatformIntegrator Analyzer ModuleIntegrator IM-PD1Integrator/IM-AD1Integrator/PP1 & PP2Firmware Suite

ATX motherboard


ARM Integrator within a ATX PC CaseARM Integrator within a ATX PC Case


Inside the CaseInside the Case


Logic ModuleLogic Module

ZBTSSRAMFlash

AHB SSRMcontrollerAHB/APB

bridge

CSR

IntCntl

APB IPAHB IP

Multi-ICEConfig

PLDXchecker/Download

EXPA/EXPBconnector

EXPIMconnector

Prototyping grid (16x17)

FPGA

LEDsSwitchsOSCsTrace

Push BLA C

LM


Extension with Prototyping GridExtension with Prototyping Grid

You can use the prototyping

grid to:

wire to off-board circuitry

mount connectors

mount small components


ARM Integrator – One ConfigurationARM Integrator – One Configuration

System bus

GPIO Keyboard

Mouse

Serial 2

2xUART

LEDs

ClockPLLRTCosc.

CSR

Interruptcontroller

RTC

3 x timer/counter

Resetcontrol

Bridge

PCI bridgecontroller

Peripheral bus

SMC

reset

EBI

ArbiterExternal systemBus interface

3 PCI slots

PCI PCIbridge

CompatPCI

Boot ROM

(32MB) Flash

(512BK) SSRAM

256MBSDRAM

ARM7TDMI

Multi-ICE

SSRAM

SSRAMcontroller

Memory bus

System busbridge

SDRAMcontroller

CSRReset

controller

HDRA/HDRBconnector

Clockgenerator

ZBTSSRAMFlash

AHB SSRMcontrollerAHB/APB

bridge

CSR

IntCntl

APB IPAHB IP

Multi-ICEConfig

PLDXchecker/Download

EXPA/EXPBconnector

EXPIMconnector

Prototyping grid (16x17)

FPGA FPGA

FPGA

LEDsSwitchsOSCsTrace

Push BLA C

CM

AP

LM


System Memory MapSystem Memory Map

ROM / RAMand

peripherals

PCI

CM aliasmemory

1GB

2GB

3GB

4GB

LM

LM

LM

LM

0xC000_0000

0xD000_0000

0xE000_0000

0xF000_0000 256MB SDRAM(CM 3)

256MB SDRAM(CM 2)

256MB SDRAM(CM 1)

256MB SDRAM(CM 0) Spare

GPIOLED/Switch

MouseKeyboardUART 1UART 0

RTCInt control

Counter/TimerEBI regs

Sys controlCM regs

Reserved

EBI

Peripheral regs

CM 0, 1, 2, 3

CS 3 (EXPM)

SSRAM

Flash

Boot ROM

256MB

512MB

768MB

1GB

64MB

128MB

192MB

256MB

0x9000_0000

0xA000_0000

0x8000_0000

0xB000_0000

0x0FFF_FFFF

0x0000_0000

0x2000_0000

0x2400_0000

0x2800_0000

0x2C00_0000

0x8000_0000

0x4000_0000

0x1000_0000

0x2000_0000

0x3000_0000


Lab 1: Code DevelopmentLab 1: Code Development Goal

How to create an application using ARM Developer Suite (ADS)

How to change between ARM state and Thumb state when writing code for different instruction sets

Principles Processor’s organization ARM/Thumb Procedure

Call Standard (ATPCS) Guidance

Flow diagram of this Lab Preconfigured project

stationery files

Steps Basic software developmen

t (tool chain) flow ARM/Thumb Interworking

Requirements and Exercises See next slide

Discussion The advantages and disadv

antages of ARM and Thumb instruction sets.


Lab 1: Code Development (cont’)Lab 1: Code Development (cont’)ARM/Thumb Interworking

Exercise 1: C/C++ for “Hello” programCaller: ThumbCallee: ARM

Exercise 2: Assembly for “SWAP” program, w/wo veneersCaller: ThumbCallee: ARM

Exercise 3: Mixed language for “SWAP” program, ATPCS for parameters passingCaller: Thumb in AssemblyCallee: ARM in C/C++


Lab 2: Debugging and EvaluationLab 2: Debugging and EvaluationGoal

A variety of debugging tasks and software quality evaluationDebugging skills

Set breakpoints and watchpointsLocate, examine and change the contents of variables, registers and memory

Skills to evaluate software quality:Memory requirement of the programProfiling: Build up a picture of the percentage of time spent in each procedure.Evaluate software performance prior to implement on hardware

Thought in this Lab the debugger target is ARMulator, but the skills can be applied to Multi-ICE/Angel with the ARM development board(s).

The instructions are based on the Dhrystone test software


Lab 2: Debugging and Evaluation (cont’)Lab 2: Debugging and Evaluation (cont’)

Principles The Dhrystone Benchmark CPU’s organization

Guidance Steps only

Steps Debugging skills Memory requirement and

Profiling Efficient C programming

JTAG and Multi-ICE Test Access and System

Debugging

Requirements and Exercises Optimize 8x8 inverse discrete

cosine transform (IDCT) according to ARM’s architecture.

Deliverables

Discussion Explain the approaches you

apply to minimize the code size and enhance the performance of the lotto program according to ARM’s architecture.

Select or modify the algorithms of the code segments used in your program to fit to ARM's architecture.


Lab 3: Core PeripheralsLab 3: Core Peripherals Goal

Understand the HW/SW coordination

Memory-mapped device Operation mechanism of polli

ng and Timer/Interrupt HAL

Understand available resource of ARM Integrator

semihosting

Principles Semihosting Interrupt handler Architecture of Timer and Inter

rupter controller Guidance

Introduction to Important functions used in interrupt handler

Steps The same to that of code d

evelopment

Requirements and Exercises Use the timer/interrupt to e

valuate the performance of other applications.

Discussion How to use muliti-timer/inte

rrupt.


Lab 4: Standard I/OLab 4: Standard I/O Goal

introduce students to control IO and learn the principle of polling, interrupt, and semihosting through this Lab.

Principle How to access I/O via the exist

ing library function call. Guidance

Micro Hardware Abstraction Layer

How CPU access input devices

Steps This program controls the Inter

gator board LED and print strings to the host using uHal API.

Requirements and Exercises Modify the LED example.

When it counts, we press any key to stop counting and then press any key to continue counting numbers.

Discussion Explain the advantage and

disadvantage of polling & interrupt.

A system can be divided into hardware, software, and firmware. Which one contains μHAL.


Lab 5: External I/O ControlLab 5: External I/O Control Goal

Understand the operation mechanism of a GPIO (General Purpose Input/Output) unit

Design a GPIO and verify the design on the Logic Module

Learn the method of connecting an external I/O device to the ARM Integrator.

Employ the GPIO to control the external I/O device.

Guidance The GPIO is an AMBA slave

module that connects to the APB

Requirements and Exercises Modify the application program suc

h that you can use the GPIO unit to control an external text LCD such that you can display an arbitrary strin

g in the LCD. Discussion

Read the ARM PrimeCell General Purpose Input/Output (PL061) Technical Reference Manual and compare the differences between GPIO PL060 and GPIO PL061.


Lab 6: On-Chip BusLab 6: On-Chip Bus Goal

To introduce the interface design conceptually. Study the communication between FPGA on logic module and ARM processor on core module. We will introduce the ARMB in detail.

Principle Overview of the AMBA

specification Introducing the AMBA AHB AMBA AHB signal list The ARM-based system

overview Guide

We use a simple program to lead student understanding the AMBA.

Requirements and Exercises To trace the hardware code

and software code, indicate that software how to communicate with hardware using the ARMB interface.

Discussion If we want to design an

accumulator (1,2,3…) , how could you do to implement it using the scratch code?

If we want to design a hardware using FPGA, how could you do to add your code to the scratch code and debugger it ?

To study the ARMB bus standard, try to design a simple ARMB interface.


Lab 7: ASIC LogicLab 7: ASIC Logic Goal

HW/SW Co-verification using Rapid Prototyping

Principles Basics and work flow for prototyping

with ARM Integrator Target platform: AMBA AHB sub-sy

stem Guidance

Overview of examples used in the Steps

Steps Understand the files for the example

designs and FPGA tool Steps for synthesis with Xilinx Foun

dation 5.1i

Requirements and Exercises RGB-to-YUV converting

hardware module

Discussion Discuss the following items

about Flash, RAM, and ROM. (1) Speed, (2) Capacity, and (3)

Internal/External Draw the interconnect among the

functional units and explain the relationships of those interconnect and functional units in AHB sub-system

Compare the differences of polling and interrupt mechanism


Lab 8: Real Time OSLab 8: Real Time OS Goal

This lab is a guide to Real-time Operating System (RTOS) in SoC design. This lab is based on μC/OS-II, a compact but complete RTOS shipped with ARM Firmware Suite (AFS). Internal mechanism of μC/OS-II is beyond the scope of this lab.

Principles Soft Real-time – tasks are pe

rformed as fast as possible Multitasking – support 64 tas

ks simultaneously; including 8 reserved tasks….

Guidance Driver, Function Kernels, Sch

eduler, API, and Communication/Memory Management

Requirements and Exercises Write an ID checking engine.

The checking rule is in the reference section.

Discussion What are the advantages of u

sing RTOS in SoC design? And what are the disadvantages?


Case designCase design Goal

Study how to use the ARM-based platform to implement JPEG encoder. In this chapter, we will describe the JPEG algorithm in detail.

Principle Detail of design method and

corresponding algorithm

Guidance In this section, we will introdu

ce the JPEG software file (.cpp) in detail. We will introduce the hardware module.

Steps We divide our program into

two parts:HardwareSoftware

Requirements and Exercises Try to understand the

communication between the software part and hardware part. To check the computing result is correct. You can easily check that the output value from the FPGA on LM


Case design (cont’)Case design (cont’) Discussion

We describe the decoder part algorithm on reference 3, try to implement it on ARM-based platform. You can divide to two parts: software & hardware.

PS: This Lab is three 4-hour classes and you can familiar with

all the steps.


SummarySummaryThe ARM has played a leading role in the opening of

this era since its very small core size leaves more silicon resources available for the rest of the system functions.

The company licenses its high-performance, low-cost, power-efficient 16/32-bit RISC processors, peripherals, and system-chip designs to leading international electronics companies.

Have major market share in portable and embedded systems.


Summary (cont.)Summary (cont.) To build SoC labs

Software tools Code development\debug\evaluation (e.g. ARM Developer Sui

te) Cell-based design EDA tools

Development boards, e.g., ARM Integrator Core Module: 7TDMI, 720T, 920T, etc Logic Module (Xilin XCV2000E, Altera LM-EP20K1000E) ASIC Development Platform (Integrator/AP AHB ) Multi-ICE Interface

Prerequisite C/Verilog/VHDL programming skills Microprocessor and experiments Computer Organization and Architecture (Required) VLSI Design (Preferred)


ReferenceReference[1]http://twins.ee.nctu.edu.tw/courses/ip_core_02/index.html

[2] ARM System-on-Chip Architecture by S.Furber, Addison Wesley Longman: ISBN 0-201-67519-6.

[3] http://www.arm.com

s&ip consortium course material soc overview and arm integrator prof. an-yeu (andy) wu...

Documents