sjd / tab1 fiber tasks preliminary design review december 5, 2001
TRANSCRIPT
SJD / TAB 4
Phone System
• Two phones per antennas, – Vertex room and Pedestal
• Phone numbers remain with the antenna• Will use the fiber system• Will use COTS hardware
• Responsible for providing the Fiber from the Termination panel to Phone Room
SJD / TAB 5
Battery Backed-upCommunication
• Similar to VLA WYE Monitor
• Un-interruptible power supply
SJD / TAB 6
MCB Network
• Standard Ethernet ( two Fibers )• COTS Network Router• 1 Gbit/s to antennas• 100 Mbit/s in the antennas• Support ~48 nodes in each antenna
– Two multi-mode fibers per node
– Fiber to the Module
• Patch Panel will be located in the computer room
SJD / TAB 7
LO System
• Responsible for Lasers, Modulators, Fiber, Circulators, Receivers– Maybe integrated into the LO module– Phase stable system
• LO Patch panel – located in the Electronics Room– Fiber test equipment
• System Self-tests included
SJD / TAB 8
IF System
• Transmitters
• MUX-Fiber-DeMUX components
• Fiber Amplifiers
• Receivers
• Online monitoring
SJD / TAB 9
IF Transmitters
• Twelve Lasers – ITU spacing • Automated Test
– Output Power Measured at Each Laser ( 1% tap)– MCB accessible
• Manual Optical Power Measurements– Can be measured at the MUX output
SJD / TAB 10
IF Patch Panel
• Located in the Correlator room
• Includes De-MUX hardware
• Includes Fiber Amplifiers
• Manual Test Equipment– Full Signal Communication Analyzer
SJD / TAB 11
Rack Mount EDFA
• MCB adjusted Gain of each amplifier
• Also measures in/out optical power
SJD / TAB 12
IF Communication Analyzer
• IF Patch Panel– Manual measurements during reconfiguration
• Complete Diagnostic– Jitter– Q Factor– Noise Margin– Rise / Fall times
SJD / TAB 13
IF System On Board Tests
• Test Patterns Generated at each Transmitter
• Nine Test Patterns– No Sync, alternating 1/0, all Ones, all Zeros– Parity Errors
• MCB controlled
SJD / TAB 15
Divided Sync Word
• Required to Identify Correct 1/2 Sequence
• 10 Bits long, – 6 bit identify Start-of-Frame– Barker Sequence - equal Ones versus Zeros
• Three Stage Synchronization Process
SJD / TAB 16
Sync Implementation
selector
32 bits
@
250 MHz
64 bitlatch
64 bitlatch
16 bit partioningand re-ordering
multiplexby 5
multiplexby 5
selector
multiplexby 16
16 Format bits@ 62.5 MHz
16 Format bits@ 62.5 MHz
64 bits@ 62.5 MHz
64 bits@ 62.5 MHz
80 bits@ 62.5 MHz
80 bits@ 62.5 MHz
16 bits@ 312.5 MHz
16 bits@ 312.5 MHz
16 bits@ 625 MHz
1 bit@ 10 GHz
160 bit Frames @10 GHz
SJD / TAB 17
Three Stage Synchronization
• Stage 1 - Search bits for frame pattern
• Stage 2 – Monitor for “Correct” sync
• Stage 3 – If two “Bad” frames in a row
or 2-out-of-8 fames are “Bad”
Then Start Search Again
SJD / TAB 18
Timing Signals
• Metaframe Index
• Metaframe Sequence Count
• 1 PPS
• 1 Pulse per 10 seconds
SJD / TAB 19
Data Valid Signal
• Initiated at the antenna– Toggle Switch– MCB controlled
• Passed to correlator
SJD / TAB 20
Check Sum - BER
• Each 19 bits Generate a check Sum
• Provides continuous Bit-Error-Rate Performance Monitoring
• Only odd # of errors per 19 bits Detected
• Flags Correlator when over threshold
SJD / TAB 21
Scrambling
• Frame Synchronous Scrambling– Select pattern is modulo 2 added– Entire frame – except sync bits
• Pattern results in– Equal number of Ones/Zeros providing
• Balance ac content, sufficient transitions• Minimize low frequency content
SJD / TAB 22
Conclusion
• Five systems will be supported
• On Board Tests Incorporated ( MCB)
• Patch Panels will have test equipment
• IF Data Format will support Growth