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S.K.P. Engineering College, Tiruvannamalai II SEM

Computer Science Engineering Department 1 Digital Principles and System Design

Digital Principles and System Design

SKP Engineering College

Tiruvannamalai – 606611

A Course Material

on

By

G.Shanthi

Assistant Professor

Computer Science and Engineering Department



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This is to Certify that the Electronic Study Material

Subject Code: CS6201

Subject Name:Digital Principles and System Design

Year/Sem: I / II

Being prepared by me and it meets the knowledge requirement of the University

curriculum.

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Name: G.Shanthi

Designation: Assistant Professor

This is to certify that the course material being prepared by Mrs.G.Shanthi is of the

adequate quality. He has referred more than five books and one among them is from

abroad author.

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Name: K.Baskar Name: Dr.V.Subramania Bharathi

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CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C 3 0 0 3

OBJECTIVES:

The student should be made to:

Learn the various number systems.

Learn Boolean Algebra

Understand the various logic gates.

Be familiar with various combinational circuits.

Be familiar with designing synchronous and asynchronous sequential circuits.

Be exposed to designing using PLD

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9

Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods – Logic Gates – NAND and NOR Implementations.

UNIT II COMBINATIONAL LOGIC 9

Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations, Code Conversion – Decoders and Encoders – Multiplexers and Demultiplexers – Introduction to HDL – HDL Models of Combinational circuits.

UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 9

Sequential Circuits – Latches and Flip Flops – Analysis and Design Procedures – State Reduction and State Assignment – Shift Registers – Counters – HDL for Sequential Logic Circuits.

UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 9

Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.

UNIT V MEMORY AND PROGRAMMABLE LOGIC 9

RAM and ROM – Memory Decoding – Error Detection and Correction – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices – Application Specific Integrated Circuits.



TOTAL: 45 PERIODS

OUTCOMES:

At the end of this course, the student will be able to:

Perform arithmetic operations in any number system.

Simplify the Boolean expression using K-Map and Tabulation techniques.

Use boolean simplification techniques to design a combinational hardware circuit.

Design and Analysis of a given digital circuit – combinational and sequential.

Design using PLD.

TEXT BOOK:

1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008.

REFERENCES:

1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 2007.

2. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House, Mumbai, 2003.

3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.

4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.



CONTENTS

S.No Particulars Page

1 Unit – I 7

2 Unit – II 22

3 Unit – III 43

4 Unit – IV 69

5 Unit – V 80



Prerequiste

You must know atleast the basics of logical gates , number systems including Binary to octal, decimal to binary and the basic laws which include Demorgan’s law, Distributive law, Cummulative and Associative law.



Unit – I

Boolean Algebra And Logic Gates

Part – A

1. Convert the following binary code into a Gray code : 10101110002 [CO1-L1-April/

May 2016] Given binary code is : 10101110002

Equivalent gray code is : 1111100100

2. Determine (377)10 in Octal and Hexadecimal equivalent. [CO1-L1-Nov/Dec 2014] (377)10= (571)10

(377)10= (179)16

3. Convert : [CO1-L1-May 2015] (a) (475.25)8 to its decimal equivalent (b) (549.B4)16 to its binary equivalent (a) (475.25)8 = (319.625)10 (b) (549.B4)16= (010101001001.10110100)2

4. What is the need of number conversions in digital system? [CO1-L1] The need of number conversions in digital system is essential to perform basic

mathematical calculations. It finds more importance in digital computers and

microprocessor based control systems.

5. Classify the binary codes. [CO1-L2]

Weighted codes Non-weighted codes Alphanumeric codes Cyclic codes Error detection and correction codes.

6. What are weighted binary codes? [CO1-L1]

A code which consists of bit weightage for each digit present in the binary code is called weighted binary code.Example : 8421 code and 2421 code.



7. What are non-weighted binary codes? [CO1-L1]

Non-weighted binary codes are not having any weightage for the digits present in binary

code. Example:Gray code and Excess-3 code.

8. What is gray code? Why it is called as reflective code? [CO1-H1] A gray code is an un-weighted binary code. The four bit gray code can be used to

represent the decimal number from 0 to 15. In this representation the last and first entry of

gray code consequently differs only in one bit position (MSB bit). So this is also

calledreflective code.

9. List the most widely used alphanumeric codes? [CO1-L1] ASCII - American Standard Code for Information Interchange EBCDIC -Extended Binary Coded Decimal Interchange Code

10. What is BCD code? [CO1-L1]

BCD stands for Binary Coded Decimal. The BCD code represents the number 0 to 9 with

the binary representation 0000 to 1001. The decimal numbers are directly represented with

the weightages of 8421 in BCD code.

11. What are the basic properties of Boolean algebra? [CO1-L1]

12. List the types of Arithmetic operator. [CO1-L1] • Binary Addition • Binary Subtraction • Binary multiplication • Binary division



13. What is meant by Boolean Functions? [CO2-L1]

Boolean functions consists of binary variables, the constants 0 and 1, and the logic operation symbols. A Boolean function can be represented in a truth table. A Boolean function expresses the logical relationship between binary variables. A Booleanfunctions can be transformed from an algebraic expression into a circuit diagram composedof logic gates. 14.Express the following function in truth table and Logic Diagram. [CO2-L3] F1 = x + y'z , F2 = x’y’z+x’yz+xy’

15.Simplify the function x +x'y. [CO2-L3].

x +x'y = (x+x')(x+y) = 1(x+y) = x + y. 16.Write the POS representation of the following SOP function : F(x,y,z) = ∑m (0,1,3,5,7) [CO2- L3 – April /May 2016]

The POS function is written as F(x,y,z) = πM (2,4,6) (or) F(x,y,z) = (x+y’+z) (x’+y+z) (x’+y’+z)

17.Convert the given expression in canonical SOP form : Y = AC +AB +BC [CO2-H1-April/May 2015] Y = AC(B+B’)+AB(C+C’)+BC(A+A’) ABC+AB’C+ABC+ABC’+ABC+A’BC(Remove Identical term) ABC + AB’C + ABC’+A’BC (or) Y (A,B,C) = ∑m(3,5,6,7)



18. Define Minterm and Maxterm. [CO2-L1]

Each individual term in standard SOP form is called minterm. Minterms are standard product.(AND terms) Each individual term in standard POS form is called maxterm. Maxterms are standard sum.(OR terms) 19. What are Canonical form?[CO2-L1]

Any Boolean function that is expressed as a sum of minterms or as a product of max terms is said to be in its “canonical form”.It mainly involves in two Boolean terms, “minterms” and “maxterms”.

20. Define SOP and POS. [CO2-L1] Sum of Products (SOP): The logical sum of two or more logical product terms is called a

Sum of Products expression. It is basically an OR operation of AND operated variables.Example :AB + ABC + CDE Product of Sum (POS): A product of sums expression is a logical product of two or more logical sum terms. It is basically an AND operation of OR operated variables. Example :(A+B) * (A + B + C) * (C +D) 21.What are Don’t care terms? [CO2-L1-April/May 2013] In some logic circuits, certain input conditions never occur, therefore the corresponding never appears. In such cases, the output level is not defined and it can be either High or Low. These output levels are indicated by ‘ X’ or ‘d’ in the truth table . These terms are called as don’t care terms or don’t care conditions.

22. What are the methods adopted to reduce Boolean function? [CO2-L1] (i) Minimization using Boolean theorems (ii) Karnaugh mapping (iii) Quine-McCluskey method (Tabulation method) 23. Define prime implicant. [CO2-L1]

All the implicants of a function determined using a Karnaugh map are called prime

implicants.

24.Implemen AND gate using only NAND gates. [CO2-L3- NOV /DEC 2014] Input Output Rule ((XY)'(XY)')' = ((XY)')' Idempotent

= (XY) Involution



25. Prove the following statement using Demorgan’s Theorem: ((A+B)’)’= A + B [CO2 – H2]

+ = . from theorem 2 ( . ) ′=A+B from theorem 1.

Theorem 1: = ̅ + The complement of a product is equal to the sum of the complements. ℎ 2 ∶ + = . The complement of a sum is equal to the product of the complements.

Part – B

1. Discuss Briefly about different number system conversions performed in digital System . [CO1 – L2]

The hexadecimal (base 16) number system (often called "hex" for short) provides us with a shorthand method of working with binary numbers. One digit in hex corresponds to four binary digits (bits), so the internal representation of one byte can be represented either by eight binary digits or two hexadecimal digits. Less commonly used is the octal (base 8) number system, where one digit in octal corresponds to three binary digits (bits). In the event that a computer user (programmer, operator, end user, etc.) needs to examine a display of the internal representation of computer data (such a display is called a "dump"), viewing the data in a "shorthand" representation (such as hex or octal) is less tedious than viewing the data in binary representation. The binary, hexadecimal , and octal number systems will be looked at in the following pages.

The decimal number system that we are all familiar with is a positional number system. The actual number of symbols used in a positional number system depends on its base (also called the radix). The highest numerical symbol always has a value of one less than the base. The decimal number system has a base of 10, so the numeral with the highest value is 9; the octal number system has a base of 8, so the numeral with the highest value is 7, the binary number system has a base of 2, so the numeral with the highest value is 1, etc.

Any number can be represented by arranging symbols in specific positions. You know that

in the decimal number system, the successive positions to the left of the decimal point



represent units (ones), tens, hundreds, thousands, etc. Put another way, each position represents a specific power of base 10. For example, the decimal number 1,275 (written

1,27510)* can be expanded as follows. Example: 11 = 1 x 20+ 1 x 2

1 = 3.

2.Define Binary Code. Describe in detail about different types of Binary codes.

[CO1- L1]

The alphabetic data, numeric data, alphanumeric data, symbols, sound data and video data, all are represented as combination of bits in the computer. The bits are grouped in a fixed size, such as 8 bits, 6 bits or 4 bits. A code is made by combining bits of definite size. Binary Coding schemes represent the data such as alphabets, digits 0-9, and symbols in a standard code. A combination of bits represents a unique symbol in the data. The standard code enables any programmer to use the same combination of bits to represent a symbol in the data.



Types of binary codes

1. Weighted codes

2. Non Weighted Codes

Weighted Binary Systems

Weighted binary codes are those which obey the positional weighting principles, each position of the number represents a specific weight. The binary counting sequence is an example.

8421 Code/BCD Code

The BCD (Binary Coded Decimal) is a straight assignment of the binary equivalent. It is

possible to assign weights to the binary bits according to their positions. The weights in the BCD code are 8,4,2,1.

Example: The bit assignment 1001, can be seen by its weights to represent the decimal 9

Because:1x8+0x4+0x2+1x1 =9

2421 Code This is a weighted code, its weights are 2, 4, 2 and 1. A decimal number is represented in 4- bit form and the total four bits weight is 2 + 4 + 2 + 1 = 9. Hence the 2421 code represents the decimal numbers from 0 to 9.

5211 code This is a weighted code; its weights are 5, 2, 1 and 1. A decimal number is represented in 4- bit form and the total four bits weight is 5 + 2 + 1 + 1 = 9. Hence the 5211 code represents the decimal numbers from 0 to 9.



Reflective Code A code is said to be reflective when code for 9 is complement for the code for 0, and so is for 8 and 1 codes, 7 and 2, 6 and 3, 5 and 4. Codes 2421, 5211, and excess-3 are reflective, whereas the 8421 code is not.

Sequential Codes A code is said to be sequential when two subsequent codes, seen as numbers in binary Representation, differ by one. This greatly aids mathematical manipulation of data. The 8421 and Excess-3 codes are sequential, whereas the 2421 and 5211 codes are not.

Non Weighted Codes Non weighted codes are codes that are not positionally weighted. That is, each position within the binary number is not assigned a fixed value.

Excess 3 codes

Excess-3 is a non weighted code used to express decimal numbers. The code derives its name from the fact that each binary code is the corresponding 8421 code plus 0011(3).Example: 1000 of 8421 = 1011 in Excess-3

Gray Code The gray code belongs to a class of codes called minimum change codes, in which only

one bit in the code changes when moving from one code to the next. The Gray code is non- weighted code, as the position of bit does not contain any weight. The gray code is a reflective digital code which has the special property that any two subsequent numbers

codes differ by only one bit. This is also called a unit-distance code. In digital Gray code has got a special place.



3.State and Prove properties of Boolean Algebra in detail. [CO1 – H2] Properties of Boolean Algebra

i.Commutative Property

ii.Associative Property

iii.Distributive Property

Definition of Boolean properties i) Commutative law: - Using OR operation the Law is given as - A + B = B + A This law using AND operation is - A.B = B.A

This mean the same as previous the only difference is here the operator is (.). Here the order of the AND operations conducted on the variables makes no difference. This is an important law in Boolean algebra.

ii) Associative law: This law is given as - A+(B+C) = (A+B)+C , This is for several variables, where the OR operation of the variables result is same though the grouping of

the variables. This law is quite same in case of AND operator. It is A.(B.C) = (A.B).C Thus according to this law grouping of Boolean expressions do not make any difference

during the AND operation of several variables. Though but these laws are also very important. iii) Distributive law :- Among the laws of Boolean algebra this law is very famous and important too. This law is composed of two operators. AND and OR. The law is A + BC = (A + B) (A + C) Here the logic is, AND operation of several variables and then the OR operation of the result with a single variable is equivalent to the AND of the OR of single variable to one of

the variable of several variables to make it simple, set BC be the several variables then A will be OR with B. Firstly and again A will be OR with C, then the result of the OR operation will be AND. The proof of this law in Boolean algebra is given below:-

Proof A + BC = A.1 + BC [ Since, A.1 = A] = A(1 + B) + BC [Since, B+1 = 1] = A.1 + AB + BC = A.(1 + C) + AB + BC [Since, A.A = A.1 = A] = A (A + C) + B (A+C)

A+BC = (A+B)(A+C) This law can also be for Boolean multiplication.



Boolean Theorems and their proof

(i) A+AB = A Proof. A+AB = A.1 + AB [A.1 = A] = A(1+B) [Since, 1 + B = 1] = A.1 = A ii) A(A+B) = A Proof. A(A+B) = A.A + A.B = A+AB [Since, A.A = A] = A(1+B) = A.1 = A iii) A+ĀB = A+B Proof: A+ĀB = (A+Ā) [Since, A+BC = (A+B)(A+C) using distributive law.] = 1 (A+B) [Since, A+Ā = 1] = A+B iv) A.(Ā+B) = AB Proof: A.( Ā+B) = A. Ā+AB = AB [ AĀ = 0] (v) AB + ĀC+BC = AB+ĀC Proof: AB+ĀC+BC = AB + ĀC + BC.1

= AB+ĀC+BC(A+Ā) [ A+Ā=1] = AB+ĀC+ABC+ĀBC

= AB(1+C)+ ĀC(1+B) [‡ 1+B=1=1+C] = AB+ĀC

(vi) (A+B)( Ā+C)(B+C) = (A+B)( Ā+C) Proof. (A+B)( Ā+C)(B+C) = (A+B)( Ā+C)(B+C+O)

= (A+B)( Ā+C)(B+C+AĀ) [ By distributive law] = (A+B)(A+B+C)( Ā+C)( Ā+C+B)

= (A+B)( Ā+C) [‡ A(A+B)= A]

The other small laws of Boolean are given below.

(a) A+0 = A (b) A+1 = 1 (c) A+A = A (b) A+Ā = 1 (e) A.1 = A (f) A.0 = 0

(c) A.A = A (h) A. Ā = 0 (i) A' = A

Demorgan’s theorem: (A+B)’=A’B’, (AB)’=A’+B’



4.Simplify the following Boolean functions by using K‘Map in SOP & POS. F (w, x, y, z) = (0,1, 4, 5, 8,9, 12, 13) [CO2 – L3].



5.Simplify the Boolean function using Quine-McCluskey method F=(1,2,3,7,8,9,10,11,14,15). [CO2 – L3] Rules of tabulation method The algorithm may be performed manually using the following steps: 1. Have available the minterms of the function to be minimized. There may be X's for don't care cases. 2. Create groups of minterms, starting with the minterms with the fewest number of ones. 3. All minterms in a group must have the same number of ones and if any X's, the X's must be in the same position. There may be some groups with only one minterm. Create new minterms by combining minterms from groups that differ by a count of one. of the newly created minterm. Mark the minterms that are used in combining (they will be deleted at the end of this step). Delete the marked minterms. Repeat steps 2) 3) and 4) until no more minterms are combined.The minimized function is the remaining minterms,deleting any X's. Firstly these minterms are represented in the binary form as shown in the table below. The above binary representations are grouped into a number of sections in terms of the number of 1's as shown in the table below. 1. Binary representation of minterms

2. Group of minterms for different number of 1's 3.Any two numbers in these groups which differ from each other by only one variable



can be chosen and combined, to get 2-cell combination, as shown in the table below.



6. Implement the Logic Gates using NAND and NOR Gates. [CO2 – L3] Realization of logic function using NAND gates Any logic function can be implemented using NAND gates. To achieve this,first the Logic function has to be written in Sum of Product (SOP) form. Once logic function is converted to SOP, then is very easy to implement using NAND gate. In other words any logic circuit with AND gates in first level and OR gates in second level can be converted into a NAND-NAND gate circuit.

Consider the following SOP expression

F = W.X.Y + X.Y.Z + Y.Z.W

The above expression can be implemented with three AND gates in first stage and one OR gate in second stage as shown in figure.



Relization of logic function using NOR gates Any logic function can be implemented using NOR gates. To achieve this, first the logic function has to be written in Product of Sum (POS) form. Once it is converted to POS, then it's very easy to implement using NOR gate. In other words any logic circuit with OR gates in first level and AND gates in second level can be converted into a NOR-NOR gate circuit. Consider the following POS expression F = (X+Y). (Y+Z) The above expression can be implemented with three OR gates in first stage and one AND gate in second stage as shown in figure.



Unit II

Combinational Logic

Part – A

1. Define Combinational circuit. [CO3 – L1]

A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination of inputs without regard to previous inputs.

2. Explain the design procedure for combinational circuits . [CO3 – L2] Determine the number of available input variables & required O/P variables. Assigning letter symbols to I/O variables Obtain simplified Boolean expression for each O/P. Obtain the logic diagram.

3. What is code conversion? [CO3 – L1] If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit, which converts one system of codes to the other. The process of conversion is referred to as code conversion.

4. What is code converter? [CO3 – L1] It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter.

5.List the Analysis procedure for combinational circuits. [CO3 – L1] Find the given circuit is combinational or sequential. Combinational circuit has a logic gate with no feedback paths or memory elements. A feedback path is a connection from the output of one gate to the input of second gate that forms part of the input to the first gate.

6. List the Design procedure for combinational circuits. [CO3 – L1] Determine the required number of inputs and outputs and assign a symbol to each. Derive the truth table that defines the required relationship between inputs and outputs. Obtain the simplified Boolean functions for each output as a function of the input variables. Draw the logic diagram and verify the correctness of the design.



7. What is a multiplexer? [CO3 – L1]

A multiplexer (MUX) also called a data selector, is a combinational circuit with more than one input line, one output line and more than one selection line. A multiplexer selects binary information present on any one of the input lines, depending upon the logic status of the selection inputs and routes it to the output line. If there are n selection lines,then the number of maximum possible input lines is 2n and the multiplexer is referred to as a 2n-to-1multiplexer or 2n×1 multiplexer.

8. Give one application each for Multiplexer and Decoder. [CO3 – L1- Nov/Dec 2014]

Application of Multiplexer: In telephone network, multiple audio signals are integrated on a single line for transmission with the help of multiplexers Application of Decoder: Used in code converters and for address decoding.

9. Differentiate a decoder from a demultiplexer. [CO3 – L2- Nov/Dec 2009]

Decoder Demultiplexer

Converts binary information from n

input lines to 2n unique output lines.

It receives information on a single input

and transmits the same information

over one of several (2n) output lines.

There are no selection lines. The selection of specific output line is

controlled by the value of selection line.

10.Realize the Boolean function using appropriate multiplexer-F(A, B, C)=∑(1, 2, 5, 7) [CO3 – L3].



11. List few applications of Multiplexer. [CO3 – L1- April/May 2012]

Data routing Logic function generator Control sequencer and Parallel to Serial converter

12. Draw the logic diagram of a 4 line to 1 line Multiplexer. [CO3 – L3- April/May 2013]

13. Draw the logic diagram of a 2 :1 Multiplexer. [CO3 – L3]

14.What is encoder?[CO3 – L1- April /May 2012]

A encoder is a combinational circuit that has 2n input lines and n output lines. Converts an active input signal into a coded output signal . No of outputs is less than the number of inputs.



15. What is priority encoder? [CO3 – L1- May 2014]

A priority encoder is an encoder circuit in which if two or more inputs are equal to 1 at the

same time, the input having the highest priority will take precedence.

16. Design a half subtractor. [CO4 – H3- April/May 2016]

17. Write an expression for borrow and difference in a full subtractor circuit. [CO3 – L1- A/M 2010]

Borrow = ̅ + ̅ + (or)

= ̅ + + ( ⊕ )

Difference = ⊕ ( ⊕ )

18. Define Hardware Description Language (HDL). [CO4 – L1] The size and complexity of the digital systems increases, they cannot be designed manually; their design is highly complex. At the most detailed level, they may consists of millions of elements i.e.) transistor or logic gates. So the computer-aided tools are used to design the Hardware Description Language. 19. Write the Structure of Verilog module ?[CO4 – L1]

module <module name> <port list>; <declares> <module items> endmodule

20. List the Operators in Verilog HDL . [CO4 – L1] Boolean logical Unary reduction logical Bitwise logical Relational Binary arithmetic Unary arithmetic



21. What are the Verilog data types? [CO4 – L1]

reg and wire reg-variables store the last value that was procedurally assigned to them whereas the wire - variables represent physical connections between structural entities such as gates.

Part - B

1.Explain about the Analysis Procedure for Combinational Circuit. [CO3 – L2] 1. The analysis for a combinational circuit consists of determining the function that the circuit implements. 2. The analysis starts with a given logic circuit diagram and culminates with a set of Boolean functions or a truth table, together with a possible explanation of the operation of the circuit. 3. If the logic diagram to be analyzed is accompanied by a recognizable function name or a statement of what the diagram is assumed to accomplish, then the analysis problem reduces to a verification of the stated function.

Steps of analysis procedure Label all gate outputs that are a function only of input variables or their complements with arbitrary symbols. Determine the Boolean functions for each gate output. Label the gates that are a function of input variables and previously labeled gates with different arbitrary symbols. Find the Boolean functions for the outputs of these gates. Repeat the process outlined in step 2 until the outputs of the circuit are obtained in terms of the input variables.

Analyse the following Boolean Function F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1; F1 = T3 + T2 F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC



Note that the circuit has four binary input variables A, B, and C and two binary output variables and. The outputs of gates that are a function of input variables only are and. The Boolean functions for these two outputs are F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1; F1 = T3 + T2 F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC Derivation of truth table from logic diagram and Boolean function Determine the number of input variables in the circuit. For n inputs, list the binary numbers from 0 to 2n – 1 in a table. 1. Break the circuit into small single-output blocks by labeling each block output with an arbitrary symbol. 2. Obtain the truth table for the blocks with functions that depend on input variables only. 3. Proceed to obtain the truth table for blocks with functions that depend on previously defined inputs and block outputs, until the columns for all circuit outputs are determined



2. Design a Code Conversion that converts a BCD to Excess 3 Code. [CO3 - H3 – May/June 14]

Conversion of signals, or groups of signals, in one code into corresponding signals, or groups of signals, in another code. Principle of Code Conversion A process for converting a code of some predetermined bit structure, such as 5, 7, or 14 bits per character interval, to another code with the same or a different number of bits per character interval.

Types of codeconversion BCD to Gray code. and viceversa. BCD to excess3 code and viceversa. Binary to gray code and viceversa Implementation of code conversion circuit BCD and Excess-3 codes



K map and Boolean expression - For each symbol of the Excess-3 code, we use 1’s to draw the map for simplifying Boolean function.

Circuit implementation z = D’; y = CD + C’D’ = CD + (C + D)’ , x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’ ,w = A + BC + BD = A + B(C + D)



3.Design a Full Adder and derive expression for sum and carry. Realize using Gates.

[CO3 – H3 – Nov/Dec15] A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output. Such a building block becomes a necessity when it comes to adding binary numbers with a large number of bits. The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits only. Let us recall the procedure for adding larger binary numbers. We begin with the addition of LSBs of the two numbers. We record the sum under the LSB column and take the carry, if any, forward to the next higher column bits. As a result, when we add the next adjacent higher column bits, we would be required to add three bits if there were a carry from the previous addition. We have a similar situation for the other higher column bits. Also until we reach the MSB. A full adder is therefore essential for the hardware implementation of an adder circuit capable of adding larger binary numbers. A half-adder can be used for addition of LSBs only.



Truth Table

Boolean expression using K map



S = x’y’z + x’yz’ + xy’z’ + xyz C = xy + xz + yz Implementation of Full adder circuit

4. With neat diagram explain the 4-bit adder with carr lookahead. [CO3 – L2- A/M 15] This is also called Ripple Carry Adder, because of the construction with full adders are connected in cascade. Truth Table



Implementation of Binary adder circuit

Carry Look Ahead Adder The most widely used technique employs the principle of carry look-ahead to improve the speed of the algorithm. Boolean expression Pi = Ai + Bi steady state value Gi = AiBi steady state value Output sum and carry Si = Pi + Ci Ci+1 = Gi + PiCi Gi : carry generate Pi : carry propagate C0 = input carry C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0



Implementation of Carry Look ahead adder circuit

5.Explain about Decoder with an implementation of Boolean Function. [CO3 – L3]

The decoder is called n-to-m-line decoder, where m≤2n the decoder is also used in

conjunction with other code converters such as a BCD-to-seven segment decoder.

3-to-8 line decoder: For each possible input combination, there are seven outputs that are equal to 0 and only one that is equal to 1. Some decoders are constructed with NAND gates, it becomes more economical to generate the decoder minters in their complemented form. As indicated by the truth table, only one output can be equal to 0 at any given time, all other outputs are equal to 1. Types of decoder

2 to 4 decoder 3 to 8 decoder 4 to 16 decoder and so on.



Implementation of decoder circuit 3 to 8 decoder



2 to 4 decoder

6.Explain about Encoder with an implementation of Boolean Function. [CO3 – L3]

An encoder is the inverse operation of a decoder (ie) contains m inputs and convert it into to n outputs. If two inputs are active simultaneously, the output produces an undefined combination. We can establish an input priority to ensure that only one input is encoded. Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the inputs are 0; the output is the same as when D0 is equal to 1.

Types of Encoder 4to2 encoder, 8to3 encoder, 16to4 encoder, Priority encoder and so on

Implementation of encoder circuit 8 to 3 encoder z = D1 + D3 + D5 + D7 ,y = D2 + D3 + D6 + D7 ,x = D4 + D5 + D6 + D7



V=0 no valid inputs, V=1 valid inputs X’s in output columns represent don’t-care conditions. X’s in the input columns are useful for representing a truth table in condensed form. Instead of listing all 16 minterms of four variables.



x = D2 + D3 , y = D3 + D1D’2 , V = D0 + D1 + D2 + D3



7.Define Multiplexer. Design the following Boolean Functions with a Multiplexer: F(x, y, z) = (1,2,6,7). [CO3 – H3 – April/May15]

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector.

Types of Muliplexer 2 to 1 MUX 4 to 1 MUX 16 to 1 MUX and so on

Implementation of MUX circuit 2 to 1 MUX S = 0, Y = I0 S = 1, Y = I1 Truth Table S Y Y = S’I0 + SI1 0 I0

1 I1



4 to 1 MUX

Boolean function implementation A more efficient method for implementing a Boolean function of n variables with a multiplexer that has n-1 selection inputs. F(x, y, z) = (1,2,6,7)



8.What is HDL. Write a Verilog HDL Code for 2:1 Multiplexer with different model description. [CO3-L3] In electronics, a Hardware Description Language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. Modelling Techniques A module can be described in any one of the following modeling techniques:

Gate-level modeling uses instantiation of primitive gates and user-defined modules.

Dataflow modeling uses continuous assignment statements with keyword assign.

Behavioral modeling uses procedural assignment statements with keyword always.

Gate-level modeling A circuit is specified by its logic gates and their interconnection. Verilog recognizes

12 basic gates as predefined primitives. The logic values of each gate may be 1, 0, x (unknown), z(high-impedance).



Behavioral modeling It is used mostly to describe sequential circuits, but can be used also to describe

combinational circuits. Behavioral descriptions use the keyword always followed by a list of procedural

assignment statements.

Data Flow Modelling A continuous assignment is a statement that assigns a value to a net. The data type net is used in Verilog HDL to represent a physical connection

between circuit elements. A net defines a gate output declared by an output or wire.



Unit III

Synchronous Sequential Logic

Part- A

1. What is sequential circuit? [CO4 – L1] Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path.

2. List the classifications of sequential circuit. [CO4 – L1] i) Synchronous sequential circuit. ii) Asynchronous sequential circuit.

3. What is Synchronous sequential circuit?[CO4 – L1] A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time.

4. What is a clocked sequential circuit? [CO4 – L1] Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don’t cause instability problems.

5.Show how the JK flip flop can be modified into a D flip flop or a T flip flop. [CO4 – H1-Nov/Dec 2014]

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations.J and K are expressed in terms of D and Qp. The four combinationconversion table, the K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to D are given below.



6.Draw the truth table and state diagram of SR flip-flop. [CO4 – L1-Nov/Dec 2015]

State diagram

Truth table

7.Give the characteristic equation and characteristic table of SR flip-flop.[CO4 – L1- April/May 2016]



8.Write down the characteristic equation for JK flip-flop. [CO4 – L1- May’11]

Characteristic equation for JK flip-flop is Qt+1 = +

9.How do you eliminate the race around condition in a JK flip-flop. [CO4 – H1- Dec 2010]

Race around condition in a JK flip-flop can be eliminated using master-slave configuration. A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and other as a slave. The output of the master is fed as an input to the slave.

10.Realize JK flip flop using D flip flop. [CO4 – L3-Dec 2011] In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp. The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below.

11.Realise T-FF from JK-FF. [CO4 – L3]



12.Draw the state table and excitation table of T flip-flop.[CO4–L1-Dec 2010]

13.How a D flipflop is converted into T flip-flop./ Convert D flip to T flip-flop. [CO4 – L3-Dec 2012, May 2013].



14. How many flipflops are required to build a binary counter that counts from 0 to 1023. [CO4 – L3 - May 2013]

Number of flip-flops is given as 2n ≥ count +1, where n is the number of flipflops. Therefore, 2n ≥ 1023 +1 , i.e., 2n ≥ 1024. It implies , n = 10 Hence, 10 flip-flops are required to build a binary counter that counts form 0 to 1023.

15.Define : Latches. [CO4 – L1 -Nov 2013]

The flip-flops that operate with signal levels are referred as latches. Latch is a memory cell which is capable of storing one bit of information , ie. Logic 1 or logic 0. Latches are controlled by enable signals and they are level sensitive devices. Latches are basic building blocks of flip-flops.

16.Sketch the logic diagram of a clocked SR flip flop.[CO4 – L1 - May 2014]

17.Draw the master-slave JK flip-flop. [CO4 – L1]



18.What are edge triggered flip flops?[ CO4 – L1-Nov/Dec 2015]

Flip-flop changes its state either at positive edge or negative edge of the clock pulse and is sensitive to its inputs only at this transition of the clock. These type of flipflops are referred to as edge triggered flip flops. 19.What are level triggering flip flops? [CO4 – L1]

20.Mention any two differences between the edge triggering and level triggering. [CO4 – H1 -May’2010,2012]

Edge Triggering Level Triggering

The flip flop changes its state either at positive edge or negative edge of the clock pulse and is sensitive to its inputs only at this transition of the clock.

hen the clock pulse goes high the flip-flop is said to be level triggered flip-flop.

hen flip-flop, changes its state by applying positive clock- positive level triggering.

hen flip-flop, changes its state by applying negative clock – negative level triggering.

21. What is meant by programmable counter? Mention its application. [CO4 – L1-May 2010]

A counter that divides an input frequency by a number which can be programmed is called programmable counter. Applications: Frequency division, digital clock, stop watch and

programmable logic controller.



22. Compare the logics of synchronous counter and ripple counter. [CO4–H1-May14]

Synchronous counter Ripple ( Asynchronous counter)

In Synchronous counter, no connection exists between output of first flip-flop and clock input of next flip-flop.

Here flip-flops are connected in such a way that output of first flip-flop drives the clock for the next flip-flop.

All flip-flops are clocked simultaneously. All flip-flops are not clocked simultaneously.

Circuit is simple. Circuit is complex.

High speed counters. Low speed is the drawback.

23. What is a ripple counter?[CO4 – L1]

A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock input of the following flip-flop. A ripple counter is also called as asynchronous counter or a serial counter, as the clock input is applied only to the first flip c flop, also called the input flip-flop in the cascaded arrangement. 24.What is a shift register?[CO4 – L1]

A register capable of shifting its binary information in one or both directions is called a shift register. 25.Mention the types of shift register?[CO4 – L1]

SISO – Serial in Serial Out SIPO - Serial in Parallel Out PISO- Parallel in Serial Out PIPO – Parallel in Parallel Out Bidirectional shift register 26.State the differences between Mealy and Moore state machines.[CO4 – H1- N/D

2014 & April/May 2016]

Moore Machine Mealy Machine

Its output is a function of present state only.

Its output is a function of present state as well as present input.

Input changes does not affect the output. Input changes may affect the output of the circuit.

It requires more number of states for implementing the same function.

It requires less number of states for implementing the same function.



27.State the rules for state assignment. [CO4 – H1-April /May 2015]

Assignment of values to state variables is called state assignment. A binary value is assigned to each of the states.

28.What is statereduction?[CO4 – L1]

The reduction of number of states in a state table is called as state reduction .By state reduction the number of flip-flops in a sequential circuit is reduced. 29.Draw the circuit for Mealy and Moore Model. [CO4 – L1]

Part - B

1.Explain about different types of Flipflops with neat sketch.[CO4 – L2]

Flip-flops are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Compare Flipflop and Latches Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); The simple ones are commonly called latches Flip-flop is edge-sensitive A latch is level-sensitive



Types of Flipflop

JK Flip-Flop

T Flip-flop

Edge-triggered D flip-flop Flip-flop and their description JK Flip-Flop: Edge-triggered D flip-flop Store binary information during edge trigger, Require the smallest number of gates Other types of flip-flops can be constructed using it JK Flip-Flop: D=JQ'+K'Q. J=0, K=0: D=Q ⇒ Q no change J=0, K=1: D=0 ⇒ Q =0 reset to 0 J=1, K=0: D=1 ⇒ Q =1 set to 1 J=1, K=1: D=Q’ ⇒ Q =Q’ complement output

T Flip-flop T (toggle) flip-flop: D = T⊕ Q = TQ'+T'Q T=0: D=Q, no change,T=1: D=Q' ⇒ Q=Q', Characteristic equations D flip-flop Q (t+1) = D,JK flip-flop Q (t+1) = JQ’+K’Q, T flop-flop Q (t+1) = T.Q = TQ’ + T’Q



Edge-triggered D flip-flop Store binary info during transition Method 1: Master-slave D flip-flop Two separate flip-flops,a master flip-flop (positive-level triggered),a slave flip-flop (negative-level triggered)change only during negative edge of clock Longer propagation delay.

Method 2: D-type positive-edge-triggered flip-flop The most efficient flip-flop constructed with 3 SR latches CLK=0 ⇒ S=R=1, no change, CLK=positive transition ↑⇒ Q=D (state changes once) D=0 when CLK becomes 1 ⇒ R=1 to 0 ⇒ D changes further, no effect D=1 when CLK becomes 1 ⇒ R=stay 1 ⇒ D changes further, no effect CLK=negative transition or 1 ⇒ quiescent condition (state holds)



2.Analyze the following clocked sequential circuit andobtain the state equations and state diagram. [CO4 - H3 – Nov/Dec15]

Analysis Procedure

The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of inputs, outputs, and internal states: the state table or the state diagram. It is also possible to write Boolean expressions including the necessary time sequence.

The same information available in a state table can be represented graphically in a state diagram.



Steps of analysis procedure

Derive excitation equations

Derive next-state and output equations

Generate next-state and output tables

Generate state diagram Given circuit

State equation (transition equation) A (t+1) =Ax+Bx B (t+1) =A’x y= (A+B) x’ State Table or Transition Table State table state equation CSC diagram

Four sections: present state, input, next state and output. List all possible binary combinations of present state and inputs. Determine next states and outputs from the logic diagram or from the state equations m flip-flops and n inputs,2m+n rows, m column of next-state



State diagram

Analysis with D flipflops Given: Input function: DA=A(+) x (+) y,

State equation: A (t+1) = A(+) x (+)y



State Table:

State diagram

3.Realize the sequential circuit for the state diagram shown below.[CO4-L3-N/D14]



Design of Sequential Circuits

Design of a clocked sequential circuit. Starts from a Set of Specifications

Obtains a State Table/Diagram (Or Equivalences).

Culminates in A Logic Diagram (Or A List Of Boolean Functions) Steps of design procedure 1) Derive the state diagram and state table for the circuit. 2) Count the number of states in the state diagram (call it N) and calculate the number of flip-flops needed (call it P) by solving the equation 2P-1 < N 2P. This is best solved by guessing the value of P. 3) Assign a unique P-bit binary number (state vector) to each state.Often, the first state = 0, the next state = 1, etc. 4) Derive the state transition table and the output table. 5) Separate the state transition table into P tables, one for each flip-flop. 6) Decide on the types of flip-flops to use. When in doubt, use all JK’s. 7) Derive the input table for each flip-flop using the excitation tables for the type. 8) Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops. 9) Summarize the equations by writing them in one place. 10) Draw the circuit diagram.



Step1-4: Assign binary codes and list state table

Step 5: Choose type of flip-flops (synthesis with D flip-flop)



Step 6 – Draw the logic diagram (using simplified functions)

4.Explain about State Reduction Principle and State Assignment with an example. (CO4 – L2) Reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirements unchanged. Algorithm to state reduction principle Look for two present states that go to the same next state and have the same output for both input combinations Remove one of the equivalent state and replace by the other state each time it occurs in the table. State Assignment Assign coded binary values to the state.In order to design a sequential circuit with physical components. A circuit with m states need n bits where 2n >= m



Illustration with an example-State Reduction Reduce the states for the state diagram given below

Step1:

Step2:



Step3:

Step4:

Illustration with an example-State Assignment

Step1: Step2



Step 3:

5.Discuss in detail about Shift Register and its types.[CO4 – L1]

An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information.

Types of Shift Register 1. Serial in/shift right/serial out 2. Serial in/shift left/serial out 3. Parallel in/serial out 4. Serial in/parallel out 5. Parallel in / parallel out



Serial in/shift right/serial out Accepts data serially – one bit at a time – and also produces output serially.

Application: Serial transfer of data from one register to another.

Serial In/Parallel Out Shift Registers Accepts data serially. Outputs of all stages are available simultaneously.



Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial

Parallel In/Parallel Out Shift Registers Simultaneous input and output of all data bits.

Universal Shift Regiser: Data shifted in both the direction simultaneously (i.e.) either left or right, using a control line is known as universal shift register.

6.With the necessary diagrams describe the operation of a Synchronous and Asynchronous Counters. [CO4 – L3 – Nov/Dec 15] Counters are circuits that cycle through a specified number of states.



Types of Counters Synchronous (Parallel) Counters Asynchronous (Ripple) Counters

Synchronous (Parallel) Counters Synchronous counters apply the same clock to all flip-flops.Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse. Example: 2-bit synchronous binary counter using T flip-flops

State diagram State Table

Characteristic equation TA1 = A0 TA0 = 1 2bit parallel Counters



Asynchronous (Ripple) Counters Ripple counters allow some flip-flop outputs to be used as a source of clock for other

flip-flops. Asynchronous counters: the flip-flops do not change states at exactly the same time

as they do not have a common clock pulse. Also known as ripple counters, as the input clock pulse “ripples” through the counter

cumulative delay is a drawback. N flip-flops a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.) Output of the last flip-flop (MSB) divides the input clock frequency by the MOD

number of the counter; hence a counter is also a frequency divider.

Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock input

of the next more-significant flip-flop.

7. Analyze and Design HDL Implementation Sequential Circuits. [CO4 – H3] HDL is a language that describes the hardware of digital systems in a textual form.

It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors.

The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represent mostly serial operations. The most common use of a HDL is to provide an alternative to schematics.



HDL can be used to represent logic diagrams, Boolean expressions, and other more complex digital circuits.

Thus, in top down design, a very high-level description of a entire system can be precisely specified using an HDL.

This high-level description can then be refined and partitioned into lower-level descriptions as a part of the design process.

There are two applications of HDL processing: Simulation and Synthesis. HDL coding for T flipflop D Flipflop module D_FF (Q,D,CLK); output Q; input D,CLK; reg Q; always @ (posedge CLK) Q = D; endmodule T flipflop module TFF (Q,T,CLK,RST); output Q; input T,CLK,RST; wire DT; assign DT = Q ^ T ; //Instantiate the D flip-flop DFF TF1 (Q,DT,CLK,RST); endmodule HDL coding for Ripple Counter module ripplecounter(count, reset, A0, A1, A2, A3); input count; input reset; output A0, A1, A2, A3; TFF T0(count, reset, A0); TFF T1(A0, reset, A1); TFF T2(A1, reset, A2); TFF T3(A2, reset, A3); endmodule



Three State Gates

Three-state gates have a control input that can place the gate into a high-impedance state. (symbolized by z in HDL).

The bufif1 gate behaves like a normal buffer if control=1. The output goes to a highimpedance state z when control=0.

bufif0 gate behaves in a similar way except that the high-impedance state occurs when control=1

Two not gates operate in a similar manner except that the o/p is the complement of the input when the gate is not in a high impedance state.

The gates are instantiated with the statementgate name (output, input, control);

Three state gates in HDL The output of 3-state gates can be connected together to form a common output line. To identify such connections, HDL uses the keyword tri (for tri-state) to indicate that the output has multiple drivers.



Unit IV

Asynchronous Sequential Logic

Part – A

1. Define Asynchronous sequential circuit?[CO4 – L1] In asynchronous sequential circuits change in input signals can affect memory element at any instant of time. 2. Comparison between synchronous & Asynchronous sequential circuits? [CO4 –H1 - A/M15]

3. What is fundamental mode sequential circuit?[CO4 – L1]

-input variables changes if the circuit is stable -inputs are levels, not pulses -only one input can change at a given time. 4. What is the significance of state assignment? [CO4 – L1] In synchronous circuits-state assignments are made with the objective of circuit reduction. Asynchronous circuits-its objective is to avoid critical races. 5. When do race conditions occur? [CO4 – L3 - May/June 14] Two or more binary state variables change their value in response to the change in input variable. 6. Write short note on shared row state assignment. [CO4 – L1] Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.



7. Write short note on one hot state assignment. [CO4 – L1]

The one hot state assignment is another method for finding a race free state assignment. In this method, only one variable is active or hot for each row in the original flow table, i.e., it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions. 8. What are the different techniques used in state assignment? [CO4 – L3]

shared row state assignment one hot state assignment

9. What are the steps for the design of asynchronous sequential circuit?[CO4 – L1]

construction of primitive flow table

reduction of flow table

state assignment is made

realization of primitive flow table 10. What is hazard? [CO4 – L1 - May/June 14] Hazard is an unwanted switching transient. 11. What are the steps for the design of asynchronous sequential circuit? [CO4 – L1]

1. Construction of a primitive flow table from the problem statement. 2. Primitive flow table is reduced by eliminating redundant states using the state Reduction 3. State assignment is made 4. The primitive flow table is realized using appropriate logic elements. 12. Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous circuit. [CO4 – L3]

In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races. 13. What are races? [CO4 – L1] When 2 or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner.



14. Define non critical race. [CO4 – L1]

If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race. 15. Define critical race? [CO4 – L1 - A/M 15]

If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race. 16. Define flow table in asynchronous sequential circuit. [CO4 – L1]

In asynchronous sequential circuit state table is known as flow table because of the behavior of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to flow from one to another. 17. Define merger graph. [CO4 – L1]

The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn. 18. What is fundamental mode? [CO4 – L1] A transition from one stable state to another occurs only in response to a change in the input state. After a change in one input has occurred, no other change in any input occurs until the circuit enters a stable state. Such a mode of operation is referred to as a fundamental mode.

PART – B

1. Explain the steps for the design Procedure of asynchronous sequential circuits. [CO4 – L2 - May/June 14 ]

To analyze the circuits with basic operation and steps

Transition Table

Flow Table-map

Race Conditions

Stability Consideration Example to illustrate analysis procedure Analyze the given circuit according to the major steps and transition equation,



Y1 = xy1 + x'y2, Y2 = xy'1 + x'y2

Transition Table For a state to be stable, the value of Y must be the same as that of y = y1y2 Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2

In general, if a change in the input takes the circuit to an unstable state, y will change until it reaches a stable state.

Flow Table-map Transition table whose states are named by letter symbol instead of binary values. It is called primitive flow table because it has only one stable state in each row. It is a flow table with more than one stable state in the same row.



Race Conditions Two or more binary state variables change value in response to a change in an input Variable Stability Consideration Column 11 has no stable state. With input x1 x2 = 11, Y and y are never the same.



2. Design a Gated D and SR latch Circuit. [CO4 – H3 ] Features of Gated D latch circuit Accept the value of D when G=1.Retain this value after G goes to 0 (D has no effects now)

Two inputs G (gate) and D (data), and one output Q. Primitive Flow table Obtain the flow table by listing all possible states. Dash marks are given when both inputs change simultaneously. Outputs of unstable states are don’t care.

Reduction of the Primitive Flow Table Two of more rows in the primitive flow table can be merged into one row if there are non-conflicting states and outputs in each of the columns.

Assigning Output to Unstable States. Assign a 0 to an output variable that has a 0 in the corresponding output variable. Assign a 1 to an output variable associated that have a 1 in the corresponding output variable. Assign a don't-care condition to an output variable s that has different values in the corresponding output variable. Transition Table and Logic Diagram Assign a binary value to each state to generate the transition table.a=0, b=1 in this



example Directly use the simplified Boolean function for the excitation variable Y An asynchronous circuit without latch is produced

Implementation with SR Latch Listed according to the transition table and the excitation table of SR latch



3. What is meant by Race Conditions? How race condition can be avoided in a circuit. [CO4 – H1 - Nov/Dec 14] Two or more binary state variables change value in response to a change in an input Variable. Noncritical race The final stable state that the circuit reaches does not depend on the order in which the state variables change. Need of using race free state assignment

The primary objective in choosing a proper binary state assignment is the prevention of critical races.

Critical races can be avoided by making a binary state assignment in such a way that only one variable changes at any given time when a state transition occurs in the flow table. Examples of race free state assignment Three-Row Flow-Table Example This assignment will cause a critical race during the transition from a to c.

The transition from a to c must now go through d, thus avoiding a critical race.



Multiple-Row Method In the multiple-row assignment, each state in the original flow table is replaced by

two or more combinations of state variables.

4. Explain in detail about hazard and its types. Implement the Hazard free circuit for the following function Y = X1X2 +X2’X3. [CO4 – H3 - May/June 14]

Hazards Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delay. Types of Hazards

The first implementation may cause the output to go to 0 when it should remain

at 1 (Static 1‐hazard), while the second implementation may cause the output to

go to 1 when it should remain at 0 (Static 0‐hazard).



The dynamic hazard causes the output to change three or four times when it should change from 1 to 0 or from 0 to 1.

Hazards in Combinational Circuits

Before the output of gate 2 changes to 1. In that case, the output goes to 0 for short interval of time.

Y = x1 x2 + x2 ' x3 or Y = (x1 + x2 ' )(x2 + x3 ) (sum of products) (product of sums)

Hazards in Sequential Circuits



If the circuit is in total state yx1x2 = 111 and input x2 changes from 1 to 0, the next total state should be 110. However, because of the hazard, output Y may go 0 momentarily. If this false signal feeds back into gate 2, the output of gate 2 will remain at 0 and the circuit will switch to the incorrect total state 010. This problem can be eliminated by adding an extra gate.

Essential Hazards

An Essential Hazard: is caused by unequal delays along two or more paths that originate from the same input.

Essential hazards cannot be corrected by adding redundant gates as in static hazards.

The problem can be corrected by adjusting the amount of delay in the affected paths. Hazard Free Circuit The hazard exists because the change of input results in a different product term covering the two minterms.

The remedy for eliminating a hazard is to enclose the two minterms in question with another product term that overlap both grouping.



Unit V

Memory And Programmable Logic

Part – A

1. List basic types of programmable logic devices. [CO5 – L1] Read only memory Programmable logic Array Programmable Array Logic

2. Explain ROM. [CO5 – L2]

A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n.

3. Define address and word: [CO5 – L1] In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.

4. State the types of ROM. [CO5 – L1] . Masked ROM. . Programmable Read only Memory . Erasable Programmable Read only memory. . Electrically Erasable Programmable Read only Memory.

5. What is programmable logic array? How it differs from ROM?[CO5 – H1] In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

6. Explain PROM. [CO5 – L2] It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20μs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.



7. Explain EPROM. [CO5 – L2] EPROM (Erasable Programmable Read Only Memory) - EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.

8. Explain EEPROM. [CO5 – L2]

EEPROM (Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.

9. What is RAM? [CO5 – L1] Random Access Memory-Read and write operations can be carried out.

10. What is programmable logic array? How it differs from ROM? [CO5 – H1]

In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

11. What is mask - programmable? [CO5 – L1]

With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.

12. What is field programmable logic array? [CO5 – L1]

The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.

13. List the major differences between PLA and PAL. [CO5 – H1]

Both AND and OR arrays are programmable and Complex Costlier than PAL PAL, AND arrays are programmable OR arrays are fixed Cheaper and Simpler.



14. Define PLD. [CO5 – L1]

Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve specific logic functions.

15. Give the classification of PLDs. [CO5 – L1]

PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL).

16. Define PROM. [CO5 – L1]

PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.

17. Define PLA. [CO5 – L1]

PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array.

18. Define PAL. [CO5 – L1]

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.

19. Why was PAL developed? [CO5 – H1]

It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.

20. Why the input variables to a PAL are buffered? [CO5 – H1] The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.

21. What does PAL 10L8 specify? [CO5 – L2] PAL - Programmable Logic Array 10 - Ten inputs L - Active LOW Ouput 8 - Eight Outputs.

22. Give the comparison between PROM and PLA. [CO5 – H1- April/May 14]



Part - B

1.Discuss on the concept of working and types of ROM. [CO5 - L2 - Nov/Dec 14]

A ROM is essentially a memory device in which permanent binary information is stored.

The inputs provide the address for memory and the outputs give the data bits of the stored word that is selected by the address. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words.

The five inputs are decoded into 32 distinct outputs by means of a 5×32 decoder. Each output of the decoder represents a memory address. The 32 outputs of the decoder are connected to each of the eight OR gates. Each OR gate must be considered as having 32 inputs. Each output of the decoder is connected to one of the inputs of each OR gate. Since each OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32 x 8 = 256 internal connections.



A programmable connection between two lines is logically equivalent to a switch that can be altered to be either closed (meaning that the two lines are connected) or open (meaning that the two lines are disconnected). The programmable intersection between two lines is sometimes called a cross point.

For example, programming the ROM according to the truth table given by table. Every 0 listed in the truth table specifies the absence of a connection and every 1 listed specifies a path that is obtained by a connection.



Types of ROMs The required paths in a ROM may be programmed in four different ways.

The first is called mask programming and is done by the semiconductor company during the last fabrication process of the unit. This procedure is costly because the vendor charges the customer a special fee for custom masking the particular ROM.

For small quantities, it is more economical to use a second type of ROM called programmable

READ-ONLY MEMORY- PROM. The fuses in the PROM are blown by the application of a high-voltage pulse to the device through a special pin. A blown fuse defines a binary 0 state and an intact fuse gives a binary 1 state. The hardware procedure for programming ROMs or PROMs is irreversible and once programmed, the fixed pattern is permanent and cannot be altered.

A third type of R OM is the erasable PROM or EPROM, which can be restructured to the initial state even though it has been programmed previously. When the EPROM is placed under a special ultraviolet light for a given length of time. the shortwave radiation discharges the internal floating gates that serve as the programmed connections. After erasure, the EPROM returns to its initial state and can be reprogrammed to a new set of values.

The fourth type of ROM is the electrically erasable PROM (EEPROM or E2PROM). This device is like the EPROM except that the previously programmed connections can be erased with an electrical signal instead of ultraviolet light. The advantage is that the device can be erased without removing it from its socket.

Flash memory devices are similar to EEPROMs, but have additional built-in circuitry to selectively program and erase the device in-circuit, without the need for a special programmer. They have widespread application in modern technology in cell phones, digital cameras, set-top boxes, digital TV, telecommunications, non volatile data storage and microcontrollers. Their low consumption of power makes them an attractive storage medium for laptop and notebook computers.

2. Discuss in detail about working concept of write and read operation of Random Access Memory. [CO5 – L2] A memory unit is a collection of storage cells together with associated circuits needed to transfer information into and out of a device. The time it takes to transfer information to or from any desired random location is always the same-hence the name random access memory, abbreviated as RAM.



A memory unit stores binary information in groups of bits called words. A word in memory is an entity of bits that move in and out of storage as a unit. A memory word is a group of 1 's and 0's and may represent a number, an instruction , one or more alphanumeric characters or any other binary-coded information. A group of 8 bits is called a byte. Most computer memories use words that are multiples of 8 bits in length.

Each word in memory is assigned an identification number called an address starting from 0 upto 2k-1. where k is the number of address lines. Consider for example, a memory unit with a capacity of 1K words of 16 bits each. Since 1K=1024 = 210 and 16 bits constitute two bytes, we can say that the memory can accommodate 2048 = 2K bytes.

Read and write operations- The two operations that RAM can perform are the write and

read operations. The steps that must be taken for the purpose of transferring a new word to be stored into memory are as follows:

Apply the binary address of the desired word to the address lines.

Apply the data bits that must be stored in memory to the data input lines.

Activate the write input. The memory unit will then take the bits from the input data lines and store them in the word specified by the address lines. The steps that must be taken for the purpose of transferring a stored word out of memory are as follows:

Apply the binary address of the desired word to the address lines.

Activate the read input.



The memory enable (sometimes called the chip select) is used to enable the particular memory chip in a multichip implementation of a large memory. When the memory enable is inactive, the memory chip is not selected and no operation is performed. When the memory enable input is active, the read/write input determines the operation to be performed.

Timing Waveforms The operation of the memory unit is controlled by an external device such as a central processing unit (CPU). The CPU is usually synchronized by its own clock .The memory however doesn’t employ an internal clock. Instead it’s read and write operations are specified by control inputs. The access time of memory is the time required to select a word and read it. The cycle time of memory is the time required to complete a write operation.

The read cycle shown in figure has an address for the memory provided by the CPU. The memoryenable and read/write signals must be in their high level for a read operation. The memory places the data of the word selected by the address into the output data lines within a 50-ns interval (or less) from the time that the memory enable is activated. The CPU can transfer the data into one of its internal registers during the negative transition of T3.The next T1 cycle is available for another memory request.



For a write operation, the CPU must provide the address and input data to the memory. This is done at the beginning of TI. The memory enable and the read/write signals must be activated after the signals in the address lines are stable in order to avoid destroying data in other memory words. The memory enable signal switches to the high level and the read/write signal switches to the low level to indicate a write operation. The two control signals must stay active for at least 50 ns. The address and data signals must remain stable for a short time after the control signals are deactivated. At the completion of the third clock cycle, the memory write operation is completed and the CPU can access the memory again with the next TI cycle.

Types of RAM Integrated circuit RAM units are available in two operating modes: static and dynamic. Static RAM (SRAM) consists essentially of internal latches that store the binary information. The stored information remains valid as long as power is applied to the unit. Dynamic RAM (DRAM) stores the binary information in the form of electric charges on capacitors provided inside the chip by MOS transistors. The stored charge on the capacitors tends to discharge with time, and the capacitors must be periodically recharged by refreshing the dynamic memory. Refreshing is done by cycling through the words every few milliseconds to restore the decaying charge. DRAM offers reduced power consumption and larger storage capacity in a single memory chip. SRAM is easier to use and has shorter read and write cycles.



ROM is another nonvolatile memory. A nonvolatile memory enables digital computers to store programs that will be needed again after the computer is turned on. Programs and data that cannot be altered are stored in ROM, while other large programs are maintained on magnetic disk.

3. Explain about different error detection and correction techniques with an example. [CO5 – L2]

The reliability of a memory unit may be improved by employing error-detecting and error-correcting codes. The most common error detection scheme is the parity bit. A parity bit is generated and stored along with the data word in memory. The parity of the word is checked after reading it from memory. The data word is accepted if the parity of the bits read out is correct. If the parity checked results in an inversion, an error is detected, but it cannot be corrected. An error-correcting code generates multiple parity check bits that are stored with the data word in memory. Each check bit is parity over a group of bits in the data word. When the word is read back from memory, the associated parity bits are also read from memory and compared with a new set of check bits generated from the data that have been read. If the check bits are correct, no error has occurred. If the check bits do not match the stored parity, they generate a unique pattern called a syndrome, which can be used to identify the bit that is in error. A single error occurs when a bit changes in value from 1 to 0 or from 0 to 1 during the write or read operation. If the specific bit in error is identified, then the error can be corrected by complementing the erroneous bit. Hamming Code One of the most common error-correcting codes used in RAMs was devised by R. W. Hamming. In the Hamming code, k. parity bits are added to an n-bit data word, forming a new word of n + k bits. The bit positions are numbered in sequence from 1 to n + k, these positions numbered as a power of 2 are reserved for the parity bits. The remaining bits are the data bits. Consider, for example the 8-bit data word 11000100. We include 4 parity bits with the 8-bit word and arrange the 12 bits as follows:



The 4 parity bits P1, P2, P4 and P8 are in positions 1, 2, 4 and 8 respectively. The 8 bits of the data word are in the remaining positions. Each parity bit is calculated as follows:

The 8-bit data word is stored in memory together with the 4 parity bits as a 12-bit composite word. Substituting the 4 P bits in their proper positions, we obtain the 12-bit composite word stored in memory.

When the 12 bits are read from memory, they are checked again for errors. The parity is checked over the same combination of bits, including the parity bit. The 4 check bits are evaluated as follows:

A 0 check bit designates even parity over the checked bits and a 1 designates odd parity. Since the bits were stored with even parity, the result, C = C8C4C2C1 = 0000, indicates that no error has occurred. However, if C≠0, then the 4 -bit binary number formed by the check bits gives the position of the erroneous bit. For example, consider the following three cases:



Single-Error Correction, Double-Error Detection

The Hamming code can detect and correct only a single error. By adding another parity bit to the coded word, the Hamming code can be used to correct a single error and detect double errors.

4. Explain about Combinational PLDs in detail. [CO5 – L2] Combinational programmable logic device (PLD)

Programmable gates divided into an AND array and an OR array

Provide an AND-OR sum of product implementation

A fixed AND array constructed as a decoder

A programmable OR array to implement Boolean functions in sum of minterms

A programmable AND array: to provide the product terms for Boolean functions

Both can be programmed

Most flexible



Programmable Logic Array

An array of programmable AND gates Can generate any product terms of the inputs An array of programmable OR gates Can generate the sums of the products Only the needed product terms are generated (not all) More flexible than ROM; use less circuits than ROM Size of PLA: specified by # of inputs, product terms and outputs n inputs, k product terms and m outputs n buffer-inverter gates, k AND gates, m OR gates, and m XOR gates Typical PLA may have 16 inputs, 48 product terms and 8 outputs



Designing a digital system with a PLA Reduce the number of distinct product terms The number of literals in a product is not important

5. Implement the following two Boolean Functions with a PLA. F1 = AB′ + AC + A′BC′ F2 = (AC + BC) ′[CO5 – H3 - April/May15] Design PLA programming table: 4 sections 1. List the product terms 2. Specify the required paths between inputs and and gates 3. Specify the paths between the and and or gates 4. Specifying the fuse map and submitted to the manufacturer XOR gates can invert the outputs

Invert: connected to 1

Not change: connected to 0



PLA - Example 2 Implement: F1(A, B, C) = Σ (0, 1, 2, 4); F2(A, B, C) = Σ (0, 5, 6, 7) 1. Simply both the true and complement of the functions in sum of products 2. Find the combination with minimum number of product terms F1=(AB+AC+BC)’ F2=AB+AC+A’B’C’ 3. Obtain the PLA Programming table



6. Implement the following Boolean Functions with a PLA. [CO5 – H3] w(A,B,C,D) = Σ(2,12,13) x(A,B,C,D) = Σ(7,8,9,10,11,12,13,14,15) y(A,B,C,D) = Σ(0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = Σ(1,2,8,12,13) Programmable Array Logic PAL: a programmable AND array and a fixed OR array – easier to program, but not as flexible as PLA

Example: PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure (Figure 7-16)

Each input has a buffer-inverter gate •each output is generated by a fixed OR gate 4 sections of 3-wide AND-OR array – each AND gate has 10 programmable input connections.

A typical PAL may have 8 inputs, 8 outputs, and 8 sections, each consisting of an 8- wide AND-OR array may use two sections to implement a large Boolean function Product terms cannot be Shared .

Each function is simplified itself. Implement the following functions w(A,B,C,D) = Σ(2,12,13) x(A,B,C,D) = Σ(7,8,9,10,11,12,13,14,15) y(A,B,C,D) = Σ(0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = Σ(1,2,8,12,13) Simplify the functions using k map



w = ABC′ + A′B′CD′ x = A + BCD y = A′B + CD + B′D′ z = ABC′ + A′B′CD′ + AC′D′ + A′B′C′D = w + AC′D′ + A′B′C′D



7.Briefly discuss the Sequential programmable devices.[CO5–L2-April/May15]



Combinational PLD + flip-flops perform a variety of sequential-circuit functions

Three major types

Field-programmable logic sequencer (FPLS)

Complex programmable logic device (CPLD)

Field programmable gate array (FPGA) Many commercial vendor-specific variants and internal logic of these devices is too

complex to be shown here. Sequential (or simple) programmable logic device (SPLD)

Includes flip-flops and AND-OR array , flip-flops connected to form a register,FF outputs could be included in product terms of AND array.

Field-programmable logic sequencer (FPLS), First programmable device developed, FF may be of D or JK type, not succeed commercially due to too many programmable connections. Combinational PAL together with D flip-flops: most used

Macrocell: a section of an SPLD, a circuit containing a sum-of-products combinational logic

function and an optional flip-flop a typical SPLD contains 8-10 macrocells

Features:

Programming AND array

Use or bypass the flip-flop

Select clock edge polarity

Preset or clear for the register

Complement an output

FF is connected to a common clock

OE (output enable) signal also

Controls all the three-state buffers



FF output is fed back to PAL inputs

CPLD - Complex Programmable Logic Device CPLD: a collection of PLDs to be connected to each othe rthrough a programmable

switch matrix .

Input/output blocks provide connections to IC pins.

Each I/O pin is driven by a three-state buffer and can be programmed to act as input or output .

Switch matrix receives inputs from I/O block and directs it to individual microcells.

Selected outputs from microcells are sent to the outputs as needed.

Each PLD typically contains from 8 to 16 microcells.



FPGA – Field-Programmable Gate Array

Gate array: basic component used in VLSI–consist of a pattern of gates fabricated in an area of silicon and repeated thousands of times.

FPGA: an array of hundreds or thousands of logic blocks – surrounded by programmable input and output blocks– connected together via programmable interconnections.

A logic block consists of look-up tables, multiplexers, gates, and flip-flops.

Look-up table: a truth table stored in a SRAM and providing combinational circuit functions for the logic block.

SRAM instead of ROM

Advantage: the table can be programmed.

Drawback: memory is volatile, reload/reprogram required after power on againo Complexity

PALs, PLAs = 10 - 100 Gate Equivalents

FPGAs = 100 - 1000(s) of Gate Equivalents

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