skup instrukcija mikropocesora mips

Skup instrukcija

mikropocesora MIPS

MIPS register convention

Register 1, called $at, is reserved for the assembler, and registers 26-27, called $k0-$k1, are reserved for the operationg system.

Name Register number

Usage Preserved on call?

$zero 0 the constant value 0 n.a.

$v0-$v1

2-3 values for results and expression evalution

no

$a0-$a3

4-7 arguments yes

$t0-$t7

8-15 temporaries no

$s0-$s7

16-23 saved yes

$t8-$t9

24-15 more tempporaries no

$gp 28 global pointer yes

$sp 29 stack pointer yes

$fp 30 frame pointer yes

$ra 31 return address yes

MIPS operands

Name Example Comments

32 registers

$s0-$s7, $t0-$t9, $gp, $fp, $zero, $sp, $ra, $at, Hi, Lo

Fast locations for data, In MIPS, data must be in registers to perform arithmetic. MIPS register $zero always equals 0. Register $at is reserved for the assumbler to handle large constants. Hi and Lo contain the results of multiply and divide.

230 memory words

Memory [0], Memory [4], ..., Memory [4294967292]

Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential words differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls.

Main MIPS assembly language instruction set

Category

Instruction Example Meaning Comments

Arithmetic

add add $sl, $s2, $s3

$s1 = $s2 + $s3

Three operands; overflow detected

subtract sub $s1, $s2, $s3

$s1 = $s2 - $s3 Three operands; overflow detected

add immediate addi $s1, $s2, 100

$s1 = $s2 + 100

+ constant; overflow detected

add unsigned addu $s1, $s2, $s3

$s1 = $s2 + $s3

Three operands; overflow undetected

subtract unsigned subu $sl, $s2, $s3

$s1 = $s2 - $s3 Three operands; overflow undetected

add immediate unsigned

addiu $s1, $s2, 100

$s1 = $s2 + 100

+ constant; overflow undetected

move from coporoc. reg.

mfc0 $s1, $epc $s1 = $epc Used to copy Exception PC plus other special registers

multiply mult $s2, $s3 Hi, Lo = $s2 * $s3

64-bit signed product in Hi, Lo

multiply unsigned multu $s2, $s3 Hi, Lo = $s2 * $s3

64-bit unsigned product in Hi, Lo

divide div $s2, $s3 Lo = $s2/ $s3, Hi = $s2 mod $s3

Lo = quotient, Hi = remainder

divide unsigned divu $s2, $s3 Lo = $s2/ $s3, Hi = $s2 mod $s3

Unsigned quotient and remainder

move from Hi mfhi $s1 $s1 = Hi Used to get copy of Hi

move from Lo mflo $s1 $s1 = Lo Used to get copy of Lo

Category


Logical and and $s1, $s2, $s3

$s1 = $s2 & $s3 Three reg. operands; logical AND

or or $s1, $s2, $s3

$s1 = $s2 ! $s3 Three reg. operands; logical OR

and immediate

andi $s1, $s2, 100

$s1 = $s2 & 100 Logical AND reg. constant

or ori $s1, $s2, 100

$s1 = $s2 ! 100 Logical OR reg. constant

shiftr left logical

sll $s1, $s2, 10 $s1 = $s2 << 10 Shift left by constant

shift right logical

srl $s1, $s2, 10 $s1 = $s2 >> 10 Shift right by constant

Data transfer

load word lw $s1, 100($s2)

$s1 = Memory [$s2+100]

Word from memory to register

store word sw $s1, 100($s2)

Memory [$s2+100]= $s1

Word from register to memory

load byte unsigned

lbu $s1, 100($s2)

$s1 = Memory [$s2+100]

Byte from memory to register

store byte sb $s1, 100($s2)

Memory [$s2+100]= $s1

Byte from register to memory

load upper immediate

lui $s1, 100 $s1 = 100*216 Loads constant in upper 16 bits

Main MIPS assembly language instruction set– cont.

Category


Conditional branch

branch on equal

beq $s1, $s2, 25

if ($s1 ==$s2) go to PC + 4 + 100

Equal test; PC relative branch

branch on not equal

bne $s1, $s2, 25

if ($s1!=$s2) go to PC + 4 + 100

Not equal test; PC relative

set on less than

slt $s1, $s2, $s3

if($s2< $s3) $s1 = 1; else $s1 = 0

Compare less than; two's complement

set less than immediate

slti $s1, $s2, 100

if ($s2< 100) $s1 = 1; else $s1 = 0

Compare < constant; two's complement

set less than unsigned

sltu $s1, $s2, $s3

if($s2< $s3) $s1 = 1; else $s1 = 0

Compare less than; natural numbers

set less than unsigned immediate

sltiu $s1, $s2, 100

if($s2< 100) $s1 = 1; else $s1 = 0

Compare < constant; natural numbers

Unconditi-onal jump

jump j 2500 go to 10000 Jump to target address

jump register jr $ra go to $ra For switch, procedure return

jump and link jal 2500 $ra =PC+4; go to 10000

For procedure call

Main MIPS assembly language instruction set– cont.

MIPS machine Language Example

Name Format

6 bits

5 bits

5 bits 5 bits 5 bits

6 bits

Coments

add R 0 2 3 1 0 32 add $1, $2, $3

sub R 0 2 3 1 0 34 sub $1, $2, $3

addi I 8 2 1 100 addi $1, $2,100

addu R 0 2 3 1 0 33 addu $1, $2, $3

subu R 0 2 3 1 0 35 subu $1, $2, $3

addiu I 9 2 1 100 addiu $1,$2,100

mfc0 R 16 0 1 14 0 0 mfc0 $1, $epc

mult R 0 2 3 0 0 24 mult $2, $3

multu R 0 2 3 0 0 25 multu $2, $3

div R 0 2 3 0 0 26 div $2, $3

divu R 0 2 3 0 0 27 divu $2, $3

mfhi R 0 0 0 1 0 16 mfhi $1

mflo R 0 0 0 1 0 18 mflo $1

and R 0 2 3 1 0 36 and $1, $2, $3

or R 0 2 3 1 0 37 or $1, $2, $3

Example

Name Format

6 bits 5 bits 5 bits 5 bits

5 bits

6 bits Coments

andi I 12 2 1 100 andi $1, $2,100

ori I 13 2 1 100 ori $1, $2,100

sll R 0 0 2 1 10

0 sll $1, $2, 10

srl R 0 0 2 1 10

2 srl $1, $2, 10

lw I 35 2 1 100 lw $1,100($2)

sw I 43 2 1 100 sw $1,100($2)

lui I 15 0 1 100 lui $1,100

beq I 4 1 2 25 beq $1,$2,100

bne I 5 1 2 25 bne $1,$2,100

slt R 0 2 3 1 0 42 slt $1, $2, $3

slti I 10 2 1 100 slti $1,$2,100

sltu R 0 2 3 1 0 43 sltu $1, $2, $3

sltiu I 11 2 1 100 sltiu $1,$2,100

j J 2 2500 j 10000

jr R 0 31 0 0 0 8 jr $31

jal J 3 2500 jal 10000

MIPS machine Language – cont.

MIPS Instruction formats

Name Flelds

Comments

Field size

6 bits

5 bits 5 bits

5 bits 5 bits

6 bits

All MIPS instructions 32 bits

R-format

op rs rt rd shamt

funct Arithemetic instruction format

I-Format

op rs rt address/immediate Arithemetic instruction format

J-Format

op target address Jump instruction format

Main MIPS machine language, Formats and examples are shown, with values in each field: op and funct fields form the opcode (each 6 bits), rs field gives a source register (5 bits), rt is also normally a source register (5 bits), rd is the destination register (5 bits), and shamt supplies the shift amount (5 bits). The field values are all in decimal. Floating-point machine language instructions are shown in Figure 4.47 on page 291. Appendix A gives the full MIPS machine language.

MIPS floating-point operands

Name Example Comments

32 floating point registers

$f0, $f1, $f2..., $f31,

MIPS floating -point registers are used in pairs for double precision numbers.

230 memory words

Memory [0], Memory [4], ....,Memory [4294967292]

Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential words differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls.

MIPS floating-point assembly language

Category


Arthmetic

FP add single add.s $f2, $f4, $f6

$f2 = $f4 + $f6 FP add (single precision)

FP subtract single

sub.s $f2, $f4, $f6

$f2 = $f4 - $f6 FP sub (single precision)

FP multiply single

mul.s $f2, $f4, $f6

$f2 = $f4 * $f6 FP. multiply(single precision)

FP divide single

div.s $f2, $f4, $f6

$f2 = $f4 / $f6 FP divide (single precision)

FP add double add.d $f2, $f4, $f6

$f2 = $f4 + $f6 FP add (double precision)

FP subtract double

sub.d $f2, $f4, $f6

$f2 = $f4 - $f6 FP sub (double precision)

FP multiply double

mul.d $f2, $f4, $f6

$f2 = $f4 * $f6 FP multiply (double precis.)

FP divide double

div.d $f2, $f4, $f6

$f2 = $f4 / $f6 FP divide (double precis.)

Data transfer

load word copr.1

lwc1 $f1, 100($s2)

$f1 = Mem [$s2+100] 32-bit data to FP register

store word copr.1

swc1 $f1,100($s2)

Mem[$s2+100] =$f1 32-bit data to memory

Conditional branch

branch on FP true

bclt 25 if(cond==1) go to PC+4+100

PC relative branch if FP cond.

branch on FP false

bclf 25 if(cond==0) go to PC+4+100

PC relative branch if not cond.

FP compare single (eq.ne.lt.le.gt.ge)

c.lt.s $f2, $f4 if($f2 < $f4) cond=1; else cond = 0

FP compare less than single precision

FP compare double

c.lt.d $f2, $f4 if($f2 <$f4) (eq.ne.lt.le.gt.ge) cond=1; else cond = 0

FP compare less than single precision

MIPS floating-point machine language

Name Format

Example Comments

add.s R 17 16 6 4 2 0 add.s $f2, $f4 $f6

sub.s R 17 16 6 4 2 1 sub.s $f2, $f4 $f6

mul.s R 17 16 6 4 2 2 mul.s $f2, $f4 $f6

div.s R 17 16 6 4 2 3 div.s $f2, $f4 $f6

add.d R 17 17 6 4 2 0 add.d $f2, $f4 $f6

sub.d R 17 17 6 4 2 1 sub.d $f2, $f4 $f6

mul.d R 17 17 6 4 2 2 mul.d $f2, $f4 $f6

div.d R 17 17 6 4 2 3 div.d $f2, $f4 $f6

lwc1 I 49 20 2 100 lwc1 $f2, 100($s4)

swc1 I 57 20 2 100 swc1 $f2, 100($s4)

bc1t I 17 8 1 25 bc1t 25

bc1f I 17 8 0 25 bc1f 25

c.lt.s R 17 16 4 2 0 60 c.lt.s $f2, $f4

c.lt.d R 17 17 4 2 0 60 c.lt.d $f2, $f4

Field size

6 bits

5 bits

5 bits 5 bits 5 bits 6 bits All MIPS instruction 32 bits

Arithmetic and Logical Instructions

Addition (with overflow)

add rd,rs,rt 6 5 5 5 5 6

0 rs rt rd 0 0x20

Absolute value

abs rdest,rsrc pseudoinstruction

Put the absolute value of register rsrc in register rdest.

Addition (without overflow)

addu rd,rs,rt 6 5 5 5 5 6

Put the sum of registers rs and rt into register rd.

0 rs rt rd 0 0x21

Addition immediate (without overflow)

addi rt,rs,imm 6 5 5 16

Arithmetic and Logical Instructions – con.

8 rs rt imm

Addition immediate (without overflow)

addi rt,rs,imm 6 5 5 16

Put the sum of registers rs and sign-extended immediate into register rt.

9 rs rt imm

AND

and rd,rs,rt 6 5 5 5 5 6

Put the logical AND of registers rs and rt into register rd.


And immediate

andi rd,rs,imm 6 5 5 16

Put the logical AND of register rs and the zero-extended immediate into register rt.

0xc rs rt imm

0 rs rt rd 0 0x24


Divide (with overflow)

div rs,rt 6 5 5 10 6

Divide (with overflow)

div rdest,rsrc 1,src2 pseudoinstruction

Divide (without overflow)

divu rs,rt 6 5 5 10 6

0 rs rt 0 0x1a

0 rs rt 0 0x1b

Divide (without overflow)

div rdest,rsrc 1,src2 pseudoinstruction

Put the quotient of register rsrc1 and src2 into register rdest.

Divide register rs by register rt. Leave the quotient in register lo and the remainder in register hi.


Multiply

mult rs,rt 6 5 5 10 6

Multiply (without overflow)

mul rdest,rsrc 1,src2 pseudoinstruction

Unsigned multiply

multu rs,rt 6 5 5 10 6

0 rs rt 0 0x18

0 rs rt 0 0x19

Unsigned multiply (with overflow)

mulou rdest,rsrc1,src2 pseudoinstruction

Put the product of register rsrc1 and src2 into register rdest.

Multiply (with overflow)

mulo rdest,rsrc 1,src2 pseudoinstruction

Multiply register rs and rt. Leave the low-order word of the product in register lo and the high-order word in register hi.


NOR

nor rd,rs,rt 6 5 5 5 5 6

Put the logical NOR of registers rs and rt into register rd.

0 rs rt rd 0 0x27

Negate value (with overflow)

neg rdest,rsrc pseudoinstruction

NOT

not rdest,rsrc pseudoinstruction

Put the sum of registers rs and rt into register rd.

Negate value (without overflow)

negu rdest,rsrc pseudoinstruction

Put the negative of register rsrc into register rdst.

OR

or rd,rs,rt 6 5 5 5 5 6

Put the logical OR of registers rs and rt into register rd.

OR immediate

ori rt,rs,imm 6 5 5 16

Put the logical OR of register rs and the zero-extended immediate into register rt.

0xd rs rt imm

0 rs rt rd 0 0x25


Remainder

rem rdest,rsrc1,rsrc2 pseudoinstruction

Unsigned remainder

remu rdest,rsrc1,rsrc2 pseudoinstructionPut the remainder od register rsrc1 divided by register rsrc2 into register rdest. Note that if an operand is negative, the remainder is unspecified by the MIPS architecture and depends on the convention of the machine on which SPIM is run.


Shift left logical

sll rd,rt,shamt 6 5 5 5 5 6

0 rs rt rd shamt 0

Shift left logical variable

sllv rd,rt,rs 6 5 5 5 5 6

0 rs rt rd 0 4

Shift right arithmetic

sra rd,rt,shamt 6 5 5 5 5 6

0 rs rt rd shamt 3

Shift right arithmetic variable

srav rd,rt,rs 6 5 5 5 5 6

0 rs rt rd 0 7


Shift right logical

sra rd,rt,shamt 6 5 5 5 5 6

0 rs rt rd shamt 2

Shift right logical variable

srlv rd,rt,rs 6 5 5 5 5 6

Shift register rt left (right) by the distance indicated by immediate shamt or the register rs and put the result in register rd.

0 rs rt rd 0 6

Rotate left

rol rdest,rsrc1,rsrc2 pseudoinstruction

Rotate right

ror rdest,rsrc1,rsrc2 pseudoinstructionRotate register rsrc1 left(right) by the distance indicated by rsrc2 and put the result in register rdest.


Subtract (with overflow)

sub rd,rs,rt 6 5 5 5 5 6

Subtract (without overflow)

subu rd,rs,rt 6 5 5 5 5 6

Put the difference of register rs and rt into register rd.

0 rs rt rd 0 0x22

0 rs rt rd 0 0x23

Exclusive OR

xor rd,rs,rt 6 5 5 5 5 6

Put the logical XOR of registers rs and the zero-extended immediate into register rt.

0 rs rt rd 0 0x26

XOR immediate

xori rt,rs,imm 6 5 5 16

Put the logical XOR of register rs and the zero-extended immediate into register rt.

0xe rs rt imm

Constant-Manipulating Instructions

Load upper immediate

lui rt,imm 6 5 5 16

Load the lower halfword of the immediate imm into the upper halfword of registers rt. The lower bits of the register are set to 0.

0xf rs rt imm

Load immediate

li rdest,imm pseudoinstructionMove the immediate imm into register rdest.

Comparison Instructions Set less than

slt rd,rs,rt 6 5 5 5 5 6

Set less than unsigned

sltu rd,rs,rt 6 5 5 5 5 6

Set register rd to 1 if register rs is less than rt, and to 0 otherwise.

0 rs rt rd 0 0x2a

0 rs rt rd 0 0x2b

Set less than immediate

slti rd,rs,imm 6 5 5 16

Set less than unsigned immediate

sltiu rd,rs,imm 6 5 5 16

Set register rd to 1 if register rs is less than the sign-extended immediate, and to 0 otherwise.

0xb rs rd imm

0xa rs rd imm

Comparison Instructions – cont.

Set greater than equal

sge rdest,rsrc1,rsrc2 pseudoinstruction

Set equal

seq rdest,rsrc1,rsrc2 pseudoinstruction

Set register rdest to 1 if register rsrc1 equals rsrc2, and to 0 otherwise.

Set greater than equal unsigned

sgeu rdest,rsrc1,rsrc2 pseudoinstructionSet register rdest to 1 if register rsrc1 is greater than or equal to rsrc2, and to 0 otherwise.

Set greater than

sgt rdest,rsrc1,rsrc2 pseudoinstruction

Comparison Instructions – cont.

Set greater than unsigned

sgtu rdest,rsrc1,rsrc2 pseudoinstructionSet register rdest to 1 if register rsrc1 is greater than rsrc2, and to 0 otherwise.

Set less than equal

sle rdest,rsrc1,rsrc2 pseudoinstruction

Set less than equal unsigned

sleu rdest,rsrc1,rsrc2 pseudoinstructionSet register rdest to 1 if register rsrc1 is less than or equal to rsrc2, and to 0 otherwise.

Set not equal

sne rdest,rsrc1,rsrc2 pseudoinstructionSet register rdest to 1 if register rsrc1 is not equal to rsrc2, and to 0 otherwise.

Branch Instructions

Branch Instruction

b label pseudoinstructionUnconditionally branch to the instruction at the label.

Branch coprocessor z true

bczt label 6 5 5 16

Branch coprocessor z false

bczf label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if z's condition flag is true (false). z is 0, 1, 2, or 3. The floating-point unit is z = 1.

0x1z 8 1 offset

0x1z 8 0 offset

Branch Instructions – cont.

Branch on equal

beq rs,rt,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs equals rt.

Branch on greater than equal zero

bgez rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0.

4 rs rt offset

1 rs 1 offset

Branch on greater than equal zero and link

bgezal rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Save the address of the next instruction in register 31.

1 rs 0x11 offset


Branch on greater than zero

bgtz rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is greater than 0.

Branch on less than equal zero

blez rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is less than or equal to 0.

7 rs 0 offset

6 rs 0 offset

Branch on less than equal zero and link

bltzal rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is less than 0. Save the address of the next instruction in register 31.

1 rs 0x10 offset


Branch on less than zero

bltz rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is less than 0.

Branch on not equal

bne rs,label 6 5 5 16

Conditionally branch the number of instructions specified by the offset if register rs is not equal to rt.

1 rs 0 offset

5 rs rt offset

Branch on equal zero

beqz rsrc,label pseudoinstruction

Conditionally branch to the instructions at the label if rsrc1 equals 0.


Branch on greater than equal

bge rsrc1,rsrc2,label pseudoinstruction

Branch on greater than equal unsigned

bgeu rsrc1,rsrc2,label pseudoinstruction

Conditionally branch to the instruction at the label if register rsrc1 is greater than or equal to rsrc2.

Branch on greater than

bgt rsrc1,rsrc2,label pseudoinstruction

Branch on greater than unsigned

bgtu rsrc1,rsrc2,label pseudoinstruction

Conditionally branch to the instruction at the label if register rsrc1 is greater than rsrc2.

Branch Instructions – cont. Branch on less than equal

ble rsrc1,rsrc2,label pseudoinstruction

Branch on less than equal unsigned

bleu rsrc1,rsrc2,label pseudoinstructionConditionally branch to the instruction at the label if register rsrc1 is less than or equal to rsrc2.

Branch on less than

blt rsrc1,rsrc2,label pseudoinstruction

Branch on less than unsigned

bltu rsrc1,rsrc2,label pseudoinstructionConditionally branch to the instruction at the label if register rsrc1 is less than rsrc2. Branch on not equal zero

bnez rsrc,label pseudoinstructionConditionally branch to the instruction at the label if register rsrc is not equal to 0.

Jump Instructions

Jump

J target 6 26

Unconditionally jump to the instruction at target.

Jump and link

jal target 6 26

Unconditionally jump to the instruction at target. Save the address of the next instruction in register rd.

2 target

2 target

Jump and link register

jalr rs,rd 6 5 5 5 5 6

Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31).

0 rs 0 rd 0 9

Jump Instructions – cont. Jump register

jr rs 6 5 5 16

Unconditionally jump to the instruction whose address is in register rs.

0x0 rs 0 0x8

Load address

la rdest,address pseudoinstructionLoad computed address-not the contents of the location-into register rdest.

Load byte

lb rt,address 6 5 5 16

0x20 rs rt offset

Load unsigned byte

lbu rt,address 6 5 5 16

Load the byte at address into register rt. The byte is sign-extended by lb, but not by lbu.

0x24 rs rt offset

Load halfword

lh rt,address 6 5 5 16

0x21 rs rt offset

Load unsigned halfword

lhu rt,address 6 5 5 16

Load the 16-bit quantity (halfword) at address into register rt. The halfword is sign-extended by lh, but not by lhu.

0x25 rs rt offset

Jump Instructions – cont.

Load word

lw rt,address 6 5 5 16

Load the 32-bit quantity (word) at address into register rt.

0x23 rs rt offset

Jump Instructions – cont.

Load word coprocessor

lwcz rt,address 6 5 5 16

Load the word at address into register rt of coprocessor z (0-3). The floating-point unit is z=1.

0x3z rs rt offset

Load word left

lwl rt,address 6 5 5 16

0x22 rs rt offset

Load word right

lwr rt,address 6 5 5 16

Load the left (right) bytes from the word at the possibly unaligned address into register rt.

0x23 rs rt offset

Jump Instructions – cont. Load doubleword

ld rdest,address pseudoinstruction Load the 64-bit quantity at address into register rdest and rdest + 1.

Unaligned load halfword

ulh rdest,address pseudoinstruction

Unsigned load halfword unaligned

ulhu rdest,address pseudoinstruction Load the 16-bit quantity (halfword) at the possibly unaligned address into register rdest. The halfword is sign-extended by ulh, but not ulhu.

Unsigned load word

ulw rdest,address pseudoinstruction Load the 32-bit quantity (word) at the possibly unaligned address into register rdest.

Store Instructions Store byte

sb rt,address 6 5 5 16

Store the low byte from register rt at address.

0x28 rs rt 0x8

Store word

sw rt,address 6 5 5 16

Store the word from register rt at address.

0x2b rs rt offset

Store word coprocessor

swcz rt,address 6 5 5 16

Store the word from register rt of coprocessor z at address. The floating point unit is z = 1.

0x3(1-z) rs rt offset

Store halfword

sh rt,address 6 5 5 16

Store the low halfword from register rt at address.

0x29 rs rt 0x8

Store Instructions – cont. Store word left

swl rt,address 6 5 5 16

0x2a rs rt 0x8

Store doublewordsd rsrc,address pseudoinstruction

Store the 64-bit quantity in registers rsrc and rsrc + 1 address.

Store word right

swr rt,address 6 5 5 16

Store the left (right) bytes from register rt at the possibly unaligned address.

0x29 rs rt 0x8

Unaligned store halfwordush rsrc,address pseudoinstruction Store the low halfword from register rsrc at the possibly unaligned address.

Unaligned store wordusw rsrc,address pseudoinstruction Store the word from register rsrc at the possibly unaligned address.

Data Movement Instructions Move

move rdest,rsrc pseudoinstructionMove register rsrc to rdest.

Move from hi

mfhi rd 6 10 5 5 6

0 0 rd 0 0x10

Move from lo

mflo rd 6 10 5 5 6

Move the hi (lo) register to register rd.

0 0 rd 0 0x12

Move to hi

mthi 6 5 15 6

0 rs 0 0x11

Move to lo

mtlo 6 5 15 6

Move register rs to the hi (lo) register.

Data Movement Instructions – cont.

0 rs 0 0x11

Move from coprocessor z

mfcz rt,rd 6 5 5 5 11

Move coprocessor z's register rd to CPU register rt. The floating-point unit is coprocessor z=1.

0x1z 0 rt rd 0

Move double from coprocessor zmfcl,d rdest,rsrc1 pseudoinstructionMove floating-point registers frsrc1 and frsrc1 + 1 to CPU registers rdest and rdest + 1.

Move to coprocessor z

mtcz rt,rd 6 5 5 5 11

Move CPU register rt to coprocessor z's register rd.

0x1z 0 rt rd 0

Floating-Point Instructions Floating-point absolute value double

abs.d fd,fs 6 5 5 5 5 6

0x11 1 0 fs fd 5

Floating-point absolute value single

abs.s fd,fs 6 5 5 5 5 6

Compute the absolute value of the floating-point double (single) in register fs and put it in register fd.

0x11 1 0 fs fd 5

Floating-point addition double

add.d fd,fs,ft 6 5 5 5 5 6

0x11 1 0 fs fd 5

Floating-point addition single

add.s fd,fs,ft 6 5 5 5 5 6

Compute the sum of the floating-point double (single) in register fs and ft and put it in register fd.

0x11 1 0 fs fd 5

Floating-Point Instructions – cont. Compare equal double

c.eq.d fs,ft 6 5 5 5 5 2 4

0x11 1 ft fs fd FC 2

Compare equal single

c.eq.s fs,ft 6 5 5 5 5 2 4

Compare the floating-point double in register fs against the one in ft and set the floating-point condition flag true if they are equal.


Compare less than equal double

c.le.d fs,ft 6 5 5 5 5 2 4


Compare less than equal single

c.le.s fs,ft 6 5 5 5 5 2 4

Compute the floating-point double in register fs against the one in ft and set the floating-point condition flag true if the first is less than or equal to the second. Use the bclt or bclf instructions to test the value of this flag.


Floating-Point Instructions – cont. Compare less than double

c.lt.d fs,ft 6 5 5 5 5 2 4

0x11 1 ft fs 0 FC 2

Compare less than single

c.lt.s fs,ft 6 5 5 5 5 2 4

Compute the floating-point double in register fs against the one in ft and set the condition flag true if the first is less than the second. Use the bclt or bclf instructions to test the value of this flag.

0x11 0 ft fs 0 FC 2

Convert single to double

cvt.d.s fd,fs 6 5 5 5 5 6

0x11 1 0 fs fd 0x21

Convert integer to double

cvt.d.s fd,fs 6 5 5 5 5 6

Convert the single precisioion floating-point number or integer in register fs to a double precision number and put it in register fd.

0x11 1 0 fs fd 0x21

Floating-Point Instructions – cont. Convert double to single

cvt.s.d fd,fs 6 5 5 5 5 6

0x11 1 0 fs fd 0x20

Convert integer to single

cvt.s.w fd,fs 6 5 5 5 5 6

Convert the double precisioion floating-point number or integer in register fs to a single precision number and put it in register fd.

0x11 0 0 fs fd 0x20

Convert double to integer

cvt.w.d fd,fs 6 5 5 5 5 6

0x11 1 0 fs fd 0x24

Convert single to integer

cvt.w.s fd,fs 6 5 5 5 5 6

Convert the double or single precisioion floating-point number in register fs to an integer and put it in register fd.

0x11 0 0 fs fd 0x24

Floating-Point Instructions – cont.

Floating-point divide double

div.d fd,fs,ft 6 5 5 5 5 6

0x11 1 ft fs fd 3

Floating-point divide single

div.s fd,fs,ft 6 5 5 5 5 6

Compute the quotient of the floating-point doubles (singles) in registers fs and ft and put it in register fd.

0x11 0 ft fs fd 3

Load floating-point double

l.d fdest,address pseudoinstruction

Load floating-point single

l.s fdest,address pseudoinstruction

Load the floating-point double (single) at address into register fdest.


Move floating-point double

mov.d fd,fs 6 5 5 5 5 6

0x11 1 0 fs fd 6

Move floating-point single

mov.s fd,fs 6 5 5 5 5 6

Move the floating-point double (single) from register fs to register fd.

0x11 0 0 fs fd 6

Floating-point multiply double

mul.d fd,fs,ft 6 5 5 5 5 6

0x11 1 ft fs fd 2

Floating-point multiply single

mul.s fd,fs,ft 6 5 5 5 5 6

Compute the product of the floating-point dobule (single) in registers fs and ft and put it in register fd.

0x11 0 ft fs fd 2


Negate double

neg.d fd,fs 6 5 5 5 5 6

0x11 1 ft fs fd 7

Negate single

neg.s fd,fs 6 5 5 5 5 6

Negate the floating-point double (single) in register fs and put it in register fd.

0x11 0 0 fs fd 7

Store floating-point double

s.d fdest,address pseudoinstruction

Store floating-point single

s.s fdest,address pseudoinstructionStore the floating-point double (single) in register fdest at address.


Floating-point subtract double

sub.d fd,fs,ft 6 5 5 5 5 6

0x11 1 ft fs fd 1

Floating-point subtract single

sub.s fd,fs,ft 6 5 5 5 5 6

Compute the difference of the floating-point double (single) in registers fs and ft and put it in register fd.

0x11 0 ft fs fd 1

Floating-Point Instructions Return from exception

rfe 6 1 19 6

Restore the Status register.

0x10 1 0 0x20

System call

syscall 6 20 6

Register $v0 contains the number of the system call.

0 0 0xc

Break

break 6 20 6

Cause exception code. Exception 1 is reserved for the debugger.

0 code 0xd

No operation

nop 6 5 5 5 5 6

Do nothing.

0 0 0 0 0 0

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