slua653b 5w usb flyback design review
TRANSCRIPT
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Application Report
SLUA653B Revised July 2013
1
5W USB Flyback Design Review/App l ication Repo rt
Michael OLoughlin Senior Power Applications Engineer
Introduction:In USB and isolated low power converter designs-quasi resonant and discontinuous conduction mode
flyback converter topologies are a popular choice, due to their low parts count and relatively low cost.
To reduce the cost even further, TI has developed a quasi-resonant/discontinuous current mode flybackcontroller with primary-side control. This removes the need for optocoupler and TL431 feedback
circuitry reducing the cost of these low power designs even more. To achieve relatively low no load
input power and regulate the output voltage and output current this device uses a control methodology
known as control law. This control methodology uses a combination of primary peak current amplitudemodulation (AM) and frequency modulation (FM) to regulate the output current and voltage please refer
to the data sheet [1] for details. This application report reviews the design of the 5W adapter,
UCC28700EVM-068, evaluation module [2] using the UCC28700 power supply controller. The designcalculations are based on typical values. In a production design the values need to be modified forworst case conditions. Also note there is a MathCAD design tool [3] that goes along with this
application note to make the power supply design process easier using this device.
Design Specifications:
Description Minimum Typical Maximum Units
RMS Input Voltage 90 (VINMIN) 115/230 265 (VINMAX) V
No Load Input Power 30 (PINL) mW
Output Voltage 4.75 5 (VOUT) 5.25 VOutput Voltage Ripple 100 (VRIPPLE) mVpp
Output Load Step(0.1 to 0.6A), (0.6 to 0.1A)
4.1 (VOTRM) 6.0 V
Output Current 1(IOUT) A
Switching Frequency 105 (fMAX) kHz
Full Load Efficiency(230/115V RMS input)
73() %
Table 1, Design Specifications
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Functional Schematic:
VIN
DA
DB
DC
DD
2
6
5
3
4
1
UCC28700
CS
VDD DRV
GNDCBC/
NTC
T1
T1
VS
VOUT+
VOUT-
CA CB
LA
RS1
RS2
RCBC
RLC
RF1
CDD
DZ RS
CS
COUT
RCSRG2
RG1
RZ
RT
3.01k
DE
DF
DG
10
10k
330nF
22
NP NS
NA
RL
10
470uH
QA1nF
Figure 1, UCC28700 5W Offline Flyback Functional Schematic
Selecting RCB/NTC Resistor:In this design cable compensation was not used and resistor R8 was not populated.
Please refer to the data sheet on how to setup cable compensation [1].
Initial Power Budget:To meet the efficiency () goal an initial powerloss budget (PBUDGET) needs to be set.
WAVIVP OUTOUTOUT 515
WPP
P OUTOUT
BUDGET 85.174.0
Bridge Rectifier Selection (DA ..DD):
For this design a 600V, 0.8A, bridge rectifier from Diodes Incorporated was chosen for the bridgerectifier diode (DA.. DD), part number HD06.
VVFDA 1 , forward voltage drop of bridge rectifier diode (VFDA)
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mA
V
W
V
P
I
INMIN
OUT
DA85
22
90
74.0
5
22
, bridge rectifier average diode current (IDA)
mWIVP DAFDADA 85 , estimate power dissipated in bridge rectifier diode (PDA)
Estimate remaining power budget based on bridge rectifier loss.
WPPP DABUDGETBUDGET 68.12
Transformer Calculations (T1):
Transformer demagnetizing duty cycle (DMAG) is fixed to 42.5% based on the UCC28700 control lawmethodology [1].
425.0MAGD
TRis the estimated period of the LC resonant frequency at the switch node.
usTR 2
Calculate maximum duty cycle (DMAX):
47.02
2105425.01
21
skHz
TfDD R
MAXMAGMAX
Calculate transformer primary peak current (IPPK) based on a minimum flyback input voltage. This
calculation includes a factor of 0.6 to account for the reduction in flyback input voltage caused by the
ripple voltage across the input capacitors (CA and CB).
mAV
W
DV
PI
MAXINMIN
OUTPPK
38247.06.029074.0
52
6.02
2
Selected primary magnetizing inductance (LPM) based on minimum flyback input voltage, transformer,primary peak current, efficiency and maximum switching frequency (fMAX).
uH
kHzmA
W
fI
P
LMAXPPK
OUT
PM 896105376
74.0
522
22
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VVQAON 2 , estimated voltage drop across FET during conduction
VVRCS 75.0 , voltage drop across current sense resistor
VVDG 6.0 , estimated forward voltage drop across output diode
Calculate transformer turns ratio primary to secondary (a1) based on volt-second balance.Note in the following equation LSM is secondary magnetizing inductance.
5.146.02
1
DGOUTMAG
RCSAONINMINMAX
SM
PM
S
P
VVD
VVVD
L
L
N
Na
VVDDMIN 8 , UCC28700 minimum VDD voltage before UVLO turnoff.
VVDE 3.0 , estimated auxiliary diode forward voltage drop
VV INITOUT 2_ , Minimum voltage on the output when adapter is connected to a device with a depleted
battery.
Calculate transformer auxiliary to secondary turns ratio (a2)
2.3_
2
DGINITOUT
DEDDMIN
S
A
VV
VV
N
Na
Transformer primary RMS current (IPRMS)
mAD
II MAXPPKPRMS 1513
Transformer secondary peak current RMS current (ISPK)
ADV
PI
MAGOUT
OUTSPK 7.4
2
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Transformer secondary RMS current (ISRMS)
AD
II MAGSPKSRMS 8.13
, transformer secondary RMS current
For this design we estimated the power dissipated by the UCC28700 (PIC) would be 50mW maximum.
Note this will vary in the design based on the FET that is being driven and the maximum frequency it is
being driven at.
mWPIC 50
Calculate auxiliary winding peak current (IAPK)
mADaVV
PI
MAGDEOUT
IC
APK13
)(
2
2
Calculate auxiliary winding RMS current (IARMS)
mAD
II MAGAPKARMS 0.53
For this transformer we allow for 3% efficiency loss from the transformer (PT1)
mWPP OUTT 15003.01
Recalculate remaining power budget
WPPP TBUDGETBUDGET 53.11
A Wurth Electronik transformer was designed for this application, part number 750312723, which hasthe following specifications:
a1 = 15.33
a2 = 3.83
uHLPM 925
uHLLK 16 , primary leakage inductance
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Input Capacitor Selection (CIN = CA + CB):
Calculate input capacitor charge time (tCH) based on 40% input capacitor ripple voltage.
msHz
V
VV
tINMIN
INMININMIN
CH 4.3474
2
6.022sin1
1
Calculate flyback average primary current (IPT1) during input capacitor discharge.
mAV
P
V
P
I INMIN
OUT
INMIN
OUT
PT 722
6.0221
Calculate total input capacitance (CIN) based on minimum flyback input voltage and 40% ripple voltage
across the input capacitor.
msHz
TRL 11472
1
, longest period of the rectified line voltage
VVV INMININRIPPLE 9.504.02 , input ripple to the flyback converter
uF
V
tTIC
INRIPPLE
CHRLPT
IN 101
uFC
CC INBA 52
Calculate input capacitor (CA) RMS current (IC_ARMS) based on 40% input capacitor ripple voltage.
mAt
VCCI
CH
INMINBACINP 311
4.02)(2
, peak input capacitor charge current (ICINP)
mAI
T
tTI
T
tII PT
RL
CHRLCINP
RL
CHCINPRMSCA 82
23232
2
1
22
_
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Estimate of capacitor CBs low frequency (1/TRL) RMS current ( LFRMSCBI _ )
RMSCALFRMSCB II __
Estimate of CBs high frequency RMS current (ICB_HFRMS)
mAD
ID
II MAXPPKMAX
PPKHFRMSCB 12223
22
_
Estimate of CBs total RMS current (ICB_RMS)
mAIII HFRMSCBLFRMSCBRMSCB 1472
_
2
__
For this design 4.7uF, 400V electrolytic capacitors, from Nichicon part number UVR2G4R7MPD were
chosen for the design.
uFCC BA 7.4
These capacitors had a measured ESR of 6 ohms at 105 kHz
ESRCA = ESRCB = 6
Recalculate remaining power budget based on power dissipation by the ESRs in the input capacitors.
WESRIESRIPP CBRMSCBCARMSCABUDGETBUDGET 36.12
_
2
_
Filter Inductor (LA):Filter inductor (LA) is used for EMI filtering. In this design it is just a place holder and the design has
not been optimized for EMI. 470uH inductor from Bourns was chosen, part number RLB0608-471KL.
This inductor has a DCR of 6.5 ohms.
5.6DCR
Recalculate power budget based on DCR losses
WDCRIPP PRMSBUDGETBUDGET 212.12
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Fusible Resistor (RL):
To limit the inrush current during power and for safety a 10 ohm, 3W fusible resistor from Bourn, partnumber PWR4522AS10R0JA was placed at the input of this design.
10LR
Recalculate power budget based on estimated RL losses
WRIPP LPRMSBUDGETBUDGET 984.02
Trickle Charge Resistor (RT):
To reduce no load power losses RT and to keep no load power to a minimum, three 5.11M are used inseries for RT
MMRT 33.15311.5
mW
R
VP
T
INMAXRT 2.9
22
, Total trickle charge resistor power dissipation
Recalculate power budget
WPPP RTBUDGETBUDGET 974.0
VDD Capacitor Selection (CDD):
The CDD is selected with the following equation based on the desired startup time (dtCDDS) of the
UCC28700 controller and knowing the start current (ISTART), as well as, the UCC28700 device startupthreshold (VVDD(on)). For this design a 330nF capacitor was selected.
sdtCDDS 1
uAISTART 5.1
VV onVDD 21)(
nFnFV
dtIR
V
ConVDD
CDDSSTART
T
INMIN
DD 330324
2
)(
Note after CDD has been charged up to the device turn on threshold (VVDD(on)), the UCC28700 willinitiate three small gate drive pulses (DRV) and start sensing current and voltage. (Please refer to figure
2) If a fault is detected such as an input under voltage or any other fault, the UCC28700 will terminate
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the gate drive pulses and discharge CDD to initiate an under voltage lockout. This capacitor will be
discharged with the run current of the UCC28700 (IRUN) intil the VDD turnoff (VVDD(off)) threshold isreached. Note the CDD discharge time (tCDDD) from this forced soft start can be calculated knowing the
controller run current (IRUN) without out gate driver switching and the controllers VDD turnoff
threshold (VVDD(off)) and the following equations. If no fault is detected, the UCC28700 will continue
driving QA and controlling the input and output currents [1] and a soft start will not be initiated.
mAIRUN 1.2
VV offVDD 8)(
ms
IR
V
VVCdt
RUN
T
INMAX
offVDDonVDD
DDCDD71
2
)()(
VDD
0VDRV
VVDD(on) =21V
VVDD(off) =8V3 Initial DRV Pulses After VDD(ON)
Figure 2, VDD and DRV at Startup with Fault
Current Sense Resistor (RCS):
For this design 2.05 ohm resistor was selected based on a nominal maximum current sense signal of0.75V.
ohmI
VR
PPK
CS 05.2965.175.0
WRIP CSPRMSRCS 046.02
, nominal current sense resistor power dissipation
Recalculate power budget
WPPP RCSBUDGETBUDGET 928.0
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Select Output Diode (DG):
Calculate diode reverse voltage (VRDG)
VaVVV INMAXOUTRDG 45.29
1
21
Calculate peak output diode (IDGPK)
AII SPKDGPK 7.4
For this design we selected a 3A, 40V schottky rectifier with a forward voltage drop (VFDG) of 0.31V.
VVFDG 31.0
Estimated diode power loss (PDG)
OUT
FDGOUTDG
V
VPP 0.31W
Recalculate power budget
WPPP DGBUDGETBUDGET 618.0
Select Output Capacitors (COUT):
Select output ESR based on 90% of the allowable output ripple voltage
mA
mV
I
VESR
SPK
RIPPLECOUT 19
7.4
9.01009.0
For this design the output capacitor (COUT) was selected to prevent VOUT from dropping below the
minimum output voltage during transients (VOTRM).
VVOTRM 1.4
mFVV
V
Pms
COTRMOUT
OUT
OUT
OUT 1.12
2
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For this design two 560uF capacitors were used in parallel on the output, with an ESR of 13m each.
mFuFCOUT 12.15602
mm
ESRCOUT 5.62
13
Estimate total output capacitor RMS current (ICOUT_RMS)
AV
PDII
OUT
OUTMAGSPK
RMSCOUT 46.13
22
_
Estimate total output capacitor loss (PCOUT)
mWESRIP COUTRMSCOUTCOUT 142_
Recalculate power budget
WPPP COUTBUDGETBUDGET 604.0
Select FET QA:
For this design we had chosen a 600V rated MOSFET with the following characteristics:
ohmRDSON 5.4 , FET QA on resistance
pFCOSS 5.8 , average FET drain to source capacitance
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Figure 3, Gate Charge vs Vgs
Estimate FET losses (PQA)
AIDRIVE 35.0 , maximum FET gate drive current
nCQg 9 , gate charge just above the miller plateau
ns
I
QtDRIVE
gr 522
, estimated FET Vds rise and fall time
Estimate FET power loss by driving the FETs gate (Pg)
nCQg 121 , Gate charge at 12V drive clamp
VVg 12
mWfQVP MAXgg 1512 1
Calculate the average input voltage to the flyback at the maximum input voltage (VINMAX).
VVV
VV FDAINRIPPLE
INMAXFLY 34722
2
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Estimate FET average switching loss (PSW)
mWftI
aVVVP MAXrPPKVDGOUTFLYSW 2692
1
Estimated FET Coss power dissipation (PCOSS)
pFCOSS 5.8 , average FET drain to source capacitance
mWfVC
P MAXFLYOSS
COSS 542
2
Calculate power loss from Rdson (PRDSON)
WRIP DSONPRMSRDSON 1.0)(2
Estimate total FET losses (PQA)
mWPPPPP COSSgSWRDSONQA 441
Recalculate the power budget
mWPPP QABUDGETBUDGET 163
Setup Zener Clamp to Protect FET QA:
VVZ 82 , Zener Clamp Voltage (DZ)
VV MAXds 600_ , FET maximum drain to source voltage
VVVV INMAXMAXdsCLAMP 2.16529.0_ , Available Clamp Voltage to Protect FET QA
5.2166.0
PPK
ZCLAMPS
I
VVR
Select a standard resistor for the design.
215SR
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Estimate Zener Clamp/LLKpower dissipation (PLK)
mW
fILP MAXPPKLPKLLK 122
2
2
Recalculate power budget
mWPPP LLKBUDGETBUDGET 40
Select VS voltage divider (RS1, RS2):
uAI runVSL 220)( VS Line-sense run current
Note RS1 so the converter will go into under voltage lockout when the input is below 80% of the
minimum specified input voltage.
kI
Va
a
RrunVSL
INMIN
S 6.115
8.02
)(
1
2
1
Select a standard resistor for the design
kRS 1211
k
R
VaVV
VR
S
DGOUT
S 7.274
4
1
2
2
Calculated RS2 is a starting point and will need to be adjusted in circuit. To have a 5V regulated output
this resistor was adjusted to 30.1k
kRS 1.302
Calculate VS divider power dissipation (PVS)
mWRR
aVVDP
SS
DGOUTMAX
VS 3.121
2
2
Select auxiliary diode (DE) for this design that had a forward voltage drop (VDE) of 0.6V.
VVDE 6.0
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VVaVVV DEDGOUTDD 8.202 , UCC28700 supply voltage at VDD
Va
aVVV INMAXDDRDE 1152
1
2 , maximum reverse voltage across VDE
mAIRUN 1.2 , UCC28700 bias current when gate drive = 0V
mAV
VIPI
DD
VDDRUNg
DD 8.2
, Estimated UCC28700 VDD current.
Calculate DE power dissipation (PDE)
mWVIP DEDDDE 7.1
Recalculated power budget
mWPPPP DEVSBUDGETBUDGET 037
Preload Resistor Selection (RZ):
To keep the output voltage from climbing at no load a pre-load resistor is required. This is generally a
trial an error process. For this designs the preload resistor that kept the output regulated under no loadconditions was 3.01 k.
KRZ 01.3
Calculate RZ power dissipation (PRZ)
mW
R
VP
Z
OUTRZ 3.8
2
Recalculated power budget and there is 29 mW of margin left in the power budget to meet the efficiencyrequirements of the design. Note in production designs, more margin might be required. Also note
these calculations are estimations and the final design may need to be adjusted to hit efficiency and
regulation requirements.
mWPPP RZBUDGETBUDGET 29
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Internal BlankingThe UCC2870X controller regulates the output voltage by sensing the auxiliary (Aux) winding. This
removes the need for opto isolator feedback scheme reducing the cost of the design. However, this
voltage control feedback scheme is susceptible to leakage spikes at the switch node that occur in most
flyback converters. This signal is coupled through the turns ratio of the transformer (T1) and shows upon the Aux winding during tLK_RESET , please refer to figure 4 for details.
To help insure the leakage spike on the Aux winding does not cause a control issues, the UCC2870X
blanks (tB) the Aux signal to the controller for 500 ns to 1.5 us depending on loading. Please see the
data sheet details [1]. Note the ringing on the auxiliary winding needs to be less than 100mV peak
to peak after tB. Snubbing circuitry on the secondary and/or auxiliary winding may be required to
reduce ringing.
Aux/
DE Cathode
RCS
DRV
0V
tB
0V
tLK_RESET
VS Samples Aux Voltage for Control
QA on
QA off
Aux Ringing after tB < 100mV
Figure 4, Auxiliary Winding VS Blanking
To ensure the leakage spike does not cause control issues it needs to be dissipated before the Aux
blanking (tB) has terminated. The tank frequency (fLC) between the switch node capacitance (CSWN) and
the transformer leakage inductance (LLK) should be greater than 1MHz.
SWNLK
LC
CL
f
2
1
MHzns
fLC 15002
1
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Select line compensation resistor RLC:Resistor RLCprovides offset to the peak current comparator input (CS). RLC is adjusted to terminate the
gate drive signal (B) early to prevent primary current (A) from over shooting [1]. Please refer to figures
5 and 6 for details.
Figure 5, Peak Current Limit Comparator Figure 6, CS(A), QAg(B), VQADS Signals
25LCK , Line Compensating Ratio [1]
Calculate RLC initial resistor setting based on QADS rise and fall time (tr)
kL
atRRKR
PM
rCSSLCLC 29.5
11 , Starting Point for RLC
In circuit adjust RLC so the maximum output current is (IOUT). For this design RLC was set to 4.64 k.
kRLC 64.4
Estimate no load input power (PNL):
kHzfMIN
1 , Minimum operating frequency
uWfQVP MINggg 144 , gate drive power dissipation at fMIN
uAIWAIT 85 , VDD input current at 1 kHz operating frequency [1]
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mWVIPP DDWAITgVDD 9.1 , Estimated UCC28700 power dissipation at fMIN
Estimate switching losses (PSWFM) at high line at fMIN
uWft
I
aVVVPMINrPPK
VDGOUTFLYSWFM 9452
31
mWfVC
P MINFLYOSS
COSS 5.02
2 , estimated COSS losses at fMIN
uW
fI
L
P
MINPPK
LPK
LLK 1292
3
2
, estimate of leakage power dissipation at no load
The estimated no load input power (PNL) is roughly 22 mW. In the actual 5W design the no load inputpower was roughly 20 mW at 230V RMS input voltage.
mWPRZ 3.8
mWPRT 2.9
mWPPPPPPP LLKRTRZCOSSSWFMVDDNL 22
5W EVM Schematic:
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Figure 7, Schematic
Efficiency:
Efficiency
64%
66%
68%
70%
72%
74%
76%
78%
25% 50% 75% 100%
Output Power
%E
fficiency
Efficiency @ 115V RMS
Efficiency @ 230V RMS
Figure 8, Efficiency
Load Transient at 115V RMS
CH1 = IOUT, CH4 = VOUT with a 5V offset
Figure 9, 0.1 to 0.6A load step Figure 10, 0.6 to 0.1A load step
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Load Transient at 230V RMS
a. CH1 = IOUT, CH4 = VOUT with a 5V offset
Figure 11, 0.1 to 0.6A load step Figure 12, 0.6 to 0.1A load step
REFERENCES
[1] UCC28700/1/2/3 Data Sheet, Constant-Voltage, Constant-Current Controller with Primary Side
Regulation, SLUSB41, July 2012, http://www.ti.com/lit/gpn/ucc28700[2]Using the UCC28700EVM-068, UCC28700EVM-068 5W USB Adapter, SLUU968, July 2012,
http://www.ti.com/litv/pdf/sluu968
[3] UCC28700 MathCAD design tool,http://www.ti.com/litv/zip/sluc381
http://www.ti.com/lit/gpn/ucc28700http://www.ti.com/lit/gpn/ucc28700http://www.ti.com/litv/pdf/sluu968http://www.ti.com/litv/pdf/sluu968http://www.ti.com/litv/zip/sluc381http://www.ti.com/litv/zip/sluc381http://www.ti.com/litv/zip/sluc381http://www.ti.com/litv/zip/sluc381http://www.ti.com/litv/pdf/sluu968http://www.ti.com/lit/gpn/ucc28700 -
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Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have notbeen so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defenseMicrocontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
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