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SLX FPGA Quick Start Guide

Version 2020.4

Date 2021-01-11

Quick Start Guide

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Contents

Introduction ............................................................................................................................................................................................................. 1

The SLX FPGA Workflow ........................................................................................................................................................................... 1

SLX FPGA Features....................................................................................................................................................................................... 1

Getting Started ....................................................................................................................................................................................................... 3

Installing SLX .................................................................................................................................................................................................... 3

Install Xilinx Tools .......................................................................................................................................................................................... 3

Starting SLX ....................................................................................................................................................................................................... 3

Importing Project ............................................................................................................................................................................................ 5

Configuring the SLX FPGA Project ...................................................................................................................................................... 6

Application Transformation Toward Optimized IP Block .............................................................................................................. 9

Discovering and Resolving Synthesizability Issues .................................................................................................................. 9

Finding and Optimizing Parallel Loops .......................................................................................................................................... 11

Hardware Optimization ............................................................................................................................................................................. 14

HLS Pragma Insertion ............................................................................................................................................................................... 15

Performing Synthesis ............................................................................................................................................................................... 16

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Introduction

SLX FPGA is a tool that accelerates the process of converting C/C++ code into a high-performance FPGA implementation. This document provides a quick step-by-step guide to navigate through the different features of an SLX FPGA project for creating FPGA IP blocks.

The SLX FPGA Workflow

SLX FPGA takes in C/C++ code and first performs a static analysis to provide the user with an overview of its functions and dependencies. The user can then use the tool to check functions of interest for synthesizability, perform deep tracing and most importantly, conduct dynamic analysis of the code. SLX FPGA provides aide to the following upon code analysis:

• Refactor non-Synthesizable C/C++ code – SLX FPGA provides automatic and guided refactoring of C/C++ code to make the code synthesizable by the HLS compiler.

• Parallelism Detection – SLX FPGA detects code regions within an application that can be executed in parallel when implemented in hardware.

• Hardware Optimization – After detecting parallelism in the application, SLX FPGA determines the ideal hardware implementation of the parallel function C/C++ software based on user supplied constraints, ensuring an optimized implementation.

• HLS Pragma Insertion - Once the optimized hardware implementation is determined, SLX FPGA inserts HLS Pragmas into the source code to direct the HLS compiler on how to implement the function in hardware.

After these steps are completed, the application source code is exported to Vivado or Vitis HLS as an SLX optimized project.

SLX FPGA Features

The most important SLX FPGA features are accessible through the SLX menu or via the SLX toolbar buttons.

Figure 1.1: SLX toolbar features

The table on the next page explains these features.

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Command Functionality

Configure Project Primary GUI mechanism to edit the configuration of the project.

Clean Project

Cleans all generated output files for the project. The action must be triggered after any major modification of the configuration or source code.

Run Code Compiles and runs the application binary generated using the SLX compiler to ensure that application functionality is correct prior to further analysis.

Workflow tools for Transforming Application to Optimized IP Block:

Function Mapping Editor

Opens the editor that helps defining hardware (FPGA) and software partitioning, checking HW mapped functions for synthesizability, analyzing selected functions for parallelism, triggering SLX optimization to properly exploit HLS pragmas, and performing manual design space exploration.

Find and Optimize Parallel Loops

Analyzes the program to discover potential parallelism and run optimization algorithms to determine appropriate HLS pragmas.

Generate HLS-Aware Code

Generate the HLS pragmas automatically calculated by SLX, or manually set up in the application source code. Opens a CodeGen wizard allowing the review and reconfiguration of the generated pragma.

Synthesize

Calls the Vivado/Vitis HLS compiler to run on the modified source code with inserted pragmas. A bitstream for the hardware accelerators is produced as a result.

Show Synthesis Report

Displays statistics such as Performance Estimates, Utilization Estimates, Interface Summary and other relevant data after the project has been synthesized.

Code Analysis and Optimization Reports:

SLX Hints

Navigates through the generated hints in the SLX Hints view. Provides a view of all available hints, such detected parallelism, data dependencies and partitioning hints.

Call Graph

Displays the software call graph of the application with data on function runtimes, latency estimates, relationships between function callers and callees.

Code Analysis Graph

Displays a graphical representation that combines function execution times with the variable accesses in the entire program, which can be filtered over multiple criteria.

Memory Analysis

Displays detailed statistics for all the variables in the application. This includes read and write accesses with reference to source code location of each access. It covers all global, local and heap variables.

Table 1.1: SLX FPGA features

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Getting Started

Installing SLX

The following steps are described in detail in the Installation Guide

• Download the installation package and activate your SLX license entitlement from the Silexica Licensing portal

• Install SLX and set up the license on your machine

Install Xilinx Tools

Before we begin, make sure that one of the following versions of Xilinx tools is installed:

• Vitis HLS 2020.2

• Vivado HLS 2020.1 (Vivado Design Suite 2020.1)

• Vivado HLS 2019.2 (Vivado Design Suite 2019.2)

Starting SLX

SLX FPGA can be started by clicking the SLX desktop icon (Windows, Linux). Alternatively, to run SLX from the command line on Linux, open the terminal and navigate to the root folder of the SLX installation. Next, type the following commands to start SLX FPGA: “source exports” followed by “SLX”.

The first time SLX starts, the following dialog screen is displayed to configure the default workspace:

Figure 2.1: SLX Launcher

Specify a desired workspace directory and click “Launch”. The following Welcome screen is displayed for creating a new project or importing an existing project.

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Figure 2.2: SLX Welcome Screen

The first section in the Welcome Screen is a guided tour for new users. It enables users to take a design of their choice and walks them through the various steps of the flow, providing basic instructions and recommendations at each step. It is recommended to take this tour when first using SLX. We will not walk through the steps of this tour in this Quick Start Guide.

Figure 2.3: SLX Guided Tour

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Importing Project

SLX FPGA comes with a series of sample projects; the example project called “keccak” is used in this document for illustration purposes. Click “Import FPGA Project” from the Welcome screen.

Figure 2.4: Import Project screen

From the list of projects under silexica/examples/fpga, check the “keccak” checkbox. Click Finish to import the project into the workspace.

Configuring the path to Xilinx Tools

SLX FPGA needs to be configured with the installation path of Xilinx Vivado tools. In the following dialog box, select the path to the desired Xilinx tool (Vitis HLS 2020.2, Vivado HLS 2020.1 or Vivado HLS 2019.2). For this demonstration, Vitis HLS 2020.2 will be used.

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Figure 2.5: SLX FPGA Xilinx tools configuration screen

Configuring the SLX FPGA Project

Click configure to set the Configuration Details for the project.

The Basic Options section is used to select the FPGA Part. The FPGA Part corresponds to one of the supported Xilinx devices, which belongs to a device family and an architecture. The FPGA Part xczu9eg-ffvb1156-2-e is selected by default. Click the “Select” button if you wish to select a different FPGA Part.

Figure 2.6: Configuring the Basic Options

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Figure 2.7: The FPGA Part selector

The filters at the top of the screen can be used to help narrow down the selection criteria. Click OK to

finalize the selection.

Figure: 2.8: Basic Options

The Xilinx Platform Archive field allow for the configuration of a FPGA Part by importing an existing DSA

(Xilinx Device Support Archive) file or XSA (Xilinx Support Archive) file; this method of choosing the FPGA

Part will not be utilized for this demonstration.

Configure the Build Options section as follows. For the keccak project, the following values should

already be pre-populated. Ensure that the base path is set to “.”, which means all the files within the

project tree are in scope of analysis.

Figure: 2.9: Configuring the Build Options

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Figure: 2.10: Finishing the other parts of the project configuration

Complete the other parts of the project configuration according to the screenshot above.

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Application Transformation Toward Optimized IP Block

A Top-Level Hardware Function must be selected. When creating an FPGA IP block, the top-level function and everything below it will become the FPGA IP. The Top-Level Hardware function can be selected via the HLS Options section in the Configuration Editor. For this project, the Top-Level Hardware Function “keccak” is selected by default.

Figure 3.1: Setting a Top-Level Hardware Function in the Configuration Editor

If a thorough code analysis of an application is required, utilize the Function Mapping Editor. This feature provides a centralized interface to facilitate access to the most important SLX FPGA features: select a Top-Level Hardware function (if one has not been selected), check its Synthesizability using the context menu, and run “Find and Optimize Parallel Loops” to perform automatic design space exploration for the supported HLS pragmas.

To open the Function Mapping Editor, click the toolbar button.

Discovering and Resolving Synthesizability Issues

Clicking on the Function Mapping Editor opens the static Callgraph. Functions in the application are represented using rounded rectangles. The border color represents where functions are mapped: functions that have been mapped to the FPGA display a red border, while those that are not mapped have a blue border. The top-left icon represents the synthesizability status of functions.

• A function whose synthesizability is unknown because it was not yet evaluated for synthesizability will

display a question mark .

• Functions which can be mapped to the FPGA (synthesizable) display a green check mark

• Functions which need to be rewritten to be made synthesizable display a red cross .

A function mapped to the FPGA as a Top-Level Function will also show a star icon .

To check a function for synthesizability, right-click on the function and click “Check for Synthesizability”.

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Figure 3.2: Checking individual functions for synthesizability

If a function is found to be synthesizable, it can be mapped to the FPGA by right-clicking and selecting “Map to FPGA” in the context menu (Figure 3.3). For this demonstration, the function “keccak” is already selected to be mapped to the FPGA via the project configuration editor.

Figure 3.3: Selecting a Synthesizable function to map to the FPGA

If a function is found to be not synthesizable, the following notification is displayed:

Status is “Not synthesizable”: “” is not synthesizable, click here

to investigate.

Clicking the link opens a source panel with the function highlighted and centered, as well as synthesizability hints for the function. In general, a code rewrite must be performed for this case to ensure that the source code can be synthesized. After the code has been modified, repeat the steps above to re-run synthesizability checks until the

desired outcome has been achieved. Figure 3.4 displays an example of a hint accessed by clicking the icon to the right of the function in the SLX Hints view.

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Figure 3.4: Resolving Synthesizability Issues

The Auto-select FPGA functions option automatically maps functions to the FPGA and optimizes all synthesizable functions whose execution time is above a configurable threshold. Running this feature is optional and may require some time.

Figure 3.5: Auto-select FPGA functions

Finding and Optimizing Parallel Loops

SLX FPGA can automatically extract available Data-Level Parallelism (DLP) and Pipeline-Level Parallelism (PLP) in the application. Parallelism detection and optimization can be invoked when a function is first mapped to the FPGA, by clicking on the notification displayed at the top of the Function Mapping Editor Graph (Fig 3.2). The

analysis can also be triggered by clicking Find and Optimize parallel loops in the context menu or by right-

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clicking on the Function Mapping Editor Graph and selecting “Find and Optimize Parallel Loops”. SLX will also analyze all existing callee functions whenever “Find and Optimize Parallel Loops” is executed on the selected function.

Figure 3.6: Find and Optimize Parallel Loops within a Function

The parallel regions of a function can be viewed in the Properties tab > Parallel Loops section of the Function Mapping Editor. The parallel code blocks detected by SLX FPGA are sorted by the order in which they appear in the source code. If there are nested loops, the inner loops in the source code are grouped inside their outer loops in hierarchical order. Clicking on a loop populates the details of the loop to the right. The loop number and its line number are displayed at the top. Under the loop name are configurations that help take advantage of available parallelism:

• Unrolling and Pipelining options can be enabled, disabled and configured for the loop.

• Pragmas are automatically generated for available unroll and pipelining options.

• The Unroll Factor is only used for DLP loops and represents the number of times, n, that the body of a loop has been replicated to create n copies. The Initiation Interval represents the number of clock cycles between the start times of consecutive loop iterations in pipelined loops.

For more information on Loop Pipelining and Loop Unrolling, see the Xilinx Support article.

Figure 3.7: Displaying and Configuring Parallel Loops within a function

Parallel loops are also displayed within the SLX Hints view, accessed by clicking the SLX Hints tab or by right-clicking on the function in the Function Mapping Editor and clicking “Show related hints”. Hints are organized in a hierarchical manner as a table, reflecting the application structure. To see only hints related to Parallelism, type “PARTITIONING” in the Name column filter:

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Figure 3.8: SLX Hints for the function keccak

• The Name column displays icons that either correspond to a hint or structural information about the application. These icons help distinguish between the different classes of information:

o corresponds to a function in the source code

o corresponds to a loop

o groups hints related to a particular type of parallelism

o corresponds to information specific to a type of parallel partition. For instance, hints with

this icon will report available parallelism or the causes for missing parallelism

• The Status column indicates the Status of a parallel partition by a small checkbox:

o the parallelization strategy associated with the code section (i.e., a loop) is feasible, meaning that the code in the loop can be executed concurrently

o the parallelization strategy associated with the code section is not feasible, and there are blockers that hinder parallelism

• The CPU Total Cost column indicates the total execution time contribution of the function or loop with respect to the overall application. The CPU metrics are useful in identifying the hotspots of the application and the functions to be mapped to the FPGA. These are not normally generated to ensure faster analysis as the FPGA Total Cost data is usually more relevant. To obtain the CPU metrics, please run Auto-select FPGA functions from the Function Mapping Editor (Figure 3.5).

• The FPGA Total Cost column convey the design latency of functions and loops on the FPGA after they have been optimized by SLX. Please run Find and Optimize Parallel Loops before accessing the FPGA metrics.

To view only SLX Hints related to parallelism, type “PARTITIONING” in the Name filter.

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Figure 3.9: SLX Hints window showing parallel sections

Double-click a line of interest in the SLX Hints view to jump to the line of code and reveal pragmas inserted by SLX.

Figure 3.10: Revealing pragmas within code

Hardware Optimization

SLX FPGA will try to maximize the performance of every function that needs to be implemented as an IP block, while respecting the resource constraints imposed by the available FPGA resources or set manually by the user. The suggested design is computed during a global optimization that simultaneously considers:

• Loop unrolling and pipelining

• Array partitioning and reshaping

• In-lining and selecting appropriate interfaces

The estimated hardware performance can be seen in the synthesis report opened at the completion of HLS synthesis. For advanced cases, where adjustments to the SLX FPGA proposed design need to be made, SLX FPGA

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allows reconfiguration of the Parallel regions, Interfaces and Bandwidth to achieve the desired effect. Using the Properties view of the Function Mapping Editor, the:

• Interfaces section allows the selection of interface ports for the return values and arguments of the Top-Level hardware function. The detailed information includes the interface type to be used for the selected port as well as all its associated configurations.

• Bandwidth section allows setting the data-rate constraint for both input and output ports of the IP block in terms of bandwidth. As an alternative, a specific bus width can also be specified on individual ports in the Interfaces section.

Figure 3.11: Interfaces and Bandwidth in the function’s Properties view

HLS Pragma Insertion

From the SLX FPGA main menu, click Generate HLS-Aware Code . Pragma code generation is guided through a Code Transformation Wizard.

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Figure 3.12: Code Transformation Wizard

The code transformation wizard allows the selection of pragmas. Pragmas can be selected or un-selected by clicking the checkbox next to the pragma at the top of the wizard. When desired pragmas have been selected, click Next. The next screen allows the user to modify any parameters in the generated pragmas by editing the generated code if necessary. Once satisfied with the results, click Finish.

Performing Synthesis

From the SLX menu, click Synthesize Project . At this point, SLX will invoke the Vivado/Vitis HLS tool to synthesize the C/C++ code, guided by the SLX inserted pragmas, into an RTL IP block. The IP block can then be used in either the Vivado Design Suite or in the Xilinx Platform Studio (XPS). This can be seen in the “hls” folder within the project (it is a Vivado/Vitis HLS project folder which can be directly imported into Vivado/Vitis HLS).

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Figure 3.13: IP generated after synthesis with Pre-synthesis Synthesis Strategy

The Performance, Utilization Estimates and Interface Summary data can be seen in the Synthesis Report (Figure 3.13). To view a raw-text version of the report, click the “Show detailed report” link.

Figure 3.14: Sample Synthesis Report