s.monteilps/spd commissioning1 outline 1)status summary. 2)plans and operations for the next month....

S.Monteil PS/SPD COMMISSIONING 1

PS/SPD COMMISSIONING

OUTLINE

1) STATUS SUMMARY.

2) PLANS AND OPERATIONS FOR THE NEXT MONTH.

3) CONCLUSION.

COMMISSIONING MEETING – NOVEMBER 2007



PS/SPD SCHEME

Flash LEDs w/ ODIN signalTubes response

VFE integrates signal Transmission to FE Board

Digitalize and correct PS data

DAQ PATH @ L0PSTELL1DAQ/ORWELLHIstogrammingRecompute the trigger response

TRIGGER PATH @ 40 MHzTrigger cabling Build Trigger InformationGo to SPD CBGo to Validation Board



Flash LEDs w/ ODIN signal

PS: All C-side is measured. Many problems found and fixed in a collaborative work with INR. One problem left : on FEB004 in SM4 (innermost). LED triggered signal driven by internal ChannelB from Croc. FIXED.

SPD: All detector is measured w/ list of problems reported (LED triggered with a standalone system).

•2 boards (64 channels) w/ no signal.•Plus 2 groups of 16 channels broken.

PLANNED ON WEEK 7 (INR/BCN work)

MAIN MESSAGE: MOST LIKELY IN GOOD SHAPE.


COMMISIONNING MEETING – OCTOBER 2007

3) COMMISSIONING THE TUBES/DETECTOR WITH LEDs SYSTEM

Tubes are OK. All relevant projects are now fine (LED and HV).See November talk. SPD measured w/ LED week 6

4) COMMISSIONING THE VFE

PS: still clock connection concerns (We lose 64 channels in a once), see Valentin’s talk yesterday.

SPD: no major concern. Pedestals and noise fine for both systems.Survey : made easy by the cooling system.Keep in mind we will need a « final » access for visual inspection.


COMMISSIONING MEETING – DECEMBER 2007

5) COMMISSIONING THE TEMPERATURE SYSTEM

C-side.

The water has been made flowing on Monday, 3rd of December.

Project PSDCSTEMP is working with FSM installed.

The temperature VFE off is around 16 degrees (actually this is the water temperature).

Then switch VFE on for temperature measurements.



C-side.




C-side.

1 VFE IS NOT SUPPLIED. NICE, IT ALLOWS TO SEE THE REFERENCE.




C-side.

Actually, we see a regulator board not supplied, because of one miscabled fuse.




Conclusion:

Water cooling cools.

PSDCSTEMP project is working fine (Maxim Martemiyanov).

Temperature on boards (VFE and regulators) is below or about 25 °C.

All C-side VFE have been supplied. Few miscabling fixed. All OK.

Temperature cut-off has to be DSS-interfaced. I’d suggest 30 °C as a starting value.




6) COMMISSIONING PSFEB (Digitization and data treatment):

All PSFEB repaired to cure the delatch problem. All recabled and remeasured. In addition, succesful crate configuration test.

Pedestal measurements and subtraction : all measured. Pedestals are stable and noise is satisfactory (PS 1mV, SPD 2 mV). (For other parameters, wait for particles).

Scan the phases range (ADC and signal sampling, integration time, sampling the SPD signal). Automated processes exist.

Get the adequate synchronization for Croc.



6) 1) TIME-ALIGNMENT WITHIN THE BOARDS.

Five phasers to be dealt with. Some correlated.Most important. 1) ADC-FE , the sampling of ADC signal by the FE-PGA.2) VFE-ADC , the sampling of VFE signal by the ADC.3) VFE , the integration starting time.

The Alignment:

Fix a VFE value, scan the allowed (ADC-FE , VFE-ADC) region with pedestals.

Fix a correct ADC-FE, scan the allowed (VFE- VFE-ADC) difference, with LEDs fired by the LHC clock. Select the value for which we get S(BC-1)/S(BC) = 1% ( best value driven by test beam analysis).



6) 1) TIME-ALIGNMENT WITHIN THE BOARDSAll C-side is measured. PRS_1 to be completed.



6) 2) SYNCHRONIZING CROC All C-side expect PRS_1 is measured. PRS_3 problematic (see

Valentin’s talk).

PRS_3Ideal picture (1 board)



7) THE DAQ PATH The two last weeks before Christmas

PRS_0 was set on TFC_7 Configure Croc and FEBs at the best measured values. Let FEBs

measure the VFE pedestal.

Configure the PSTell1 (see StephaneTJ’s talk for a report on problems)

Send periodic Trigger.

Build the events and ask Orwell to produce a Ntuple (For fun, Olivier D. ran succesfully the presenter).

453 useful events were recorded.




13 out 14 boards of PRS_0

FEB_6 is bizarre

As an example, look at FEB_4

In that plot, only 64 values of pedestals. We took an even periodic trigger. VFE chips don’t flip.




As an example, one pedestal of channel 15 (FEB_4).

FEB_6 is bizarre. Croc header is an Hcal one as seen in spy memory of Tell1. As a consequence, it is not reconstructed. Must be disabled in Crate configuration.

No severe pathology observed elsewhere (no deep scrutiny yet).



1. Check connectivity (trigger cables)

PS NEIGHBOURS (Done, problems found, see yesterday)

TVB (on the way, miscabling found, fixed) ECAL1 AND ECAL2 (Started, no problems found so far)

2. Simultaneously get the phasers for incoming data sampling (measuring the allowed intervals and choice a safe phase value).

3. SPD CB backplane connections have been checked OK.

4. Optical link (SPD to selection board) have been checked.

8) COMMISSIONING THE PS/SPD TRIGGER PATH



OPERATIONS AND PLANNING FOR THE NEXT 4 WEEKS

CONCENTRATE ON PRS_0, DEBUG THE WHOLE CHAINS DAQ AND TRIGGER. ONCE HAPPY, ENHANCE THE SYSTEM.

Week 4: Power on again and reproduce the latest achievements

PS: PSFEB ECS: Update and Tuning. DAQ PATH TEST: Concentrate on TELL1. HARDWARE: Neighbour Trigger cable backplane slot 2 (Pit/Bdg 156). CROC PRS_3 exchange to check the origin of small range.

SPD: CB ECS: Installation of SPD CB PVSS Tuning. SW: Installation of the Threshold Scan C++CAT.



Week 5:

PS - Complete ECS work. CROC and PSFEB settings. DAQ PATH TEST - Complete TELL1, Orwell, histogramming … TAKE PEDESTALS

SPD - Complete ECS work. Bit Error Rate systematic measurements. Threshold_Scan w/ LEDs Generic VFE tests (control, settings, regulator boards).

OPERATIONS AND PLANNING FOR THE NEXT 4 WEEKS- C-side



Week 6: PS - Global commissioning week. Data analysis.

SPD - Global commissioning week.

Common tests of SPD/PS (PRS_2/PRS_3) . Sampling phase of SPD data. Time align PS and SPD w/ LEDs.




Week 7:

PS - Make C-side fully operationnal.

SPD -LEDs w/ INR

SPD and PS - Connectivity test LED by LED w/ dedicated driver board. Check mappings.




There are specific works which are not mentionned in the mainstream, but mandatory and has to be performed in the periods crates are available :

• Complete test of all trigger cables. • Systematic measurements of the PSFEB phases. • Monitoring/Survey of the FE and VFE connections. • Access required to reconnect VFE SM2-T01.• Should start the time alignment of the trigger path (w/ Rams).• Measure Cosmics when possible.




A-Side :

It is not poorly known: both for PS and SPD, Tubes, VFE and FEB channels have been already checked « individually ». It means we are not expecting nasty hardware problems.

It is mandatory yet to measure the LEDs for both systems: PS was not measured, SPD showed really weird results. As at some point the works on the two sides compete, . Sergey and Evgueni already started to monitor LED w/ the CAT software. As at some point the works on the two sides compete, we shall aim at making the two actvities quickly as independant as possible.




A lot has been made.

A lot has to be made.

C-Side shall be fully operationnal : Week 8.

A-side hw checks completed : Week 8.

Not a word this week from PS on the monitoring and calibration software, neither on time alignment development or database. In this state of the manpower, we need to rely on unilateral mutualisation of SPD, ECAL,HCAL developments.

CONCLUSIONS/MILESTONES

s.monteilps/spd commissioning1 outline 1)status summary. 2)plans and operations for the next month....

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